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/aosp_15_r20/external/coreboot/src/vendorcode/amd/fsp/cezanne/
H A DFspmUpd.h18 typedef struct __packed { struct
19 /** Offset 0x0040**/ uint32_t bert_size;
20 /** Offset 0x0044**/ uint32_t tseg_size;
21 /** Offset 0x0048**/ uint32_t pci_express_base_addr;
22 /** Offset 0x004C**/ uint8_t misc_reserved[32];
23 /** Offset 0x006C**/ uint32_t serial_port_base;
24 /** Offset 0x0070**/ uint32_t serial_port_use_mmio;
25 /** Offset 0x0074**/ uint32_t serial_port_baudrate;
26 /** Offset 0x0078**/ uint32_t serial_port_refclk;
27 /** Offset 0x007C**/ uint32_t serial_reserved;
[all …]
H A Dplatform_descriptors.h165 typedef struct __packed { struct
166 uint8_t connector_type; // see ddi_connector_type
167 uint8_t aux_index; // see ddi_aux_type
168 uint8_t hdp_index; // see ddi_hdp_type
169 uint8_t reserved;
197 typedef struct __packed { struct
198 uint8_t engine_type; // See dxio_engine_type
199 uint8_t start_logical_lane; // Start lane of the pci device
200 uint8_t end_logical_lane; // End lane of the pci device
201 uint8_t gpio_group_id; // GPIO number used as reset
[all …]
H A Dfsp_h_c99.h30 typedef struct __packed { struct
40 typedef struct __packed { argument
41 uint8_t Revision;
42 uint8_t Reserved[3];
44 uint32_t NvsBufferPtr;
46 uint32_t StackBase;
47 uint32_t StackSize;
48 uint32_t BootLoaderTolumSize;
49 uint32_t BootMode;
50 uint8_t Reserved1[8];
H A DFspsUpd.h12 typedef struct __packed { struct
21 typedef struct __packed { argument
22 /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
23 /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig;
/aosp_15_r20/external/coreboot/src/vendorcode/amd/fsp/mendocino/
H A DFspmUpd.h18 typedef struct __packed { struct
19 /** Offset 0x0040**/ uint32_t bert_size;
20 /** Offset 0x0044**/ uint32_t tseg_size;
21 /** Offset 0x0048**/ uint32_t pci_express_base_addr;
22 /** Offset 0x004C**/ uint8_t misc_reserved[32];
23 /** Offset 0x006C**/ uint32_t serial_port_base;
24 /** Offset 0x0070**/ uint32_t serial_port_use_mmio;
25 /** Offset 0x0074**/ uint32_t serial_port_baudrate;
26 /** Offset 0x0078**/ uint32_t serial_port_refclk;
27 /** Offset 0x007C**/ uint32_t serial_reserved;
[all …]
H A Dplatform_descriptors.h196 typedef struct __packed { struct
219 typedef struct __packed { argument
220 uint8_t engine_type; // See dxio_engine_type
221 uint8_t start_logical_lane; // Start lane of the pci device
222 uint8_t end_logical_lane; // End lane of the pci device
223 uint8_t gpio_group_id; // GPIO number used as reset
224 uint32_t port_present :1; // Should be TRUE if train link
225 uint32_t reserved_3 :7;
226 uint32_t device_number :5; // Desired root port device number
227 uint32_t function_number :3; // Desired root port function number
[all …]
H A Dfsp_h_c99.h30 typedef struct __packed { struct
40 typedef struct __packed { argument
41 uint8_t Revision;
42 uint8_t Reserved[3];
44 uint32_t NvsBufferPtr;
46 uint32_t StackBase;
47 uint32_t StackSize;
48 uint32_t BootLoaderTolumSize;
49 uint32_t BootMode;
50 uint8_t Reserved1[8];
H A DFspsUpd.h12 typedef struct __packed { struct
22 typedef struct __packed { argument
23 /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
24 /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig;
/aosp_15_r20/external/coreboot/src/vendorcode/amd/fsp/glinda/
H A DFspmUpd.h20 typedef struct __packed { struct
21 /** Offset 0x0040**/ uint32_t bert_size;
22 /** Offset 0x0044**/ uint32_t tseg_size;
23 /** Offset 0x0048**/ uint32_t pci_express_base_addr;
24 /** Offset 0x004C**/ uint8_t misc_reserved[32];
25 /** Offset 0x006C**/ uint32_t serial_port_base;
26 /** Offset 0x0070**/ uint32_t serial_port_use_mmio;
27 /** Offset 0x0074**/ uint32_t serial_port_baudrate;
28 /** Offset 0x0078**/ uint32_t serial_port_refclk;
29 /** Offset 0x007C**/ uint32_t serial_reserved;
[all …]
H A Dplatform_descriptors.h170 typedef struct __packed { struct
193 typedef struct __packed { argument
194 uint8_t engine_type; // See dxio_engine_type
195 uint8_t start_logical_lane; // Start lane of the pci device
196 uint8_t end_logical_lane; // End lane of the pci device
197 uint8_t gpio_group_id; // GPIO number used as reset
198 uint32_t port_present :1; // Should be TRUE if train link
199 uint32_t reserved_3 :7;
200 uint32_t device_number :5; // Desired root port device number
201 uint32_t function_number :3; // Desired root port function number
[all …]
H A DFspsUpd.h12 typedef struct __packed { struct
21 typedef struct __packed { argument
22 /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
23 /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig;
/aosp_15_r20/external/coreboot/src/vendorcode/amd/fsp/phoenix/
H A DFspmUpd.h20 typedef struct __packed { struct
21 /** Offset 0x0040**/ uint32_t bert_size;
22 /** Offset 0x0044**/ uint32_t tseg_size;
23 /** Offset 0x0048**/ uint32_t pci_express_base_addr;
24 /** Offset 0x004C**/ uint8_t misc_reserved[32];
25 /** Offset 0x006C**/ uint32_t serial_port_base;
26 /** Offset 0x0070**/ uint32_t serial_port_use_mmio;
27 /** Offset 0x0074**/ uint32_t serial_port_baudrate;
28 /** Offset 0x0078**/ uint32_t serial_port_refclk;
29 /** Offset 0x007C**/ uint32_t serial_reserved;
[all …]
H A Dplatform_descriptors.h210 typedef struct __packed { struct
226 typedef struct __packed { argument
227 uint8_t engine_type; // See dxio_engine_type
228 uint8_t start_lane; // Start lane of the pci device
229 uint8_t end_lane; // End lane of the pci device
230 uint8_t gpio_group_id; // GPIO number used as reset
231 uint32_t port_present :1; // Should be TRUE if train link
233 uint32_t device_number :5; // Desired root port device number
234 uint32_t function_number :3; // Desired root port function number
235 uint32_t link_speed_capability :2; // See dxio_link_speed_cap
[all …]
H A DFspsUpd.h12 typedef struct __packed { struct
21 typedef struct __packed { argument
22 /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
23 /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig;
/aosp_15_r20/external/coreboot/src/vendorcode/amd/fsp/picasso/
H A DFspmUpd.h14 typedef struct __packed { struct
15 /** Offset 0x0040**/ uint32_t pci_express_base_addr;
16 /** Offset 0x0044**/ uint32_t serial_port_base;
17 /** Offset 0x0048**/ uint32_t serial_port_use_mmio;
18 /** Offset 0x004C**/ uint32_t serial_port_stride;
19 /** Offset 0x0050**/ uint32_t serial_port_baudrate;
20 /** Offset 0x0054**/ uint32_t serial_port_refclk;
21 /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA;
22 /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA;
23 /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA;
[all …]
H A DFspsUpd.h17 typedef struct __packed { struct
18 /** Offset 0x0020**/ uint32_t emmc0_mode;
19 /** Offset 0x0024**/ uint16_t emmc0_init_khz_preset;
20 /** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength;
21 /** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength;
22 /** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength;
23 /** Offset 0x0029**/ uint8_t unused0[7];
24 …* Offset 0x0030**/ uint8_t dxio_descriptor[FSPS_UPD_DXIO_DESCRIPTOR_COUNT][16];
25 /** Offset 0x00B0**/ uint8_t unused1[16];
26 /** Offset 0x00C0**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT];
[all …]
H A Dplatform_descriptors.h124 typedef struct __packed { struct
125 uint8_t connector_type;
126 uint8_t aux_index;
127 uint8_t hdp_index;
128 uint8_t reserved;
171 typedef struct __packed { struct
172 uint8_t engine_type; // See dxio_engine_type
173 uint8_t start_logical_lane; // Start lane of the pci device
174 uint8_t end_logical_lane; // End lane of the pci device
175 uint8_t gpio_group_id; // Currently unused by FSP
[all …]
H A Dfsp_h_c99.h30 typedef struct __packed { struct
39 typedef struct __packed { argument
40 uint8_t Revision;
41 uint8_t Reserved[3];
43 uint32_t NvsBufferPtr;
45 uint32_t StackBase;
46 uint32_t StackSize;
47 uint32_t BootLoaderTolumSize;
48 uint32_t BootMode;
49 uint8_t Reserved1[8];
/aosp_15_r20/external/coreboot/src/southbridge/intel/lynxpoint/
H A Dme.h54 struct __packed { struct
55 u32 working_state: 4;
56 u32 mfg_mode: 1;
57 u32 fpt_bad: 1;
58 u32 operation_state: 3;
59 u32 fw_init_complete: 1;
60 u32 ft_bup_ld_flr: 1;
61 u32 update_in_progress: 1;
62 u32 error_code: 4;
63 u32 operation_mode: 4;
[all …]
/aosp_15_r20/external/coreboot/src/mainboard/prodrive/hermes/
H A Deeprom.h8 struct __packed { struct
9 char name[50];
10 char manufacturer[50];
11 uint8_t ranks;
12 uint8_t controller_id;
13 uint8_t data_width_bits;
14 uint8_t bus_width_bits;
15 uint32_t capacity_mib;
16 uint32_t max_tdp_milliwatts;
27 struct __packed { struct
[all …]
/aosp_15_r20/external/coreboot/src/soc/qualcomm/ipq806x/
H A Dlcc.c18 typedef struct __packed { struct
22 typedef struct __packed { struct
32 typedef struct __packed { argument
39 typedef struct __packed { argument
45 typedef struct __packed { argument
46 uint32_t pri;
47 uint32_t sec;
/aosp_15_r20/external/coreboot/src/soc/qualcomm/ipq40xx/
H A Dlcc.c18 typedef struct __packed { struct
22 typedef struct __packed { struct
32 typedef struct __packed { argument
39 typedef struct __packed { argument
45 typedef struct __packed { argument
46 uint32_t pri;
47 uint32_t sec;
/aosp_15_r20/external/coreboot/src/vendorcode/amd/fsp/common/
H A Dfsp_h_c99.h30 typedef struct __packed { struct
40 typedef struct __packed { argument
41 uint8_t Revision;
42 uint8_t Reserved[3];
44 uint32_t NvsBufferPtr;
46 uint32_t StackBase;
47 uint32_t StackSize;
48 uint32_t BootLoaderTolumSize;
49 uint32_t BootMode;
50 uint8_t Reserved1[8];
/aosp_15_r20/external/trusty/arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/
Dti_sci_protocol.h74 } __packed; variable
84 } __packed; variable
111 } __packed; variable
125 } __packed; variable
149 } __packed; variable
186 } __packed; variable
199 } __packed; variable
223 } __packed; variable
242 } __packed; variable
289 } __packed; variable
[all …]
/aosp_15_r20/external/arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/
H A Dti_sci_protocol.h70 } __packed; variable
93 } __packed; variable
107 } __packed; variable
144 } __packed; variable
157 } __packed; variable
181 } __packed; variable
200 } __packed; variable
247 } __packed; variable
264 } __packed; variable
283 } __packed; variable
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