1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpi_gnvs.h>
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <device/pci_ids.h>
8 #include <device/pci_ops.h>
9 #include <device/mmio.h>
10 #include <soc/adsp.h>
11 #include <soc/device_nvs.h>
12 #include <soc/pch.h>
13 #include <soc/rcba.h>
14 #include <soc/intel/broadwell/pch/chip.h>
15 #include <southbridge/intel/lynxpoint/iobp.h>
16
adsp_init(struct device * dev)17 static void adsp_init(struct device *dev)
18 {
19 const struct soc_intel_broadwell_pch_config *config = config_of(dev);
20 struct resource *bar0, *bar1;
21 u32 tmp32;
22
23 /* Ensure memory and bus master are enabled */
24 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
25
26 /* Find BAR0 and BAR1 */
27 bar0 = probe_resource(dev, PCI_BASE_ADDRESS_0);
28 if (!bar0)
29 return;
30 bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1);
31 if (!bar1)
32 return;
33
34 /*
35 * Set LTR value in DSP shim LTR control register to 3ms
36 * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
37 */
38 tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
39 write32(res2mmio(bar0, tmp32 + ADSP_SHIM_LTRC, 0),
40 ADSP_SHIM_LTRC_VALUE);
41
42 /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
43 pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
44
45 /* Program ADSP IOBP VDLDAT1 to 0x040100 */
46 pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE);
47
48 /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
49 tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
50 if (pch_is_wpt()) {
51 if (config->adsp_d3_pg_enable) {
52 tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
53 if (config->adsp_sram_pg_enable)
54 tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
55 else
56 tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
57 } else {
58 tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
59 }
60 } else {
61 if (config->adsp_d3_pg_enable) {
62 tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
63 if (config->adsp_sram_pg_enable)
64 tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
65 else
66 tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
67 } else {
68 tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
69 }
70 }
71 pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
72
73 /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */
74 RCBA32_OR(0x3350, (1 << 10));
75
76 /* Set DSP IOBP PMCTL 0x1e0=0x3f */
77 pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
78
79 if (config->sio_acpi_mode) {
80 struct device_nvs *dev_nvs = acpi_get_device_nvs();
81
82 /* Configure for ACPI mode */
83 printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n");
84
85 /* Save BAR0 and BAR1 to ACPI NVS */
86 dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base;
87 dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base;
88 dev_nvs->enable[SIO_NVS_ADSP] = 1;
89
90 /* Set PCI Config Disable Bit */
91 pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD);
92
93 /* Set interrupt de-assert/assert opcode override to IRQ3 */
94 pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3);
95
96 /* Enable IRQ3 in RCBA */
97 RCBA32_OR(ACPIIRQEN, ADSP_ACPI_IRQEN);
98
99 /* Set ACPI Interrupt Enable Bit */
100 pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD,
101 ADSP_PCICFGCTL_ACPIIE);
102
103 /* Put ADSP in D3hot */
104 tmp32 = read32(res2mmio(bar1, PCH_PCS, 0));
105 tmp32 |= PCH_PCS_PS_D3HOT;
106 write32(res2mmio(bar1, PCH_PCS, 0), tmp32);
107 } else {
108 printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");
109
110 /* Configure for PCI mode */
111 pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
112
113 /* Clear ACPI Interrupt Enable Bit */
114 pch_iobp_update(ADSP_IOBP_PCICFGCTL,
115 ~(ADSP_PCICFGCTL_SPCBAD | ADSP_PCICFGCTL_ACPIIE), 0);
116 }
117 }
118
119 static struct device_operations adsp_ops = {
120 .read_resources = pci_dev_read_resources,
121 .set_resources = pci_dev_set_resources,
122 .enable_resources = pci_dev_enable_resources,
123 .init = adsp_init,
124 .ops_pci = &pci_dev_ops_pci,
125 };
126
127 static const unsigned short pci_device_ids[] = {
128 0x9c36, /* LynxPoint */
129 0x9cb6, /* WildcatPoint */
130 0
131 };
132
133 static const struct pci_driver pch_adsp __pci_driver = {
134 .ops = &adsp_ops,
135 .vendor = PCI_VID_INTEL,
136 .devices = pci_device_ids,
137 };
138