1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef __ARCH_CPU_H__
4 #define __ARCH_CPU_H__
5
6 #include <stdint.h>
7 #include <device/device.h>
8
cpu_relax(void)9 static inline void cpu_relax(void) { }
10
11 #define asmlinkage
12
13 struct cpu_driver {
14 struct device_operations *ops;
15 const struct cpu_device_id *id_table;
16 };
17
18 struct cpuinfo_arm {
19 uint8_t arm; /* CPU family */
20 uint8_t arm_vendor; /* CPU vendor */
21 uint8_t arm_model;
22 };
23
24 /* Primitives for CPU and MP cores. */
25
26 /* read Main Id register (MIDR) */
read_midr(void)27 static inline uint32_t read_midr(void)
28 {
29 uint32_t value;
30 asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r"(value));
31 return value;
32 }
33
34 /* read Multiprocessor Affinity Register (MPIDR) */
read_mpidr(void)35 static inline uint32_t read_mpidr(void)
36 {
37 uint32_t value;
38 asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r"(value));
39 return value;
40 }
41
42 /* read Auxiliary Control Register (ACTLR) */
read_actlr(void)43 static inline uint32_t read_actlr(void)
44 {
45 uint32_t val = 0;
46 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val));
47 return val;
48 }
49
50 /* write Auxiliary Control Register (ACTLR) */
write_actlr(uint32_t val)51 static inline void write_actlr(uint32_t val)
52 {
53 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val));
54 }
55
56 /* wait for interrupt. */
wfi(void)57 static inline void wfi(void)
58 {
59 asm volatile ("wfi" : : : "memory");
60 }
61
62 /* wait for event. */
wfe(void)63 static inline void wfe(void)
64 {
65 asm volatile ("wfe");
66 }
67
68 /* set event (to bring up cores in WFE state). */
sev(void)69 static inline void sev(void)
70 {
71 asm volatile ("sev");
72 }
73
74 /* puts CPU into System mode and disable interrupts. */
set_system_mode(void)75 static inline void set_system_mode(void)
76 {
77 asm volatile("msr cpsr_c, %0" :: "r"(0x1f | 0xc0));
78 }
79
80 #endif /* __ARCH_CPU_H__ */
81