1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8173_SPM_H__ 4 #define __SOC_MEDIATEK_MT8173_SPM_H__ 5 6 #include <soc/addressmap.h> 7 #include <soc/mtcmos.h> 8 #include <stddef.h> 9 10 enum { 11 SPM_PROJECT_CODE = 0xb16 12 }; 13 14 enum { 15 DISP_PWR_STA_MASK = 0x1 << 3, 16 DISP_SRAM_PDN_MASK = 0xf << 8, 17 DISP_SRAM_ACK_MASK = 0x1 << 12, 18 AUDIO_PWR_STA_MASK = 0x1 << 24, 19 AUDIO_SRAM_PDN_MASK = 0xf << 8, 20 AUDIO_SRAM_ACK_MASK = 0xf << 12, 21 }; 22 23 struct mtk_spm_regs { 24 u32 poweron_config_set; 25 u32 reserved1[3]; 26 u32 power_on_val0; /* 0x010 */ 27 u32 power_on_val1; 28 u32 reserved2[58]; 29 u32 clk_settle; /* 0x100 */ 30 u32 reserved3[63]; 31 u32 ca7_cpu0_pwr_con; /* 0x200 */ 32 u32 ca7_dbg_pwr_con; 33 u32 ca7_cputop_pwr_con; 34 u32 reserved4; 35 u32 vde_pwr_con; /* 0x210 */ 36 u32 mfg_pwr_con; 37 u32 ca7_cpu1_pwr_con; /* 0x218 */ 38 u32 ca7_cpu2_pwr_con; 39 u32 ca7_cpu3_pwr_con; /* 0x220 */ 40 u32 reserved5[3]; 41 u32 ven_pwr_con; /* 0x230 */ 42 u32 ifr_pwr_con; 43 u32 isp_pwr_con; 44 u32 dis_pwr_con; 45 u32 dpy_pwr_con; /* 0x240 */ 46 u32 ca7_cputop_l2_pdn; /* 0x244 */ 47 u32 ca7_cputop_l2_sleep; 48 u32 reserved6[4]; 49 struct { /* 0x25c */ 50 u32 l1_pdn; 51 u32 reserved; 52 } ca7_cpu[4]; 53 u32 gcpu_sram_con; /* 0x27c */ 54 u32 dpy2_pwr_con; /* 0x280 */ 55 u32 md_pwr_con; 56 u32 reserved11[2]; 57 u32 mcu_pwr_con; /* 0x290 */ 58 u32 ifr_sramrom_con; 59 u32 mjc_pwr_con; 60 u32 audio_pwr_con; 61 u32 ca15_cpu_pwr_con[4]; /* 0x2a0 */ 62 u32 ca15_cputop_pwr_con; /* 0x2b0 */ 63 u32 ca15_l1_pwr_con; /* 0x2b4 */ 64 u32 ca15_l2_pwr_con; /* 0x2b8 */ 65 u32 reserved12; 66 u32 mfg_2d_pwr_con; /* 0x2c0 */ 67 u32 mfg_async_pwr_con; 68 u32 vpu_sram_con; 69 u32 reserved13[17]; 70 u32 pcm_con0; /* 0x310 */ 71 u32 pcm_con1; 72 u32 pcm_im_ptr; 73 u32 pcm_im_len; 74 u32 pcm_reg_data_ini; /* 0x320 */ 75 u32 reserved14[7]; 76 u32 pcm_event_vector0; /* 0x340 */ 77 u32 pcm_event_vector1; 78 u32 pcm_event_vector2; 79 u32 pcm_event_vector3; 80 u32 reserved15; 81 u32 pcm_mas_pause_mask; /* 0x354 */ 82 u32 pcm_pwr_io_en; 83 u32 pcm_timer_val; 84 u32 pcm_timer_out; 85 u32 reserved16[7]; 86 u32 pcm_reg_data[16]; /* 0x380 */ 87 u32 pcm_event_reg_sta; 88 u32 pcm_fsm_sta; 89 u32 pcm_im_host_rw_ptr; 90 u32 pcm_im_host_rw_dat; 91 u32 pcm_event_vector4; 92 u32 pcm_event_vector5; 93 u32 pcm_event_vector6; 94 u32 pcm_event_vector7; 95 u32 pcm_sw_int_set; 96 u32 pcm_sw_int_clear; 97 u32 reserved17[6]; 98 u32 clk_con; /* 0x400 */ 99 u32 sleep_dual_vcore_pwr_con; /* 0x404 */ 100 u32 sleep_ptpod2_con; 101 u32 reserved18[125]; 102 u32 apmcu_pwrctl; /* 0x600 */ 103 u32 ap_dvfs_con_set; 104 u32 ap_stanby_con; 105 u32 pwr_status; /* 0x60c */ 106 u32 pwr_status_2nd; /* 0x610 */ 107 u32 ap_bsi_req; 108 u8 reserved19[0x720 - 0x618]; 109 u32 sleep_timer_sta; /* 0x720 */ 110 u32 reserved20[15]; 111 u32 sleep_twam_con; /* 0x760 */ 112 u32 sleep_twam_status0; 113 u32 sleep_twam_status1; 114 u32 sleep_twam_status2; 115 u32 sleep_twam_status3; /* 0x770 */ 116 u32 reserved21[39]; 117 u32 sleep_wakeup_event_mask; /* 0x810 */ 118 u32 sleep_cpu_wakeup_event; 119 u32 sleep_md32_wakeup_event_mask; 120 u32 reserved22[2]; 121 u32 pcm_wdt_timer_val; /* 0x824 */ 122 u32 pcm_wdt_timer_out; 123 u32 reserved23; 124 u32 pcm_md32_mailbox; /* 0x830 */ 125 u32 pcm_md32_irq; 126 u32 reserved24[50]; 127 u32 sleep_isr_mask; /* 0x900 */ 128 u32 sleep_isr_status; 129 u32 reserved25[2]; 130 u32 sleep_isr_raw_sta; /* 0x910 */ 131 u32 sleep_md32_isr_raw_sta; 132 u32 sleep_wakeup_misc; 133 u32 sleep_bus_protect_rdy; 134 u32 sleep_subsys_idle_sta; /* 0x920 */ 135 u8 reserved26[0xb00 - 0x924]; 136 u32 pcm_reserve; /* 0xb00 */ 137 u32 pcm_reserve2; 138 u32 pcm_flags; 139 u32 pcm_src_req; 140 u32 reserved27[4]; 141 u32 pcm_debug_con; /* 0xb20 */ 142 u32 reserved28[3]; 143 u32 ca7_cpu_irq_mask[4]; /* 0xb30 */ 144 u32 ca15_cpu_irq_mask[4]; 145 u32 reserved29[4]; 146 u32 pcm_pasr_dpd[4]; /* 0xb60 */ 147 u8 reserved30[0xf00 - 0xb70]; 148 u32 sleep_ca7_wfi_en[4]; /* 0xf00 */ 149 u32 sleep_ca15_wfi_en[4]; 150 }; 151 152 check_member(mtk_spm_regs, sleep_ca15_wfi_en[3], 0xf1c); 153 154 static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; 155 156 static const struct power_domain_data disp[] = { 157 { 158 .pwr_con = &mtk_spm->dis_pwr_con, 159 .pwr_sta_mask = DISP_PWR_STA_MASK, 160 .sram_pdn_mask = DISP_SRAM_PDN_MASK, 161 .sram_ack_mask = DISP_SRAM_ACK_MASK, 162 }, 163 }; 164 165 static const struct power_domain_data audio[] = { 166 { 167 .pwr_con = &mtk_spm->audio_pwr_con, 168 .pwr_sta_mask = AUDIO_PWR_STA_MASK, 169 .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, 170 .sram_ack_mask = AUDIO_SRAM_ACK_MASK, 171 }, 172 }; 173 174 #endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */ 175