1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/mmu.h>
4 #include <assert.h>
5 #include <soc/addressmap.h>
6 #include <soc/mmu_operations.h>
7 #include <symbols.h>
8 #include <types.h>
9
tegra210_mmu_config(void)10 static void tegra210_mmu_config(void)
11 {
12 uintptr_t start, end;
13 const unsigned long devmem = MA_DEV | MA_S | MA_RW;
14 const unsigned long cachedmem = MA_MEM | MA_NS | MA_RW;
15 const unsigned long secure_mem = MA_MEM | MA_S | MA_RW;
16 uintptr_t tz_base_mib;
17 size_t tz_size_mib;
18
19 print_carveouts();
20
21 memory_in_range_below_4gb(&start,&end);
22
23 /* Device memory below DRAM */
24 mmu_config_range((void *)TEGRA_ARM_LOWEST_PERIPH, start * MiB, devmem);
25
26 /* DRAM */
27 mmu_config_range((void *)(start * MiB), (end-start) * MiB, cachedmem);
28
29 memory_in_range_above_4gb(&start,&end);
30
31 mmu_config_range((void *)(start * MiB), (end-start) * MiB, cachedmem);
32
33 /* SRAM */
34 mmu_config_range(_sram, REGION_SIZE(sram), cachedmem);
35
36 /* Add TZ carveout. */
37 carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
38
39 mmu_config_range((void *)(tz_base_mib * MiB),
40 tz_size_mib * MiB, secure_mem);
41 }
42
tegra210_mmu_init(void)43 void tegra210_mmu_init(void)
44 {
45 uintptr_t tz_base_mib;
46 size_t tz_size_mib;
47
48 mmu_init();
49 tegra210_mmu_config();
50 /*
51 * Page tables are at the end of the trust zone region, but we should
52 * double-check that memlayout and addressmap.c are in sync.
53 *
54 * TZDRAM layout is as follows:
55 *
56 * +--------------------------+ <----+DRAM_END
57 * | |
58 * | |
59 * | |
60 * +--------------------------+ <----+0x100000000
61 * | |
62 * | coreboot page tables |
63 * +--------------------------+
64 * | |
65 * | BL32 |
66 * +--------------------------+
67 * | |
68 * | BL31 |
69 * +--------------------------+ <----+TZDRAM_BASE
70 * | |
71 * | |
72 * | |
73 * | |
74 * +--------------------------+ <----+DRAM_BASE
75 *
76 */
77 carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
78 assert((uintptr_t)_ttb + REGION_SIZE(ttb) == (tz_base_mib + tz_size_mib)
79 * MiB && REGION_SIZE(ttb) <= tz_size_mib * MiB);
80
81 mmu_enable();
82 }
83