1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <soc/dramc_param.h>
5 #include <soc/dramc_pi_api.h>
6 #include <soc/dramc_register.h>
7 #include <soc/emi.h>
8 #include <soc/infracfg.h>
9 #include <soc/mt6358.h>
10 #include <soc/spm.h>
11
12 static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = {
13 [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200,
14 [DRAM_DFS_SHUFFLE_2] = LP4X_DDR2400,
15 [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
16 };
17
18 static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = {
19 [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3600,
20 [DRAM_DFS_SHUFFLE_2] = LP4X_DDR3200,
21 [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
22 };
23
24 static const u32 frequency_table[LP4X_DDRFREQ_MAX] = {
25 [LP4X_DDR1600] = 1600,
26 [LP4X_DDR2400] = 2400,
27 [LP4X_DDR3200] = 3200,
28 [LP4X_DDR3600] = 3600,
29 };
30
31 static const u32 vcore_lp4x[LP4X_DDRFREQ_MAX] = {
32 [LP4X_DDR1600] = 725000,
33 [LP4X_DDR2400] = 725000,
34 [LP4X_DDR3200] = 762500,
35 [LP4X_DDR3600] = 800000,
36 };
37
38 struct emi_regs *emi_regs = (void *)EMI_BASE;
39 const u8 phy_mapping[CHANNEL_MAX][16] = {
40 [CHANNEL_A] = {
41 1, 0, 2, 4, 3, 7, 5, 6,
42 9, 8, 12, 11, 10, 15, 13, 14
43 },
44
45 [CHANNEL_B] = {
46 0, 1, 5, 6, 3, 7, 4, 2,
47 9, 8, 12, 15, 11, 14, 13, 10
48 }
49 };
50
51 struct optimize_ac_time {
52 u8 trfc;
53 u8 trfrc_05t;
54 u8 trfc_pb;
55 u8 trfrc_pb05t;
56 u16 tx_ref_cnt;
57 };
58
dramc_set_broadcast(u32 onoff)59 void dramc_set_broadcast(u32 onoff)
60 {
61 write32(&mt8183_infracfg->dramc_wbr, onoff);
62 }
63
dramc_get_broadcast(void)64 u32 dramc_get_broadcast(void)
65 {
66 return read32(&mt8183_infracfg->dramc_wbr);
67 }
68
get_shu_freq(u8 shu)69 u32 get_shu_freq(u8 shu)
70 {
71 const u8 *freq_tbl = CONFIG(MT8183_DRAM_EMCP) ?
72 freq_shuffle_emcp : freq_shuffle;
73 return frequency_table[freq_tbl[shu]];
74 }
75
get_ch_rank_size(u8 chn,u8 rank)76 static u64 get_ch_rank_size(u8 chn, u8 rank)
77 {
78 u32 shift_for_16bit = 1;
79 u32 col_bit, row_bit;
80 u32 emi_cona = read32(&emi_regs->cona);
81
82 shift_for_16bit = (emi_cona & 0x2) ? 0 : 1;
83
84 col_bit = ((emi_cona >> (chn * 16 + rank * 2 + 4)) & 0x03) + 9;
85 row_bit = ((((emi_cona >> (24 - chn * 20 + rank)) & 0x01) << 2) +
86 ((emi_cona >> (12 + chn * 16 + rank * 2)) & 0x03)) + 13;
87
88 /* Data width (bytes) * 8 banks */
89 return ((u64)(1 << (row_bit + col_bit))) *
90 ((u64)(4 >> shift_for_16bit) * 8);
91 }
92
dramc_get_rank_size(u64 * dram_rank_size)93 void dramc_get_rank_size(u64 *dram_rank_size)
94 {
95 u64 ch0_rank0_size, ch0_rank1_size, ch1_rank0_size, ch1_rank1_size;
96 u64 ch_rank0_size = 0, ch_rank1_size = 0;
97 u32 emi_cona = read32(&emi_regs->cona);
98 u32 emi_conh = read32(&emi_regs->conh);
99
100 dram_rank_size[0] = 0;
101 dram_rank_size[1] = 0;
102
103 ch0_rank0_size = (emi_conh >> 16) & 0xf;
104 ch0_rank1_size = (emi_conh >> 20) & 0xf;
105 ch1_rank0_size = (emi_conh >> 24) & 0xf;
106 ch1_rank1_size = (emi_conh >> 28) & 0xf;
107
108 /* CH0 EMI */
109 if (ch0_rank0_size == 0)
110 ch_rank0_size = get_ch_rank_size(CHANNEL_A, RANK_0);
111 else
112 ch_rank0_size = (ch0_rank0_size * 256 << 20);
113
114 /* Dual rank enable */
115 if ((emi_cona & (1 << 17)) != 0) {
116 if (ch0_rank1_size == 0)
117 ch_rank1_size = get_ch_rank_size(CHANNEL_A, RANK_1);
118 else
119 ch_rank1_size = (ch0_rank1_size * 256 << 20);
120 }
121
122 dram_rank_size[0] = ch_rank0_size;
123 dram_rank_size[1] = ch_rank1_size;
124
125 if (ch1_rank0_size == 0)
126 ch_rank0_size = get_ch_rank_size(CHANNEL_B, RANK_0);
127 else
128 ch_rank0_size = (ch1_rank0_size * 256 << 20);
129
130 if ((emi_cona & (1 << 16)) != 0) {
131 if (ch1_rank1_size == 0)
132 ch_rank1_size = get_ch_rank_size(CHANNEL_B, RANK_1);
133 else
134 ch_rank1_size = (ch1_rank1_size * 256 << 20);
135 }
136 dram_rank_size[0] += ch_rank0_size;
137 dram_rank_size[1] += ch_rank1_size;
138 }
139
sdram_size(void)140 size_t sdram_size(void)
141 {
142 size_t dram_size = 0;
143 u64 rank_size[RANK_MAX];
144
145 dramc_get_rank_size(rank_size);
146
147 for (int i = 0; i < RANK_MAX; i++)
148 dram_size += rank_size[i];
149
150 return dram_size;
151 }
152
set_rank_info_to_conf(const struct sdram_params * params)153 static void set_rank_info_to_conf(const struct sdram_params *params)
154 {
155 bool is_dual_rank = (params->emi_cona_val & (0x1 << 17)) != 0;
156 clrsetbits32(&ch[0].ao.rstmask, 0x1 << 12,
157 (is_dual_rank ? 0 : 1) << 12);
158 }
159
cbt_mrr_pinmux_mapping(void)160 void cbt_mrr_pinmux_mapping(void)
161 {
162 for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
163 const u8 *map = phy_mapping[chn];
164 write32(&ch[chn].ao.mrr_bit_mux1,
165 (map[8] << 0) | (map[9] << 8) |
166 (map[10] << 16) | (map[11] << 24));
167
168 write32(&ch[chn].ao.mrr_bit_mux2,
169 (map[12] << 0) | (map[13] << 8));
170 }
171 }
172
set_mrr_pinmux_mapping(void)173 void set_mrr_pinmux_mapping(void)
174 {
175 for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
176 const u8 *map = phy_mapping[chn];
177 write32(&ch[chn].ao.mrr_bit_mux1,
178 (map[0] << 0) | (map[1] << 8) |
179 (map[2] << 16) | (map[3] << 24));
180
181 write32(&ch[chn].ao.mrr_bit_mux2,
182 (map[4] << 0) | (map[5] << 8) |
183 (map[6] << 16) | (map[7] << 24));
184
185 write32(&ch[chn].ao.mrr_bit_mux3,
186 (map[8] << 0) | (map[9] << 8) |
187 (map[10] << 16) | (map[11] << 24));
188
189 write32(&ch[chn].ao.mrr_bit_mux4,
190 (map[12] << 0) | (map[13] << 8) |
191 (map[14] << 16) | (map[15] << 24));
192 }
193 }
194
global_option_init(const struct sdram_params * params)195 static void global_option_init(const struct sdram_params *params)
196 {
197 set_rank_info_to_conf(params);
198 set_mrr_pinmux_mapping();
199 }
200
set_vcore_voltage(u8 freq_group)201 static void set_vcore_voltage(u8 freq_group)
202 {
203 const u32 vcore = vcore_lp4x[freq_group];
204 dramc_dbg("Set DRAM voltage (freq %d): vcore = %u\n",
205 frequency_table[freq_group], vcore);
206 pmic_set_vcore_vol(vcore);
207 }
208
set_vdram1_vddq_voltage(void)209 static void set_vdram1_vddq_voltage(void)
210 {
211 const u32 vdram1 = 1125000;
212 const u32 vddq = 600000;
213 dramc_dbg("Set DRAM voltage: vdram1 = %u, vddq = %u\n",
214 vdram1, vddq);
215 pmic_set_vdram1_vol(vdram1);
216 pmic_set_vddq_vol(vddq);
217 }
218
emi_esl_setting1(void)219 static void emi_esl_setting1(void)
220 {
221 dramc_set_broadcast(DRAMC_BROADCAST_ON);
222
223 write32(&emi_regs->cona, 0xa053a154);
224 write32(&emi_regs->conb, 0x17283544);
225 write32(&emi_regs->conc, 0x0a1a0b1a);
226 write32(&emi_regs->cond, 0x3657587a);
227 write32(&emi_regs->cone, 0x80400148);
228 write32(&emi_regs->conf, 0x00000000);
229 write32(&emi_regs->cong, 0x2b2b2a38);
230 write32(&emi_regs->conh, 0x00000000);
231 write32(&emi_regs->coni, 0x00008803);
232 write32(&emi_regs->conm, 0x000001ff);
233 write32(&emi_regs->conn, 0x00000000);
234 write32(&emi_regs->mdct, 0x11338c17);
235 write32(&emi_regs->mdct_2nd, 0x00001112);
236 write32(&emi_regs->iocl, 0xa8a8a8a8);
237 write32(&emi_regs->iocl_2nd, 0x25252525);
238 write32(&emi_regs->iocm, 0xa8a8a8a8);
239 write32(&emi_regs->iocm_2nd, 0x25252525);
240 write32(&emi_regs->testb, 0x00060037);
241 write32(&emi_regs->testc, 0x38460000);
242 write32(&emi_regs->testd, 0x00000000);
243 write32(&emi_regs->arba, 0x4020524f);
244 write32(&emi_regs->arbb, 0x4020504f);
245 write32(&emi_regs->arbc, 0xa0a050c6);
246 write32(&emi_regs->arbd, 0x000070cc);
247 write32(&emi_regs->arbe, 0x40406045);
248 write32(&emi_regs->arbf, 0xa0a070d5);
249 write32(&emi_regs->arbg, 0xa0a0504f);
250 write32(&emi_regs->arbh, 0xa0a0504f);
251 write32(&emi_regs->arbi, 0x00007108);
252 write32(&emi_regs->arbi_2nd, 0x00007108);
253 write32(&emi_regs->slct, 0x0001ff00);
254
255 write32(&ch[0].emi.chn_cona, 0x0400a051);
256 write32(&ch[0].emi.chn_conb, 0x00ff2048);
257 write32(&ch[0].emi.chn_conc, 0x00000000);
258 write32(&ch[0].emi.chn_mdct, 0x88008817);
259 write32(&ch[0].emi.chn_testb, 0x00030027);
260 write32(&ch[0].emi.chn_testc, 0x38460002);
261 write32(&ch[0].emi.chn_testd, 0x00000000);
262 write32(&ch[0].emi.chn_md_pre_mask, 0x00000f00);
263 write32(&ch[0].emi.chn_md_pre_mask_shf, 0x00000b00);
264 write32(&ch[0].emi.chn_arbi, 0x20406188);
265 write32(&ch[0].emi.chn_arbi_2nd, 0x20406188);
266 write32(&ch[0].emi.chn_arbj, 0x3719595e);
267 write32(&ch[0].emi.chn_arbj_2nd, 0x3719595e);
268 write32(&ch[0].emi.chn_arbk, 0x64f3fc79);
269 write32(&ch[0].emi.chn_arbk_2nd, 0x64f3fc79);
270 write32(&ch[0].emi.chn_slct, 0x00080888);
271 write32(&ch[0].emi.chn_arb_ref, 0x82410222);
272 write32(&ch[0].emi.chn_emi_shf0, 0x8a228c17);
273 write32(&ch[0].emi.chn_rkarb0, 0x0006002f);
274 write32(&ch[0].emi.chn_rkarb1, 0x01010101);
275 write32(&ch[0].emi.chn_rkarb2, 0x10100820);
276 write32(&ch[0].emi.chn_eco3, 0x00000000);
277
278 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
279 }
280
emi_esl_setting2(void)281 static void emi_esl_setting2(void)
282 {
283 dramc_set_broadcast(DRAMC_BROADCAST_ON);
284
285 write32(&ch[0].emi.chn_conc, 0x01);
286 write32(&emi_regs->conm, 0x05ff);
287
288 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
289 }
290
emi_init(const struct sdram_params * params)291 static void emi_init(const struct sdram_params *params)
292 {
293 emi_esl_setting1();
294
295 write32(&emi_regs->cona, params->emi_cona_val);
296 write32(&emi_regs->conf, params->emi_conf_val);
297 write32(&emi_regs->conh, params->emi_conh_val);
298
299 for (size_t chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) {
300 write32(&ch[chn].emi.chn_cona, params->chn_emi_cona_val[chn]);
301 write32(&ch[chn].emi.chn_conc, 0);
302 }
303 }
304
emi_init2(const struct sdram_params * params)305 static void emi_init2(const struct sdram_params *params)
306 {
307 emi_esl_setting2();
308
309 setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4);
310 setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4);
311 if (CONFIG(MT8183_DRAM_EMCP))
312 write32(&emi_regs->bwct0, 0x0d000705);
313 else
314 write32(&emi_regs->bwct0, 0x0a000705);
315 write32(&emi_regs->bwct0_3rd, 0x0);
316
317 /* EMI QoS 0.5 */
318 write32(&emi_regs->bwct0_2nd, 0x00030023);
319 write32(&emi_regs->bwct0_4th, 0x00c00023);
320 write32(&emi_regs->bwct0_5th, 0x00240023);
321 }
322
dramc_init_pre_settings(void)323 static void dramc_init_pre_settings(void)
324 {
325 clrsetbits32(&ch[0].phy.ca_cmd[8],
326 (0x1 << 21) | (0x1 << 20) | (0x1 << 19) | (0x1 << 18) |
327 (0x1f << 8) | (0x1f << 0),
328 (0x1 << 19) | (0xa << 8) | (0xa << 0));
329
330 setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 12);
331 clrbits32(&ch[0].phy.misc_ctrl1, 0x1 << 13);
332 setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31);
333 }
334
dramc_ac_timing_optimize(u8 freq_group,u8 density)335 static void dramc_ac_timing_optimize(u8 freq_group, u8 density)
336 {
337 u8 rfcab_grp = 0;
338 u8 trfc, trfrc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt;
339 enum tRFCAB {
340 tRFCAB_130 = 0,
341 tRFCAB_180,
342 tRFCAB_280,
343 tRFCAB_380,
344 tRFCAB_NUM
345 };
346
347 const struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX][tRFCAB_NUM] = {
348 [LP4X_DDR1600] = {
349 [tRFCAB_130] = {.trfc = 14, .trfrc_05t = 0, .trfc_pb = 0,
350 .trfrc_pb05t = 0, .tx_ref_cnt = 32},
351 [tRFCAB_180] = {.trfc = 24, .trfrc_05t = 0, .trfc_pb = 6,
352 .trfrc_pb05t = 0, .tx_ref_cnt = 42},
353 [tRFCAB_280] = {.trfc = 44, .trfrc_05t = 0, .trfc_pb = 16,
354 .trfrc_pb05t = 0, .tx_ref_cnt = 62},
355 [tRFCAB_380] = {.trfc = 64, .trfrc_05t = 0, .trfc_pb = 26,
356 .trfrc_pb05t = 0, .tx_ref_cnt = 82}
357 },
358 [LP4X_DDR2400] = {
359 [tRFCAB_130] = {.trfc = 27, .trfrc_05t = 0, .trfc_pb = 6,
360 .trfrc_pb05t = 0, .tx_ref_cnt = 46},
361 [tRFCAB_180] = {.trfc = 42, .trfrc_05t = 0, .trfc_pb = 15,
362 .trfrc_pb05t = 0, .tx_ref_cnt = 61},
363 [tRFCAB_280] = {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30,
364 .trfrc_pb05t = 0, .tx_ref_cnt = 91},
365 [tRFCAB_380] = {.trfc = 102, .trfrc_05t = 0, .trfc_pb = 45,
366 .trfrc_pb05t = 0, .tx_ref_cnt = 121}
367 },
368 [LP4X_DDR3200] = {
369 [tRFCAB_130] = {.trfc = 40, .trfrc_05t = 0, .trfc_pb = 12,
370 .trfrc_pb05t = 0, .tx_ref_cnt = 59},
371 [tRFCAB_180] = {.trfc = 60, .trfrc_05t = 0, .trfc_pb = 24,
372 .trfrc_pb05t = 0, .tx_ref_cnt = 79},
373 [tRFCAB_280] = {.trfc = 100, .trfrc_05t = 0, .trfc_pb = 44,
374 .trfrc_pb05t = 0, .tx_ref_cnt = 119},
375 [tRFCAB_380] = {.trfc = 140, .trfrc_05t = 0, .trfc_pb = 64,
376 .trfrc_pb05t = 0, .tx_ref_cnt = 159}
377 },
378 [LP4X_DDR3600] = {
379 [tRFCAB_130] = {.trfc = 48, .trfrc_05t = 1, .trfc_pb = 16,
380 .trfrc_pb05t = 0, .tx_ref_cnt = 68},
381 [tRFCAB_180] = {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30,
382 .trfrc_pb05t = 0, .tx_ref_cnt = 92},
383 [tRFCAB_280] = {.trfc = 118, .trfrc_05t = 1, .trfc_pb = 53,
384 .trfrc_pb05t = 1, .tx_ref_cnt = 138},
385 [tRFCAB_380] = {.trfc = 165, .trfrc_05t = 0, .trfc_pb = 76,
386 .trfrc_pb05t = 1, .tx_ref_cnt = 185}
387 },
388 };
389
390 switch (density) {
391 case 0x0:
392 rfcab_grp = tRFCAB_130;
393 break;
394 case 0x1:
395 case 0x2:
396 rfcab_grp = tRFCAB_180;
397 break;
398 case 0x3:
399 case 0x4:
400 rfcab_grp = tRFCAB_280;
401 break;
402 case 0x5:
403 case 0x6:
404 rfcab_grp = tRFCAB_380;
405 break;
406 default:
407 dramc_err("density err!\n");
408 break;
409 }
410
411 const struct optimize_ac_time *ac_tim = &rf_cab_opt[freq_group][rfcab_grp];
412 trfc = ac_tim->trfc;
413 trfrc_05t = ac_tim->trfrc_05t;
414 trfc_pb = ac_tim->trfc_pb;
415 trfrc_pb05t = ac_tim->trfrc_pb05t;
416 tx_ref_cnt = ac_tim->tx_ref_cnt;
417 dramc_dbg("Density %d, trfc %u, trfrc_05t %d, tx_ref_cnt %d, trfc_pb %d, trfrc_pb05t %d\n",
418 density, trfc, trfrc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t);
419
420 for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
421 clrsetbits32(&ch[chn].ao.shu[0].actim[3],
422 0xff << 16, trfc << 16);
423 clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t,
424 0x1 << 2, trfrc_05t << 2);
425 clrsetbits32(&ch[chn].ao.shu[0].actim[4],
426 0x3ff << 0, tx_ref_cnt << 0);
427 clrsetbits32(&ch[chn].ao.shu[0].actim[3],
428 0xff << 0, trfc_pb << 0);
429 clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t,
430 0x1 << 1, trfrc_pb05t << 1);
431 }
432 }
433
spm_pinmux_setting(void)434 static void spm_pinmux_setting(void)
435 {
436 clrsetbits32(&mtk_spm->poweron_config_set,
437 (0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0));
438 clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
439 write32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff);
440 write32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff);
441 }
442
dfs_init_for_calibration(const struct sdram_params * params,u8 freq_group,struct dram_shared_data * shared)443 static void dfs_init_for_calibration(const struct sdram_params *params,
444 u8 freq_group,
445 struct dram_shared_data *shared)
446 {
447 dramc_init(params, freq_group, shared);
448 dramc_apply_config_before_calibration(freq_group, params->cbt_mode_extern);
449 }
450
init_dram(const struct sdram_params * params,u8 freq_group,struct dram_shared_data * shared)451 static void init_dram(const struct sdram_params *params, u8 freq_group,
452 struct dram_shared_data *shared)
453 {
454 global_option_init(params);
455 emi_init(params);
456
457 dramc_set_broadcast(DRAMC_BROADCAST_ON);
458 dramc_init_pre_settings();
459 spm_pinmux_setting();
460
461 dramc_sw_impedance_cal(params, ODT_OFF, &shared->impedance);
462 dramc_sw_impedance_cal(params, ODT_ON, &shared->impedance);
463
464 dramc_init(params, freq_group, shared);
465 dramc_apply_config_before_calibration(freq_group, params->cbt_mode_extern);
466 emi_init2(params);
467 }
468
enable_emi_dcm(void)469 void enable_emi_dcm(void)
470 {
471 clrbits32(&emi_regs->conm, 0xff << 24);
472 clrbits32(&emi_regs->conn, 0xff << 24);
473
474 for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
475 clrbits32(&ch[chn].emi.chn_conb, 0xff << 24);
476 }
477
478 struct shuffle_reg_addr {
479 u32 start;
480 u32 end;
481 };
482
483 #define AO_SHU_ADDR(s, e) \
484 { \
485 .start = offsetof(struct dramc_ao_regs_shu, s), \
486 .end = offsetof(struct dramc_ao_regs_shu, e), \
487 }
488
489 static const struct shuffle_reg_addr dramc_regs[] = {
490 AO_SHU_ADDR(actim, hwset_vrcg),
491 AO_SHU_ADDR(rk[0], rk[0].dqs2dq_cal5),
492 AO_SHU_ADDR(rk[1], rk[1].dqs2dq_cal5),
493 AO_SHU_ADDR(rk[2], rk[2].dqs2dq_cal5),
494 AO_SHU_ADDR(dqsg_retry, dqsg_retry),
495 };
496
497 #define PHY_SHU_ADDR(s, e) \
498 { \
499 .start = offsetof(struct ddrphy_ao_shu, s), \
500 .end = offsetof(struct ddrphy_ao_shu, e), \
501 }
502
503 static const struct shuffle_reg_addr phy_regs[] = {
504 PHY_SHU_ADDR(b[0], b[0].dll[1]),
505 PHY_SHU_ADDR(b[1], b[1].dll[1]),
506 PHY_SHU_ADDR(ca_cmd, ca_dll[1]),
507 PHY_SHU_ADDR(pll[0], pll[15]),
508 PHY_SHU_ADDR(pll20, misc0),
509 PHY_SHU_ADDR(rk[0].b[0], rk[0].b[0].rsvd_20[3]),
510 PHY_SHU_ADDR(rk[0].b[1], rk[0].b[1].rsvd_20[3]),
511 PHY_SHU_ADDR(rk[0].ca_cmd, rk[0].rsvd_22[1]),
512 PHY_SHU_ADDR(rk[1].b[0], rk[1].b[0].rsvd_20[3]),
513 PHY_SHU_ADDR(rk[1].b[1], rk[1].b[1].rsvd_20[3]),
514 PHY_SHU_ADDR(rk[1].ca_cmd, rk[1].rsvd_22[1]),
515 PHY_SHU_ADDR(rk[2].b[0], rk[2].b[0].rsvd_20[3]),
516 PHY_SHU_ADDR(rk[2].b[1], rk[2].b[1].rsvd_20[3]),
517 PHY_SHU_ADDR(rk[2].ca_cmd, rk[2].rsvd_22[1]),
518 };
519
dramc_save_result_to_shuffle(u32 src_shuffle,u32 dst_shuffle)520 static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
521 {
522 u32 offset, chn, index, value;
523 u8 *src_addr, *dst_addr;
524
525 if (src_shuffle == dst_shuffle)
526 return;
527
528 dramc_dbg("Save shuffle %u to shuffle %u\n", src_shuffle, dst_shuffle);
529
530 for (chn = 0; chn < CHANNEL_MAX; chn++) {
531 /* DRAMC */
532 for (index = 0; index < ARRAY_SIZE(dramc_regs); index++) {
533 for (offset = dramc_regs[index].start;
534 offset <= dramc_regs[index].end; offset += 4) {
535 src_addr = (u8 *)&ch[chn].ao.shu[src_shuffle] +
536 offset;
537 dst_addr = (u8 *)&ch[chn].ao.shu[dst_shuffle] +
538 offset;
539 write32(dst_addr, read32(src_addr));
540 }
541 }
542
543 /* DRAMC-exception-1 */
544 src_addr = (u8 *)&ch[chn].ao.shuctrl2;
545 dst_addr = (u8 *)&ch[chn].ao.dvfsdll;
546 value = read32(src_addr) & 0x7f;
547
548 if (dst_shuffle == DRAM_DFS_SHUFFLE_2)
549 clrsetbits32(dst_addr, 0x7f << 8, value << 8);
550 else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
551 clrsetbits32(dst_addr, 0x7f << 16, value << 16);
552
553 /* DRAMC-exception-2 */
554 src_addr = (u8 *)&ch[chn].ao.dvfsdll;
555 value = (read32(src_addr) >> 1) & 0x1;
556
557 if (dst_shuffle == DRAM_DFS_SHUFFLE_2)
558 clrsetbits32(src_addr, 0x1 << 2, value << 2);
559 else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
560 clrsetbits32(src_addr, 0x1 << 3, value << 3);
561
562 /* PHY */
563 for (index = 0; index < ARRAY_SIZE(phy_regs); index++) {
564 for (offset = phy_regs[index].start;
565 offset <= phy_regs[index].end; offset += 4) {
566 src_addr = (u8 *)&ch[chn].phy.shu[src_shuffle] +
567 offset;
568 dst_addr = (u8 *)&ch[chn].phy.shu[dst_shuffle] +
569 offset;
570 write32(dst_addr, read32(src_addr));
571 }
572 }
573 }
574 }
575
run_calib(const struct dramc_param * dparam,struct dram_shared_data * shared,const int shuffle,bool * first_run)576 static int run_calib(const struct dramc_param *dparam,
577 struct dram_shared_data *shared,
578 const int shuffle, bool *first_run)
579 {
580 u8 density;
581 const u8 *freq_tbl;
582
583 if (CONFIG(MT8183_DRAM_EMCP))
584 freq_tbl = freq_shuffle_emcp;
585 else
586 freq_tbl = freq_shuffle;
587
588 const u8 freq_group = freq_tbl[shuffle];
589 const struct sdram_params *params = &dparam->freq_params[shuffle];
590
591 set_vcore_voltage(freq_group);
592
593 dramc_show("Run calibration (freq: %u, first: %d)\n",
594 frequency_table[freq_group], *first_run);
595
596 if (*first_run)
597 init_dram(params, freq_group, shared);
598 else
599 dfs_init_for_calibration(params, freq_group, shared);
600 *first_run = false;
601
602 dramc_dbg("Start K (current clock: %u\n", params->frequency);
603 if (dramc_calibrate_all_channels(params, freq_group, &shared->mr,
604 !!(dparam->header.config & DRAMC_CONFIG_DVFS)) != 0)
605 return -1;
606 get_dram_info_after_cal(&density, params->rank_num);
607 dramc_ac_timing_optimize(freq_group, density);
608 dramc_dbg("K finished (current clock: %u\n", params->frequency);
609
610 dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle);
611 return 0;
612 }
613
after_calib(const struct mr_value * mr,u32 rk_num)614 static void after_calib(const struct mr_value *mr, u32 rk_num)
615 {
616 dramc_apply_config_after_calibration(mr, rk_num);
617 dramc_runtime_config(rk_num);
618 }
619
mt_set_emi(const struct dramc_param * dparam)620 int mt_set_emi(const struct dramc_param *dparam)
621 {
622 struct dram_shared_data shared;
623 bool first_run = true;
624 set_vdram1_vddq_voltage();
625
626 if (dparam->header.config & DRAMC_CONFIG_DVFS) {
627 if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_3,
628 &first_run) != 0)
629 return -1;
630 if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_2,
631 &first_run) != 0)
632 return -1;
633 }
634
635 if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_1, &first_run) != 0)
636 return -1;
637
638 after_calib(&shared.mr, dparam->freq_params[DRAM_DFS_SHUFFLE_1].rank_num);
639 return 0;
640 }
641