1 #ifndef __CB_BDK_HAL_MDIO_H__ 2 #define __CB_BDK_HAL_MDIO_H__ 3 /***********************license start*********************************** 4 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights 5 * reserved. 6 * 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: 11 * 12 * * Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 15 * * Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 20 * * Neither the name of Cavium Inc. nor the names of 21 * its contributors may be used to endorse or promote products 22 * derived from this software without specific prior written 23 * permission. 24 * 25 * This Software, including technical data, may be subject to U.S. export 26 * control laws, including the U.S. Export Administration Act and its 27 * associated regulations, and may be subject to export or import 28 * regulations in other countries. 29 * 30 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 31 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 32 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT 33 * TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 34 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 35 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 36 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 37 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, 38 * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK 39 * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 40 ***********************license end**************************************/ 41 42 /** 43 * @file 44 * 45 * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3 46 * clause 22 and clause 45 operations. 47 * 48 * <hr>$Revision: 51350 $<hr> 49 * 50 * @addtogroup hal 51 * @{ 52 */ 53 54 /** 55 * PHY register 0 from the 802.3 spec 56 */ 57 #define BDK_MDIO_PHY_REG_CONTROL 0 58 typedef union 59 { 60 uint16_t u16; 61 struct 62 { 63 #if __BYTE_ORDER == __BIG_ENDIAN 64 uint16_t reset : 1; 65 uint16_t loopback : 1; 66 uint16_t speed_lsb : 1; 67 uint16_t autoneg_enable : 1; 68 uint16_t power_down : 1; 69 uint16_t isolate : 1; 70 uint16_t restart_autoneg : 1; 71 uint16_t duplex : 1; 72 uint16_t collision_test : 1; 73 uint16_t speed_msb : 1; 74 uint16_t unidirectional_enable : 1; 75 uint16_t reserved_0_4 : 5; 76 #else 77 uint16_t reserved_0_4 : 5; 78 uint16_t unidirectional_enable : 1; 79 uint16_t speed_msb : 1; 80 uint16_t collision_test : 1; 81 uint16_t duplex : 1; 82 uint16_t restart_autoneg : 1; 83 uint16_t isolate : 1; 84 uint16_t power_down : 1; 85 uint16_t autoneg_enable : 1; 86 uint16_t speed_lsb : 1; 87 uint16_t loopback : 1; 88 uint16_t reset : 1; 89 #endif 90 } s; 91 } bdk_mdio_phy_reg_control_t; 92 93 /** 94 * PHY register 1 from the 802.3 spec 95 */ 96 #define BDK_MDIO_PHY_REG_STATUS 1 97 typedef union 98 { 99 uint16_t u16; 100 struct 101 { 102 #if __BYTE_ORDER == __BIG_ENDIAN 103 uint16_t capable_100base_t4 : 1; 104 uint16_t capable_100base_x_full : 1; 105 uint16_t capable_100base_x_half : 1; 106 uint16_t capable_10_full : 1; 107 uint16_t capable_10_half : 1; 108 uint16_t capable_100base_t2_full : 1; 109 uint16_t capable_100base_t2_half : 1; 110 uint16_t capable_extended_status : 1; 111 uint16_t capable_unidirectional : 1; 112 uint16_t capable_mf_preamble_suppression : 1; 113 uint16_t autoneg_complete : 1; 114 uint16_t remote_fault : 1; 115 uint16_t capable_autoneg : 1; 116 uint16_t link_status : 1; 117 uint16_t jabber_detect : 1; 118 uint16_t capable_extended_registers : 1; 119 #else 120 uint16_t capable_extended_registers : 1; 121 uint16_t jabber_detect : 1; 122 uint16_t link_status : 1; 123 uint16_t capable_autoneg : 1; 124 uint16_t remote_fault : 1; 125 uint16_t autoneg_complete : 1; 126 uint16_t capable_mf_preamble_suppression : 1; 127 uint16_t capable_unidirectional : 1; 128 uint16_t capable_extended_status : 1; 129 uint16_t capable_100base_t2_half : 1; 130 uint16_t capable_100base_t2_full : 1; 131 uint16_t capable_10_half : 1; 132 uint16_t capable_10_full : 1; 133 uint16_t capable_100base_x_half : 1; 134 uint16_t capable_100base_x_full : 1; 135 uint16_t capable_100base_t4 : 1; 136 #endif 137 } s; 138 } bdk_mdio_phy_reg_status_t; 139 140 /** 141 * PHY register 2 from the 802.3 spec 142 */ 143 #define BDK_MDIO_PHY_REG_ID1 2 144 typedef union 145 { 146 uint16_t u16; 147 struct 148 { 149 uint16_t oui_bits_3_18; 150 } s; 151 } bdk_mdio_phy_reg_id1_t; 152 153 /** 154 * PHY register 3 from the 802.3 spec 155 */ 156 #define BDK_MDIO_PHY_REG_ID2 3 157 typedef union 158 { 159 uint16_t u16; 160 struct 161 { 162 #if __BYTE_ORDER == __BIG_ENDIAN 163 uint16_t oui_bits_19_24 : 6; 164 uint16_t model : 6; 165 uint16_t revision : 4; 166 #else 167 uint16_t revision : 4; 168 uint16_t model : 6; 169 uint16_t oui_bits_19_24 : 6; 170 #endif 171 } s; 172 } bdk_mdio_phy_reg_id2_t; 173 174 /** 175 * PHY register 4 from the 802.3 spec 176 */ 177 #define BDK_MDIO_PHY_REG_AUTONEG_ADVER 4 178 typedef union 179 { 180 uint16_t u16; 181 struct 182 { 183 #if __BYTE_ORDER == __BIG_ENDIAN 184 uint16_t next_page : 1; 185 uint16_t reserved_14 : 1; 186 uint16_t remote_fault : 1; 187 uint16_t reserved_12 : 1; 188 uint16_t asymmetric_pause : 1; 189 uint16_t pause : 1; 190 uint16_t advert_100base_t4 : 1; 191 uint16_t advert_100base_tx_full : 1; 192 uint16_t advert_100base_tx_half : 1; 193 uint16_t advert_10base_tx_full : 1; 194 uint16_t advert_10base_tx_half : 1; 195 uint16_t selector : 5; 196 #else 197 uint16_t selector : 5; 198 uint16_t advert_10base_tx_half : 1; 199 uint16_t advert_10base_tx_full : 1; 200 uint16_t advert_100base_tx_half : 1; 201 uint16_t advert_100base_tx_full : 1; 202 uint16_t advert_100base_t4 : 1; 203 uint16_t pause : 1; 204 uint16_t asymmetric_pause : 1; 205 uint16_t reserved_12 : 1; 206 uint16_t remote_fault : 1; 207 uint16_t reserved_14 : 1; 208 uint16_t next_page : 1; 209 #endif 210 } s; 211 } bdk_mdio_phy_reg_autoneg_adver_t; 212 213 /** 214 * PHY register 5 from the 802.3 spec 215 */ 216 #define BDK_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5 217 typedef union 218 { 219 uint16_t u16; 220 struct 221 { 222 #if __BYTE_ORDER == __BIG_ENDIAN 223 uint16_t next_page : 1; 224 uint16_t ack : 1; 225 uint16_t remote_fault : 1; 226 uint16_t reserved_12 : 1; 227 uint16_t asymmetric_pause : 1; 228 uint16_t pause : 1; 229 uint16_t advert_100base_t4 : 1; 230 uint16_t advert_100base_tx_full : 1; 231 uint16_t advert_100base_tx_half : 1; 232 uint16_t advert_10base_tx_full : 1; 233 uint16_t advert_10base_tx_half : 1; 234 uint16_t selector : 5; 235 #else 236 uint16_t selector : 5; 237 uint16_t advert_10base_tx_half : 1; 238 uint16_t advert_10base_tx_full : 1; 239 uint16_t advert_100base_tx_half : 1; 240 uint16_t advert_100base_tx_full : 1; 241 uint16_t advert_100base_t4 : 1; 242 uint16_t pause : 1; 243 uint16_t asymmetric_pause : 1; 244 uint16_t reserved_12 : 1; 245 uint16_t remote_fault : 1; 246 uint16_t ack : 1; 247 uint16_t next_page : 1; 248 #endif 249 } s; 250 } bdk_mdio_phy_reg_link_partner_ability_t; 251 252 /** 253 * PHY register 6 from the 802.3 spec 254 */ 255 #define BDK_MDIO_PHY_REG_AUTONEG_EXPANSION 6 256 typedef union 257 { 258 uint16_t u16; 259 struct 260 { 261 #if __BYTE_ORDER == __BIG_ENDIAN 262 uint16_t reserved_5_15 : 11; 263 uint16_t parallel_detection_fault : 1; 264 uint16_t link_partner_next_page_capable : 1; 265 uint16_t local_next_page_capable : 1; 266 uint16_t page_received : 1; 267 uint16_t link_partner_autoneg_capable : 1; 268 #else 269 uint16_t link_partner_autoneg_capable : 1; 270 uint16_t page_received : 1; 271 uint16_t local_next_page_capable : 1; 272 uint16_t link_partner_next_page_capable : 1; 273 uint16_t parallel_detection_fault : 1; 274 uint16_t reserved_5_15 : 11; 275 #endif 276 } s; 277 } bdk_mdio_phy_reg_autoneg_expansion_t; 278 279 /** 280 * PHY register 9 from the 802.3 spec 281 */ 282 #define BDK_MDIO_PHY_REG_CONTROL_1000 9 283 typedef union 284 { 285 uint16_t u16; 286 struct 287 { 288 #if __BYTE_ORDER == __BIG_ENDIAN 289 uint16_t test_mode : 3; 290 uint16_t manual_master_slave : 1; 291 uint16_t master : 1; 292 uint16_t port_type : 1; 293 uint16_t advert_1000base_t_full : 1; 294 uint16_t advert_1000base_t_half : 1; 295 uint16_t reserved_0_7 : 8; 296 #else 297 uint16_t reserved_0_7 : 8; 298 uint16_t advert_1000base_t_half : 1; 299 uint16_t advert_1000base_t_full : 1; 300 uint16_t port_type : 1; 301 uint16_t master : 1; 302 uint16_t manual_master_slave : 1; 303 uint16_t test_mode : 3; 304 #endif 305 } s; 306 } bdk_mdio_phy_reg_control_1000_t; 307 308 /** 309 * PHY register 10 from the 802.3 spec 310 */ 311 #define BDK_MDIO_PHY_REG_STATUS_1000 10 312 typedef union 313 { 314 uint16_t u16; 315 struct 316 { 317 #if __BYTE_ORDER == __BIG_ENDIAN 318 uint16_t master_slave_fault : 1; 319 uint16_t is_master : 1; 320 uint16_t local_receiver_ok : 1; 321 uint16_t remote_receiver_ok : 1; 322 uint16_t remote_capable_1000base_t_full : 1; 323 uint16_t remote_capable_1000base_t_half : 1; 324 uint16_t reserved_8_9 : 2; 325 uint16_t idle_error_count : 8; 326 #else 327 uint16_t idle_error_count : 8; 328 uint16_t reserved_8_9 : 2; 329 uint16_t remote_capable_1000base_t_half : 1; 330 uint16_t remote_capable_1000base_t_full : 1; 331 uint16_t remote_receiver_ok : 1; 332 uint16_t local_receiver_ok : 1; 333 uint16_t is_master : 1; 334 uint16_t master_slave_fault : 1; 335 #endif 336 } s; 337 } bdk_mdio_phy_reg_status_1000_t; 338 339 /** 340 * PHY register 15 from the 802.3 spec 341 */ 342 #define BDK_MDIO_PHY_REG_EXTENDED_STATUS 15 343 typedef union 344 { 345 uint16_t u16; 346 struct 347 { 348 #if __BYTE_ORDER == __BIG_ENDIAN 349 uint16_t capable_1000base_x_full : 1; 350 uint16_t capable_1000base_x_half : 1; 351 uint16_t capable_1000base_t_full : 1; 352 uint16_t capable_1000base_t_half : 1; 353 uint16_t reserved_0_11 : 12; 354 #else 355 uint16_t reserved_0_11 : 12; 356 uint16_t capable_1000base_t_half : 1; 357 uint16_t capable_1000base_t_full : 1; 358 uint16_t capable_1000base_x_half : 1; 359 uint16_t capable_1000base_x_full : 1; 360 #endif 361 } s; 362 } bdk_mdio_phy_reg_extended_status_t; 363 364 365 /** 366 * PHY register 13 from the 802.3 spec 367 */ 368 #define BDK_MDIO_PHY_REG_MMD_CONTROL 13 369 typedef union 370 { 371 uint16_t u16; 372 struct 373 { 374 #if __BYTE_ORDER == __BIG_ENDIAN 375 uint16_t function : 2; 376 uint16_t reserved_5_13 : 9; 377 uint16_t devad : 5; 378 #else 379 uint16_t devad : 5; 380 uint16_t reserved_5_13 : 9; 381 uint16_t function : 2; 382 #endif 383 } s; 384 } bdk_mdio_phy_reg_mmd_control_t; 385 386 /** 387 * PHY register 14 from the 802.3 spec 388 */ 389 #define BDK_MDIO_PHY_REG_MMD_ADDRESS_DATA 14 390 typedef union 391 { 392 uint16_t u16; 393 struct 394 { 395 uint16_t address_data : 16; 396 } s; 397 } bdk_mdio_phy_reg_mmd_address_data_t; 398 399 /* MMD identifiers, mostly for accessing devices within XENPAK modules. */ 400 #define BDK_MMD_DEVICE_PMA_PMD 1 401 #define BDK_MMD_DEVICE_WIS 2 402 #define BDK_MMD_DEVICE_PCS 3 403 #define BDK_MMD_DEVICE_PHY_XS 4 404 #define BDK_MMD_DEVICE_DTS_XS 5 405 #define BDK_MMD_DEVICE_TC 6 406 #define BDK_MMD_DEVICE_CL22_EXT 29 407 #define BDK_MMD_DEVICE_VENDOR_1 30 408 #define BDK_MMD_DEVICE_VENDOR_2 31 409 410 /** 411 * Perform an MII read. This function is used to read PHY 412 * registers controlling auto negotiation. 413 * 414 * @param node Node to use in a Numa setup. Can be an exact ID or a special 415 * value. 416 * @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX) 417 * support multiple busses. 418 * @param phy_id The MII phy id 419 * @param location Register location to read 420 * 421 * @return Result from the read or -1 on failure 422 */ 423 extern int bdk_mdio_read(bdk_node_t node, int bus_id, int phy_id, int location); 424 425 /** 426 * Perform an MII write. This function is used to write PHY 427 * registers controlling auto negotiation. 428 * 429 * @param node Node to use in a Numa setup. Can be an exact ID or a special 430 * value. 431 * @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX) 432 * support multiple busses. 433 * @param phy_id The MII phy id 434 * @param location Register location to write 435 * @param val Value to write 436 * 437 * @return -1 on error 438 * 0 on success 439 */ 440 extern int bdk_mdio_write(bdk_node_t node, int bus_id, int phy_id, int location, int val); 441 442 /** 443 * Perform an IEEE 802.3 clause 45 MII read. This function is used to read PHY 444 * registers controlling auto negotiation. 445 * 446 * @param node Node to use in a Numa setup. Can be an exact ID or a special 447 * value. 448 * @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX) 449 * support multiple busses. 450 * @param phy_id The MII phy id 451 * @param device MDIO Manageable Device (MMD) id 452 * @param location Register location to read 453 * 454 * @return Result from the read or -1 on failure 455 */ 456 457 extern int bdk_mdio_45_read(bdk_node_t node, int bus_id, int phy_id, int device, int location); 458 459 /** 460 * Perform an IEEE 802.3 clause 45 MII write. This function is used to write PHY 461 * registers controlling auto negotiation. 462 * 463 * @param node Node to use in a Numa setup. Can be an exact ID or a special 464 * value. 465 * @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX) 466 * support multiple busses. 467 * @param phy_id The MII phy id 468 * @param device MDIO Manageable Device (MMD) id 469 * @param location Register location to write 470 * @param val Value to write 471 * 472 * @return -1 on error 473 * 0 on success 474 */ 475 extern int bdk_mdio_45_write(bdk_node_t node, int bus_id, int phy_id, int device, int location, 476 int val); 477 478 int bdk_mdio_init(bdk_node_t node); 479 480 /** @} */ 481 #endif 482