1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef _BAYTRAIL_GPIO_H_
4 #define _BAYTRAIL_GPIO_H_
5
6 #include <stdint.h>
7 #include <device/mmio.h>
8 #include <soc/iomap.h>
9
10 /* #define GPIO_DEBUG */
11
12 #define CROS_GPIO_DEVICE_NAME "BayTrail"
13
14 /* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */
15 #define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
16 #define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE)
17 #define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
18
19 /* DIRQ registers start at pad base + 0x980 */
20 #define PAD_BASE_DIRQ_OFFSET 0x980
21
22 /* Pad register offset */
23 #define PAD_CONF0_REG 0x0
24 #define PAD_CONF1_REG 0x4
25 #define PAD_VAL_REG 0x8
26
27 /* Legacy IO register base */
28 #define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00)
29 #define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80)
30 /* Some banks have no legacy GPIO interface */
31 #define GP_LEGACY_BASE_NONE 0xFFFF
32
33 #define LEGACY_USE_SEL_REG 0x00
34 #define LEGACY_IO_SEL_REG 0x04
35 #define LEGACY_GP_LVL_REG 0x08
36 #define LEGACY_TPE_REG 0x0C
37 #define LEGACY_TNE_REG 0x10
38 #define LEGACY_TS_REG 0x14
39 #define LEGACY_WAKE_EN_REG 0x18
40
41 /* Number of GPIOs in each bank */
42 #define GPNCORE_COUNT 27
43 #define GPSCORE_COUNT 102
44 #define GPSSUS_COUNT 44
45
46 /* GPIO legacy IO register settings */
47 #define GPIO_USE_MMIO 0
48 #define GPIO_USE_LEGACY 1
49
50 #define GPIO_DIR_OUTPUT 0
51 #define GPIO_DIR_INPUT 1
52
53 #define GPIO_LEVEL_LOW 0
54 #define GPIO_LEVEL_HIGH 1
55
56 #define GPIO_PEDGE_DISABLE 0
57 #define GPIO_PEDGE_ENABLE 1
58
59 #define GPIO_NEDGE_DISABLE 0
60 #define GPIO_NEDGE_ENABLE 1
61
62 /* config0[29] - Disable second mask */
63 #define PAD_MASK2_DISABLE (1 << 29)
64
65 /* config0[27] - Direct Irq En */
66 #define PAD_IRQ_EN (1 << 27)
67
68 /* config0[26] - gd_tne */
69 #define PAD_TNE_IRQ (1 << 26)
70
71 /* config0[25] - gd_tpe */
72 #define PAD_TPE_IRQ (1 << 25)
73
74 /* config0[24] - Gd Level */
75 #define PAD_LEVEL_IRQ (1 << 24)
76 #define PAD_EDGE_IRQ (0 << 24)
77
78 /* config0[17] - Slow clkgate / glitch filter */
79 #define PAD_SLOWGF_ENABLE (1 << 17)
80
81 /* config0[16] - Fast clkgate / glitch filter */
82 #define PAD_FASTGF_ENABLE (1 << 16)
83
84 /* config0[15] - Hysteresis enable (inverted) */
85 #define PAD_HYST_DISABLE (1 << 15)
86 #define PAD_HYST_ENABLE (0 << 15)
87
88 /* config0[14:13] - Hysteresis control */
89 #define PAD_HYST_CTRL_DEFAULT (2 << 13)
90
91 /* config0[11] - Bypass Flop */
92 #define PAD_FLOP_BYPASS (1 << 11)
93 #define PAD_FLOP_ENABLE (0 << 11)
94
95 /* config0[10:9] - Pull str */
96 #define PAD_PU_2K (0 << 9)
97 #define PAD_PU_10K (1 << 9)
98 #define PAD_PU_20K (2 << 9)
99 #define PAD_PU_40K (3 << 9)
100
101 /* config0[8:7] - Pull assign */
102 #define PAD_PULL_DISABLE (0 << 7)
103 #define PAD_PULL_UP (1 << 7)
104 #define PAD_PULL_DOWN (2 << 7)
105
106 /* config0[2:0] - Func. pin mux */
107 #define PAD_FUNC0 0x0
108 #define PAD_FUNC1 0x1
109 #define PAD_FUNC2 0x2
110 #define PAD_FUNC3 0x3
111 #define PAD_FUNC4 0x4
112 #define PAD_FUNC5 0x5
113 #define PAD_FUNC6 0x6
114
115 /* pad config0 power-on values - We will not often want to change these */
116 #define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \
117 PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \
118 PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS)
119
120 /* pad config1 reg power-on values - Shouldn't need to change this */
121 #define PAD_CONFIG1_DEFAULT 0x8000
122
123 /* pad_val[2] - Iinenb - active low */
124 #define PAD_VAL_INPUT_DISABLE (1 << 2)
125 #define PAD_VAL_INPUT_ENABLE (0 << 2)
126
127 /* pad_val[1] - Ioutenb - active low */
128 #define PAD_VAL_OUTPUT_DISABLE (1 << 1)
129 #define PAD_VAL_OUTPUT_ENABLE (0 << 1)
130
131 /* Input / Output state should usually be mutually exclusive */
132 #define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE)
133 #define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE)
134
135 /* pad_val[0] - Value */
136 #define PAD_VAL_HIGH (1 << 0)
137 #define PAD_VAL_LOW (0 << 0)
138
139 /* pad_val reg power-on default varies by pad, and apparently can cause issues
140 * if not set correctly, even if the pin isn't configured as GPIO. */
141 #define PAD_VAL_DEFAULT PAD_VAL_INPUT
142
143 /* Configure GPIOs as MMIO by default */
144 #define GPIO_INPUT_PU_10K \
145 { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \
146 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
147 .pad_val = PAD_VAL_INPUT, \
148 .use_sel = GPIO_USE_MMIO, \
149 .is_gpio = 1 }
150
151 #define GPIO_INPUT_PU_20K \
152 { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \
153 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
154 .pad_val = PAD_VAL_INPUT, \
155 .use_sel = GPIO_USE_MMIO, \
156 .is_gpio = 1 }
157
158 #define GPIO_INPUT_PD_10K \
159 { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \
160 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
161 .pad_val = PAD_VAL_INPUT, \
162 .use_sel = GPIO_USE_MMIO, \
163 .is_gpio = 1 }
164
165 #define GPIO_INPUT_PD_20K \
166 { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \
167 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
168 .pad_val = PAD_VAL_INPUT, \
169 .use_sel = GPIO_USE_MMIO, \
170 .is_gpio = 1 }
171
172 #define GPIO_INPUT_NOPU \
173 { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
174 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
175 .pad_val = PAD_VAL_INPUT, \
176 .use_sel = GPIO_USE_MMIO, \
177 .is_gpio = 1 }
178
179 #define GPIO_INPUT_LEGACY_NOPU \
180 { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
181 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
182 .pad_val = PAD_VAL_INPUT, \
183 .use_sel = GPIO_USE_LEGACY, \
184 .io_sel = GPIO_DIR_INPUT, \
185 .is_gpio = 1 }
186
187 /* Direct / dedicated IRQ input - pass signal directly to APIC */
188 #define GPIO_DIRQ \
189 { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
190 | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
191 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
192 .pad_val = PAD_VAL_INPUT, }
193
194 /* Direct / dedicated IRQ input - pass signal directly to APIC */
195 #define GPIO_DIRQ_LEVELHIGH_NO_PULL \
196 { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
197 | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
198 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
199 .pad_val = PAD_VAL_INPUT, }
200
201 /* Direct / dedicated IRQ input - pass signal directly to APIC */
202 #define GPIO_DIRQ_LEVELLOW_PU_20K \
203 { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
204 | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \
205 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
206 .pad_val = PAD_VAL_INPUT, }
207
208 /* Direct / dedicated IRQ input - pass signal directly to APIC */
209 #define GPIO_DIRQ_EDGELOW_PU_20K \
210 { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
211 | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
212 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
213 .pad_val = PAD_VAL_INPUT, }
214
215 /* Direct / dedicated IRQ input - pass signal directly to APIC */
216 #define GPIO_DIRQ_EDGEHIGH_PD_20K \
217 { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
218 | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \
219 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
220 .pad_val = PAD_VAL_INPUT, }
221
222 /* Direct / dedicated IRQ input - pass signal directly to APIC */
223 #define GPIO_DIRQ_EDGELOW_PD_20K \
224 { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
225 | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
226 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
227 .pad_val = PAD_VAL_INPUT, }
228
229 /* Direct / dedicated IRQ input - pass signal directly to APIC */
230 #define GPIO_DIRQ_EDGEBOTH_PU_20K \
231 { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
232 | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \
233 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
234 .pad_val = PAD_VAL_INPUT, }
235
236 #define GPIO_OUT_LOW \
237 { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
238 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
239 .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \
240 .use_sel = GPIO_USE_LEGACY, \
241 .io_sel = GPIO_DIR_OUTPUT, \
242 .gp_lvl = GPIO_LEVEL_LOW, \
243 .is_gpio = 1 }
244
245 #define GPIO_OUT_HIGH \
246 { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
247 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
248 .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \
249 .use_sel = GPIO_USE_LEGACY, \
250 .io_sel = GPIO_DIR_OUTPUT, \
251 .gp_lvl = GPIO_LEVEL_HIGH, \
252 .is_gpio = 1 }
253
254 /* Define no-pull / PU / PD configs for each functional config option */
255 #define GPIO_FUNC(_func, _pudir, _str) \
256 { .use_sel = GPIO_USE_MMIO, \
257 .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \
258 PAD_CONFIG0_DEFAULT, \
259 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
260 .pad_val = PAD_VAL_DEFAULT }
261
262 /* Default functional configs -- no PU */
263 #define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K)
264 #define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K)
265 #define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K)
266 #define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K)
267 #define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K)
268 #define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K)
269 #define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K)
270
271 /* ACPI GPIO routing. Assume everything is externally pulled and negative edge
272 * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */
273 #define GPIO_ACPI_SCI \
274 { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \
275 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
276 .pad_val = PAD_VAL_INPUT, \
277 .use_sel = GPIO_USE_LEGACY, \
278 .io_sel = GPIO_DIR_INPUT, \
279 .tne = 1, \
280 .sci = 1, \
281 .wake_en = 1, }
282 #define GPIO_ACPI_WAKE \
283 { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \
284 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
285 .pad_val = PAD_VAL_INPUT, \
286 .use_sel = GPIO_USE_LEGACY, \
287 .io_sel = GPIO_DIR_INPUT, \
288 .tne = 1, \
289 .wake_en = 1, }
290 #define GPIO_ACPI_SMI \
291 { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \
292 .pad_conf1 = PAD_CONFIG1_DEFAULT, \
293 .pad_val = PAD_VAL_INPUT, \
294 .use_sel = GPIO_USE_LEGACY, \
295 .io_sel = GPIO_DIR_INPUT, \
296 .tne = 1, \
297 .smi = 1}
298
299 /* End marker */
300 #define GPIO_LIST_END 0xffffffff
301
302 #define GPIO_END \
303 { .pad_conf0 = GPIO_LIST_END }
304
305 /* Common default GPIO settings */
306 #define GPIO_INPUT GPIO_INPUT_NOPU
307 #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU
308 #define GPIO_INPUT_PU GPIO_INPUT_PU_20K
309 #define GPIO_INPUT_PD GPIO_INPUT_PD_20K
310 #define GPIO_NC GPIO_OUT_HIGH
311 #define GPIO_DEFAULT GPIO_FUNC0
312
313 /* 16 DirectIRQs per supported bank */
314 #define GPIO_MAX_DIRQS 16
315
316 /* Most pins are GPIO function 0. Some banks have a range of pins with GPIO
317 * function 1. Indicate first / last GPIOs with function 1. */
318 #define GPIO_NONE 255
319 /* All NCORE GPIOs are function 0 */
320 #define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE
321 #define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE
322 /* SCORE GPIO [92:93] are function 1 */
323 #define GPSCORE_GPIO_F1_RANGE_START 92
324 #define GPSCORE_GPIO_F1_RANGE_END 93
325 /* SSUS GPIO [11:21] are function 1 */
326 #define GPSSUS_GPIO_F1_RANGE_START 11
327 #define GPSSUS_GPIO_F1_RANGE_END 21
328
329 struct soc_gpio_map {
330 u32 pad_conf0;
331 u32 pad_conf1;
332 u32 pad_val;
333 u32 use_sel : 1;
334 u32 io_sel : 1;
335 u32 gp_lvl : 1;
336 u32 tpe : 1;
337 u32 tne : 1;
338 u32 wake_en : 1;
339 u32 smi : 1;
340 u32 is_gpio : 1;
341 u32 sci : 1;
342 } __packed;
343
344 struct soc_gpio_config {
345 const struct soc_gpio_map *ncore;
346 const struct soc_gpio_map *score;
347 const struct soc_gpio_map *ssus;
348 const u8 (*core_dirq)[GPIO_MAX_DIRQS];
349 const u8 (*sus_dirq)[GPIO_MAX_DIRQS];
350 };
351
352 /* Description of GPIO 'bank' ex. {ncore, score. ssus} */
353 struct gpio_bank {
354 const int gpio_count;
355 const u8 *gpio_to_pad;
356 const int legacy_base;
357 const unsigned long pad_base;
358 const u8 has_wake_en :1;
359 const u8 gpio_f1_range_start;
360 const u8 gpio_f1_range_end;
361 };
362
363 void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap);
364 /* This function is weak and can be overridden by a mainboard function. */
365 struct soc_gpio_config* mainboard_get_gpios(void);
366
367 /* Functions / defines for changing GPIOs in romstage */
368 /* SCORE Pad definitions. */
369 #define UART_RXD_PAD 82
370 #define UART_TXD_PAD 83
371 #define PCU_SMB_CLK_PAD 88
372 #define PCU_SMB_DATA_PAD 90
373 #define SOC_DDI1_VDDEN_PAD 16
374
ncore_pconf0(int pad_num)375 static inline u32 *ncore_pconf0(int pad_num)
376 {
377 return (u32 *)(GPNCORE_PAD_BASE + pad_num * 16);
378 }
379
ncore_select_func(int pad,int func)380 static inline void ncore_select_func(int pad, int func)
381 {
382 uint32_t reg;
383 u32 *pconf0_addr = ncore_pconf0(pad);
384
385 reg = read32(pconf0_addr);
386 reg &= ~0x7;
387 reg |= func & 0x7;
388 write32(pconf0_addr, reg);
389 }
390
score_pconf0(int pad_num)391 static inline u32 *score_pconf0(int pad_num)
392 {
393 return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16);
394 }
395
ssus_pconf0(int pad_num)396 static inline u32 *ssus_pconf0(int pad_num)
397 {
398 return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16);
399 }
400
score_select_func(int pad,int func)401 static inline void score_select_func(int pad, int func)
402 {
403 uint32_t reg;
404 uint32_t *pconf0_addr = score_pconf0(pad);
405
406 reg = read32(pconf0_addr);
407 reg &= ~0x7;
408 reg |= func & 0x7;
409 write32(pconf0_addr, reg);
410 }
411
ssus_select_func(int pad,int func)412 static inline void ssus_select_func(int pad, int func)
413 {
414 uint32_t reg;
415 uint32_t *pconf0_addr = ssus_pconf0(pad);
416
417 reg = read32(pconf0_addr);
418 reg &= ~0x7;
419 reg |= func & 0x7;
420 write32(pconf0_addr, reg);
421 }
422
423 /* These functions require that the input pad be configured as an input GPIO */
score_get_gpio(int pad)424 static inline int score_get_gpio(int pad)
425 {
426 uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
427
428 return read32(val_addr) & PAD_VAL_HIGH;
429 }
430
ssus_get_gpio(int pad)431 static inline int ssus_get_gpio(int pad)
432 {
433 uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
434
435 return read32(val_addr) & PAD_VAL_HIGH;
436 }
437
ssus_disable_internal_pull(int pad)438 static inline void ssus_disable_internal_pull(int pad)
439 {
440 const uint32_t pull_mask = ~(0xf << 7);
441 write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
442 }
443
ssus_enable_internal_pull(int pad,int mask)444 static inline void ssus_enable_internal_pull(int pad, int mask)
445 {
446 const int pull_mask = ~(0xf << 7);
447 write32(ssus_pconf0(pad),
448 (read32(ssus_pconf0(pad)) & pull_mask) | mask);
449 }
450
451 #endif /* _BAYTRAIL_GPIO_H_ */
452