1/*
2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_a55.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19	.globl cortex_a55_reset_func
20	.globl cortex_a55_core_pwr_dwn
21
22/* ERRATA_DSU_798953:
23 * The errata is defined in dsu_helpers.S but applies to cortex_a55
24 * as well. Henceforth creating symbolic names to the already existing errata
25 * workaround functions to get them registered under the Errata Framework.
26 */
27.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953
28.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa
29add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
30
31/* ERRATA_DSU_936184:
32 * The errata is defined in dsu_helpers.S but applies to cortex_a55
33 * as well. Henceforth creating symbolic names to the already existing errata
34 * workaround functions to get them registered under the Errata Framework.
35 */
36.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184
37.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa
38add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
39
40workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
41	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
42workaround_reset_end cortex_a55, ERRATUM(768277)
43
44check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0)
45
46workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703
47	sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL
48	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
49workaround_reset_end cortex_a55, ERRATUM(778703)
50
51check_erratum_custom_start cortex_a55, ERRATUM(778703)
52	mov	x16, x30
53	mov	x1, #0x00
54	bl	cpu_rev_var_ls
55	/*
56	 * Check that no private L2 cache is configured
57	 */
58	mrs	x1, CORTEX_A55_CLIDR_EL1
59	and	x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3
60	cmp	x1, #0
61	mov	x2, #ERRATA_NOT_APPLIES
62	csel	x0, x0, x2, eq
63	ret	x16
64check_erratum_custom_end cortex_a55, ERRATUM(778703)
65
66workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797
67	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
68workaround_reset_end cortex_a55, ERRATUM(798797)
69
70check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
71
72workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
73	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
74workaround_reset_end cortex_a55, ERRATUM(846532)
75
76check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1)
77
78workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758
79	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
80workaround_reset_end cortex_a55, ERRATUM(903758)
81
82check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
83
84workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
85	mov	x0, #0x0020
86	movk	x0, #0x0850, lsl #16
87	msr	CPUPOR_EL3, x0
88	mov	x0, #0x0000
89	movk	x0, #0x1FF0, lsl #16
90	movk	x0, #0x2, lsl #32
91	msr	CPUPMR_EL3, x0
92	mov	x0, #0x03fd
93	movk	x0, #0x0110, lsl #16
94	msr	CPUPCR_EL3, x0
95	mov	x0, #0x1
96	msr	CPUPSELR_EL3, x0
97	mov	x0, #0x0040
98	movk	x0, #0x08D0, lsl #16
99	msr	CPUPOR_EL3, x0
100	mov	x0, #0x0040
101	movk	x0, #0x1FF0, lsl #16
102	movk	x0, #0x2, lsl #32
103	msr	CPUPMR_EL3, x0
104	mov	x0, #0x03fd
105	movk	x0, #0x0110, lsl #16
106	msr	CPUPCR_EL3, x0
107workaround_reset_end cortex_a55, ERRATUM(1221012)
108
109check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0)
110
111check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
112
113/* erratum has no workaround in the cpu. Generic code must take care */
114add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET
115
116cpu_reset_func_start cortex_a55
117cpu_reset_func_end cortex_a55
118
119errata_report_shim cortex_a55
120
121	/* ---------------------------------------------
122	 * HW will do the cache maintenance while powering down
123	 * ---------------------------------------------
124	 */
125func cortex_a55_core_pwr_dwn
126	sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK
127	isb
128	ret
129endfunc cortex_a55_core_pwr_dwn
130
131	/* ---------------------------------------------
132	 * This function provides cortex_a55 specific
133	 * register information for crash reporting.
134	 * It needs to return with x6 pointing to
135	 * a list of register names in ascii and
136	 * x8 - x15 having values of registers to be
137	 * reported.
138	 * ---------------------------------------------
139	 */
140.section .rodata.cortex_a55_regs, "aS"
141cortex_a55_regs:  /* The ascii list of register names to be reported */
142	.asciz	"cpuectlr_el1", ""
143
144func cortex_a55_cpu_reg_dump
145	adr	x6, cortex_a55_regs
146	mrs	x8, CORTEX_A55_CPUECTLR_EL1
147	ret
148endfunc cortex_a55_cpu_reg_dump
149
150declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \
151	cortex_a55_reset_func, \
152	cortex_a55_core_pwr_dwn
153