1 #ifndef __BDK_CSRS_SGP_H__
2 #define __BDK_CSRS_SGP_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
36 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
39 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium SGP.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration sgp_bar_e
57 *
58 * SGPIO Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_SGP_BAR_E_SGP_PF_BAR0_CN8 (0x87e027000000ll)
62 #define BDK_SGP_BAR_E_SGP_PF_BAR0_CN8_SIZE 0x800000ull
63 #define BDK_SGP_BAR_E_SGP_PF_BAR0_CN9 (0x87e027000000ll)
64 #define BDK_SGP_BAR_E_SGP_PF_BAR0_CN9_SIZE 0x80000ull
65
66 /**
67 * Enumeration sgp_tx_act_e
68 *
69 * SGPIO Transmit Activity Enumeration
70 * Enumerates the values of SGP_TX()[*_ACT].
71 */
72 #define BDK_SGP_TX_ACT_E_A_OFF_ON (3)
73 #define BDK_SGP_TX_ACT_E_A_ON_OFF (2)
74 #define BDK_SGP_TX_ACT_E_BRIEF_END (4)
75 #define BDK_SGP_TX_ACT_E_BRIEF_START (5)
76 #define BDK_SGP_TX_ACT_E_B_OFF_ON (7)
77 #define BDK_SGP_TX_ACT_E_B_ON_OFF (6)
78 #define BDK_SGP_TX_ACT_E_STATIC_OFF (0)
79 #define BDK_SGP_TX_ACT_E_STATIC_ON (1)
80
81 /**
82 * Enumeration sgp_tx_err_e
83 *
84 * SGPIO Transmit Error Enumeration
85 * Enumerates the values of SGP_TX()[*_ERR].
86 */
87 #define BDK_SGP_TX_ERR_E_A_OFF_ON (3)
88 #define BDK_SGP_TX_ERR_E_A_ON_OFF (2)
89 #define BDK_SGP_TX_ERR_E_B_OFF_ON (7)
90 #define BDK_SGP_TX_ERR_E_B_ON_OFF (6)
91 #define BDK_SGP_TX_ERR_E_STATIC_OFF (0)
92 #define BDK_SGP_TX_ERR_E_STATIC_ON (1)
93 #define BDK_SGP_TX_ERR_E_STATIC_ON4 (4)
94 #define BDK_SGP_TX_ERR_E_STATIC_ON5 (5)
95
96 /**
97 * Enumeration sgp_tx_loc_e
98 *
99 * SGPIO Transmit Locate Enumeration
100 * Enumerates the values of SGP_TX()[*_LOC].
101 */
102 #define BDK_SGP_TX_LOC_E_A_OFF_ON (3)
103 #define BDK_SGP_TX_LOC_E_A_ON_OFF (2)
104 #define BDK_SGP_TX_LOC_E_STATIC_OFF (0)
105 #define BDK_SGP_TX_LOC_E_STATIC_ON (1)
106
107 /**
108 * Register (RSL32b) sgp_cfg0
109 *
110 * SGPIO Configuration 0 Register
111 */
112 union bdk_sgp_cfg0
113 {
114 uint32_t u;
115 struct bdk_sgp_cfg0_s
116 {
117 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
118 uint32_t drive_cnt : 8; /**< [ 31: 24](RO) Number of supported drives.
119 Internal:
120 Corresponds to SATA(0..15). */
121 uint32_t gp_cnt : 4; /**< [ 23: 20](RO) Number of general purpose data registers. */
122 uint32_t cfg_cnt : 3; /**< [ 19: 17](RO) Number of configuration registers. */
123 uint32_t ena : 1; /**< [ 16: 16](R/W) SGPIO enable. Enables the SGPIO inputs and outputs. When zero the bus is not driven,
124 inputs are zero, and shifts do not occur. A change from enabled to disabled does not take
125 effect until the current bit-stream has completed. */
126 uint32_t ver : 4; /**< [ 15: 12](RO) Version. */
127 uint32_t reserved_0_11 : 12;
128 #else /* Word 0 - Little Endian */
129 uint32_t reserved_0_11 : 12;
130 uint32_t ver : 4; /**< [ 15: 12](RO) Version. */
131 uint32_t ena : 1; /**< [ 16: 16](R/W) SGPIO enable. Enables the SGPIO inputs and outputs. When zero the bus is not driven,
132 inputs are zero, and shifts do not occur. A change from enabled to disabled does not take
133 effect until the current bit-stream has completed. */
134 uint32_t cfg_cnt : 3; /**< [ 19: 17](RO) Number of configuration registers. */
135 uint32_t gp_cnt : 4; /**< [ 23: 20](RO) Number of general purpose data registers. */
136 uint32_t drive_cnt : 8; /**< [ 31: 24](RO) Number of supported drives.
137 Internal:
138 Corresponds to SATA(0..15). */
139 #endif /* Word 0 - End */
140 } s;
141 /* struct bdk_sgp_cfg0_s cn; */
142 };
143 typedef union bdk_sgp_cfg0 bdk_sgp_cfg0_t;
144
145 #define BDK_SGP_CFG0 BDK_SGP_CFG0_FUNC()
146 static inline uint64_t BDK_SGP_CFG0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SGP_CFG0_FUNC(void)147 static inline uint64_t BDK_SGP_CFG0_FUNC(void)
148 {
149 return 0x87e027000000ll;
150 }
151
152 #define typedef_BDK_SGP_CFG0 bdk_sgp_cfg0_t
153 #define bustype_BDK_SGP_CFG0 BDK_CSR_TYPE_RSL32b
154 #define basename_BDK_SGP_CFG0 "SGP_CFG0"
155 #define device_bar_BDK_SGP_CFG0 0x0 /* PF_BAR0 */
156 #define busnum_BDK_SGP_CFG0 0
157 #define arguments_BDK_SGP_CFG0 -1,-1,-1,-1
158
159 /**
160 * Register (RSL32b) sgp_cfg1
161 *
162 * SGPIO Configuration 1 Register
163 */
164 union bdk_sgp_cfg1
165 {
166 uint32_t u;
167 struct bdk_sgp_cfg1_s
168 {
169 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
170 uint32_t reserved_24_31 : 8;
171 uint32_t blink_b : 4; /**< [ 23: 20](R/W) Blink generator rate B. */
172 uint32_t blink_a : 4; /**< [ 19: 16](R/W) Blink generator rate A:
173 0x0 = 1/8 second.
174 0x1 = 2/8 second.
175 ...
176 0xF = 16/8 seconds. */
177 uint32_t force_off : 4; /**< [ 15: 12](R/W) Force activity off time. The minimum amount of time to disable the activity indicator if
178 it has been continually enabled for the [MAX_ON] time, and the SGP_TX()[*_ACT] is
179 0x4 or 0x5.
180 0x0 = No minimum.
181 0x1 = 1/8 second.
182 ...
183 0xF = 15/8 seconds. */
184 uint32_t max_on : 4; /**< [ 11: 8](R/W) Maximum activity on time. The maximum amount of time to enable the activity indicator if
185 SGP_TX()[*_ACT] is 0x4 or 0x5. Note all drives will not reach the [MAX_ON] time
186 simultaneously, the pattern will appear somewhat random.
187 0x0 = No maximum.
188 0x1 = 1/4 second.
189 ...
190 0xF = 15/4 seconds. */
191 uint32_t stretch_off : 4; /**< [ 7: 4](R/W) Stretch activity off. The minimum amount of time to disable the activity indicator if
192 SGP_TX()[*_ACT] is 0x4 or 0x5.
193 0x0 = No minimum.
194 0x1 = 1/64 second.
195 ...
196 0xF = 15/64 seconds. */
197 uint32_t stretch_on : 4; /**< [ 3: 0](R/W) Stretch activity on. The minimum amount of time to enable the activity indicator if
198 SGP_TX()[*_ACT] is 0x4 or 0x5.
199 0x0 = 1/64 second.
200 0x1 = 2/64 second.
201 ...
202 0xF = 16/64 seconds. */
203 #else /* Word 0 - Little Endian */
204 uint32_t stretch_on : 4; /**< [ 3: 0](R/W) Stretch activity on. The minimum amount of time to enable the activity indicator if
205 SGP_TX()[*_ACT] is 0x4 or 0x5.
206 0x0 = 1/64 second.
207 0x1 = 2/64 second.
208 ...
209 0xF = 16/64 seconds. */
210 uint32_t stretch_off : 4; /**< [ 7: 4](R/W) Stretch activity off. The minimum amount of time to disable the activity indicator if
211 SGP_TX()[*_ACT] is 0x4 or 0x5.
212 0x0 = No minimum.
213 0x1 = 1/64 second.
214 ...
215 0xF = 15/64 seconds. */
216 uint32_t max_on : 4; /**< [ 11: 8](R/W) Maximum activity on time. The maximum amount of time to enable the activity indicator if
217 SGP_TX()[*_ACT] is 0x4 or 0x5. Note all drives will not reach the [MAX_ON] time
218 simultaneously, the pattern will appear somewhat random.
219 0x0 = No maximum.
220 0x1 = 1/4 second.
221 ...
222 0xF = 15/4 seconds. */
223 uint32_t force_off : 4; /**< [ 15: 12](R/W) Force activity off time. The minimum amount of time to disable the activity indicator if
224 it has been continually enabled for the [MAX_ON] time, and the SGP_TX()[*_ACT] is
225 0x4 or 0x5.
226 0x0 = No minimum.
227 0x1 = 1/8 second.
228 ...
229 0xF = 15/8 seconds. */
230 uint32_t blink_a : 4; /**< [ 19: 16](R/W) Blink generator rate A:
231 0x0 = 1/8 second.
232 0x1 = 2/8 second.
233 ...
234 0xF = 16/8 seconds. */
235 uint32_t blink_b : 4; /**< [ 23: 20](R/W) Blink generator rate B. */
236 uint32_t reserved_24_31 : 8;
237 #endif /* Word 0 - End */
238 } s;
239 /* struct bdk_sgp_cfg1_s cn; */
240 };
241 typedef union bdk_sgp_cfg1 bdk_sgp_cfg1_t;
242
243 #define BDK_SGP_CFG1 BDK_SGP_CFG1_FUNC()
244 static inline uint64_t BDK_SGP_CFG1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SGP_CFG1_FUNC(void)245 static inline uint64_t BDK_SGP_CFG1_FUNC(void)
246 {
247 return 0x87e027000004ll;
248 }
249
250 #define typedef_BDK_SGP_CFG1 bdk_sgp_cfg1_t
251 #define bustype_BDK_SGP_CFG1 BDK_CSR_TYPE_RSL32b
252 #define basename_BDK_SGP_CFG1 "SGP_CFG1"
253 #define device_bar_BDK_SGP_CFG1 0x0 /* PF_BAR0 */
254 #define busnum_BDK_SGP_CFG1 0
255 #define arguments_BDK_SGP_CFG1 -1,-1,-1,-1
256
257 /**
258 * Register (RSL32b) sgp_imp_clk
259 *
260 * SGPIO Implementation Clock Register
261 */
262 union bdk_sgp_imp_clk
263 {
264 uint32_t u;
265 struct bdk_sgp_imp_clk_s
266 {
267 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
268 uint32_t reserved_27_31 : 5;
269 uint32_t div : 27; /**< [ 26: 0](R/W) Coprocessor-clock divisor. Number of coprocessor clock cycles per
270 GPIO_SCLOCK. May only be changed when SGP_CFG0[ENA] and SGP_IMP_CTL[BUSY] are
271 clear. Should be programmed to yield a frequency between 64 Hz and 100 kHz;
272 reset value assumes a coprocessor clock of 800 MHz and a SGPIO_SCLOCK of 100
273 KHz. */
274 #else /* Word 0 - Little Endian */
275 uint32_t div : 27; /**< [ 26: 0](R/W) Coprocessor-clock divisor. Number of coprocessor clock cycles per
276 GPIO_SCLOCK. May only be changed when SGP_CFG0[ENA] and SGP_IMP_CTL[BUSY] are
277 clear. Should be programmed to yield a frequency between 64 Hz and 100 kHz;
278 reset value assumes a coprocessor clock of 800 MHz and a SGPIO_SCLOCK of 100
279 KHz. */
280 uint32_t reserved_27_31 : 5;
281 #endif /* Word 0 - End */
282 } s;
283 /* struct bdk_sgp_imp_clk_s cn8; */
284 struct bdk_sgp_imp_clk_cn9
285 {
286 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
287 uint32_t reserved_27_31 : 5;
288 uint32_t div : 27; /**< [ 26: 0](R/W) 100 MHz reference-clock divisor. Number of 100 MHz reference clock cycles per
289 SGPIO_SCLOCK. May only be changed when SGP_CFG0[ENA] and SGP_IMP_CTL[BUSY] are
290 clear. Should be programmed to yield a frequency between 64 Hz and 100 kHz;
291 reset value assumes a SGPIO_SCLOCK of 100 KHz. */
292 #else /* Word 0 - Little Endian */
293 uint32_t div : 27; /**< [ 26: 0](R/W) 100 MHz reference-clock divisor. Number of 100 MHz reference clock cycles per
294 SGPIO_SCLOCK. May only be changed when SGP_CFG0[ENA] and SGP_IMP_CTL[BUSY] are
295 clear. Should be programmed to yield a frequency between 64 Hz and 100 kHz;
296 reset value assumes a SGPIO_SCLOCK of 100 KHz. */
297 uint32_t reserved_27_31 : 5;
298 #endif /* Word 0 - End */
299 } cn9;
300 };
301 typedef union bdk_sgp_imp_clk bdk_sgp_imp_clk_t;
302
303 #define BDK_SGP_IMP_CLK BDK_SGP_IMP_CLK_FUNC()
304 static inline uint64_t BDK_SGP_IMP_CLK_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SGP_IMP_CLK_FUNC(void)305 static inline uint64_t BDK_SGP_IMP_CLK_FUNC(void)
306 {
307 return 0x87e027030010ll;
308 }
309
310 #define typedef_BDK_SGP_IMP_CLK bdk_sgp_imp_clk_t
311 #define bustype_BDK_SGP_IMP_CLK BDK_CSR_TYPE_RSL32b
312 #define basename_BDK_SGP_IMP_CLK "SGP_IMP_CLK"
313 #define device_bar_BDK_SGP_IMP_CLK 0x0 /* PF_BAR0 */
314 #define busnum_BDK_SGP_IMP_CLK 0
315 #define arguments_BDK_SGP_IMP_CLK -1,-1,-1,-1
316
317 /**
318 * Register (RSL32b) sgp_imp_ctl
319 *
320 * SGPIO Implementation Control Register
321 */
322 union bdk_sgp_imp_ctl
323 {
324 uint32_t u;
325 struct bdk_sgp_imp_ctl_s
326 {
327 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
328 uint32_t reserved_5_31 : 27;
329 uint32_t datains : 3; /**< [ 4: 2](R/W) Number of SGP_SDATAIN connections:
330 0x0 = No SGP_SDATAIN, all input shift data will be zero.
331 0x1 = SGP_SDATAIN(0) for drives 0-15.
332 0x2 = SGP_SDATAIN(0) for drives 0-7, (1) for drives 8-15.
333 0x3 = SGP_SDATAIN(0) for drives 0-3, (1) for drives 4-7, (2) for drives 8-11, (3) for
334 drives 12-15.
335 0x4-0x7 = Reserved. */
336 uint32_t hold : 1; /**< [ 1: 1](R/W) Hold shift. When set, automatic shifts will not occur, and the SGP_TX_GP_CFG[COUNT] must
337 be used to initiate a shift operation. */
338 uint32_t busy : 1; /**< [ 0: 0](RO/H) Shift in progress. */
339 #else /* Word 0 - Little Endian */
340 uint32_t busy : 1; /**< [ 0: 0](RO/H) Shift in progress. */
341 uint32_t hold : 1; /**< [ 1: 1](R/W) Hold shift. When set, automatic shifts will not occur, and the SGP_TX_GP_CFG[COUNT] must
342 be used to initiate a shift operation. */
343 uint32_t datains : 3; /**< [ 4: 2](R/W) Number of SGP_SDATAIN connections:
344 0x0 = No SGP_SDATAIN, all input shift data will be zero.
345 0x1 = SGP_SDATAIN(0) for drives 0-15.
346 0x2 = SGP_SDATAIN(0) for drives 0-7, (1) for drives 8-15.
347 0x3 = SGP_SDATAIN(0) for drives 0-3, (1) for drives 4-7, (2) for drives 8-11, (3) for
348 drives 12-15.
349 0x4-0x7 = Reserved. */
350 uint32_t reserved_5_31 : 27;
351 #endif /* Word 0 - End */
352 } s;
353 /* struct bdk_sgp_imp_ctl_s cn8; */
354 struct bdk_sgp_imp_ctl_cn9
355 {
356 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
357 uint32_t reserved_5_31 : 27;
358 uint32_t datains : 3; /**< [ 4: 2](R/W) Number of SGPIO_SDATAIN connections:
359 0x0 = No SGPIO_SDATAIN, all input shift data will be zero.
360 0x1 = SGPIO_SDATAIN\<0\> for drives 0-19.
361 0x2 = SGPIO_SDATAIN\<0\> for drives 0-15, \<1\> for drives 16-19.
362 0x3 = SGPIO_SDATAIN\<0\> for drives 0-7, \<1\> for drives 8-15, \<2\> for drives 16-19.
363 0x4 = SGPIO_SDATAIN\<0\> for drives 0-3, \<1\> for drives 4-7, \<2\> for drives 8-11, \<3\> for
364 drives 12-15, \<4\> for drives 16-19.
365 0x5-0x7 = Reserved. */
366 uint32_t hold : 1; /**< [ 1: 1](R/W) Hold shift. When set, automatic shifts will not occur, and the SGP_TX_GP_CFG[COUNT] must
367 be used to initiate a shift operation. */
368 uint32_t busy : 1; /**< [ 0: 0](RO/H) Shift in progress. */
369 #else /* Word 0 - Little Endian */
370 uint32_t busy : 1; /**< [ 0: 0](RO/H) Shift in progress. */
371 uint32_t hold : 1; /**< [ 1: 1](R/W) Hold shift. When set, automatic shifts will not occur, and the SGP_TX_GP_CFG[COUNT] must
372 be used to initiate a shift operation. */
373 uint32_t datains : 3; /**< [ 4: 2](R/W) Number of SGPIO_SDATAIN connections:
374 0x0 = No SGPIO_SDATAIN, all input shift data will be zero.
375 0x1 = SGPIO_SDATAIN\<0\> for drives 0-19.
376 0x2 = SGPIO_SDATAIN\<0\> for drives 0-15, \<1\> for drives 16-19.
377 0x3 = SGPIO_SDATAIN\<0\> for drives 0-7, \<1\> for drives 8-15, \<2\> for drives 16-19.
378 0x4 = SGPIO_SDATAIN\<0\> for drives 0-3, \<1\> for drives 4-7, \<2\> for drives 8-11, \<3\> for
379 drives 12-15, \<4\> for drives 16-19.
380 0x5-0x7 = Reserved. */
381 uint32_t reserved_5_31 : 27;
382 #endif /* Word 0 - End */
383 } cn9;
384 };
385 typedef union bdk_sgp_imp_ctl bdk_sgp_imp_ctl_t;
386
387 #define BDK_SGP_IMP_CTL BDK_SGP_IMP_CTL_FUNC()
388 static inline uint64_t BDK_SGP_IMP_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SGP_IMP_CTL_FUNC(void)389 static inline uint64_t BDK_SGP_IMP_CTL_FUNC(void)
390 {
391 return 0x87e027030000ll;
392 }
393
394 #define typedef_BDK_SGP_IMP_CTL bdk_sgp_imp_ctl_t
395 #define bustype_BDK_SGP_IMP_CTL BDK_CSR_TYPE_RSL32b
396 #define basename_BDK_SGP_IMP_CTL "SGP_IMP_CTL"
397 #define device_bar_BDK_SGP_IMP_CTL 0x0 /* PF_BAR0 */
398 #define busnum_BDK_SGP_IMP_CTL 0
399 #define arguments_BDK_SGP_IMP_CTL -1,-1,-1,-1
400
401 /**
402 * Register (RSL32b) sgp_imp_drive#
403 *
404 * SGPIO Implementation Drive Map Register
405 */
406 union bdk_sgp_imp_drivex
407 {
408 uint32_t u;
409 struct bdk_sgp_imp_drivex_s
410 {
411 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
412 uint32_t reserved_9_31 : 23;
413 uint32_t pres_det : 1; /**< [ 8: 8](R/W) "Presence detect. If set, logically OR SGPIO_SDATAIN's ID#.0 bit with any GPIO related
414 present detect and send to the relevant SATA controller's mechanical presence detect." */
415 uint32_t reserved_5_7 : 3;
416 uint32_t ctrlr : 5; /**< [ 4: 0](R/W) SATA controller attached to this index's SGPIO drive. Indicates which SATA(0..15) connects
417 to the corresponding indexed SGPIO drive 0..15. Resets to the index number; controller 0
418 for drive 0, controller 1 for drive 1, etc.
419
420 If SGP_TX()[D0_ACT]..[D3_ACT] = SGP_TX_ACT_E::BRIEF_START or
421 SGP_TX_ACT_E::BRIEF_END, the activity input will come from SATA controller
422 number [CTRLR]. Else, the activity indication is controlled by software alone.
423
424 If [PRES_DET] is set, SATA controller number [CTRLR] will receive the indexed drive's
425 presence detect. */
426 #else /* Word 0 - Little Endian */
427 uint32_t ctrlr : 5; /**< [ 4: 0](R/W) SATA controller attached to this index's SGPIO drive. Indicates which SATA(0..15) connects
428 to the corresponding indexed SGPIO drive 0..15. Resets to the index number; controller 0
429 for drive 0, controller 1 for drive 1, etc.
430
431 If SGP_TX()[D0_ACT]..[D3_ACT] = SGP_TX_ACT_E::BRIEF_START or
432 SGP_TX_ACT_E::BRIEF_END, the activity input will come from SATA controller
433 number [CTRLR]. Else, the activity indication is controlled by software alone.
434
435 If [PRES_DET] is set, SATA controller number [CTRLR] will receive the indexed drive's
436 presence detect. */
437 uint32_t reserved_5_7 : 3;
438 uint32_t pres_det : 1; /**< [ 8: 8](R/W) "Presence detect. If set, logically OR SGPIO_SDATAIN's ID#.0 bit with any GPIO related
439 present detect and send to the relevant SATA controller's mechanical presence detect." */
440 uint32_t reserved_9_31 : 23;
441 #endif /* Word 0 - End */
442 } s;
443 struct bdk_sgp_imp_drivex_cn8
444 {
445 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
446 uint32_t reserved_9_31 : 23;
447 uint32_t pres_det : 1; /**< [ 8: 8](R/W) "Presence detect. If set, logically OR SGPIO_SDATAIN's ID#.0 bit with any GPIO related
448 present detect and send to the relevant SATA controller's mechanical presence detect." */
449 uint32_t reserved_4_7 : 4;
450 uint32_t ctrlr : 4; /**< [ 3: 0](R/W) SATA controller attached to this index's SGPIO drive. Indicates which SATA(0..15) connects
451 to the corresponding indexed SGPIO drive 0..15. Resets to the index number; controller 0
452 for drive 0, controller 1 for drive 1, etc.
453
454 If SGP_TX()[D0_ACT]..[D3_ACT] = SGP_TX_ACT_E::BRIEF_START or
455 SGP_TX_ACT_E::BRIEF_END, the activity input will come from SATA controller
456 number [CTRLR]. Else, the activity indication is controlled by software alone.
457
458 If [PRES_DET] is set, SATA controller number [CTRLR] will receive the indexed drive's
459 presence detect. */
460 #else /* Word 0 - Little Endian */
461 uint32_t ctrlr : 4; /**< [ 3: 0](R/W) SATA controller attached to this index's SGPIO drive. Indicates which SATA(0..15) connects
462 to the corresponding indexed SGPIO drive 0..15. Resets to the index number; controller 0
463 for drive 0, controller 1 for drive 1, etc.
464
465 If SGP_TX()[D0_ACT]..[D3_ACT] = SGP_TX_ACT_E::BRIEF_START or
466 SGP_TX_ACT_E::BRIEF_END, the activity input will come from SATA controller
467 number [CTRLR]. Else, the activity indication is controlled by software alone.
468
469 If [PRES_DET] is set, SATA controller number [CTRLR] will receive the indexed drive's
470 presence detect. */
471 uint32_t reserved_4_7 : 4;
472 uint32_t pres_det : 1; /**< [ 8: 8](R/W) "Presence detect. If set, logically OR SGPIO_SDATAIN's ID#.0 bit with any GPIO related
473 present detect and send to the relevant SATA controller's mechanical presence detect." */
474 uint32_t reserved_9_31 : 23;
475 #endif /* Word 0 - End */
476 } cn8;
477 struct bdk_sgp_imp_drivex_cn9
478 {
479 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
480 uint32_t reserved_9_31 : 23;
481 uint32_t pres_det : 1; /**< [ 8: 8](R/W) "Presence detect. If set, logically OR SGPIO_SDATAIN's ID#.0 bit with any GPIO related
482 present detect and send to the relevant SATA controller's mechanical presence detect." */
483 uint32_t reserved_5_7 : 3;
484 uint32_t ctrlr : 5; /**< [ 4: 0](R/W) SATA controller attached to this index's SGPIO drive. Indicates which SATA(0..19) connects
485 to the corresponding indexed SGPIO drive 0..19. Resets to the index number; controller 0
486 for drive 0, controller 1 for drive 1, etc.
487
488 If SGP_TX()[D0_ACT]..[D3_ACT] = SGP_TX_ACT_E::BRIEF_START or
489 SGP_TX_ACT_E::BRIEF_END, the activity input will come from SATA controller
490 number [CTRLR]. Else, the activity indication is controlled by software alone.
491
492 If [PRES_DET] is set, SATA controller number [CTRLR] will receive the indexed drive's
493 presence detect. */
494 #else /* Word 0 - Little Endian */
495 uint32_t ctrlr : 5; /**< [ 4: 0](R/W) SATA controller attached to this index's SGPIO drive. Indicates which SATA(0..19) connects
496 to the corresponding indexed SGPIO drive 0..19. Resets to the index number; controller 0
497 for drive 0, controller 1 for drive 1, etc.
498
499 If SGP_TX()[D0_ACT]..[D3_ACT] = SGP_TX_ACT_E::BRIEF_START or
500 SGP_TX_ACT_E::BRIEF_END, the activity input will come from SATA controller
501 number [CTRLR]. Else, the activity indication is controlled by software alone.
502
503 If [PRES_DET] is set, SATA controller number [CTRLR] will receive the indexed drive's
504 presence detect. */
505 uint32_t reserved_5_7 : 3;
506 uint32_t pres_det : 1; /**< [ 8: 8](R/W) "Presence detect. If set, logically OR SGPIO_SDATAIN's ID#.0 bit with any GPIO related
507 present detect and send to the relevant SATA controller's mechanical presence detect." */
508 uint32_t reserved_9_31 : 23;
509 #endif /* Word 0 - End */
510 } cn9;
511 };
512 typedef union bdk_sgp_imp_drivex bdk_sgp_imp_drivex_t;
513
514 static inline uint64_t BDK_SGP_IMP_DRIVEX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SGP_IMP_DRIVEX(unsigned long a)515 static inline uint64_t BDK_SGP_IMP_DRIVEX(unsigned long a)
516 {
517 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=15))
518 return 0x87e027040000ll + 8ll * ((a) & 0xf);
519 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=19))
520 return 0x87e027040000ll + 8ll * ((a) & 0x1f);
521 __bdk_csr_fatal("SGP_IMP_DRIVEX", 1, a, 0, 0, 0);
522 }
523
524 #define typedef_BDK_SGP_IMP_DRIVEX(a) bdk_sgp_imp_drivex_t
525 #define bustype_BDK_SGP_IMP_DRIVEX(a) BDK_CSR_TYPE_RSL32b
526 #define basename_BDK_SGP_IMP_DRIVEX(a) "SGP_IMP_DRIVEX"
527 #define device_bar_BDK_SGP_IMP_DRIVEX(a) 0x0 /* PF_BAR0 */
528 #define busnum_BDK_SGP_IMP_DRIVEX(a) (a)
529 #define arguments_BDK_SGP_IMP_DRIVEX(a) (a),-1,-1,-1
530
531 /**
532 * Register (RSL32b) sgp_imp_sec_clk
533 *
534 * SGPIO Implementation Seconds Clock Register
535 */
536 union bdk_sgp_imp_sec_clk
537 {
538 uint32_t u;
539 struct bdk_sgp_imp_sec_clk_s
540 {
541 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
542 uint32_t reserved_16_31 : 16;
543 uint32_t div : 16; /**< [ 15: 0](R/W) Coprocessor-clock seconds divisor. Number of GPIO_SCLOCKs per 1/64th second. May
544 only be changed when SGP_CFG0[ENA] and SGP_IMP_CTL[BUSY] are clear. Should be
545 programmed to yield a frequency of 64 Hz; reset value assumes GPIO_SCLOCK of 100
546 kHz. */
547 #else /* Word 0 - Little Endian */
548 uint32_t div : 16; /**< [ 15: 0](R/W) Coprocessor-clock seconds divisor. Number of GPIO_SCLOCKs per 1/64th second. May
549 only be changed when SGP_CFG0[ENA] and SGP_IMP_CTL[BUSY] are clear. Should be
550 programmed to yield a frequency of 64 Hz; reset value assumes GPIO_SCLOCK of 100
551 kHz. */
552 uint32_t reserved_16_31 : 16;
553 #endif /* Word 0 - End */
554 } s;
555 /* struct bdk_sgp_imp_sec_clk_s cn8; */
556 struct bdk_sgp_imp_sec_clk_cn9
557 {
558 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
559 uint32_t reserved_16_31 : 16;
560 uint32_t div : 16; /**< [ 15: 0](R/W) 100 MHz reference-clock seconds divisor. Number of SGPIO_SCLOCK cycles per 1/64th
561 second. May only be changed when SGP_CFG0[ENA] and SGP_IMP_CTL[BUSY] are
562 clear. Should be programmed to yield a frequency of 64 Hz; reset value assumes
563 SGPIO_SCLOCK of 100 kHz. */
564 #else /* Word 0 - Little Endian */
565 uint32_t div : 16; /**< [ 15: 0](R/W) 100 MHz reference-clock seconds divisor. Number of SGPIO_SCLOCK cycles per 1/64th
566 second. May only be changed when SGP_CFG0[ENA] and SGP_IMP_CTL[BUSY] are
567 clear. Should be programmed to yield a frequency of 64 Hz; reset value assumes
568 SGPIO_SCLOCK of 100 kHz. */
569 uint32_t reserved_16_31 : 16;
570 #endif /* Word 0 - End */
571 } cn9;
572 };
573 typedef union bdk_sgp_imp_sec_clk bdk_sgp_imp_sec_clk_t;
574
575 #define BDK_SGP_IMP_SEC_CLK BDK_SGP_IMP_SEC_CLK_FUNC()
576 static inline uint64_t BDK_SGP_IMP_SEC_CLK_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SGP_IMP_SEC_CLK_FUNC(void)577 static inline uint64_t BDK_SGP_IMP_SEC_CLK_FUNC(void)
578 {
579 return 0x87e027030020ll;
580 }
581
582 #define typedef_BDK_SGP_IMP_SEC_CLK bdk_sgp_imp_sec_clk_t
583 #define bustype_BDK_SGP_IMP_SEC_CLK BDK_CSR_TYPE_RSL32b
584 #define basename_BDK_SGP_IMP_SEC_CLK "SGP_IMP_SEC_CLK"
585 #define device_bar_BDK_SGP_IMP_SEC_CLK 0x0 /* PF_BAR0 */
586 #define busnum_BDK_SGP_IMP_SEC_CLK 0
587 #define arguments_BDK_SGP_IMP_SEC_CLK -1,-1,-1,-1
588
589 /**
590 * Register (RSL32b) sgp_rx#
591 *
592 * SGPIO Receive Registers
593 */
594 union bdk_sgp_rxx
595 {
596 uint32_t u;
597 struct bdk_sgp_rxx_s
598 {
599 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
600 uint32_t reserved_27_31 : 5;
601 uint32_t rx3 : 3; /**< [ 26: 24](RO/H) Three bits received on SGPIO_SDATAIN corresponding to drive 3+4*index. */
602 uint32_t reserved_19_23 : 5;
603 uint32_t rx2 : 3; /**< [ 18: 16](RO/H) Three bits received on SGPIO_SDATAIN corresponding to drive 2+4*index. */
604 uint32_t reserved_11_15 : 5;
605 uint32_t rx1 : 3; /**< [ 10: 8](RO/H) Three bits received on SGPIO_SDATAIN corresponding to drive 1+4*index. */
606 uint32_t reserved_3_7 : 5;
607 uint32_t rx0 : 3; /**< [ 2: 0](RO/H) Three bits received on SGPIO_SDATAIN corresponding to drive 0+4*index. */
608 #else /* Word 0 - Little Endian */
609 uint32_t rx0 : 3; /**< [ 2: 0](RO/H) Three bits received on SGPIO_SDATAIN corresponding to drive 0+4*index. */
610 uint32_t reserved_3_7 : 5;
611 uint32_t rx1 : 3; /**< [ 10: 8](RO/H) Three bits received on SGPIO_SDATAIN corresponding to drive 1+4*index. */
612 uint32_t reserved_11_15 : 5;
613 uint32_t rx2 : 3; /**< [ 18: 16](RO/H) Three bits received on SGPIO_SDATAIN corresponding to drive 2+4*index. */
614 uint32_t reserved_19_23 : 5;
615 uint32_t rx3 : 3; /**< [ 26: 24](RO/H) Three bits received on SGPIO_SDATAIN corresponding to drive 3+4*index. */
616 uint32_t reserved_27_31 : 5;
617 #endif /* Word 0 - End */
618 } s;
619 /* struct bdk_sgp_rxx_s cn; */
620 };
621 typedef union bdk_sgp_rxx bdk_sgp_rxx_t;
622
623 static inline uint64_t BDK_SGP_RXX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SGP_RXX(unsigned long a)624 static inline uint64_t BDK_SGP_RXX(unsigned long a)
625 {
626 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=3))
627 return 0x87e027000400ll + 4ll * ((a) & 0x3);
628 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
629 return 0x87e027000400ll + 4ll * ((a) & 0x7);
630 __bdk_csr_fatal("SGP_RXX", 1, a, 0, 0, 0);
631 }
632
633 #define typedef_BDK_SGP_RXX(a) bdk_sgp_rxx_t
634 #define bustype_BDK_SGP_RXX(a) BDK_CSR_TYPE_RSL32b
635 #define basename_BDK_SGP_RXX(a) "SGP_RXX"
636 #define device_bar_BDK_SGP_RXX(a) 0x0 /* PF_BAR0 */
637 #define busnum_BDK_SGP_RXX(a) (a)
638 #define arguments_BDK_SGP_RXX(a) (a),-1,-1,-1
639
640 /**
641 * Register (RSL32b) sgp_rx_gp#
642 *
643 * SGPIO Receive GPIO Registers
644 */
645 union bdk_sgp_rx_gpx
646 {
647 uint32_t u;
648 struct bdk_sgp_rx_gpx_s
649 {
650 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
651 uint32_t sdatain3 : 8; /**< [ 31: 24](RO/H) See [SDATAIN0]. */
652 uint32_t sdatain2 : 8; /**< [ 23: 16](RO/H) See [SDATAIN0]. */
653 uint32_t sdatain1 : 8; /**< [ 15: 8](RO/H) See [SDATAIN0]. */
654 uint32_t sdatain0 : 8; /**< [ 7: 0](RO/H) Raw data shifted from SGPIO_SDATAIN. The bits are not in natural 32-bit form; they are
655 assigned to registers as follows:
656 _ Bit 0 (ID0.0): SGP_RX_GP(1)[SDATAIN3]\<0\>.
657 _ Bit 8 (ID2.2): SGP_RX_GP(1)[SDATAIN2]\<0\>.
658 _ Bit 16 (ID5.1): SGP_RX_GP(1)[SDATAIN1]\<0\>.
659 _ Bit 24 (ID8.0): SGP_RX_GP(1)[SDATAIN0]\<0\>.
660 _ Bit 32 (ID10.2): SGP_RX_GP(2)[SDATAIN3]\<0\>.
661 _ Bit 40 (ID13.1): SGP_RX_GP(2)[SDATAIN2]\<0\>.
662 _ Bit 47 (ID15.2): SGP_RX_GP(2)[SDATAIN2]\<7\>.
663
664 SGP_RX_GP(2)[SDATAIN1/SDATAIN0] are always zero. */
665 #else /* Word 0 - Little Endian */
666 uint32_t sdatain0 : 8; /**< [ 7: 0](RO/H) Raw data shifted from SGPIO_SDATAIN. The bits are not in natural 32-bit form; they are
667 assigned to registers as follows:
668 _ Bit 0 (ID0.0): SGP_RX_GP(1)[SDATAIN3]\<0\>.
669 _ Bit 8 (ID2.2): SGP_RX_GP(1)[SDATAIN2]\<0\>.
670 _ Bit 16 (ID5.1): SGP_RX_GP(1)[SDATAIN1]\<0\>.
671 _ Bit 24 (ID8.0): SGP_RX_GP(1)[SDATAIN0]\<0\>.
672 _ Bit 32 (ID10.2): SGP_RX_GP(2)[SDATAIN3]\<0\>.
673 _ Bit 40 (ID13.1): SGP_RX_GP(2)[SDATAIN2]\<0\>.
674 _ Bit 47 (ID15.2): SGP_RX_GP(2)[SDATAIN2]\<7\>.
675
676 SGP_RX_GP(2)[SDATAIN1/SDATAIN0] are always zero. */
677 uint32_t sdatain1 : 8; /**< [ 15: 8](RO/H) See [SDATAIN0]. */
678 uint32_t sdatain2 : 8; /**< [ 23: 16](RO/H) See [SDATAIN0]. */
679 uint32_t sdatain3 : 8; /**< [ 31: 24](RO/H) See [SDATAIN0]. */
680 #endif /* Word 0 - End */
681 } s;
682 /* struct bdk_sgp_rx_gpx_s cn8; */
683 struct bdk_sgp_rx_gpx_cn9
684 {
685 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
686 uint32_t sdatain3 : 8; /**< [ 31: 24](RO/H) See [SDATAIN0]. */
687 uint32_t sdatain2 : 8; /**< [ 23: 16](RO/H) See [SDATAIN0]. */
688 uint32_t sdatain1 : 8; /**< [ 15: 8](RO/H) See [SDATAIN0]. */
689 uint32_t sdatain0 : 8; /**< [ 7: 0](RO/H) Raw data shifted from SGPIO_SDATAIN. The bits are not in natural 32-bit form; they are
690 assigned to registers as follows:
691 _ Bit 0 (ID0.0): SGP_RX_GP(1)[SDATAIN3]\<0\>.
692 _ Bit 8 (ID2.2): SGP_RX_GP(1)[SDATAIN2]\<0\>.
693 _ Bit 16 (ID5.1): SGP_RX_GP(1)[SDATAIN1]\<0\>.
694 _ Bit 24 (ID8.0): SGP_RX_GP(1)[SDATAIN0]\<0\>.
695 _ Bit 32 (ID10.2): SGP_RX_GP(2)[SDATAIN3]\<0\>.
696 _ Bit 40 (ID13.1): SGP_RX_GP(2)[SDATAIN2]\<0\>.
697 _ Bit 48 (ID16.0): SGP_RX_GP(2)[SDATAIN1]\<0\>.
698 _ Bit 56 (ID18.2): SGP_RX_GP(2)[SDATAIN0]\<0\>.
699 _ Bit 59 (ID19.2): SGP_RX_GP(2)[SDATAIN0]\<3\>. */
700 #else /* Word 0 - Little Endian */
701 uint32_t sdatain0 : 8; /**< [ 7: 0](RO/H) Raw data shifted from SGPIO_SDATAIN. The bits are not in natural 32-bit form; they are
702 assigned to registers as follows:
703 _ Bit 0 (ID0.0): SGP_RX_GP(1)[SDATAIN3]\<0\>.
704 _ Bit 8 (ID2.2): SGP_RX_GP(1)[SDATAIN2]\<0\>.
705 _ Bit 16 (ID5.1): SGP_RX_GP(1)[SDATAIN1]\<0\>.
706 _ Bit 24 (ID8.0): SGP_RX_GP(1)[SDATAIN0]\<0\>.
707 _ Bit 32 (ID10.2): SGP_RX_GP(2)[SDATAIN3]\<0\>.
708 _ Bit 40 (ID13.1): SGP_RX_GP(2)[SDATAIN2]\<0\>.
709 _ Bit 48 (ID16.0): SGP_RX_GP(2)[SDATAIN1]\<0\>.
710 _ Bit 56 (ID18.2): SGP_RX_GP(2)[SDATAIN0]\<0\>.
711 _ Bit 59 (ID19.2): SGP_RX_GP(2)[SDATAIN0]\<3\>. */
712 uint32_t sdatain1 : 8; /**< [ 15: 8](RO/H) See [SDATAIN0]. */
713 uint32_t sdatain2 : 8; /**< [ 23: 16](RO/H) See [SDATAIN0]. */
714 uint32_t sdatain3 : 8; /**< [ 31: 24](RO/H) See [SDATAIN0]. */
715 #endif /* Word 0 - End */
716 } cn9;
717 };
718 typedef union bdk_sgp_rx_gpx bdk_sgp_rx_gpx_t;
719
720 static inline uint64_t BDK_SGP_RX_GPX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SGP_RX_GPX(unsigned long a)721 static inline uint64_t BDK_SGP_RX_GPX(unsigned long a)
722 {
723 if ((a>=1)&&(a<=2))
724 return 0x87e027000800ll + 4ll * ((a) & 0x3);
725 __bdk_csr_fatal("SGP_RX_GPX", 1, a, 0, 0, 0);
726 }
727
728 #define typedef_BDK_SGP_RX_GPX(a) bdk_sgp_rx_gpx_t
729 #define bustype_BDK_SGP_RX_GPX(a) BDK_CSR_TYPE_RSL32b
730 #define basename_BDK_SGP_RX_GPX(a) "SGP_RX_GPX"
731 #define device_bar_BDK_SGP_RX_GPX(a) 0x0 /* PF_BAR0 */
732 #define busnum_BDK_SGP_RX_GPX(a) (a)
733 #define arguments_BDK_SGP_RX_GPX(a) (a),-1,-1,-1
734
735 /**
736 * Register (RSL32b) sgp_rx_gp_cfg
737 *
738 * SGPIO Receive GPIO Configuration Register
739 */
740 union bdk_sgp_rx_gp_cfg
741 {
742 uint32_t u;
743 struct bdk_sgp_rx_gp_cfg_s
744 {
745 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
746 uint32_t reserved_24_31 : 8;
747 uint32_t count : 8; /**< [ 23: 16](RO/H) Number of repetitions remaining. A [COUNT] of 0xFF indicates infinite repetitions are remaining. */
748 uint32_t reserved_0_15 : 16;
749 #else /* Word 0 - Little Endian */
750 uint32_t reserved_0_15 : 16;
751 uint32_t count : 8; /**< [ 23: 16](RO/H) Number of repetitions remaining. A [COUNT] of 0xFF indicates infinite repetitions are remaining. */
752 uint32_t reserved_24_31 : 8;
753 #endif /* Word 0 - End */
754 } s;
755 /* struct bdk_sgp_rx_gp_cfg_s cn; */
756 };
757 typedef union bdk_sgp_rx_gp_cfg bdk_sgp_rx_gp_cfg_t;
758
759 #define BDK_SGP_RX_GP_CFG BDK_SGP_RX_GP_CFG_FUNC()
760 static inline uint64_t BDK_SGP_RX_GP_CFG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SGP_RX_GP_CFG_FUNC(void)761 static inline uint64_t BDK_SGP_RX_GP_CFG_FUNC(void)
762 {
763 return 0x87e027000800ll;
764 }
765
766 #define typedef_BDK_SGP_RX_GP_CFG bdk_sgp_rx_gp_cfg_t
767 #define bustype_BDK_SGP_RX_GP_CFG BDK_CSR_TYPE_RSL32b
768 #define basename_BDK_SGP_RX_GP_CFG "SGP_RX_GP_CFG"
769 #define device_bar_BDK_SGP_RX_GP_CFG 0x0 /* PF_BAR0 */
770 #define busnum_BDK_SGP_RX_GP_CFG 0
771 #define arguments_BDK_SGP_RX_GP_CFG -1,-1,-1,-1
772
773 /**
774 * Register (RSL32b) sgp_tx#
775 *
776 * SGPIO Transmit Registers
777 */
778 union bdk_sgp_txx
779 {
780 uint32_t u;
781 struct bdk_sgp_txx_s
782 {
783 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
784 uint32_t d3_act : 3; /**< [ 31: 29](R/W) Drive 3+4*index's activity state. */
785 uint32_t d3_loc : 2; /**< [ 28: 27](R/W) Drive 3+4*index's locate state. */
786 uint32_t d3_err : 3; /**< [ 26: 24](R/W) Drive 3+4*index's error state. */
787 uint32_t d2_act : 3; /**< [ 23: 21](R/W) Drive 2+4*index's activity state. */
788 uint32_t d2_loc : 2; /**< [ 20: 19](R/W) Drive 2+4*index's locate state. */
789 uint32_t d2_err : 3; /**< [ 18: 16](R/W) Drive 2+4*index's error state. */
790 uint32_t d1_act : 3; /**< [ 15: 13](R/W) Drive 1+4*index's activity state. */
791 uint32_t d1_loc : 2; /**< [ 12: 11](R/W) Drive 1+4*index's locate state. */
792 uint32_t d1_err : 3; /**< [ 10: 8](R/W) Drive 1+4*index's error state. */
793 uint32_t d0_act : 3; /**< [ 7: 5](R/W) Drive 0+4*index's activity state, enumerated by SGP_TX_ACT_E. */
794 uint32_t d0_loc : 2; /**< [ 4: 3](R/W) Drive 0+4*index's locate state, enumerated by SGP_TX_LOC_E. */
795 uint32_t d0_err : 3; /**< [ 2: 0](R/W) Drive 0+4*index's error state, enumerated by SGP_TX_ERR_E. */
796 #else /* Word 0 - Little Endian */
797 uint32_t d0_err : 3; /**< [ 2: 0](R/W) Drive 0+4*index's error state, enumerated by SGP_TX_ERR_E. */
798 uint32_t d0_loc : 2; /**< [ 4: 3](R/W) Drive 0+4*index's locate state, enumerated by SGP_TX_LOC_E. */
799 uint32_t d0_act : 3; /**< [ 7: 5](R/W) Drive 0+4*index's activity state, enumerated by SGP_TX_ACT_E. */
800 uint32_t d1_err : 3; /**< [ 10: 8](R/W) Drive 1+4*index's error state. */
801 uint32_t d1_loc : 2; /**< [ 12: 11](R/W) Drive 1+4*index's locate state. */
802 uint32_t d1_act : 3; /**< [ 15: 13](R/W) Drive 1+4*index's activity state. */
803 uint32_t d2_err : 3; /**< [ 18: 16](R/W) Drive 2+4*index's error state. */
804 uint32_t d2_loc : 2; /**< [ 20: 19](R/W) Drive 2+4*index's locate state. */
805 uint32_t d2_act : 3; /**< [ 23: 21](R/W) Drive 2+4*index's activity state. */
806 uint32_t d3_err : 3; /**< [ 26: 24](R/W) Drive 3+4*index's error state. */
807 uint32_t d3_loc : 2; /**< [ 28: 27](R/W) Drive 3+4*index's locate state. */
808 uint32_t d3_act : 3; /**< [ 31: 29](R/W) Drive 3+4*index's activity state. */
809 #endif /* Word 0 - End */
810 } s;
811 /* struct bdk_sgp_txx_s cn; */
812 };
813 typedef union bdk_sgp_txx bdk_sgp_txx_t;
814
815 static inline uint64_t BDK_SGP_TXX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SGP_TXX(unsigned long a)816 static inline uint64_t BDK_SGP_TXX(unsigned long a)
817 {
818 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=3))
819 return 0x87e027000c00ll + 4ll * ((a) & 0x3);
820 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
821 return 0x87e027000c00ll + 4ll * ((a) & 0x7);
822 __bdk_csr_fatal("SGP_TXX", 1, a, 0, 0, 0);
823 }
824
825 #define typedef_BDK_SGP_TXX(a) bdk_sgp_txx_t
826 #define bustype_BDK_SGP_TXX(a) BDK_CSR_TYPE_RSL32b
827 #define basename_BDK_SGP_TXX(a) "SGP_TXX"
828 #define device_bar_BDK_SGP_TXX(a) 0x0 /* PF_BAR0 */
829 #define busnum_BDK_SGP_TXX(a) (a)
830 #define arguments_BDK_SGP_TXX(a) (a),-1,-1,-1
831
832 /**
833 * Register (RSL32b) sgp_tx_gp#
834 *
835 * SGPIO Transmit GPIO Registers
836 */
837 union bdk_sgp_tx_gpx
838 {
839 uint32_t u;
840 struct bdk_sgp_tx_gpx_s
841 {
842 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
843 uint32_t sdataout3 : 8; /**< [ 31: 24](R/W) See [SDATAOUT0]. */
844 uint32_t sdataout2 : 8; /**< [ 23: 16](R/W) See [SDATAOUT0]. */
845 uint32_t sdataout1 : 8; /**< [ 15: 8](R/W) See [SDATAOUT0]. */
846 uint32_t sdataout0 : 8; /**< [ 7: 0](R/W) Raw data to shift onto SGPIO_SDATAOUT. The bits are not in natural 32-bit form; they are
847 assigned to registers as follows:
848 _ Bit 0 (ID0.0): SGP_TX_GP(1)[SDATAOUT3]\<0\>.
849 _ Bit 8 (ID2.2): SGP_TX_GP(1)[SDATAOUT2]\<0\>.
850 _ Bit 16 (ID5.1): SGP_TX_GP(1)[SDATAOUT1]\<0\>.
851 _ Bit 24 (ID8.0): SGP_TX_GP(1)[SDATAOUT0]\<0\>.
852 _ Bit 32 (ID10.2): SGP_TX_GP(2)[SDATAOUT3]\<0\>.
853 _ Bit 40 (ID13.1): SGP_TX_GP(2)[SDATAOUT2]\<0\>.
854 _ Bit 47 (ID15.2): SGP_TX_GP(2)[SDATAOUT2]\<7\>.
855
856 SGP_TX_GP(2)[SDATAOUT1/SDATAOUT0] are ignored. */
857 #else /* Word 0 - Little Endian */
858 uint32_t sdataout0 : 8; /**< [ 7: 0](R/W) Raw data to shift onto SGPIO_SDATAOUT. The bits are not in natural 32-bit form; they are
859 assigned to registers as follows:
860 _ Bit 0 (ID0.0): SGP_TX_GP(1)[SDATAOUT3]\<0\>.
861 _ Bit 8 (ID2.2): SGP_TX_GP(1)[SDATAOUT2]\<0\>.
862 _ Bit 16 (ID5.1): SGP_TX_GP(1)[SDATAOUT1]\<0\>.
863 _ Bit 24 (ID8.0): SGP_TX_GP(1)[SDATAOUT0]\<0\>.
864 _ Bit 32 (ID10.2): SGP_TX_GP(2)[SDATAOUT3]\<0\>.
865 _ Bit 40 (ID13.1): SGP_TX_GP(2)[SDATAOUT2]\<0\>.
866 _ Bit 47 (ID15.2): SGP_TX_GP(2)[SDATAOUT2]\<7\>.
867
868 SGP_TX_GP(2)[SDATAOUT1/SDATAOUT0] are ignored. */
869 uint32_t sdataout1 : 8; /**< [ 15: 8](R/W) See [SDATAOUT0]. */
870 uint32_t sdataout2 : 8; /**< [ 23: 16](R/W) See [SDATAOUT0]. */
871 uint32_t sdataout3 : 8; /**< [ 31: 24](R/W) See [SDATAOUT0]. */
872 #endif /* Word 0 - End */
873 } s;
874 /* struct bdk_sgp_tx_gpx_s cn8; */
875 struct bdk_sgp_tx_gpx_cn9
876 {
877 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
878 uint32_t sdataout3 : 8; /**< [ 31: 24](R/W) See [SDATAOUT0]. */
879 uint32_t sdataout2 : 8; /**< [ 23: 16](R/W) See [SDATAOUT0]. */
880 uint32_t sdataout1 : 8; /**< [ 15: 8](R/W) See [SDATAOUT0]. */
881 uint32_t sdataout0 : 8; /**< [ 7: 0](R/W) Raw data to shift onto SGPIO_SDATAOUT. The bits are not in natural 32-bit form; they are
882 assigned to registers as follows:
883 _ Bit 0 (ID0.0): SGP_TX_GP(1)[SDATAOUT3]\<0\>.
884 _ Bit 8 (ID2.2): SGP_TX_GP(1)[SDATAOUT2]\<0\>.
885 _ Bit 16 (ID5.1): SGP_TX_GP(1)[SDATAOUT1]\<0\>.
886 _ Bit 24 (ID8.0): SGP_TX_GP(1)[SDATAOUT0]\<0\>.
887 _ Bit 32 (ID10.2): SGP_TX_GP(2)[SDATAOUT3]\<0\>.
888 _ Bit 40 (ID13.1): SGP_TX_GP(2)[SDATAOUT2]\<0\>.
889 _ Bit 47 (ID15.2): SGP_TX_GP(2)[SDATAOUT2]\<7\>.
890 _ Bit 48 (ID16.0): SGP_TX_GP(2)[SDATAOUT1]\<0\>.
891 _ Bit 56 (ID18.2): SGP_TX_GP(2)[SDATAOUT0]\<0\>.
892 _ Bit 59 (ID19.2): SGP_TX_GP(2)[SDATAOUT0]\<3\>. */
893 #else /* Word 0 - Little Endian */
894 uint32_t sdataout0 : 8; /**< [ 7: 0](R/W) Raw data to shift onto SGPIO_SDATAOUT. The bits are not in natural 32-bit form; they are
895 assigned to registers as follows:
896 _ Bit 0 (ID0.0): SGP_TX_GP(1)[SDATAOUT3]\<0\>.
897 _ Bit 8 (ID2.2): SGP_TX_GP(1)[SDATAOUT2]\<0\>.
898 _ Bit 16 (ID5.1): SGP_TX_GP(1)[SDATAOUT1]\<0\>.
899 _ Bit 24 (ID8.0): SGP_TX_GP(1)[SDATAOUT0]\<0\>.
900 _ Bit 32 (ID10.2): SGP_TX_GP(2)[SDATAOUT3]\<0\>.
901 _ Bit 40 (ID13.1): SGP_TX_GP(2)[SDATAOUT2]\<0\>.
902 _ Bit 47 (ID15.2): SGP_TX_GP(2)[SDATAOUT2]\<7\>.
903 _ Bit 48 (ID16.0): SGP_TX_GP(2)[SDATAOUT1]\<0\>.
904 _ Bit 56 (ID18.2): SGP_TX_GP(2)[SDATAOUT0]\<0\>.
905 _ Bit 59 (ID19.2): SGP_TX_GP(2)[SDATAOUT0]\<3\>. */
906 uint32_t sdataout1 : 8; /**< [ 15: 8](R/W) See [SDATAOUT0]. */
907 uint32_t sdataout2 : 8; /**< [ 23: 16](R/W) See [SDATAOUT0]. */
908 uint32_t sdataout3 : 8; /**< [ 31: 24](R/W) See [SDATAOUT0]. */
909 #endif /* Word 0 - End */
910 } cn9;
911 };
912 typedef union bdk_sgp_tx_gpx bdk_sgp_tx_gpx_t;
913
914 static inline uint64_t BDK_SGP_TX_GPX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SGP_TX_GPX(unsigned long a)915 static inline uint64_t BDK_SGP_TX_GPX(unsigned long a)
916 {
917 if ((a>=1)&&(a<=2))
918 return 0x87e027001000ll + 4ll * ((a) & 0x3);
919 __bdk_csr_fatal("SGP_TX_GPX", 1, a, 0, 0, 0);
920 }
921
922 #define typedef_BDK_SGP_TX_GPX(a) bdk_sgp_tx_gpx_t
923 #define bustype_BDK_SGP_TX_GPX(a) BDK_CSR_TYPE_RSL32b
924 #define basename_BDK_SGP_TX_GPX(a) "SGP_TX_GPX"
925 #define device_bar_BDK_SGP_TX_GPX(a) 0x0 /* PF_BAR0 */
926 #define busnum_BDK_SGP_TX_GPX(a) (a)
927 #define arguments_BDK_SGP_TX_GPX(a) (a),-1,-1,-1
928
929 /**
930 * Register (RSL32b) sgp_tx_gp_cfg
931 *
932 * SGPIO Transmit GPIO Configuration Register
933 */
934 union bdk_sgp_tx_gp_cfg
935 {
936 uint32_t u;
937 struct bdk_sgp_tx_gp_cfg_s
938 {
939 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
940 uint32_t reserved_28_31 : 4;
941 uint32_t sload : 4; /**< [ 27: 24](R/W) Pattern to transmit on SGPIO_SLOAD at the start of each general purpose bit stream.
942 [SLOAD]\<0\> is the first bit (L0), \<3\> is the last bit (L3). */
943 uint32_t count : 8; /**< [ 23: 16](R/W) Number of times to transmit the SGP_TX_GP(1..2) pattern and receive
944 into SGP_RX_GP(1..2). A [COUNT] of 0xFF transmits continuously until [COUNT] is set to
945 non-0xFF. */
946 uint32_t reserved_0_15 : 16;
947 #else /* Word 0 - Little Endian */
948 uint32_t reserved_0_15 : 16;
949 uint32_t count : 8; /**< [ 23: 16](R/W) Number of times to transmit the SGP_TX_GP(1..2) pattern and receive
950 into SGP_RX_GP(1..2). A [COUNT] of 0xFF transmits continuously until [COUNT] is set to
951 non-0xFF. */
952 uint32_t sload : 4; /**< [ 27: 24](R/W) Pattern to transmit on SGPIO_SLOAD at the start of each general purpose bit stream.
953 [SLOAD]\<0\> is the first bit (L0), \<3\> is the last bit (L3). */
954 uint32_t reserved_28_31 : 4;
955 #endif /* Word 0 - End */
956 } s;
957 /* struct bdk_sgp_tx_gp_cfg_s cn; */
958 };
959 typedef union bdk_sgp_tx_gp_cfg bdk_sgp_tx_gp_cfg_t;
960
961 #define BDK_SGP_TX_GP_CFG BDK_SGP_TX_GP_CFG_FUNC()
962 static inline uint64_t BDK_SGP_TX_GP_CFG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SGP_TX_GP_CFG_FUNC(void)963 static inline uint64_t BDK_SGP_TX_GP_CFG_FUNC(void)
964 {
965 return 0x87e027001000ll;
966 }
967
968 #define typedef_BDK_SGP_TX_GP_CFG bdk_sgp_tx_gp_cfg_t
969 #define bustype_BDK_SGP_TX_GP_CFG BDK_CSR_TYPE_RSL32b
970 #define basename_BDK_SGP_TX_GP_CFG "SGP_TX_GP_CFG"
971 #define device_bar_BDK_SGP_TX_GP_CFG 0x0 /* PF_BAR0 */
972 #define busnum_BDK_SGP_TX_GP_CFG 0
973 #define arguments_BDK_SGP_TX_GP_CFG -1,-1,-1,-1
974
975 #endif /* __BDK_CSRS_SGP_H__ */
976