1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef __SOC_TI_AM335X_PINMUX_H 4 #define __SOC_TI_AM335X_PINMUX_H 5 6 #include <stdint.h> 7 8 // PAD Control Fields 9 #define SLEWCTRL (0x1 << 6) 10 #define RXACTIVE (0x1 << 5) 11 #define PULLDOWN_EN (0x0 << 4) // Pull down 12 #define PULLUP_EN (0x1 << 4) // Pull up 13 #define PULLUDEN (0x0 << 3) // Pull up enabled 14 #define PULLUDDIS (0x1 << 3) // Pull up disabled 15 #define MODE(val) val 16 17 void am335x_pinmux_uart0(void); 18 void am335x_pinmux_uart1(void); 19 void am335x_pinmux_uart2(void); 20 void am335x_pinmux_uart3(void); 21 void am335x_pinmux_uart4(void); 22 void am335x_pinmux_uart5(void); 23 24 void am335x_pinmux_mmc0(int cd, int sk_evm); 25 void am335x_pinmux_mmc1(void); 26 27 void am335x_pinmux_i2c0(void); 28 void am335x_pinmux_i2c1(void); 29 30 void am335x_pinmux_spi0(void); 31 32 void am335x_pinmux_gpio0_7(void); 33 34 void am335x_pinmux_rgmii1(void); 35 void am335x_pinmux_mii1(void); 36 37 void am335x_pinmux_nand(void); 38 39 #define AM335X_PINMUX_REG_ADDR 0x44e10800 40 41 struct am335x_pinmux_regs { 42 uint32_t gpmc_ad0; 43 uint32_t gpmc_ad1; 44 uint32_t gpmc_ad2; 45 uint32_t gpmc_ad3; 46 uint32_t gpmc_ad4; 47 uint32_t gpmc_ad5; 48 uint32_t gpmc_ad6; 49 uint32_t gpmc_ad7; 50 uint32_t gpmc_ad8; 51 uint32_t gpmc_ad9; 52 uint32_t gpmc_ad10; 53 uint32_t gpmc_ad11; 54 uint32_t gpmc_ad12; 55 uint32_t gpmc_ad13; 56 uint32_t gpmc_ad14; 57 uint32_t gpmc_ad15; 58 uint32_t gpmc_a0; 59 uint32_t gpmc_a1; 60 uint32_t gpmc_a2; 61 uint32_t gpmc_a3; 62 uint32_t gpmc_a4; 63 uint32_t gpmc_a5; 64 uint32_t gpmc_a6; 65 uint32_t gpmc_a7; 66 uint32_t gpmc_a8; 67 uint32_t gpmc_a9; 68 uint32_t gpmc_a10; 69 uint32_t gpmc_a11; 70 uint32_t gpmc_wait0; 71 uint32_t gpmc_wpn; 72 uint32_t gpmc_be1n; 73 uint32_t gpmc_csn0; 74 uint32_t gpmc_csn1; 75 uint32_t gpmc_csn2; 76 uint32_t gpmc_csn3; 77 uint32_t gpmc_clk; 78 uint32_t gpmc_advn_ale; 79 uint32_t gpmc_oen_ren; 80 uint32_t gpmc_wen; 81 uint32_t gpmc_be0n_cle; 82 uint32_t lcd_data0; 83 uint32_t lcd_data1; 84 uint32_t lcd_data2; 85 uint32_t lcd_data3; 86 uint32_t lcd_data4; 87 uint32_t lcd_data5; 88 uint32_t lcd_data6; 89 uint32_t lcd_data7; 90 uint32_t lcd_data8; 91 uint32_t lcd_data9; 92 uint32_t lcd_data10; 93 uint32_t lcd_data11; 94 uint32_t lcd_data12; 95 uint32_t lcd_data13; 96 uint32_t lcd_data14; 97 uint32_t lcd_data15; 98 uint32_t lcd_vsync; 99 uint32_t lcd_hsync; 100 uint32_t lcd_pclk; 101 uint32_t lcd_ac_bias_en; 102 uint32_t mmc0_dat3; 103 uint32_t mmc0_dat2; 104 uint32_t mmc0_dat1; 105 uint32_t mmc0_dat0; 106 uint32_t mmc0_clk; 107 uint32_t mmc0_cmd; 108 uint32_t mii1_col; 109 uint32_t mii1_crs; 110 uint32_t mii1_rxerr; 111 uint32_t mii1_txen; 112 uint32_t mii1_rxdv; 113 uint32_t mii1_txd3; 114 uint32_t mii1_txd2; 115 uint32_t mii1_txd1; 116 uint32_t mii1_txd0; 117 uint32_t mii1_txclk; 118 uint32_t mii1_rxclk; 119 uint32_t mii1_rxd3; 120 uint32_t mii1_rxd2; 121 uint32_t mii1_rxd1; 122 uint32_t mii1_rxd0; 123 uint32_t rmii1_refclk; 124 uint32_t mdio_data; 125 uint32_t mdio_clk; 126 uint32_t spi0_sclk; 127 uint32_t spi0_d0; 128 uint32_t spi0_d1; 129 uint32_t spi0_cs0; 130 uint32_t spi0_cs1; 131 uint32_t ecap0_in_pwm0_out; 132 uint32_t uart0_ctsn; 133 uint32_t uart0_rtsn; 134 uint32_t uart0_rxd; 135 uint32_t uart0_txd; 136 uint32_t uart1_ctsn; 137 uint32_t uart1_rtsn; 138 uint32_t uart1_rxd; 139 uint32_t uart1_txd; 140 uint32_t i2c0_sda; 141 uint32_t i2c0_scl; 142 uint32_t mcasp0_aclkx; 143 uint32_t mcasp0_fsx; 144 uint32_t mcasp0_axr0; 145 uint32_t mcasp0_ahclkr; 146 uint32_t mcasp0_aclkr; 147 uint32_t mcasp0_fsr; 148 uint32_t mcasp0_axr1; 149 uint32_t mcasp0_ahclkx; 150 uint32_t xdma_event_intr0; 151 uint32_t xdma_event_intr1; 152 uint32_t nresetin_out; 153 uint32_t porz; 154 uint32_t nnmi; 155 uint32_t osc0_in; 156 uint32_t osc0_out; 157 uint32_t rsvd1; 158 uint32_t tms; 159 uint32_t tdi; 160 uint32_t tdo; 161 uint32_t tck; 162 uint32_t ntrst; 163 uint32_t emu0; 164 uint32_t emu1; 165 uint32_t osc1_in; 166 uint32_t osc1_out; 167 uint32_t pmic_power_en; 168 uint32_t rtc_porz; 169 uint32_t rsvd2; 170 uint32_t ext_wakeup; 171 uint32_t enz_kaldo_1p8v; 172 uint32_t usb0_dm; 173 uint32_t usb0_dp; 174 uint32_t usb0_ce; 175 uint32_t usb0_id; 176 uint32_t usb0_vbus; 177 uint32_t usb0_drvvbus; 178 uint32_t usb1_dm; 179 uint32_t usb1_dp; 180 uint32_t usb1_ce; 181 uint32_t usb1_id; 182 uint32_t usb1_vbus; 183 uint32_t usb1_drvvbus; 184 uint32_t ddr_resetn; 185 uint32_t ddr_csn0; 186 uint32_t ddr_cke; 187 uint32_t ddr_ck; 188 uint32_t ddr_nck; 189 uint32_t ddr_casn; 190 uint32_t ddr_rasn; 191 uint32_t ddr_wen; 192 uint32_t ddr_ba0; 193 uint32_t ddr_ba1; 194 uint32_t ddr_ba2; 195 uint32_t ddr_a0; 196 uint32_t ddr_a1; 197 uint32_t ddr_a2; 198 uint32_t ddr_a3; 199 uint32_t ddr_a4; 200 uint32_t ddr_a5; 201 uint32_t ddr_a6; 202 uint32_t ddr_a7; 203 uint32_t ddr_a8; 204 uint32_t ddr_a9; 205 uint32_t ddr_a10; 206 uint32_t ddr_a11; 207 uint32_t ddr_a12; 208 uint32_t ddr_a13; 209 uint32_t ddr_a14; 210 uint32_t ddr_a15; 211 uint32_t ddr_odt; 212 uint32_t ddr_d0; 213 uint32_t ddr_d1; 214 uint32_t ddr_d2; 215 uint32_t ddr_d3; 216 uint32_t ddr_d4; 217 uint32_t ddr_d5; 218 uint32_t ddr_d6; 219 uint32_t ddr_d7; 220 uint32_t ddr_d8; 221 uint32_t ddr_d9; 222 uint32_t ddr_d10; 223 uint32_t ddr_d11; 224 uint32_t ddr_d12; 225 uint32_t ddr_d13; 226 uint32_t ddr_d14; 227 uint32_t ddr_d15; 228 uint32_t ddr_dqm0; 229 uint32_t ddr_dqm1; 230 uint32_t ddr_dqs0; 231 uint32_t ddr_dqsn0; 232 uint32_t ddr_dqs1; 233 uint32_t ddr_dqsn1; 234 uint32_t ddr_vref; 235 uint32_t ddr_vtp; 236 uint32_t ddr_strben0; 237 uint32_t ddr_strben1; 238 uint32_t ain7; 239 uint32_t ain6; 240 uint32_t ain5; 241 uint32_t ain4; 242 uint32_t ain3; 243 uint32_t ain2; 244 uint32_t ain1; 245 uint32_t ain0; 246 uint32_t vrefp; 247 uint32_t vrefn; 248 }; 249 250 #endif 251