1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ops.h>
6 #include <intelblocks/lpc_lib.h>
7 #include <intelblocks/itss.h>
8 #include <soc/ramstage.h>
9 #include <soc/interrupt.h>
10 #include <soc/irq.h>
11 #include <string.h>
12
13 static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = {
14 /*
15 * cAVS(Audio, Voice, Speech), INTA is default, programmed in
16 * PciCfgSpace 3Dh
17 */
18 DEVICE_INT_CONFIG(PCH_DEVFN_HDA, int_A, cAVS_INTA_IRQ),
19 /*
20 * SMBus Controller, no default value, programmed in
21 * PciCfgSpace 3Dh
22 */
23 DEVICE_INT_CONFIG(PCH_DEVFN_SMBUS, int_A, SMBUS_INTA_IRQ),
24 /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */
25 DEVICE_INT_CONFIG(PCH_DEVFN_GBE, int_A, GbE_INTA_IRQ),
26 /* TraceHub, INTA is default, RO register */
27 DEVICE_INT_CONFIG(PCH_DEVFN_TRACEHUB, int_A, TRACE_HUB_INTA_IRQ),
28 /*
29 * SerialIo: UART #0, INTA is default,
30 * programmed in PCR[SERIALIO] + PCICFGCTRL[7]
31 */
32 DEVICE_INT_CONFIG(PCH_DEVFN_UART0, int_A, LPSS_UART0_IRQ),
33 /*
34 * SerialIo: UART #1, INTA is default,
35 * programmed in PCR[SERIALIO] + PCICFGCTRL[8]
36 */
37 DEVICE_INT_CONFIG(PCH_DEVFN_UART1, int_B, LPSS_UART1_IRQ),
38 /*
39 * SerialIo: SPI #0, INTA is default,
40 * programmed in PCR[SERIALIO] + PCICFGCTRL[10]
41 */
42 DEVICE_INT_CONFIG(PCH_DEVFN_GSPI0, int_C, LPSS_SPI0_IRQ),
43 /*
44 * SerialIo: SPI #1, INTA is default,
45 * programmed in PCR[SERIALIO] + PCICFGCTRL[11]
46 */
47 DEVICE_INT_CONFIG(PCH_DEVFN_GSPI1, int_D, LPSS_SPI1_IRQ),
48 /* SCS: eMMC (SKL PCH-LP Only) */
49 DEVICE_INT_CONFIG(PCH_DEVFN_EMMC, int_B, eMMC_IRQ),
50 /* SCS: SDIO (SKL PCH-LP Only) */
51 DEVICE_INT_CONFIG(PCH_DEVFN_SDIO, int_C, SDIO_IRQ),
52 /* SCS: SDCard (SKL PCH-LP Only) */
53 DEVICE_INT_CONFIG(PCH_DEVFN_SDCARD, int_D, SD_IRQ),
54 /* PCI Express Port, INT is default,
55 * programmed in PciCfgSpace + FCh
56 */
57 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE9, int_A, PCIE_9_IRQ),
58 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE10, int_B, PCIE_10_IRQ),
59 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE11, int_C, PCIE_11_IRQ),
60 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE12, int_D, PCIE_12_IRQ),
61 /*
62 * PCI Express Port 1, INT is default,
63 * programmed in PciCfgSpace + FCh
64 */
65 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE1, int_A, PCIE_1_IRQ),
66 /*
67 * PCI Express Port 2, INT is default,
68 * programmed in PciCfgSpace + FCh
69 */
70 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE2, int_B, PCIE_2_IRQ),
71 /*
72 * PCI Express Port 3, INT is default,
73 * programmed in PciCfgSpace + FCh
74 */
75 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE3, int_C, PCIE_3_IRQ),
76 /*
77 * PCI Express Port 4, INT is default,
78 * programmed in PciCfgSpace + FCh
79 */
80 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE4, int_D, PCIE_4_IRQ),
81 /*
82 * PCI Express Port 5, INT is default,
83 * programmed in PciCfgSpace + FCh
84 */
85 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE5, int_A, PCIE_5_IRQ),
86 /*
87 * PCI Express Port 6, INT is default,
88 * programmed in PciCfgSpace + FCh
89 */
90 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE6, int_B, PCIE_6_IRQ),
91 /*
92 * PCI Express Port 7, INT is default,
93 * programmed in PciCfgSpace + FCh
94 */
95 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE7, int_C, PCIE_7_IRQ),
96 /*
97 * PCI Express Port 8, INT is default,
98 * programmed in PciCfgSpace + FCh
99 */
100 DEVICE_INT_CONFIG(PCH_DEVFN_PCIE8, int_D, PCIE_8_IRQ),
101 /*
102 * SerialIo UART Controller #2, INTA is default,
103 * programmed in PCR[SERIALIO] + PCICFGCTRL[9]
104 */
105 DEVICE_INT_CONFIG(PCH_DEVFN_UART2, int_A, LPSS_UART2_IRQ),
106 /*
107 * SerialIo UART Controller #5, INTA is default,
108 * programmed in PCR[SERIALIO] + PCICFGCTRL[6]
109 */
110 DEVICE_INT_CONFIG(PCH_DEVFN_I2C5, int_B, LPSS_I2C5_IRQ),
111 /*
112 * SerialIo UART Controller #4, INTA is default,
113 * programmed in PCR[SERIALIO] + PCICFGCTRL[5]
114 */
115 DEVICE_INT_CONFIG(PCH_DEVFN_I2C4, int_C, LPSS_I2C4_IRQ),
116 /*
117 * SATA Controller, INTA is default,
118 * programmed in PciCfgSpace + 3Dh
119 */
120 DEVICE_INT_CONFIG(PCH_DEVFN_SATA, int_A, SATA_IRQ),
121 /* CSME: HECI #1 */
122 DEVICE_INT_CONFIG(PCH_DEVFN_CSE, int_A, HECI_1_IRQ),
123 /* CSME: HECI #2 */
124 DEVICE_INT_CONFIG(PCH_DEVFN_CSE_2, int_B, HECI_2_IRQ),
125 /* CSME: IDE-Redirection (IDE-R) */
126 DEVICE_INT_CONFIG(PCH_DEVFN_CSE_IDER, int_C, IDER_IRQ),
127 /* CSME: Keyboard and Text (KT) Redirection */
128 DEVICE_INT_CONFIG(PCH_DEVFN_CSE_KT, int_D, KT_IRQ),
129 /* CSME: HECI #3 */
130 DEVICE_INT_CONFIG(PCH_DEVFN_CSE_3, int_A, HECI_3_IRQ),
131 /*
132 * SerialIo I2C Controller #0, INTA is default,
133 * programmed in PCR[SERIALIO] + PCICFGCTRL[1]
134 */
135 DEVICE_INT_CONFIG(PCH_DEVFN_I2C0, int_A, LPSS_I2C0_IRQ),
136 /*
137 * SerialIo I2C Controller #1, INTA is default,
138 * programmed in PCR[SERIALIO] + PCICFGCTRL[2]
139 */
140 DEVICE_INT_CONFIG(PCH_DEVFN_I2C1, int_B, LPSS_I2C1_IRQ),
141 /*
142 * SerialIo I2C Controller #2, INTA is default,
143 * programmed in PCR[SERIALIO] + PCICFGCTRL[3]
144 */
145 DEVICE_INT_CONFIG(PCH_DEVFN_I2C2, int_C, LPSS_I2C2_IRQ),
146 /*
147 * SerialIo I2C Controller #3, INTA is default,
148 * programmed in PCR[SERIALIO] + PCICFGCTRL[4]
149 */
150 DEVICE_INT_CONFIG(PCH_DEVFN_I2C3, int_D, LPSS_I2C3_IRQ),
151 /*
152 * USB 3.0 xHCI Controller, no default value,
153 * programmed in PciCfgSpace 3Dh
154 */
155 DEVICE_INT_CONFIG(PCH_DEVFN_XHCI, int_A, XHCI_IRQ),
156 /* USB Device Controller (OTG) */
157 DEVICE_INT_CONFIG(PCH_DEVFN_USBOTG, int_B, OTG_IRQ),
158 /* Thermal Subsystem */
159 DEVICE_INT_CONFIG(PCH_DEVFN_THERMAL, int_C, THERMAL_IRQ),
160 /* Camera IO Host Controller */
161 DEVICE_INT_CONFIG(PCH_DEVFN_CIO, int_A, CIO_INTA_IRQ),
162 /* Integrated Sensor Hub */
163 DEVICE_INT_CONFIG(PCH_DEVFN_ISH, int_A, ISH_IRQ)
164 };
165
soc_irq_settings(FSP_SIL_UPD * params)166 void soc_irq_settings(FSP_SIL_UPD *params)
167 {
168 uint32_t i;
169 u8 irq_config[PCH_MAX_IRQ_CONFIG];
170 const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
171 const struct soc_intel_skylake_config *config = config_of(dev);
172
173 /* update irq table */
174 params->DevIntConfigPtr = (UINT32)(uintptr_t)devintconfig;
175 params->NumOfDevIntConfig = ARRAY_SIZE(devintconfig);
176
177 /* PxRC to IRQ programming */
178 for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) {
179 switch (i) {
180 case PCH_PARC:
181 case PCH_PCRC:
182 case PCH_PDRC:
183 case PCH_PERC:
184 case PCH_PFRC:
185 case PCH_PGRC:
186 case PCH_PHRC:
187 irq_config[i] = PCH_IRQ11;
188 break;
189 case PCH_PBRC:
190 irq_config[i] = PCH_IRQ10;
191 break;
192 }
193 }
194 memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG);
195 /* GPIO IRQ Route The valid values is 14 or 15 */
196 if (config->GpioIrqSelect == 0)
197 params->GpioIrqRoute = GPIO_IRQ14;
198 else
199 params->GpioIrqRoute = config->GpioIrqSelect;
200 /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */
201 if (config->SciIrqSelect == 0)
202 params->SciIrqSelect = SCI_IRQ9;
203 else
204 params->SciIrqSelect = config->SciIrqSelect;
205 /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23 */
206 if (config->TcoIrqSelect == 0)
207 params->TcoIrqSelect = TCO_IRQ9;
208 else
209 params->TcoIrqSelect = config->TcoIrqSelect;
210 /* TCO Irq enable/disable */
211 params->TcoIrqEnable = config->TcoIrqEnable;
212 }
213