1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /* This was originally for the e7500, modified for e7501
4 * The primary differences are that 7501 apparently can
5 * support single channel RAM (i haven't tested),
6 * CAS1.5 is no longer supported, The ECC scrubber
7 * now supports a mode to zero RAM and init ECC in one step
8 * and the undocumented registers at 0x80 require new
9 * (undocumented) values determined by guesswork and
10 * comparison w/ OEM BIOS values.
11 * Steven James 02/06/2003
12 */
13
14 #include <stdint.h>
15 #include <device/pci_def.h>
16 #include <arch/io.h>
17 #include <device/mmio.h>
18 #include <device/pci_ops.h>
19 #include <device/smbus_host.h>
20 #include <lib.h>
21 #include <commonlib/helpers.h>
22 #include <console/console.h>
23 #include <assert.h>
24 #include <spd.h>
25 #include <sdram_mode.h>
26 #include <timestamp.h>
27
28 #include "raminit.h"
29 #include "e7505.h"
30
31 /*-----------------------------------------------------------------------------
32 Definitions:
33 -----------------------------------------------------------------------------*/
34
35 #if CONFIG(DEBUG_RAM_SETUP)
36 #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
37 #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
38 #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
39 #else
40 #define RAM_DEBUG_MESSAGE(x)
41 #define RAM_DEBUG_HEX32(x)
42 #define RAM_DEBUG_HEX8(x)
43 #endif
44
45 #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
46 #define SPD_ERROR "Error reading SPD info\n"
47
48 #define MCHDEV PCI_DEV(0, 0, 0)
49 #define RASDEV PCI_DEV(0, 0, 1)
50 #define AGPDEV PCI_DEV(0, 1, 0)
51 #define D060DEV PCI_DEV(0, 6, 0)
52
53 // NOTE: This used to be 0x100000.
54 // That doesn't work on systems where A20M# is asserted, because
55 // attempts to access 0x1000NN end up accessing 0x0000NN.
56 #define RCOMP_MMIO ((u8 *)0x200000)
57
58 struct dimm_size {
59 unsigned long side1;
60 unsigned long side2;
61 };
62
63 static const uint32_t refresh_frequency[] = {
64 /* Relative frequency (array value) of each E7501 Refresh Mode Select
65 * (RMS) value (array index)
66 * 0 == least frequent refresh (longest interval between refreshes)
67 * [0] disabled -> 0
68 * [1] 15.6 usec -> 2
69 * [2] 7.8 usec -> 3
70 * [3] 64 usec -> 1
71 * [4] reserved -> 0
72 * [5] reserved -> 0
73 * [6] reserved -> 0
74 * [7] 64 clocks -> 4
75 */
76 0, 2, 3, 1, 0, 0, 0, 4
77 };
78
79 static const uint32_t refresh_rate_map[] = {
80 /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
81 * Select values (array value)
82 * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
83 * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
84 * 64 clock (481 ns) (7) refresh.
85 * [0] == 15.625 us -> 15.6 us
86 * [1] == 3.9 us -> 481 ns
87 * [2] == 7.8 us -> 7.8 us
88 * [3] == 31.3 us -> 15.6 us
89 * [4] == 62.5 us -> 15.6 us
90 * [5] == 125 us -> 64 us
91 */
92 1, 7, 2, 1, 1, 3
93 };
94
95 #define MAX_SPD_REFRESH_RATE (ARRAY_SIZE(refresh_rate_map) - 1)
96
97 // SPD parameters that must match for dual-channel operation
98 static const uint8_t dual_channel_parameters[] = {
99 SPD_MEMORY_TYPE,
100 SPD_MODULE_VOLTAGE,
101 SPD_NUM_COLUMNS,
102 SPD_NUM_ROWS,
103 SPD_NUM_DIMM_BANKS,
104 SPD_PRIMARY_SDRAM_WIDTH,
105 SPD_NUM_BANKS_PER_SDRAM
106 };
107
108 /* Comments here are remains of e7501 or even 855PM.
109 * They might be partially (in)correct for e7505.
110 */
111
112 /* (DRAM Read Timing Control, if similar to 855PM?)
113 * 0x80 - 0x81 documented differently for e7505
114 * This register has something to do with CAS latencies,
115 * possibly this is the real chipset control.
116 * At 0x00 CAS latency 1.5 works.
117 * At 0x06 CAS latency 2.5 works.
118 * At 0x01 CAS latency 2.0 works.
119 *
120 * This is still undocumented in e7501, but with different values
121 * CAS 2.0 values taken from Intel BIOS settings, others are a guess
122 * and may be terribly wrong. Old values preserved as comments until I
123 * figure this out for sure.
124 * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
125 * work at all.
126 * Steven James 02/06/2003
127 *
128 * NOTE: values now configured in configure_e7501_cas_latency() based
129 * on SPD info and total number of DIMMs (per Intel)
130 */
131
132 /* FDHC - Fixed DRAM Hole Control ???
133 * 0x58 undocumented for e7505, memory hole in southbridge configuration?
134 * [7:7] Hole_Enable
135 * 0 == No memory Hole
136 * 1 == Memory Hole from 15MB to 16MB
137 * [6:0] Reserved
138 */
139
140 /* Another Intel undocumented register
141 * 0x88 - 0x8B
142 * [31:31] Purpose unknown
143 * [26:26] Master DLL Reset?
144 * 0 == Normal operation?
145 * 1 == Reset?
146 * [07:07] Periodic memory recalibration?
147 * 0 == Disabled?
148 * 1 == Enabled?
149 * [04:04] Receive FIFO RE-Sync?
150 * 0 == Normal operation?
151 * 1 == Reset?
152 */
153
154 /* DDR RECOMP tables */
155 // Slew table for 2x drive?
156 static const uint32_t slew_2x[] = {
157 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
158 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
159 };
160
161 // Pull Up / Pull Down offset table, if analogous to IXP2800?
162 static const uint32_t pull_updown_offset_table[] = {
163 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
164 0x88888888, 0x88888888, 0x88888888, 0x88888888,
165 };
166
167 /*-----------------------------------------------------------------------------
168 Delay functions:
169 -----------------------------------------------------------------------------*/
170
171 /* Estimate that SLOW_DOWN_IO takes about 1 us */
172 #define SLOW_DOWN_IO inb(0x80)
local_udelay(int i)173 static void local_udelay(int i)
174 {
175 while (i--) {
176 SLOW_DOWN_IO;
177 }
178 }
179
180 /* delay for 200us */
181 #define DO_DELAY local_udelay(200)
182 #define EXTRA_DELAY DO_DELAY
183
184 /*-----------------------------------------------------------------------------
185 Handle (undocumented) control bits MCHTST and PCI_DEV(0,6,0)
186 -----------------------------------------------------------------------------*/
187 typedef enum {
188 MCHTST_CMD_0,
189 D060_ENABLE,
190 D060_DISABLE,
191 RCOMP_BAR_ENABLE,
192 RCOMP_BAR_DISABLE,
193 } mchtst_cc;
194
195 typedef enum {
196 D060_CMD_0,
197 D060_CMD_1,
198 } d060_cc;
199
200 typedef enum {
201 RCOMP_HOLD,
202 RCOMP_RELEASE,
203 RCOMP_SMR_00,
204 RCOMP_SMR_01,
205 } rcomp_smr_cc;
206
207 /**
208 * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM
209 *
210 * [31:31] Purpose unknown
211 * [30:30] Purpose unknown
212 * [29:23] Unknown - not used?
213 * [22:22] System Memory MMR Enable
214 * 0 == Disable: mem space and BAR at 0x14 are not accessible
215 * 1 == Enable: mem space and BAR at 0x14 are accessible
216 * [21:20] Purpose unknown
217 * [19:02] Unknown - not used?
218 * [01:01] D6EN (Device #6 enable)
219 * 0 == Disable
220 * 1 == Enable
221 * [00:00] Unknown - not used?
222 */
mchtest_control(mchtst_cc cmd)223 static void mchtest_control(mchtst_cc cmd)
224 {
225 uint32_t dword = pci_read_config32(MCHDEV, MCHTST);
226 switch (cmd) {
227 case MCHTST_CMD_0:
228 dword &= ~(3 << 30);
229 break;
230 case RCOMP_BAR_ENABLE:
231 dword |= (1 << 22);
232 break;
233 case RCOMP_BAR_DISABLE:
234 dword &= ~(1 << 22);
235 break;
236 case D060_ENABLE:
237 dword |= (1 << 1);
238 break;
239 case D060_DISABLE:
240 dword &= ~(1 << 1);
241 break;
242 };
243 pci_write_config32(MCHDEV, MCHTST, dword);
244 }
245
246 /**
247 *
248 */
d060_control(d060_cc cmd)249 static void d060_control(d060_cc cmd)
250 {
251 mchtest_control(D060_ENABLE);
252 uint32_t dword = pci_read_config32(D060DEV, 0xf0);
253 switch (cmd) {
254 case D060_CMD_0:
255 dword |= (1 << 2);
256 break;
257 case D060_CMD_1:
258 dword |= (3 << 27);
259 break;
260 }
261 pci_write_config32(D060DEV, 0xf0, dword);
262 mchtest_control(D060_DISABLE);
263 }
264
265 /**
266 *
267 */
rcomp_smr_control(rcomp_smr_cc cmd)268 static void rcomp_smr_control(rcomp_smr_cc cmd)
269 {
270 uint32_t dword = read32(RCOMP_MMIO + SMRCTL);
271 switch (cmd) {
272 case RCOMP_HOLD:
273 dword |= (1 << 9);
274 break;
275 case RCOMP_RELEASE:
276 dword &= ~((1 << 9) | (3 << 0));
277 dword |= (1 << 10) | (1 << 0);
278 break;
279 case RCOMP_SMR_00:
280 dword &= ~(1 << 8);
281 break;
282 case RCOMP_SMR_01:
283 dword |= (1 << 10) | (1 << 8);
284 break;
285 }
286 write32(RCOMP_MMIO + SMRCTL, dword);
287 }
288
289 /*-----------------------------------------------------------------------------
290 Serial presence detect (SPD) functions:
291 -----------------------------------------------------------------------------*/
292
die_on_spd_error(int spd_return_value)293 static void die_on_spd_error(int spd_return_value)
294 {
295 if (spd_return_value < 0)
296 die("Error reading SPD info\n");
297 }
298
299 /**
300 * Calculate the page size for each physical bank of the DIMM:
301 * log2(page size) = (# columns) + log2(data width)
302 *
303 * NOTE: Page size is the total number of data bits in a row.
304 *
305 * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
306 * @return log2(page size) for each side of the DIMM.
307 */
sdram_spd_get_page_size(uint16_t dimm_socket_address)308 static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
309 {
310 uint16_t module_data_width;
311 int value;
312 struct dimm_size pgsz;
313
314 pgsz.side1 = 0;
315 pgsz.side2 = 0;
316
317 // Side 1
318 value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
319 if (value < 0)
320 goto hw_err;
321 pgsz.side1 = value & 0xf; // # columns in bank 1
322
323 /* Get the module data width and convert it to a power of two */
324 value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
325 if (value < 0)
326 goto hw_err;
327 module_data_width = (value & 0xff) << 8;
328
329 value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
330 if (value < 0)
331 goto hw_err;
332 module_data_width |= (value & 0xff);
333
334 pgsz.side1 += log2(module_data_width);
335
336 /* side two */
337 value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
338 if (value < 0)
339 goto hw_err;
340 if (value > 2)
341 die("Bad SPD value\n");
342 if (value == 2) {
343 pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
344 value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
345 if (value < 0)
346 goto hw_err;
347 if ((value & 0xf0) != 0) {
348 // Asymmetric banks
349 pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */
350 pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */
351 }
352 }
353
354 return pgsz;
355
356 hw_err:
357 die(SPD_ERROR);
358 return pgsz; // Never reached
359 }
360
361 /**
362 * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).
363 *
364 * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
365 * @return Width in bits of each DIMM side's DRAMs.
366 */
sdram_spd_get_width(uint16_t dimm_socket_address)367 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
368 {
369 int value;
370 struct dimm_size width;
371
372 width.side1 = 0;
373 width.side2 = 0;
374
375 value = smbus_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
376 die_on_spd_error(value);
377
378 width.side1 = value & 0x7f; // Mask off bank 2 flag
379
380 if (value & 0x80) {
381 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
382 } else {
383 // If bank 2 exists, it's the same width as bank 1
384 value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
385 die_on_spd_error(value);
386
387 if (value == 2)
388 width.side2 = width.side1;
389 }
390
391 return width;
392 }
393
394 /**
395 * Calculate the log base 2 size in bits of both DIMM sides.
396 *
397 * log2(# bits) = (# columns) + log2(data width) +
398 * (# rows) + log2(banks per SDRAM)
399 *
400 * Note that it might be easier to use SPD byte 31 here, it has the DIMM size
401 * as a multiple of 4MB. The way we do it now we can size both sides of an
402 * asymmetric DIMM.
403 *
404 * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
405 * @return log2(number of bits) for each side of the DIMM.
406 */
spd_get_dimm_size(unsigned int dimm_socket_address)407 static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address)
408 {
409 int value;
410
411 // Start with log2(page size)
412 struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
413
414 if (sz.side1 > 0) {
415 value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS);
416 die_on_spd_error(value);
417
418 sz.side1 += value & 0xf;
419
420 if (sz.side2 > 0) {
421 // Double-sided DIMM
422 if (value & 0xF0)
423 sz.side2 += value >> 4; // Asymmetric
424 else
425 sz.side2 += value; // Symmetric
426 }
427
428 value = smbus_read_byte(dimm_socket_address,
429 SPD_NUM_BANKS_PER_SDRAM);
430 die_on_spd_error(value);
431
432 value = log2(value);
433 sz.side1 += value;
434 if (sz.side2 > 0)
435 sz.side2 += value;
436 }
437
438 return sz;
439 }
440
441 /**
442 * Determine whether two DIMMs have the same value for an SPD parameter.
443 *
444 * @param spd_byte_number The SPD byte number to compare in both DIMMs.
445 * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate.
446 * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate.
447 * @return 1 if both DIMM sockets report the same value for the specified
448 * SPD parameter, 0 if the values differed or an error occurred.
449 */
are_spd_values_equal(uint8_t spd_byte_number,uint16_t dimm0_address,uint16_t dimm1_address)450 static uint8_t are_spd_values_equal(uint8_t spd_byte_number,
451 uint16_t dimm0_address,
452 uint16_t dimm1_address)
453 {
454 uint8_t bEqual = 0;
455 int dimm0_value = smbus_read_byte(dimm0_address, spd_byte_number);
456 int dimm1_value = smbus_read_byte(dimm1_address, spd_byte_number);
457
458 if ((dimm0_value >= 0) && (dimm1_value >= 0)
459 && (dimm0_value == dimm1_value))
460 bEqual = 1;
461
462 return bEqual;
463 }
464
465 /**
466 * Scan for compatible DIMMs.
467 *
468 * The code in this module only supports dual-channel operation, so we test
469 * that compatible DIMMs are paired.
470 *
471 * @param ctrl PCI addresses of memory controller functions, and SMBus
472 * addresses of DIMM slots on the mainboard.
473 * @return A bitmask indicating which of the possible sockets for each channel
474 * was found to contain a compatible DIMM.
475 * Bit 0 corresponds to the closest socket for channel 0
476 * Bit 1 to the next socket for channel 0
477 * ...
478 * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0
479 * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1
480 * ...
481 * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
482 */
spd_get_supported_dimms(const struct mem_controller * ctrl)483 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
484 {
485 int i;
486 uint8_t dimm_mask = 0;
487
488 // Have to increase size of dimm_mask if this assertion is violated
489 ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
490
491 // Find DIMMs we can support on channel 0.
492 // Then see if the corresponding channel 1 DIMM has the same parameters,
493 // since we only support dual-channel.
494
495 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
496 uint16_t channel0_dimm = ctrl->channel0[i];
497 uint16_t channel1_dimm = ctrl->channel1[i];
498 uint8_t bDualChannel = 1;
499 struct dimm_size page_size;
500 struct dimm_size sdram_width;
501 int spd_value;
502
503 if (channel0_dimm == 0)
504 continue; // No such socket on this mainboard
505
506 if (smbus_read_byte(channel0_dimm, SPD_MEMORY_TYPE) !=
507 SPD_MEMORY_TYPE_SDRAM_DDR)
508 continue;
509
510 if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=
511 SPD_VOLTAGE_SSTL2)
512 continue; // Unsupported voltage
513
514 // E7501 does not support unregistered DIMMs
515 spd_value = smbus_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
516 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
517 continue;
518
519 // Must support burst = 4 for dual-channel operation on E7501
520 // NOTE: for single-channel, burst = 8 is required
521 spd_value = smbus_read_byte(channel0_dimm,
522 SPD_SUPPORTED_BURST_LENGTHS);
523 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
524 continue;
525
526 page_size = sdram_spd_get_page_size(channel0_dimm);
527 sdram_width = sdram_spd_get_width(channel0_dimm);
528
529 // Validate DIMM page size
530 // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
531 // NOTE: 4 KB = 32 Kb = 2^15
532 // 32 KB = 262 Kb = 2^18
533
534 if ((page_size.side1 < 15) || (page_size.side1 > 18))
535 continue;
536
537 // If DIMM is double-sided, verify side2 page size
538 if (page_size.side2 != 0) {
539 if ((page_size.side2 < 15)
540 || (page_size.side2 > 18))
541 continue;
542 }
543 // Validate SDRAM width
544 // The E7501 only supports x4 and x8 devices
545
546 if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
547 continue;
548
549 // If DIMM is double-sided, verify side2 width
550 if (sdram_width.side2 != 0) {
551 if ((sdram_width.side2 != 4)
552 && (sdram_width.side2 != 8))
553 continue;
554 }
555
556 // Channel 0 DIMM looks compatible.
557 // Now see if it is paired with the proper DIMM on channel 1.
558
559 ASSERT(channel1_dimm != 0); // No such socket on this mainboard??
560
561 // NOTE: unpopulated DIMMs cause read to fail
562 spd_value = smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
563 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
564 printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
565 continue;
566 }
567
568 spd_value = smbus_read_byte(channel1_dimm,
569 SPD_SUPPORTED_BURST_LENGTHS);
570 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
571 continue;
572
573 int j;
574 for (j = 0; j < sizeof(dual_channel_parameters); ++j) {
575 if (!are_spd_values_equal
576 (dual_channel_parameters[j], channel0_dimm,
577 channel1_dimm)) {
578 bDualChannel = 0;
579 break;
580 }
581 }
582
583 if (bDualChannel) {
584 // This DIMM pair is usable
585 dimm_mask |= 1 << i;
586 dimm_mask |= 1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i);
587 } else
588 printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
589 }
590
591 return dimm_mask;
592 }
593
594 /*-----------------------------------------------------------------------------
595 SDRAM configuration functions:
596 -----------------------------------------------------------------------------*/
597
598 /**
599 * Send the specified command to all DIMMs.
600 *
601 * @param command Specifies the command to be sent to the DIMMs.
602 * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
603 * register value in JEDEC format.
604 */
do_ram_command(uint8_t command,uint16_t jedec_mode_bits)605 static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
606 {
607 uint8_t dimm_start_64M_multiple;
608 uintptr_t dimm_start_address;
609 uint32_t dram_controller_mode;
610 uint8_t i;
611
612 // Configure the RAM command
613 dram_controller_mode = pci_read_config32(MCHDEV, DRC);
614 dram_controller_mode &= 0xFFFFFF8F;
615 dram_controller_mode |= command;
616 pci_write_config32(MCHDEV, DRC, dram_controller_mode);
617
618 // RAM_COMMAND_NORMAL is an exception.
619 // It affects only the memory controller and does not need to be "sent" to the DIMMs.
620 if (command == RAM_COMMAND_NORMAL) {
621 EXTRA_DELAY;
622 return;
623 }
624
625 // NOTE: for mode select commands, some of the location address bits are part of the command
626 // Map JEDEC mode bits to E7505
627 if (command == RAM_COMMAND_MRS) {
628 // Host address lines [25:18] map to DIMM address lines [7:0]
629 // Host address lines [17:16] map to DIMM address lines [9:8]
630 // Host address lines [15:4] map to DIMM address lines [11:0]
631 dimm_start_address = (jedec_mode_bits & 0x00ff) << 18;
632 dimm_start_address |= (jedec_mode_bits & 0x0300) << 8;
633 dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4;
634 } else if (command == RAM_COMMAND_EMRS) {
635 // Host address lines [15:4] map to DIMM address lines [11:0]
636 dimm_start_address = (jedec_mode_bits << 4);
637 } else {
638 ASSERT(jedec_mode_bits == 0);
639 dimm_start_address = 0;
640 }
641
642 // Send the command to all DIMMs by accessing a memory location within each
643
644 dimm_start_64M_multiple = 0;
645
646 /* FIXME: Only address the number of rows present in the system?
647 * Seems like rows 4-7 overlap with 0-3.
648 */
649 for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
650 uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i);
651
652 if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
653 dimm_start_address &= 0x3ffffff;
654 dimm_start_address |= dimm_start_64M_multiple << 26;
655 read32p(dimm_start_address);
656 // Set the start of the next DIMM
657 dimm_start_64M_multiple = dimm_end_64M_multiple;
658 }
659 }
660 EXTRA_DELAY;
661 }
662
663 /**
664 * Set the mode register of all DIMMs.
665 *
666 * The proper CAS# latency setting is added to the mode bits specified
667 * by the caller.
668 *
669 * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
670 * register value in JEDEC format.
671 */
set_ram_mode(uint16_t jedec_mode_bits)672 static void set_ram_mode(uint16_t jedec_mode_bits)
673 {
674 ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
675
676 uint32_t dram_cas_latency =
677 pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;
678
679 switch (dram_cas_latency) {
680 case DRT_CAS_2_5:
681 jedec_mode_bits |= SDRAM_CAS_2_5;
682 break;
683
684 case DRT_CAS_2_0:
685 jedec_mode_bits |= SDRAM_CAS_2_0;
686 break;
687
688 default:
689 BUG();
690 break;
691 }
692
693 do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
694 }
695
696 /*-----------------------------------------------------------------------------
697 DIMM-independent configuration functions:
698 -----------------------------------------------------------------------------*/
699
700 /**
701 * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory
702 * present in the specified DIMM.
703 *
704 * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of
705 * the DIMM.
706 * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of
707 * 64 MB) for DIMMs < dimm_index.
708 * @param dimm_index Which DIMM pair is being processed
709 * (0..MAX_DIMM_SOCKETS_PER_CHANNEL).
710 * @return New multiple of 64 MB total DRAM in the system.
711 */
configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits,uint8_t total_dram_64M_multiple,unsigned int dimm_index)712 static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned int dimm_index)
713 {
714 int i;
715
716 ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
717
718 // DIMM sides must be at least 32 MB
719 ASSERT(dimm_log2_num_bits.side1 >= 28);
720 ASSERT((dimm_log2_num_bits.side2 == 0)
721 || (dimm_log2_num_bits.side2 >= 28));
722
723 // In dual-channel mode, we are called only once for each pair of DIMMs.
724 // Each time we process twice the capacity of a single DIMM.
725
726 // Convert single DIMM capacity to paired DIMM capacity
727 // (multiply by two ==> add 1 to log2)
728 dimm_log2_num_bits.side1++;
729 if (dimm_log2_num_bits.side2 > 0)
730 dimm_log2_num_bits.side2++;
731
732 // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
733 // to the total capacity of the system
734 // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
735
736 total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
737
738 // Configure the boundary address for the row on side 1
739 pci_write_config8(MCHDEV, DRB_ROW_0 + (dimm_index << 1),
740 total_dram_64M_multiple);
741
742 // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
743 // (as a multiple of 64 MB) to the total capacity of the system
744 if (dimm_log2_num_bits.side2 >= 29)
745 total_dram_64M_multiple +=
746 (1 << (dimm_log2_num_bits.side2 - 29));
747
748 // Configure the boundary address for the row (if any) on side 2
749 pci_write_config8(MCHDEV, DRB_ROW_1 + (dimm_index << 1),
750 total_dram_64M_multiple);
751
752 // Update boundaries for rows subsequent to these.
753 // These settings will be overridden by a subsequent call if a populated physical slot exists
754
755 for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
756 pci_write_config8(MCHDEV, DRB_ROW_0 + (i << 1),
757 total_dram_64M_multiple);
758 pci_write_config8(MCHDEV, DRB_ROW_1 + (i << 1),
759 total_dram_64M_multiple);
760 }
761
762 return total_dram_64M_multiple;
763 }
764
765 /**
766 * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM).
767 *
768 * If necessary, set up a remap window so we don't waste DRAM that ordinarily
769 * would lie behind addresses reserved for memory-mapped I/O.
770 *
771 * @param ctrl PCI addresses of memory controller functions, and SMBus
772 * addresses of DIMM slots on the mainboard.
773 * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
774 */
configure_e7501_ram_addresses(const struct mem_controller * ctrl,uint8_t dimm_mask)775 static void configure_e7501_ram_addresses(const struct mem_controller
776 *ctrl, uint8_t dimm_mask)
777 {
778 int i;
779 uint8_t total_dram_64M_multiple = 0;
780 uint64_t tolm, tom;
781 uint16_t reg;
782
783 /* FIXME: Is there standard presence detect bit somewhere. */
784 const int agp_slot_disabled = 1;
785
786 /* Start with disabled remap range. */
787 uint16_t remapbase_r = 0x3ff;
788 uint16_t remaplimit_r = 0;
789
790 // Configure the E7501's DRAM row boundaries
791 // Start by zeroing out the temporary initial configuration
792 pci_write_config32(MCHDEV, DRB_ROW_0, 0);
793 pci_write_config32(MCHDEV, DRB_ROW_4, 0);
794
795 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
796 uint16_t dimm_socket_address = ctrl->channel0[i];
797 struct dimm_size sz;
798
799 if (!(dimm_mask & (1 << i)))
800 continue; // This DIMM not present
801
802 sz = spd_get_dimm_size(dimm_socket_address);
803
804 RAM_DEBUG_MESSAGE("dimm size =");
805 RAM_DEBUG_HEX32((u32)sz.side1);
806 RAM_DEBUG_MESSAGE(" ");
807 RAM_DEBUG_HEX32((u32)sz.side2);
808 RAM_DEBUG_MESSAGE("\n");
809
810 if (sz.side1 == 0)
811 die("Bad SPD value\n");
812
813 total_dram_64M_multiple =
814 configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
815 }
816
817 tom = total_dram_64M_multiple * 64ULL * MiB;
818
819 /* Reserve MMIO space. */
820 tolm = 4ULL * GiB - 512 * MiB;
821 if (agp_slot_disabled) {
822 /* Reduce apertures to 2 x 4 MiB. */
823 pci_write_config8(MCHDEV, APSIZE, 0x3F);
824 pci_write_config16(AGPDEV, APSIZE1, 0x3F);
825 } else {
826 /* Add MMIO reserve for 2 x 256 MiB apertures. */
827 tolm -= 512 * MiB;
828 }
829 tolm = MIN(tolm, tom);
830
831 /* The PCI memory hole overlaps memory setup the remap window. */
832 if (tolm < tom) {
833 uint64_t remapbase = MAX(tom, 4ULL * GiB);
834 uint64_t remaplimit = remapbase + (4ULL * GiB - tolm);
835
836 remapbase_r = remapbase / (64 * MiB);
837 remaplimit_r = remaplimit / (64 * MiB);
838
839 /* Limit register is inclusive. */
840 remaplimit_r -= 1;
841 }
842
843 /* Write the RAM configuration registers,
844 preserving the reserved bits. */
845 reg = pci_read_config16(MCHDEV, TOLM) & 0x7ff;
846 reg |= (tolm / (128 * MiB)) << 11;
847 pci_write_config16(MCHDEV, TOLM, reg);
848
849 reg = pci_read_config16(MCHDEV, REMAPBASE) & 0xfc00;
850 reg |= remapbase_r;
851 pci_write_config16(MCHDEV, REMAPBASE, reg);
852
853 reg = pci_read_config16(MCHDEV, REMAPLIMIT) & 0xfc00;
854 reg |= remaplimit_r;
855 pci_write_config16(MCHDEV, REMAPLIMIT, reg);
856 }
857
858 /**
859 * Program the DRAM Timing register (DRT) of the E7501 (except for CAS#
860 * latency, which is assumed to have been programmed already), based on the
861 * parameters of the various installed DIMMs.
862 *
863 * @param ctrl PCI addresses of memory controller functions, and SMBus
864 * addresses of DIMM slots on the mainboard.
865 * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
866 */
configure_e7501_dram_timing(const struct mem_controller * ctrl,uint8_t dimm_mask)867 static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
868 uint8_t dimm_mask)
869 {
870 int i;
871 uint32_t dram_timing;
872 int value;
873 uint8_t slowest_row_precharge = 0;
874 uint8_t slowest_ras_cas_delay = 0;
875 uint8_t slowest_active_to_precharge_delay = 0;
876 uint32_t current_cas_latency =
877 pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;
878
879 // CAS# latency must be programmed beforehand
880 ASSERT((current_cas_latency == DRT_CAS_2_0)
881 || (current_cas_latency == DRT_CAS_2_5));
882
883 // Each timing parameter is determined by the slowest DIMM
884
885 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
886 uint16_t dimm_socket_address;
887
888 if (!(dimm_mask & (1 << i)))
889 continue; // This DIMM not present
890
891 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
892 dimm_socket_address = ctrl->channel0[i];
893 else
894 dimm_socket_address =
895 ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
896
897 value = smbus_read_byte(dimm_socket_address,
898 SPD_MIN_ROW_PRECHARGE_TIME);
899 if (value < 0)
900 goto hw_err;
901 if (value > slowest_row_precharge)
902 slowest_row_precharge = value;
903
904 value = smbus_read_byte(dimm_socket_address,
905 SPD_MIN_RAS_TO_CAS_DELAY);
906 if (value < 0)
907 goto hw_err;
908 if (value > slowest_ras_cas_delay)
909 slowest_ras_cas_delay = value;
910
911 value = smbus_read_byte(dimm_socket_address,
912 SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
913 if (value < 0)
914 goto hw_err;
915 if (value > slowest_active_to_precharge_delay)
916 slowest_active_to_precharge_delay = value;
917 }
918
919 // NOTE for timing parameters:
920 // At 133 MHz, 1 clock == 7.52 ns
921
922 /* Read the initial state */
923 dram_timing = pci_read_config32(MCHDEV, DRT);
924
925 /* Trp */
926
927 // E7501 supports only 2 or 3 clocks for tRP
928 if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
929 die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks
930 else if (slowest_row_precharge > (15 << 2))
931 dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks
932 else
933 dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks
934
935 /* Trcd */
936
937 // E7501 supports only 2 or 3 clocks for tRCD
938 // Use the same value for both read & write
939 dram_timing &= ~((1 << 3) | (3 << 1));
940 if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
941 die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks
942 else if (slowest_ras_cas_delay > (15 << 2))
943 dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks
944 else
945 dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks
946
947 /* Tras */
948
949 // E7501 supports only 5, 6, or 7 clocks for tRAS
950 // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
951 dram_timing &= ~(3 << 9);
952
953 if (slowest_active_to_precharge_delay > 52)
954 die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks
955 else if (slowest_active_to_precharge_delay > 45)
956 dram_timing |= (0 << 9); // 46-52 ns: 7 clocks
957 else if (slowest_active_to_precharge_delay > 37)
958 dram_timing |= (1 << 9); // 38-45 ns: 6 clocks
959 else
960 dram_timing |= (2 << 9); // < 38 ns: 5 clocks
961
962 /* Trd */
963
964 /* Set to a 7 clock read delay. This is for 133MHz
965 * with a CAS latency of 2.5 if 2.0 a 6 clock
966 * delay is good */
967
968 dram_timing &= ~(7 << 24); // 7 clocks
969 if (current_cas_latency == DRT_CAS_2_0)
970 dram_timing |= (1 << 24); // 6 clocks
971
972 /*
973 * Back to Back Read-Write Turn Around
974 */
975 /* Set to a 5 clock back to back read to write turn around.
976 * 4 is a good delay if the CAS latency is 2.0 */
977
978 dram_timing &= ~(1 << 28); // 5 clocks
979 if (current_cas_latency == DRT_CAS_2_0)
980 dram_timing |= (1 << 28); // 4 clocks
981
982 pci_write_config32(MCHDEV, DRT, dram_timing);
983
984 return;
985
986 hw_err:
987 die(SPD_ERROR);
988 }
989
990 /**
991 * Determine the shortest CAS# latency that the E7501 and all DIMMs have in
992 * common, and program the E7501 to use it.
993 *
994 * @param ctrl PCI addresses of memory controller functions, and SMBus
995 * addresses of DIMM slots on the mainboard.
996 * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
997 */
configure_e7501_cas_latency(const struct mem_controller * ctrl,uint8_t dimm_mask)998 static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
999 uint8_t dimm_mask)
1000 {
1001 int i;
1002 int value;
1003 uint32_t dram_timing;
1004 uint16_t dram_read_timing;
1005 uint32_t dword;
1006
1007 // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
1008 // NOTE: E7501 supports only 2.0 and 2.5
1009 uint32_t system_compatible_cas_latencies =
1010 SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
1011 uint32_t current_cas_latency;
1012 uint32_t dimm_compatible_cas_latencies;
1013
1014 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1015 uint16_t dimm_socket_address;
1016
1017 if (!(dimm_mask & (1 << i)))
1018 continue; // This DIMM not usable
1019
1020 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1021 dimm_socket_address = ctrl->channel0[i];
1022 else
1023 dimm_socket_address =
1024 ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1025
1026 value = smbus_read_byte(dimm_socket_address,
1027 SPD_ACCEPTABLE_CAS_LATENCIES);
1028 if (value < 0)
1029 goto hw_err;
1030
1031 dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM
1032 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
1033
1034 // Can we support the highest CAS# latency?
1035
1036 value = smbus_read_byte(dimm_socket_address,
1037 SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
1038 if (value < 0)
1039 goto hw_err;
1040
1041 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1042 if (value > 0x75) {
1043 // Our bus is too fast for this CAS# latency
1044 // Remove it from the bitmask of those supported by the DIMM that are compatible
1045 dimm_compatible_cas_latencies &= ~current_cas_latency;
1046 }
1047 // Can we support the next-highest CAS# latency (max - 0.5)?
1048
1049 current_cas_latency >>= 1;
1050 if (current_cas_latency != 0) {
1051 value = smbus_read_byte(dimm_socket_address,
1052 SPD_SDRAM_CYCLE_TIME_2ND);
1053 if (value < 0)
1054 goto hw_err;
1055 if (value > 0x75)
1056 dimm_compatible_cas_latencies &=
1057 ~current_cas_latency;
1058 }
1059 // Can we support the next-highest CAS# latency (max - 1.0)?
1060 current_cas_latency >>= 1;
1061 if (current_cas_latency != 0) {
1062 value = smbus_read_byte(dimm_socket_address,
1063 SPD_SDRAM_CYCLE_TIME_3RD);
1064 if (value < 0)
1065 goto hw_err;
1066 if (value > 0x75)
1067 dimm_compatible_cas_latencies &=
1068 ~current_cas_latency;
1069 }
1070 // Restrict the system to CAS# latencies compatible with this DIMM
1071 system_compatible_cas_latencies &=
1072 dimm_compatible_cas_latencies;
1073
1074 /* go to the next DIMM */
1075 }
1076
1077 /* After all of the arduous calculation setup with the fastest
1078 * cas latency I can use.
1079 */
1080
1081 dram_timing = pci_read_config32(MCHDEV, DRT);
1082 dram_timing &= ~(DRT_CAS_MASK);
1083
1084 dram_read_timing =
1085 pci_read_config16(MCHDEV, DRDCTL);
1086 dram_read_timing &= 0xF000;
1087
1088 if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
1089 dram_timing |= DRT_CAS_2_0;
1090 dram_read_timing |= 0x0222;
1091 } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
1092 uint32_t dram_row_attributes =
1093 pci_read_config32(MCHDEV, DRA);
1094
1095 dram_timing |= DRT_CAS_2_5;
1096
1097 // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
1098 // different value if all DIMM slots are populated
1099
1100 if ((dram_row_attributes & 0xff)
1101 && (dram_row_attributes & 0xff00)
1102 && (dram_row_attributes & 0xff0000)
1103 && (dram_row_attributes & 0xff000000)) {
1104 // All slots populated
1105 dram_read_timing |= 0x0882;
1106 } else {
1107 // Some unpopulated slots
1108 dram_read_timing |= 0x0662;
1109 }
1110 } else
1111 die("No CAS# latencies compatible with all DIMMs!!\n");
1112
1113 pci_write_config32(MCHDEV, DRT, dram_timing);
1114
1115 /* set master DLL reset */
1116 dword = pci_read_config32(MCHDEV, 0x88);
1117 dword |= (1 << 26);
1118 pci_write_config32(MCHDEV, 0x88, dword);
1119 /* patch try register 88 is undocumented tnz */
1120 dword &= 0x0ca17fff;
1121 dword |= 0xd14a5000;
1122 pci_write_config32(MCHDEV, 0x88, dword);
1123
1124 pci_write_config16(MCHDEV, DRDCTL,
1125 dram_read_timing);
1126
1127 /* clear master DLL reset */
1128 dword = pci_read_config32(MCHDEV, 0x88);
1129 dword &= ~(1 << 26);
1130 pci_write_config32(MCHDEV, 0x88, dword);
1131
1132 return;
1133
1134 hw_err:
1135 die(SPD_ERROR);
1136 }
1137
1138 /**
1139 * Configure the refresh interval so that we refresh no more often than
1140 * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs
1141 * don't support it.
1142 *
1143 * @param ctrl PCI addresses of memory controller functions, and SMBus
1144 * addresses of DIMM slots on the mainboard.
1145 * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
1146 */
configure_e7501_dram_controller_mode(const struct mem_controller * ctrl,uint8_t dimm_mask)1147 static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl,
1148 uint8_t dimm_mask)
1149 {
1150 int i;
1151
1152 // Initial settings
1153 uint32_t controller_mode = pci_read_config32(MCHDEV, DRC);
1154 uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
1155
1156 // Code below assumes that most aggressive settings are in
1157 // force when we are called, either via E7501 reset defaults
1158 // or by sdram_set_registers():
1159 // - ECC enabled
1160 // - No refresh
1161
1162 ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC
1163 ASSERT(!(controller_mode & (7 << 8))); // Refresh
1164
1165 /* Walk through _all_ dimms and find the least-common denominator for:
1166 * - ECC support
1167 * - refresh rates
1168 */
1169
1170 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1171 uint32_t dimm_refresh_mode;
1172 int value;
1173 uint16_t dimm_socket_address;
1174
1175 if (!(dimm_mask & (1 << i))) {
1176 continue; // This DIMM not usable
1177 }
1178
1179 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1180 dimm_socket_address = ctrl->channel0[i];
1181 else
1182 dimm_socket_address =
1183 ctrl->channel1[i -
1184 MAX_DIMM_SOCKETS_PER_CHANNEL];
1185
1186 // Disable ECC mode if any one of the DIMMs does not support ECC
1187 // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
1188
1189 value = smbus_read_byte(dimm_socket_address,
1190 SPD_DIMM_CONFIG_TYPE);
1191 die_on_spd_error(value);
1192 if (value != ERROR_SCHEME_ECC) {
1193 controller_mode &= ~(3 << 20);
1194 }
1195
1196 value = smbus_read_byte(dimm_socket_address, SPD_REFRESH);
1197 die_on_spd_error(value);
1198 value &= 0x7f; // Mask off self-refresh bit
1199 if (value > MAX_SPD_REFRESH_RATE) {
1200 printk(BIOS_ERR, "unsupported refresh rate\n");
1201 continue;
1202 }
1203 // Get the appropriate E7501 refresh mode for this DIMM
1204 dimm_refresh_mode = refresh_rate_map[value];
1205 if (dimm_refresh_mode > 7) {
1206 printk(BIOS_ERR, "unsupported refresh rate\n");
1207 continue;
1208 }
1209 // If this DIMM requires more frequent refresh than others,
1210 // update the system setting
1211 if (refresh_frequency[dimm_refresh_mode] >
1212 refresh_frequency[system_refresh_mode])
1213 system_refresh_mode = dimm_refresh_mode;
1214
1215 /* go to the next DIMM */
1216 }
1217
1218 controller_mode |= (system_refresh_mode << 8);
1219
1220 // Configure the E7501
1221 pci_write_config32(MCHDEV, DRC, controller_mode);
1222 }
1223
1224 /**
1225 * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM
1226 * parameters read via SPD. This tells the controller the width of the SDRAM
1227 * chips on each DIMM side (x4 or x8) and the page size of each DIMM side
1228 * (4, 8, 16, or 32 KB).
1229 *
1230 * @param ctrl PCI addresses of memory controller functions, and SMBus
1231 * addresses of DIMM slots on the mainboard.
1232 * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
1233 */
configure_e7501_row_attributes(const struct mem_controller * ctrl,uint8_t dimm_mask)1234 static void configure_e7501_row_attributes(const struct mem_controller
1235 *ctrl, uint8_t dimm_mask)
1236 {
1237 int i;
1238 uint32_t row_attributes = 0;
1239
1240 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1241 uint16_t dimm_socket_address = ctrl->channel0[i];
1242 struct dimm_size page_size;
1243 struct dimm_size sdram_width;
1244
1245 if (!(dimm_mask & (1 << i)))
1246 continue; // This DIMM not usable
1247
1248 // Get the relevant parameters via SPD
1249 page_size = sdram_spd_get_page_size(dimm_socket_address);
1250 sdram_width = sdram_spd_get_width(dimm_socket_address);
1251
1252 // Update the DRAM Row Attributes.
1253 // Page size is encoded as log2(page size in bits) - log2(8 Kb)
1254 // NOTE: 8 Kb = 2^13
1255 row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row
1256
1257 if (sdram_width.side2 > 0)
1258 row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD
1259
1260 // Set x4 flags if appropriate
1261 if (sdram_width.side1 == 4) {
1262 row_attributes |= 0x08 << (i << 3);
1263 }
1264
1265 if (sdram_width.side2 == 4) {
1266 row_attributes |= 0x08 << ((i << 3) + 4);
1267 }
1268
1269 /* go to the next DIMM */
1270 }
1271
1272 /* Write the new row attributes register */
1273 pci_write_config32(MCHDEV, DRA, row_attributes);
1274 }
1275
1276 /*
1277 * Enable clock signals for populated DIMM sockets and disable them for
1278 * unpopulated sockets (to reduce EMI).
1279 *
1280 * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
1281 */
enable_e7501_clocks(uint8_t dimm_mask)1282 static void enable_e7501_clocks(uint8_t dimm_mask)
1283 {
1284 int i;
1285 uint8_t clock_disable = pci_read_config8(MCHDEV, CKDIS);
1286
1287 pci_write_config8(MCHDEV, 0x8e, 0xb0);
1288
1289 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1290 uint8_t socket_mask = 1 << i;
1291
1292 if (dimm_mask & socket_mask)
1293 clock_disable &= ~socket_mask; // DIMM present, enable clock
1294 else
1295 clock_disable |= socket_mask; // DIMM absent, disable clock
1296 }
1297
1298 pci_write_config8(MCHDEV, CKDIS, clock_disable);
1299 }
1300
1301 /* DIMM-dependent configuration functions */
1302
1303 /**
1304 * DDR Receive FIFO RE-Sync (?)
1305 */
RAM_RESET_DDR_PTR(void)1306 static void RAM_RESET_DDR_PTR(void)
1307 {
1308 uint8_t byte;
1309 byte = pci_read_config8(MCHDEV, 0x88);
1310 byte |= (1 << 4);
1311 pci_write_config8(MCHDEV, 0x88, byte);
1312
1313 byte = pci_read_config8(MCHDEV, 0x88);
1314 byte &= ~(1 << 4);
1315 pci_write_config8(MCHDEV, 0x88, byte);
1316 }
1317
1318 /**
1319 * Copy 64 bytes from one location to another.
1320 *
1321 * @param src_addr TODO
1322 * @param dst_addr TODO
1323 */
write_8dwords(const uint32_t * src_addr,u8 * dst_addr)1324 static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr)
1325 {
1326 int i;
1327 for (i = 0; i < 8; i++) {
1328 write32(dst_addr, *src_addr);
1329 src_addr++;
1330 dst_addr += sizeof(uint32_t);
1331 }
1332 }
1333
1334 /**
1335 * Set the E7501's (undocumented) RCOMP registers.
1336 *
1337 * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual,
1338 * RCOMP registers appear to affect drive strength, pullup/pulldown offset,
1339 * and slew rate of various signal groups.
1340 *
1341 * Comments below are conjecture based on apparent similarity between the
1342 * E7501 and these two chips.
1343 */
rcomp_copy_registers(void)1344 static void rcomp_copy_registers(void)
1345 {
1346 uint32_t dword;
1347 uint8_t strength_control;
1348
1349 RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
1350
1351 /* Begin to write the RCOMP registers */
1352 write8(RCOMP_MMIO + 0x2c, 0x0);
1353
1354 // Set CMD and DQ/DQS strength to 2x (?)
1355 strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88;
1356 strength_control |= 0x40;
1357 write8(RCOMP_MMIO + DQCMDSTR, strength_control);
1358 write_8dwords(slew_2x, RCOMP_MMIO + 0x80);
1359 write16(RCOMP_MMIO + 0x42, 0);
1360
1361 // Set CMD and DQ/DQS strength to 2x (?)
1362 strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8;
1363 strength_control |= 0x04;
1364 write8(RCOMP_MMIO + DQCMDSTR, strength_control);
1365 write_8dwords(slew_2x, RCOMP_MMIO + 0x60);
1366 write16(RCOMP_MMIO + 0x40, 0);
1367
1368 // Set RCVEnOut# strength to 2x (?)
1369 strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8;
1370 strength_control |= 0x04;
1371 write8(RCOMP_MMIO + RCVENSTR, strength_control);
1372 write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0);
1373 write16(RCOMP_MMIO + 0x50, 0);
1374
1375 // Set CS# strength for x4 SDRAM to 2x (?)
1376 strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88;
1377 strength_control |= 0x04;
1378 write8(RCOMP_MMIO + CSBSTR, strength_control);
1379 write_8dwords(slew_2x, RCOMP_MMIO + 0x140);
1380 write16(RCOMP_MMIO + 0x48, 0);
1381
1382 // Set CS# strength for x4 SDRAM to 2x (?)
1383 strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F;
1384 strength_control |= 0x40;
1385 write8(RCOMP_MMIO + CSBSTR, strength_control);
1386 write_8dwords(slew_2x, RCOMP_MMIO + 0x160);
1387 write16(RCOMP_MMIO + 0x4a, 0);
1388
1389 // Set CKE strength for x4 SDRAM to 2x (?)
1390 strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88;
1391 strength_control |= 0x04;
1392 write8(RCOMP_MMIO + CKESTR, strength_control);
1393 write_8dwords(slew_2x, RCOMP_MMIO + 0xa0);
1394 write16(RCOMP_MMIO + 0x44, 0);
1395
1396 // Set CKE strength for x4 SDRAM to 2x (?)
1397 strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F;
1398 strength_control |= 0x40;
1399 write8(RCOMP_MMIO + CKESTR, strength_control);
1400 write_8dwords(slew_2x, RCOMP_MMIO + 0xc0);
1401 write16(RCOMP_MMIO + 0x46, 0);
1402
1403 // Set CK strength for x4 SDRAM to 1x (?)
1404 strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88;
1405 strength_control |= 0x01;
1406 write8(RCOMP_MMIO + CKSTR, strength_control);
1407 write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180);
1408 write16(RCOMP_MMIO + 0x4c, 0);
1409
1410 // Set CK strength for x4 SDRAM to 1x (?)
1411 strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F;
1412 strength_control |= 0x10;
1413 write8(RCOMP_MMIO + CKSTR, strength_control);
1414 write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0);
1415 write16(RCOMP_MMIO + 0x4e, 0);
1416
1417 dword = read32(RCOMP_MMIO + 0x400);
1418 dword &= 0x7f7fffff;
1419 write32(RCOMP_MMIO + 0x400, dword);
1420
1421 dword = read32(RCOMP_MMIO + 0x408);
1422 dword &= 0x7f7fffff;
1423 write32(RCOMP_MMIO + 0x408, dword);
1424 }
1425
ram_set_rcomp_regs(void)1426 static void ram_set_rcomp_regs(void)
1427 {
1428 /* Set the RCOMP MMIO base address */
1429 mchtest_control(RCOMP_BAR_ENABLE);
1430 pci_write_config32(MCHDEV, SMRBASE, (uintptr_t)RCOMP_MMIO);
1431
1432 /* Block RCOMP updates while we configure the registers */
1433 rcomp_smr_control(RCOMP_HOLD);
1434 rcomp_copy_registers();
1435 d060_control(D060_CMD_0);
1436 mchtest_control(MCHTST_CMD_0);
1437
1438 uint8_t revision = pci_read_config8(MCHDEV, 0x08);
1439 if (revision >= 3) {
1440 rcomp_smr_control(RCOMP_SMR_00);
1441 rcomp_smr_control(RCOMP_SMR_01);
1442 }
1443 rcomp_smr_control(RCOMP_RELEASE);
1444
1445 /* Wait 40 usec */
1446 SLOW_DOWN_IO;
1447
1448 /* Clear the RCOMP MMIO base address */
1449 pci_write_config32(MCHDEV, SMRBASE, 0);
1450 mchtest_control(RCOMP_BAR_DISABLE);
1451 }
1452
1453 /*-----------------------------------------------------------------------------
1454 Public interface:
1455 -----------------------------------------------------------------------------*/
1456
1457 /**
1458 * Go through the JEDEC initialization sequence for all DIMMs, then enable
1459 * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up
1460 * and running.
1461 *
1462 * @param ctrl PCI addresses of memory controller functions, and SMBus
1463 * addresses of DIMM slots on the mainboard.
1464 */
sdram_enable(const struct mem_controller * ctrl)1465 static void sdram_enable(const struct mem_controller *ctrl)
1466 {
1467 uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD);
1468 uint32_t dram_controller_mode;
1469
1470 if (dimm_mask == 0)
1471 return;
1472
1473 /* 1 & 2 Power up and start clocks */
1474 RAM_DEBUG_MESSAGE("Ram Enable 1\n");
1475 RAM_DEBUG_MESSAGE("Ram Enable 2\n");
1476
1477 /* A 200us delay is needed */
1478 DO_DELAY; EXTRA_DELAY;
1479
1480 /* 3. Apply NOP */
1481 RAM_DEBUG_MESSAGE("Ram Enable 3\n");
1482 do_ram_command(RAM_COMMAND_NOP, 0);
1483
1484 /* 4 Precharge all */
1485 RAM_DEBUG_MESSAGE("Ram Enable 4\n");
1486 do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1487 /* wait until the all banks idle state... */
1488
1489 /* 5. Issue EMRS to enable DLL */
1490 RAM_DEBUG_MESSAGE("Ram Enable 5\n");
1491 do_ram_command(RAM_COMMAND_EMRS,
1492 SDRAM_EXTMODE_DLL_ENABLE |
1493 SDRAM_EXTMODE_DRIVE_NORMAL);
1494
1495 /* 6. Reset DLL */
1496 RAM_DEBUG_MESSAGE("Ram Enable 6\n");
1497 set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
1498 EXTRA_DELAY;
1499 /* Ensure a 200us delay between the DLL reset in step 6 and the final
1500 * mode register set in step 9.
1501 * Infineon needs this before any other command is sent to the ram.
1502 */
1503 DO_DELAY; EXTRA_DELAY;
1504
1505 /* 7 Precharge all */
1506 RAM_DEBUG_MESSAGE("Ram Enable 7\n");
1507 do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1508
1509 /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1510 /* And for good luck 6 more CBRs */
1511 RAM_DEBUG_MESSAGE("Ram Enable 8\n");
1512 int i;
1513 for (i = 0; i < 8; i++)
1514 do_ram_command(RAM_COMMAND_CBR, 0);
1515
1516 /* 9 mode register set */
1517 RAM_DEBUG_MESSAGE("Ram Enable 9\n");
1518 set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
1519
1520 /* 10 DDR Receive FIFO RE-Sync */
1521 RAM_DEBUG_MESSAGE("Ram Enable 10\n");
1522 RAM_RESET_DDR_PTR();
1523 EXTRA_DELAY;
1524
1525 /* 11 normal operation */
1526 RAM_DEBUG_MESSAGE("Ram Enable 11\n");
1527 do_ram_command(RAM_COMMAND_NORMAL, 0);
1528
1529 // Reconfigure the row boundaries and Top of Low Memory
1530 // to match the true size of the DIMMs
1531 configure_e7501_ram_addresses(ctrl, dimm_mask);
1532
1533 /* Finally enable refresh */
1534 dram_controller_mode = pci_read_config32(MCHDEV, DRC);
1535 dram_controller_mode |= (1 << 29);
1536 pci_write_config32(MCHDEV, DRC, dram_controller_mode);
1537 EXTRA_DELAY;
1538 }
1539
1540 /**
1541 * @param ctrl PCI addresses of memory controller functions, and SMBus
1542 * addresses of DIMM slots on the mainboard.
1543 */
sdram_post_ecc(const struct mem_controller * ctrl)1544 static void sdram_post_ecc(const struct mem_controller *ctrl)
1545 {
1546 /* Fast CS# Enable. */
1547 uint32_t dram_controller_mode = pci_read_config32(MCHDEV, DRC);
1548 dram_controller_mode = pci_read_config32(MCHDEV, DRC);
1549 dram_controller_mode |= (1 << 17);
1550 pci_write_config32(MCHDEV, DRC, dram_controller_mode);
1551 }
1552
1553 /**
1554 * Configure SDRAM controller parameters that depend on characteristics of the
1555 * DIMMs installed in the system. These characteristics are read from the
1556 * DIMMs via the standard Serial Presence Detect (SPD) interface.
1557 *
1558 * @param ctrl PCI addresses of memory controller functions, and SMBus
1559 * addresses of DIMM slots on the mainboard.
1560 */
sdram_set_spd_registers(const struct mem_controller * ctrl)1561 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
1562 {
1563 uint8_t dimm_mask;
1564
1565 RAM_DEBUG_MESSAGE("Reading SPD data...\n");
1566
1567 dimm_mask = spd_get_supported_dimms(ctrl);
1568
1569 if (dimm_mask == 0) {
1570 printk(BIOS_DEBUG, "No usable memory for this controller\n");
1571 } else {
1572 enable_e7501_clocks(dimm_mask);
1573
1574 RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
1575
1576 configure_e7501_row_attributes(ctrl, dimm_mask);
1577 configure_e7501_dram_controller_mode(ctrl, dimm_mask);
1578 configure_e7501_cas_latency(ctrl, dimm_mask);
1579 RAM_RESET_DDR_PTR();
1580
1581 configure_e7501_dram_timing(ctrl, dimm_mask);
1582 DO_DELAY;
1583 RAM_DEBUG_MESSAGE("done\n");
1584 }
1585
1586 /* NOTE: configure_e7501_ram_addresses() is NOT called here.
1587 * We want to keep the default 64 MB/row mapping until sdram_enable() is called,
1588 * even though the default mapping is almost certainly incorrect.
1589 * The default mapping makes it easy to initialize all of the DIMMs
1590 * even if the total system memory is > 4 GB.
1591 *
1592 * Save the dimm_mask for when sdram_enable is called, so it can call
1593 * configure_e7501_ram_addresses() without having to regenerate the bitmask
1594 * of usable DIMMs.
1595 */
1596 pci_write_config16(MCHDEV, SKPD, dimm_mask);
1597 }
1598
1599 /**
1600 * Do basic RAM setup that does NOT depend on serial presence detect
1601 * information (i.e. independent of DIMM specifics).
1602 *
1603 * @param ctrl PCI addresses of memory controller functions, and SMBus
1604 * addresses of DIMM slots on the mainboard.
1605 */
sdram_set_registers(const struct mem_controller * ctrl)1606 static void sdram_set_registers(const struct mem_controller *ctrl)
1607 {
1608 uint32_t dword;
1609 uint16_t word;
1610 uint8_t byte;
1611
1612 ram_set_rcomp_regs();
1613
1614 /* Enable 0:0.1, 0:2.1 */
1615 word = pci_read_config16(MCHDEV, DVNP);
1616 word &= ~0x05;
1617 pci_write_config16(MCHDEV, DVNP, word);
1618
1619 /* Disable high-memory remap (power-on defaults, really) */
1620 pci_write_config16(MCHDEV, REMAPBASE, 0x03ff);
1621 pci_write_config16(MCHDEV, REMAPLIMIT, 0x0);
1622
1623 /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */
1624 int i;
1625 pci_write_config8(MCHDEV, PAM_0, 0x30);
1626 for (i = 1; i <= 6; i++)
1627 pci_write_config8(MCHDEV, PAM_0 + i, 0x33);
1628
1629 /* Conservatively say each row has 64MB of ram, we will fix this up later
1630 * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13
1631 *
1632 * FIXME: Hard-coded limit to first four rows to prevent overlap!
1633 */
1634 pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201);
1635 pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404);
1636 //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605);
1637 pci_write_config16(MCHDEV, TOLM, (1<<13));
1638
1639 /* DIMM clocks off */
1640 pci_write_config8(MCHDEV, CKDIS, 0xff);
1641
1642 /* reset row attributes */
1643 pci_write_config32(MCHDEV, DRA, 0x0);
1644
1645 // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
1646 // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
1647 dword = pci_read_config32(MCHDEV, DRT);
1648 dword &= 0xC7F8FFFF;
1649 dword |= (0x28<<24)|(0x03<<16);
1650 pci_write_config32(MCHDEV, DRT, dword);
1651
1652 dword = pci_read_config32(MCHDEV, DRC);
1653 dword &= 0xffcef8f7;
1654 dword |= 0x00210008;
1655 pci_write_config32(MCHDEV, DRC, dword);
1656
1657 /* Undocumented */
1658 pci_write_config8(MCHDEV, 0x88, 0x80);
1659
1660 /* Undocumented. Set much later in vendor BIOS. */
1661 byte = pci_read_config8(MCHDEV, 0xd9);
1662 byte &= ~0x60;
1663 pci_write_config8(MCHDEV, 0xd9, byte);
1664
1665 uint8_t revision = pci_read_config8(MCHDEV, 0x08);
1666 if (revision >= 3)
1667 d060_control(D060_CMD_1);
1668 }
1669
e7505_mch_is_ready(void)1670 static int e7505_mch_is_ready(void)
1671 {
1672 uint32_t dword = pci_read_config32(MCHDEV, DRC);
1673 return !!(dword & DRC_DONE);
1674 }
1675
1676 #define HOST_BRIDGE PCI_DEV(0, 0, 0)
1677
sdram_initialize(void)1678 void sdram_initialize(void)
1679 {
1680 static const struct mem_controller memctrl[] = {
1681 {
1682 .d0 = PCI_DEV(0, 0, 0),
1683 .d0f1 = PCI_DEV(0, 0, 1),
1684 .channel0 = { 0x50, 0x52, 0, 0 },
1685 .channel1 = { 0x51, 0x53, 0, 0 },
1686 },
1687 };
1688
1689 /* If this is a warm boot, some initialisation can be skipped */
1690 if (!e7505_mch_is_ready()) {
1691 /* The real MCH initialisation. */
1692 timestamp_add_now(TS_INITRAM_START);
1693
1694 sdram_set_registers(memctrl);
1695 sdram_set_spd_registers(memctrl);
1696 sdram_enable(memctrl);
1697
1698 /* Hook for post ECC scrub settings and debug. */
1699 sdram_post_ecc(memctrl);
1700
1701 timestamp_add_now(TS_INITRAM_END);
1702 }
1703
1704
1705 if (CONFIG(SMM_TSEG))
1706 pci_write_config8(HOST_BRIDGE, ESMRAMC, TSEG_SZ_1M | T_EN);
1707
1708 printk(BIOS_DEBUG, "SDRAM is up.\n");
1709 }
1710