1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <spd.h>
4 #include <delay.h>
5 #include <stdint.h>
6 #include <device/mmio.h>
7 #include <device/pci_ops.h>
8 #include <device/pci_def.h>
9 #include <device/smbus_host.h>
10 #include <console/console.h>
11 #include <commonlib/console/post_codes.h>
12 #include <timestamp.h>
13 #include "i440bx.h"
14 #include "raminit.h"
15
16 /*
17 * Macros and definitions
18 */
19
20 /* Debugging macros. */
21 #if CONFIG(DEBUG_RAM_SETUP)
22 #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x)
23 #define DUMPNORTH() dump_pci_device(NB)
24 #else
25 #define PRINT_DEBUG(x...)
26 #define DUMPNORTH()
27 #endif
28
29 /* SDRAMC[7:5] - SDRAM Mode Select (SMS). */
30 #define RAM_COMMAND_NORMAL 0x0
31 #define RAM_COMMAND_NOP 0x1
32 #define RAM_COMMAND_PRECHARGE 0x2
33 #define RAM_COMMAND_MRS 0x3
34 #define RAM_COMMAND_CBR 0x4
35
36 /* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as
37 * defined in DRAMC[2:0].
38 *
39 * [0] == Normal 15.625 us -> 15.6 us
40 * [1] == Reduced(.25X) 3.9 us -> 7.8 ns
41 * [2] == Reduced(.5X) 7.8 us -> 7.8 us
42 * [3] == Extended(2x) 31.3 us -> 31.2 us
43 * [4] == Extended(4x) 62.5 us -> 62.4 us
44 * [5] == Extended(8x) 125 us -> 124.8 us
45 */
46 static const uint32_t refresh_rate_map[] = {
47 1, 5, 5, 2, 3, 4
48 };
49
50 /* Table format: register, value. */
51 static const u8 register_values[] = {
52 /* NBXCFG - NBX Configuration Register
53 * 0x50 - 0x53
54 *
55 * [31:24] SDRAM Row Without ECC
56 * 0 = ECC components are populated in this row
57 * 1 = ECC components are not populated in this row
58 * [23:19] Reserved
59 * [18:18] Host Bus Fast Data Ready Enable (HBFDRE)
60 * Assertion of DRAM data on host bus occurs...
61 * 0 = ...one clock after sampling snoop results (default)
62 * 1 = ...on the same clock the snoop result is being sampled
63 * (this mode is faster by one clock cycle)
64 * [17:17] ECC - EDO static Drive mode
65 * 0 = Normal mode (default)
66 * 1 = ECC signals are always driven
67 * [16:16] IDSEL_REDIRECT
68 * 0 = IDSEL1 is allocated to this bridge (default)
69 * 1 = IDSEL7 is allocated to this bridge
70 * [15:15] WSC# Handshake Disable
71 * 1 = Uni-processor mode
72 * 0 = Dual-processor mode with external IOAPIC (default)
73 * [14:14] Intel Reserved
74 * [13:12] Host/DRAM Frequency
75 * 00 = 100 MHz
76 * 01 = Reserved
77 * 10 = 66 MHz
78 * 11 = Reserved
79 * [11:11] AGP to PCI Access Enable
80 * 1 = Enable
81 * 0 = Disable
82 * [10:10] PCI Agent to Aperture Access Disable
83 * 1 = Disable
84 * 0 = Enable (default)
85 * [09:09] Aperture Access Global Enable
86 * 1 = Enable
87 * 0 = Disable
88 * [08:07] DRAM Data Integrity Mode (DDIM)
89 * 00 = Non-ECC
90 * 01 = EC-only
91 * 10 = ECC Mode
92 * 11 = ECC Mode with hardware scrubbing enabled
93 * [06:06] ECC Diagnostic Mode Enable (EDME)
94 * 1 = Enable
95 * 0 = Normal operation mode (default)
96 * [05:05] MDA Present (MDAP)
97 * Works in conjunction with the VGA_EN bit.
98 * VGA_EN MDAP
99 * 0 x All VGA cycles are sent to PCI
100 * 1 0 All VGA cycles are sent to AGP
101 * 1 1 All VGA cycles are sent to AGP, except for
102 * cycles in the MDA range.
103 * [04:04] Reserved
104 * [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO)
105 * 1 = Enable
106 * 0 = Disable
107 * [02:02] In-Order Queue Depth (IOQD)
108 * 1 = In-order queue = maximum
109 * 0 = A7# is sampled asserted (i.e., 0)
110 * [01:00] Reserved
111 */
112 NBXCFG + 0, 0x0c,
113 #if CONFIG(SMP)
114 NBXCFG + 1, 0x00,
115 #else
116 NBXCFG + 1, 0x80,
117 #endif
118 NBXCFG + 2, 0x00,
119 NBXCFG + 3, 0xff,
120
121 /* DRAMC - DRAM Control Register
122 * 0x57
123 *
124 * [7:6] Reserved
125 * [5:5] Module Mode Configuration (MMCONFIG)
126 * The combination of SDRAMPWR and this bit (set by an
127 * external strapping option) determine how CKE works.
128 * SDRAMPWR MMCONFIG
129 * 0 0 = 3 DIMM, CKE[5:0] driven
130 * X 1 = 3 DIMM, CKE0 only
131 * 1 0 = 4 DIMM, GCKE only
132 * [4:3] DRAM Type (DT)
133 * 00 = EDO
134 * 01 = SDRAM
135 * 10 = Registered SDRAM
136 * 11 = Reserved
137 * Note: EDO, SDRAM and Registered SDRAM cannot be mixed.
138 * [2:0] DRAM Refresh Rate (DRR)
139 * 000 = Refresh disabled
140 * 001 = 15.6 us
141 * 010 = 31.2 us
142 * 011 = 62.4 us
143 * 100 = 124.8 us
144 * 101 = 249.6 us
145 * 110 = Reserved
146 * 111 = Reserved
147 */
148 /* Choose SDRAM (not registered), and disable refresh for now. */
149 DRAMC, 0x08,
150
151 /*
152 * PAM[6:0] - Programmable Attribute Map Registers
153 * 0x59 - 0x5f
154 *
155 * 0x59 [3:0] Reserved
156 * 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area
157 * 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS
158 * 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS
159 * 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS
160 * 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS
161 * 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS
162 * 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS
163 * 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS
164 * 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS
165 * 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS extension
166 * 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS extension
167 * 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS extension
168 * 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS extension
169 *
170 * Bit assignment:
171 * 00 = DRAM Disabled (all access goes to memory mapped I/O space)
172 * 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space)
173 * 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space)
174 * 11 = Read/Write (all access goes to DRAM)
175 */
176
177 /*
178 * Map all legacy regions to RAM (read/write). This is required if
179 * you want to use the RAM area from 768 KB - 1 MB. If the PAM
180 * registers are not set here appropriately, the RAM in that region
181 * will not be accessible, thus a RAM check of it will also fail.
182 */
183 PAM0, 0x30,
184 PAM1, 0x33,
185 PAM2, 0x33,
186 PAM3, 0x33,
187 PAM4, 0x33,
188 PAM5, 0x33,
189 PAM6, 0x33,
190
191 /* DRB[0:7] - DRAM Row Boundary Registers
192 * 0x60 - 0x67
193 *
194 * An array of 8 byte registers, which hold the ending memory address
195 * assigned to each pair of DIMMs, in 8MB granularity.
196 *
197 * 0x60 DRB0 = Total memory in row0 (in 8 MB)
198 * 0x61 DRB1 = Total memory in row0+1 (in 8 MB)
199 * 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB)
200 * 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB)
201 * 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB)
202 * 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB)
203 * 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB)
204 * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB)
205 */
206 /* DRBs will be set later. */
207
208 /* FDHC - Fixed DRAM Hole Control Register
209 * 0x68
210 *
211 * Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB.
212 *
213 * [7:6] Hole Enable (HEN)
214 * 00 = None
215 * 01 = 512 KB - 640 KB (128 KB)
216 * 10 = 15 MB - 16 MB (1 MB)
217 * 11 = Reserved
218 * [5:0] Reserved
219 */
220 /* No memory holes. */
221 FDHC, 0x00,
222
223 /* RPS - SDRAM Row Page Size Register
224 * 0x74 - 0x75
225 *
226 * Sets the row page size for SDRAM. For EDO memory, the page
227 * size is fixed at 2 KB.
228 *
229 * Bits[1:0] Page Size
230 * 00 2 KB
231 * 01 4 KB
232 * 10 8 KB
233 * 11 Reserved
234 *
235 * RPS bits Corresponding DRB register
236 * [01:00] DRB[0], row 0
237 * [03:02] DRB[1], row 1
238 * [05:04] DRB[2], row 2
239 * [07:06] DRB[3], row 3
240 * [09:08] DRB[4], row 4
241 * [11:10] DRB[5], row 5
242 * [13:12] DRB[6], row 6
243 * [15:14] DRB[7], row 7
244 */
245 /* Power on defaults to 2KB. Will be set later. */
246
247 /* SDRAMC - SDRAM Control Register
248 * 0x76 - 0x77
249 *
250 * [15:10] Reserved
251 * [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT)
252 * 00 = Illegal
253 * 01 = Add a clock delay to the lead-off clock count
254 * 1x = Illegal
255 * [07:05] SDRAM Mode Select (SMS)
256 * 000 = Normal SDRAM Operation (default)
257 * 001 = NOP Command Enable
258 * 010 = All Banks Precharge Enable
259 * 011 = Mode Register Set Enable
260 * 100 = CBR Enable
261 * 101 = Reserved
262 * 110 = Reserved
263 * 111 = Reserved
264 * [04:04] SDRAMPWR
265 * 0 = 3 DIMM configuration
266 * 1 = 4 DIMM configuration
267 * [03:03] Leadoff Command Timing (LCT)
268 * 0 = 4 CS# Clock
269 * 1 = 3 CS# Clock
270 * [02:02] CAS# Latency (CL)
271 * 0 = 3 DCLK CAS# latency
272 * 1 = 2 DCLK CAS# latency
273 * [01:01] SDRAM RAS# to CAS# Delay (SRCD)
274 * 0 = 3 clocks between a row activate and a read or write cmd.
275 * 1 = 2 clocks between a row activate and a read or write cmd.
276 * [00:00] SDRAM RAS# Precharge (SRP)
277 * 0 = 3 clocks of RAS# precharge
278 * 1 = 2 clocks of RAS# precharge
279 */
280 #if CONFIG(SDRAMPWR_4DIMM)
281 SDRAMC, 0x10, /* The board has 4 DIMM slots. */
282 #else
283 SDRAMC, 0x00, /* The board has 3 DIMM slots. */
284 #endif
285
286 /* PGPOL - Paging Policy Register
287 * 0x78 - 0x79
288 *
289 * [15:08] Banks per Row (BPR)
290 * Each bit in this field corresponds to one row of the memory
291 * array. Bit 15 corresponds to row 7 while bit 8 corresponds
292 * to row 0. Bits for empty rows are "don't care".
293 * 0 = 2 banks
294 * 1 = 4 banks
295 * [07:05] Reserved
296 * [04:04] Intel Reserved
297 * [03:00] DRAM Idle Timer (DIT)
298 * 0000 = 0 clocks
299 * 0001 = 2 clocks
300 * 0010 = 4 clocks
301 * 0011 = 8 clocks
302 * 0100 = 10 clocks
303 * 0101 = 12 clocks
304 * 0110 = 16 clocks
305 * 0111 = 32 clocks
306 * 1xxx = Infinite (pages are not closed for idle condition)
307 */
308 /* PGPOL will be set later. */
309
310 /* PMCR - Power Management Control Register
311 * 0x7a
312 *
313 * [7] Power Down SDRAM Enable (PDSE)
314 * 1 = Enable
315 * 0 = Disable
316 * [6] ACPI Control Register Enable (SCRE)
317 * 1 = Enable
318 * 0 = Disable (default)
319 * [5] Suspend Refresh Type (SRT)
320 * 1 = Self refresh mode
321 * 0 = CBR fresh mode
322 * [4] Normal Refresh Enable (NREF_EN)
323 * 1 = Enable
324 * 0 = Disable
325 * [3] Quick Start Mode (QSTART)
326 * 1 = Quick start mode for the processor is enabled
327 * [2] Gated Clock Enable (GCLKEN)
328 * 1 = Enable
329 * 0 = Disable
330 * [1] AGP Disable (AGP_DIS)
331 * 1 = AGP disabled (Hardware strap)
332 * [0] CPU reset without PCIRST enable (CRst_En)
333 * 1 = Enable
334 * 0 = Disable
335 */
336 /* PMCR will be set later. */
337
338 /* Enable SCRR.SRRAEN and let BX choose the SRR. */
339 SCRR + 1, 0x10,
340 };
341
342 /*-----------------------------------------------------------------------------
343 SDRAM configuration functions.
344 -----------------------------------------------------------------------------*/
345
346 /**
347 * Send the specified RAM command to all DIMMs.
348 *
349 * @param command The RAM command to send to the DIMM(s).
350 */
do_ram_command(u32 command)351 static void do_ram_command(u32 command)
352 {
353 int i, caslatency;
354 u8 dimm_start, dimm_end;
355 u16 reg16;
356 void *addr;
357 u32 addr_offset;
358
359 /* Configure the RAM command. */
360 reg16 = pci_read_config16(NB, SDRAMC);
361 reg16 &= 0xff1f; /* Clear bits 7-5. */
362 reg16 |= (u16)(command << 5); /* Write command into bits 7-5. */
363 pci_write_config16(NB, SDRAMC, reg16);
364
365 /*
366 * RAM_COMMAND_NORMAL affects only the memory controller and
367 * doesn't need to be "sent" to the DIMMs.
368 */
369 if (command == RAM_COMMAND_NORMAL)
370 return;
371
372 /* Send the RAM command to each row of memory. */
373 dimm_start = 0;
374 for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
375 addr_offset = 0;
376 caslatency = 3; /* TODO: Dynamically get CAS latency later. */
377 if (command == RAM_COMMAND_MRS) {
378 /*
379 * MAA[12:11,9:0] must be inverted when sent to DIMM
380 * 2 or 3 (no inversion if sent to DIMM 0 or 1).
381 */
382 if ((i >= 0 && i <= 3) && caslatency == 3)
383 addr_offset = 0x1d0;
384 if ((i >= 4 && i <= 7) && caslatency == 3)
385 addr_offset = 0x1e28;
386 if ((i >= 0 && i <= 3) && caslatency == 2)
387 addr_offset = 0x150;
388 if ((i >= 4 && i <= 7) && caslatency == 2)
389 addr_offset = 0x1ea8;
390 }
391
392 dimm_end = pci_read_config8(NB, DRB + i);
393
394 addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset);
395 if (dimm_end > dimm_start) {
396 read32(addr);
397 }
398
399 /* Set the start of the next DIMM. */
400 dimm_start = dimm_end;
401 }
402 }
403
set_dram_buffer_strength(void)404 static void set_dram_buffer_strength(void)
405 {
406 /*
407 * Program MBSC[39:0] and MBFS[23:0].
408 *
409 * The 440BX datasheet says buffer frequency is independent from bus
410 * frequency and mismatch both ways are possible.
411 *
412 * MBSC[47:40] and MBFS[23] are reserved.
413 */
414
415 unsigned int i, reg, drb;
416 uint8_t mbsc0, mbfs0, mbfs1, mbfs2;
417 uint16_t mbsc1, mbsc3;
418
419 /*
420 * Tally how many rows between rows 0-3 and rows 4-7 are populated.
421 * This determines how to program MBFS and MBSC.
422 */
423 uint8_t dimm03 = 0;
424 uint8_t dimm47 = 0;
425
426 for (drb = 0, i = DRB0; i <= DRB7; i++) {
427 reg = pci_read_config8(NB, i);
428 if (drb != reg) {
429 if (i <= DRB3)
430 dimm03++;
431 else
432 dimm47++;
433
434 drb = reg;
435 }
436 }
437
438 if (CONFIG(SDRAMPWR_4DIMM)) {
439 /*
440 * For a 4 DIMM board, based on ASUS P2B-LS mainboard.
441 *
442 * There are four main conditions to check when programming
443 * DRAM buffer frequency and strength:
444 *
445 * a: >2 rows populated across DIMM0,1
446 * b: >2 rows populated across DIMM2,3
447 * c: >4 rows populated across all DIMM slots
448 * and either one of:
449 * 1: NBXCFG[13] strapped as 100MHz, or
450 * 6: NBXCFG[13] strapped as 66MHz
451 *
452 * CKE0/FENA ----------------------------------------------------------+
453 * CKE1/GCKE ----------------------[ MBFS ]---------------------+|
454 * DQMA/CASA[764320]# -------------[ 0 = 66MHz ]--------------------+||
455 * DQMB1/CASB1# (Fixed for 66MHz) -[ 1 = 100MHz ]-------------------+|||
456 * DQMB5/CASB5# (Fixed for 66MHz) ---------------------------------+||||
457 * DQMA1/CASA1# (Fixed for 66MHz) --------------------------------+|||||
458 * DQMA5/CASA5# (Fixed for 66MHz) -------------------------------+||||||
459 * CSA[5:0]#,CSB[5:0]# ------------------------------------++++++|||||||
460 * CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++|||||||||||||
461 * MECC[7:0] #2/#1 ----------------------------------++|||||||||||||||||
462 * MD[63:0] #2/#1 ---------------------------------++|||||||||||||||||||
463 * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||
464 * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+||||||||||||||||||||||
465 * Reserved ------------------------------------+|||||||||||||||||||||||
466 * ||||||||||||||||||||||||
467 * 3 32 21 10 0 * 2 21 10 0
468 * 9876543210987654321098765432109876543210 * 321098765432109876543210
469 * 10------------------------1010---------- a -1---------------11-----
470 * 11------------------------1111---------- !a -0---------------00-----
471 * --10--------------------------1010------ b --1----------------11---
472 * --11--------------------------1111------ !b --0----------------00---
473 * ----------------------------------1100-- c ----------------------1-
474 * ----------------------------------1011-- !c ----------------------0-
475 * ----1010101000000000000000------------00 1 ---11111111111111----1-0
476 * ----000000000000000000000010101010----00 6 ---1111111111111100000-0
477 * | | | | | | | | | | ||||||| | | | | | |
478 * | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA
479 * | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE
480 * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#
481 * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1# (66MHz: 2x)
482 * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# (66MHz: 2x)
483 * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# (66MHz: 2x)
484 * | | | | | | | | | | ||||||+------------- DQMA5/CASA5# (66MHz: 2x)
485 * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (1x)
486 * | | | | | | | | | +--------------------- CSA6#/CKE2
487 * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4
488 * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3
489 * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5
490 * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1
491 * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2
492 * | | | +--------------------------------- MD[63:0] #1
493 * | | +----------------------------------- MD[63:0] #2
494 * | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#
495 * +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
496 */
497 unsigned int fsb;
498
499 mbsc0 = 0xa0;
500 mbsc1 = 0x002a;
501 mbfs1 = 0xff;
502 mbfs2 = 0x1f;
503 if (pci_read_config8(NB, NBXCFG + 1) & 0x30) {
504 fsb = 66;
505 mbsc3 = 0xa000;
506 mbfs0 = 0x80;
507 } else {
508 fsb = 100;
509 mbsc3 = 0xaaa0;
510 mbfs0 = 0x84;
511 }
512 if (dimm03 > 2) {
513 mbfs2 |= 0x40;
514 if (fsb == 100)
515 mbfs0 |= 0x60;
516 } else {
517 mbsc3 |= 0xc000;
518 if (fsb == 100)
519 mbsc1 |= 0x003c;
520 }
521 if (dimm47 > 2) {
522 mbfs2 |= 0x20;
523 if (fsb == 100)
524 mbfs0 |= 0x18;
525 } else {
526 mbsc3 |= 0x3000;
527 if (fsb == 100) {
528 mbsc1 |= 0x0003;
529 mbsc0 |= 0xc0;
530 }
531 }
532 if ((dimm03 + dimm47) > 4) {
533 mbsc0 |= 0x30;
534 mbfs0 |= 0x02;
535 } else {
536 mbsc0 |= 0x2c;
537 }
538 } else {
539 /*
540 * For a 3 DIMM board, based on ASUS P2B mainboard.
541 *
542 * There are two main conditions to check when programming DRAM buffer
543 * frequency and strength:
544 *
545 * a: >2 rows populated across DIMM0,1
546 * c: >4 rows populated across all DIMM slots
547 *
548 * CKE0 ---------------------------------------------------------------+
549 * CKE1 ------------------------[ MBFS ]------------------------+|
550 * DQMA/CASA[764320]# ----------[ 0 = 66MHz ]-----------------------+||
551 * DQMB1/CASB1# ----------------[ 1 = 100MHz ]----------------------+|||
552 * DQMB5/CASB5# ---------------------------------------------------+||||
553 * DQMA1/CASA1# --------------------------------------------------+|||||
554 * DQMA5/CASA5# -------------------------------------------------+||||||
555 * CSA0-5#,CSB0-5# ----------------------------------------++++++|||||||
556 * CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++|||||||||||||
557 * MECC[7:0] #2/#1 (100MHz) -------------------------++|||||||||||||||||
558 * MD[63:0] #2/#1 (100MHz) ------------------------++|||||||||||||||||||
559 * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||
560 * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+||||||||||||||||||||||
561 * Reserved ------------------------------------+|||||||||||||||||||||||
562 * ||||||||||||||||||||||||
563 * 3 32 21 10 0 * 2 21 10 0
564 * 9876543210987654321098765432109876543210 * 321098765432109876543210
565 * 10------------------------1111---------- a -1----------------------
566 * 11------------------------1010---------- !a -0----------------------
567 * --110000000010101010111111----1010--1010 * --01111000000000000000-0
568 * ----------------------------------11---- c ----------------------1-
569 * ----------------------------------10---- !c ----------------------0-
570 * | | | | | | | | | | ||||||| | | | | | |
571 * | | | | | | | | | | ||||||| | | | | | +- CKE0
572 * | | | | | | | | | | ||||||| | | | | +--- CKE1
573 * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#
574 * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1#
575 * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5#
576 * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1#
577 * | | | | | | | | | | ||||||+------------- DQMA5/CASA5#
578 * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (2x)
579 * | | | | | | | | | +--------------------- CSA6#/CKE2
580 * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4
581 * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3
582 * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5
583 * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (1x)
584 * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (1x)
585 * | | | +--------------------------------- MD[63:0] #1 (1x)
586 * | | +----------------------------------- MD[63:0] #2 (1x)
587 * | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#
588 * +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
589 */
590
591 mbsc0 = 0xaa;
592 mbsc1 = 0xafea;
593 mbsc3 = 0xb00a;
594 mbfs0 = 0x00;
595 mbfs1 = 0x00;
596 mbfs2 = 0x1e;
597
598 if (dimm03 > 2) {
599 mbsc1 |= 0x003c;
600 mbfs2 |= 0x40;
601 } else {
602 mbsc3 |= 0xc000;
603 }
604 if ((dimm03 + dimm47) > 4) {
605 mbsc0 |= 0x30;
606 mbfs0 |= 0x02;
607 }
608 }
609
610 pci_write_config8(NB, MBSC + 0, mbsc0);
611 pci_write_config16(NB, MBSC + 1, mbsc1);
612 pci_write_config16(NB, MBSC + 3, mbsc3);
613 pci_write_config16(NB, MBFS + 0, mbfs1 << 8 | mbfs0);
614 pci_write_config8(NB, MBFS + 2, mbfs2);
615 }
616
617 /*-----------------------------------------------------------------------------
618 DIMM-independent configuration functions.
619 -----------------------------------------------------------------------------*/
620
spd_enable_refresh(void)621 static void spd_enable_refresh(void)
622 {
623 int i, value;
624 uint8_t reg;
625
626 reg = pci_read_config8(NB, DRAMC);
627
628 for (i = 0; i < DIMM_SOCKETS; i++) {
629 value = smbus_read_byte(DIMM0 + i, SPD_REFRESH);
630 if (value < 0)
631 continue;
632 reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
633
634 PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i);
635 }
636
637 pci_write_config8(NB, DRAMC, reg);
638 }
639
640 /*-----------------------------------------------------------------------------
641 Public interface.
642 -----------------------------------------------------------------------------*/
643
sdram_set_registers(void)644 static void sdram_set_registers(void)
645 {
646 int i, max;
647
648 PRINT_DEBUG("Northbridge %s SDRAM init:\n", "prior to");
649 DUMPNORTH();
650
651 max = ARRAY_SIZE(register_values);
652
653 /* Set registers as specified in the register_values[] array. */
654 for (i = 0; i < max; i += 2)
655 pci_write_config8(NB, register_values[i], register_values[i + 1]);
656 }
657
658 struct dimm_size {
659 u32 side1;
660 u32 side2;
661 };
662
spd_get_dimm_size(unsigned int device)663 static struct dimm_size spd_get_dimm_size(unsigned int device)
664 {
665 struct dimm_size sz;
666 int i, module_density, dimm_banks;
667 sz.side1 = 0;
668 module_density = smbus_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
669 dimm_banks = smbus_read_byte(device, SPD_NUM_DIMM_BANKS);
670
671 /* Find the size of side1. */
672 /* Find the larger value. The larger value is always side1. */
673 for (i = 512; i >= 0; i >>= 1) {
674 if ((module_density & i) == i) {
675 sz.side1 = i;
676 break;
677 }
678 }
679
680 /* Set to 0 in case it's single sided. */
681 sz.side2 = 0;
682
683 /* Test if it's a dual-sided DIMM. */
684 if (dimm_banks > 1) {
685 /* Test if there's a second value. If so it's asymmetrical. */
686 if (module_density != i) {
687 /*
688 * Find second value, picking up where we left off.
689 * i >>= 1 done initially to make sure we don't get
690 * the same value again.
691 */
692 for (i >>= 1; i >= 0; i >>= 1) {
693 if (module_density == (sz.side1 | i)) {
694 sz.side2 = i;
695 break;
696 }
697 }
698 /* If not, it's symmetrical. */
699 } else {
700 sz.side2 = sz.side1;
701 }
702 }
703
704 /*
705 * SPD byte 31 is the memory size divided by 4 so we
706 * need to multiply by 4 to get the total size.
707 */
708 sz.side1 *= 4;
709 sz.side2 *= 4;
710
711 /*
712 * It is possible to partially use larger than supported
713 * modules by setting them to a supported size.
714 */
715 if (sz.side1 > 128) {
716 PRINT_DEBUG("Side%d was %dMB but only 128MB will be used.\n",
717 1, sz.side1);
718 sz.side1 = 128;
719
720 if (sz.side2 > 128) {
721 PRINT_DEBUG("Side%d was %dMB but only 128MB will be used.\n",
722 2, sz.side2);
723 sz.side2 = 128;
724 }
725 }
726
727 return sz;
728 }
729 /*
730 * Sets DRAM attributes one DIMM at a time, based on SPD data.
731 * Northbridge settings that are set: NBXCFG[31:24], DRB0-DRB7, RPS, DRAMC.
732 */
set_dram_row_attributes(void)733 static void set_dram_row_attributes(void)
734 {
735 int i, dra, drb, col, width, value, rps;
736 u8 bpr; /* Top 8 bits of PGPOL */
737 u8 nbxecc = 0; /* NBXCFG[31:24] */
738 u8 edo, sd, regsd; /* EDO, SDRAM, registered SDRAM */
739
740 edo = 0;
741 sd = 0;
742 regsd = 1;
743 rps = 0;
744 drb = 0;
745 bpr = 0;
746
747 for (i = 0; i < DIMM_SOCKETS; i++) {
748 unsigned int device;
749 device = DIMM0 + i;
750 bpr >>= 2;
751 nbxecc >>= 2;
752
753 /* First check if a DIMM is actually present. */
754 value = smbus_read_byte(device, SPD_MEMORY_TYPE);
755 /* This is 440BX! We do EDO too! */
756 if (value == SPD_MEMORY_TYPE_EDO
757 || value == SPD_MEMORY_TYPE_SDRAM) {
758 if (value == SPD_MEMORY_TYPE_EDO) {
759 edo = 1;
760 } else if (value == SPD_MEMORY_TYPE_SDRAM) {
761 sd = 1;
762 }
763 PRINT_DEBUG("Found DIMM in slot %d\n", i);
764
765 if (edo && sd) {
766 die_with_post_code(POSTCODE_RAM_FAILURE,
767 "Mixing EDO/SDRAM unsupported!\n");
768 }
769
770 /* "DRA" is our RPS for the two rows on this DIMM. */
771 dra = 0;
772
773 /* Columns */
774 col = smbus_read_byte(device, SPD_NUM_COLUMNS);
775
776 /*
777 * Is this an ECC DIMM? Actually will be a 2 if so.
778 * TODO: Other register than NBXCFG also needs this
779 * ECC information.
780 */
781 value = smbus_read_byte(device, SPD_DIMM_CONFIG_TYPE);
782
783 /* Data width */
784 width = smbus_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
785
786 /* Exclude error checking data width from page size calculations */
787 if (value) {
788 value = smbus_read_byte(device,
789 SPD_ERROR_CHECKING_SDRAM_WIDTH);
790 width -= value;
791 /* ### ECC */
792 /* Clear top 2 bits to help set up NBXCFG. */
793 nbxecc &= 0x3f;
794 } else {
795 /* Without ECC, top 2 bits should be 11. */
796 nbxecc |= 0xc0;
797 }
798
799 /* If any installed DIMM is *not* registered, this system cannot be
800 * configured for registered SDRAM.
801 * By registered, only the address and control lines need to be, which
802 * we can tell by reading SPD byte 21, bit 1.
803 */
804 value = smbus_read_byte(device, SPD_MODULE_ATTRIBUTES);
805
806 PRINT_DEBUG("DIMM is ");
807 if ((value & MODULE_REGISTERED) == 0) {
808 regsd = 0;
809 PRINT_DEBUG("not ");
810 }
811 PRINT_DEBUG("registered\n");
812
813 /* Calculate page size in bits. */
814 value = ((1 << col) * width);
815
816 /* Convert to KB. */
817 dra = (value >> 13);
818
819 /* Number of banks of DIMM (single or double sided). */
820 value = smbus_read_byte(device, SPD_NUM_DIMM_BANKS);
821
822 /* Once we have dra, col is done and can be reused.
823 * So it's reused for number of banks.
824 */
825 col = smbus_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
826
827 if (value == 1) {
828 /*
829 * Second bank of 1-bank DIMMs "doesn't have
830 * ECC" - or anything.
831 */
832 if (dra == 2) {
833 dra = 0x0; /* 2KB */
834 } else if (dra == 4) {
835 dra = 0x1; /* 4KB */
836 } else if (dra == 8) {
837 dra = 0x2; /* 8KB */
838 } else if (dra >= 16) {
839 /* Page sizes larger than supported are
840 * set to 8KB to use module partially.
841 */
842 PRINT_DEBUG("Page size forced to 8KB.\n");
843 dra = 0x2; /* 8KB */
844 } else {
845 dra = -1;
846 }
847 /*
848 * Sets a flag in PGPOL[BPR] if this DIMM has
849 * 4 banks per row.
850 */
851 if (col == 4)
852 bpr |= 0x40;
853 } else if (value == 2) {
854 if (dra == 2) {
855 dra = 0x0; /* 2KB */
856 } else if (dra == 4) {
857 dra = 0x05; /* 4KB */
858 } else if (dra == 8) {
859 dra = 0x0a; /* 8KB */
860 } else if (dra >= 16) {
861 /* Ditto */
862 PRINT_DEBUG("Page size forced to 8KB.\n");
863 dra = 0x0a; /* 8KB */
864 } else {
865 dra = -1;
866 }
867 /* Ditto */
868 if (col == 4)
869 bpr |= 0xc0;
870 } else {
871 die_with_post_code(POSTCODE_RAM_FAILURE,
872 "# of banks of DIMM unsupported!\n");
873 }
874 if (dra == -1) {
875 die_with_post_code(POSTCODE_RAM_FAILURE,
876 "Page size not supported!\n");
877 }
878
879 /*
880 * 440BX supports asymmetrical dual-sided DIMMs,
881 * but can't handle DIMMs smaller than 8MB per
882 * side.
883 */
884 struct dimm_size sz = spd_get_dimm_size(device);
885 if ((sz.side1 < 8)) {
886 die_with_post_code(POSTCODE_RAM_FAILURE,
887 "DIMMs smaller than 8MB per side "
888 "are not supported!\n");
889 }
890
891 /* Divide size by 8 to set up the DRB registers. */
892 drb += (sz.side1 / 8);
893
894 /*
895 * Build the DRB for the next row in MSB so it gets
896 * placed in DRB[n+1] where it belongs when written
897 * as a 16-bit word.
898 */
899 drb &= 0xff;
900 drb |= (drb + (sz.side2 / 8)) << 8;
901 } else {
902 /* If there's no DIMM in the slot, set dra to 0x00. */
903 dra = 0x00;
904 /* Still have to propagate DRB over. */
905 drb &= 0xff;
906 drb |= (drb << 8);
907 }
908
909 pci_write_config16(NB, DRB + (2 * i), drb);
910
911 /* Brings the upper DRB back down to be base for
912 * DRB calculations for the next two rows.
913 */
914 drb >>= 8;
915
916 rps |= (dra & 0x0f) << (i * 4);
917 }
918
919 /* Set paging policy register. */
920 pci_write_config8(NB, PGPOL + 1, bpr);
921 PRINT_DEBUG("%s has been set to 0x%02x\n", "PGPOL[BPR]", bpr);
922
923 /* Set DRAM row page size register. */
924 pci_write_config16(NB, RPS, rps);
925 PRINT_DEBUG("RPS has been set to 0x%04x\n", rps);
926
927 /* ### ECC */
928 pci_write_config8(NB, NBXCFG + 3, nbxecc);
929 PRINT_DEBUG("%s has been set to 0x%02x\n", "NBXCFG[31:24]", nbxecc);
930
931 /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */
932
933 /* i will be used to set DRAMC[4:3]. */
934 if (regsd && sd) {
935 i = 0x10; // Registered SDRAM
936 } else if (sd) {
937 i = 0x08; // SDRAM
938 } else {
939 i = 0; // EDO
940 }
941
942 value = pci_read_config8(NB, DRAMC) & 0xe7;
943 value |= i;
944 pci_write_config8(NB, DRAMC, value);
945 PRINT_DEBUG("%s has been set to 0x%02x\n", "DRAMC", value);
946 }
947
sdram_enable(void)948 static void sdram_enable(void)
949 {
950 int i;
951
952 /* 0. Wait until power/voltages and clocks are stable (200us). */
953 udelay(200);
954
955 /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
956 PRINT_DEBUG("RAM Enable %d: %s\n", 1, "Apply NOP");
957 do_ram_command(RAM_COMMAND_NOP);
958 udelay(200);
959
960 /* 2. Precharge all. Wait tRP. */
961 PRINT_DEBUG("RAM Enable %d: %s\n", 2, "Precharge all");
962 do_ram_command(RAM_COMMAND_PRECHARGE);
963 udelay(1);
964
965 /* 3. Perform 8 refresh cycles. Wait tRC each time. */
966 PRINT_DEBUG("RAM Enable %d: %s\n", 3, "CBR");
967 for (i = 0; i < 8; i++) {
968 do_ram_command(RAM_COMMAND_CBR);
969 udelay(1);
970 }
971
972 /* 4. Mode register set. Wait two memory cycles. */
973 PRINT_DEBUG("RAM Enable %d: %s\n", 4, "Mode register set");
974 do_ram_command(RAM_COMMAND_MRS);
975 udelay(2);
976
977 /* 5. Normal operation. */
978 PRINT_DEBUG("RAM Enable %d: %s\n", 5, "Normal operation");
979 do_ram_command(RAM_COMMAND_NORMAL);
980 udelay(1);
981
982 /* 6. Finally enable refresh. */
983 PRINT_DEBUG("RAM Enable %d: %s\n", 6, "Enable refresh");
984 pci_write_config8(NB, PMCR, 0x10);
985 spd_enable_refresh();
986 udelay(1);
987
988 PRINT_DEBUG("Northbridge %s SDRAM init:\n", "following");
989 DUMPNORTH();
990 }
991
992 /* Implemented under mainboard. */
enable_spd(void)993 void __weak enable_spd(void) { }
994
sdram_initialize(int s3resume)995 void sdram_initialize(int s3resume)
996 {
997 timestamp_add_now(TS_INITRAM_START);
998 enable_spd();
999
1000 dump_spd_registers();
1001 sdram_set_registers();
1002 /* Set up DRAM row boundary registers and other attributes. */
1003 set_dram_row_attributes();
1004 /* Set up DRAM buffer strength. */
1005 set_dram_buffer_strength();
1006 sdram_enable();
1007
1008 /* Clear any errors reported during raminit. */
1009 pci_write_config32(NB, EAP, 0x3);
1010 pci_write_config8(NB, ERRSTS, 0x11);
1011 pci_write_config8(NB, ERRSTS + 1, 0x1f);
1012
1013 timestamp_add_now(TS_INITRAM_END);
1014 }
1015