1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <acpi/acpi.h>
4 #include <bootsplash.h>
5 #include <bootstate.h>
6 #include <console/console.h>
7 #include <cpu/x86/mp.h>
8 #include <device/mmio.h>
9 #include <device/device.h>
10 #include <device/pci.h>
11 #include <device/pci_ops.h>
12 #include <intelblocks/acpi.h>
13 #include <intelblocks/cfg.h>
14 #include <intelblocks/fast_spi.h>
15 #include <intelblocks/msr.h>
16 #include <intelblocks/p2sb.h>
17 #include <intelblocks/power_limit.h>
18 #include <intelblocks/xdci.h>
19 #include <fsp/api.h>
20 #include <fsp/util.h>
21 #include <gpio.h>
22 #include <intelblocks/cpulib.h>
23 #include <intelblocks/itss.h>
24 #include <intelblocks/pmclib.h>
25 #include <intelblocks/systemagent.h>
26 #include <option.h>
27 #include <soc/ahci.h>
28 #include <soc/cpu.h>
29 #include <soc/heci.h>
30 #include <soc/intel/common/vbt.h>
31 #include <soc/iomap.h>
32 #include <soc/itss.h>
33 #include <soc/msr.h>
34 #include <soc/pci_devs.h>
35 #include <soc/pm.h>
36 #include <soc/systemagent.h>
37 #include <spi-generic.h>
38 #include <timer.h>
39 #include <soc/ramstage.h>
40 #include <soc/soc_chip.h>
41 #include <types.h>
42
43 #include "chip.h"
44
45 #define DUAL_ROLE_CFG0 0x80d8
46 #define SW_VBUS_VALID_MASK (1 << 24)
47 #define SW_IDPIN_EN_MASK (1 << 21)
48 #define SW_IDPIN_MASK (1 << 20)
49 #define SW_IDPIN_HOST (0 << 20)
50 #define DUAL_ROLE_CFG1 0x80dc
51 #define DRD_MODE_MASK (1 << 29)
52 #define DRD_MODE_HOST (1 << 29)
53
54 #define CFG_XHCLKGTEN 0x8650
55 /* Naking USB2.0 EPs for Backbone Clock Gating and PLL Shutdown */
56 #define NUEFBCGPS (1 << 28)
57 /* SRAM Power Gate Enable */
58 #define SRAMPGTEN (1 << 27)
59 /* SS Link PLL Shutdown Enable */
60 #define SSLSE (1 << 26)
61 /* USB2 PLL Shutdown Enable */
62 #define USB2PLLSE (1 << 25)
63 /* IOSF Sideband Trunk Clock Gating Enable */
64 #define IOSFSTCGE (1 << 24)
65 /* BIT[23:20] HS Backbone PXP Trunk Clock Gate Enable */
66 #define HSTCGE (1 << 23 | 1 << 22)
67 /* BIT[19:16] SS Backbone PXP Trunk Clock Gate Enable */
68 #define SSTCGE (1 << 19 | 1 << 18 | 1 << 17)
69 /* XHC Ignore_EU3S */
70 #define XHCIGEU3S (1 << 15)
71 /* XHC Frame Timer Clock Shutdown Enable */
72 #define XHCFTCLKSE (1 << 14)
73 /* XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP */
74 #define XHCBBTCGIPISO (1 << 13)
75 /* XHC HS Backbone PXP Trunk Clock Gate U2 non RWE */
76 #define XHCHSTCGU2NRWE (1 << 12)
77 /* BIT[11:10] XHC USB2 PLL Shutdown Lx Enable */
78 #define XHCUSB2PLLSDLE (1 << 11 | 1 << 10)
79 /* BIT[9:8] HS Backbone PXP PLL Shutdown Ux Enable */
80 #define HSUXDMIPLLSE (1 << 9)
81 /* BIT[7:5] SS Backbone PXP PLL shutdown Ux Enable */
82 #define SSPLLSUE (1 << 6)
83 /* XHC Backbone Local Clock Gating Enable */
84 #define XHCBLCGE (1 << 4)
85 /* HS Link Trunk Clock Gating Enable */
86 #define HSLTCGE (1 << 3)
87 /* SS Link Trunk Clock Gating Enable */
88 #define SSLTCGE (1 << 2)
89 /* IOSF Backbone Trunk Clock Gating Enable */
90 #define IOSFBTCGE (1 << 1)
91 /* IOSF Gasket Backbone Local Clock Gating Enable */
92 #define IOSFGBLCGE (1 << 0)
93
94 #define CFG_XHCPMCTRL 0x80a4
95 /* BIT[7:4] LFPS periodic sampling for USB3 Ports */
96 #define LFPS_PM_DISABLE_MASK 0xFFFFFF0F
97
soc_acpi_name(const struct device * dev)98 const char *soc_acpi_name(const struct device *dev)
99 {
100 if (dev->path.type == DEVICE_PATH_DOMAIN)
101 return "PCI0";
102
103 if (dev->path.type == DEVICE_PATH_USB) {
104 switch (dev->path.usb.port_type) {
105 case 0:
106 /* Root Hub */
107 return "RHUB";
108 case 2:
109 /* USB2 ports */
110 switch (dev->path.usb.port_id) {
111 case 0: return "HS01";
112 case 1: return "HS02";
113 case 2: return "HS03";
114 case 3: return "HS04";
115 case 4: return "HS05";
116 case 5: return "HS06";
117 case 6: return "HS07";
118 case 7: return "HS08";
119 case 8:
120 if (CONFIG(SOC_INTEL_GEMINILAKE))
121 return "HS09";
122 }
123 break;
124 case 3:
125 /* USB3 ports */
126 switch (dev->path.usb.port_id) {
127 case 0: return "SS01";
128 case 1: return "SS02";
129 case 2: return "SS03";
130 case 3: return "SS04";
131 case 4: return "SS05";
132 case 5: return "SS06";
133 }
134 break;
135 }
136 return NULL;
137 }
138
139 if (dev->path.type != DEVICE_PATH_PCI)
140 return NULL;
141
142 switch (dev->path.pci.devfn) {
143 /* DSDT: acpi/northbridge.asl */
144 case SA_DEVFN_ROOT:
145 return "MCHC";
146 /* DSDT: acpi/xhci.asl */
147 case PCH_DEVFN_XHCI:
148 return "XHCI";
149 /* DSDT: acpi/pch_hda.asl */
150 case PCH_DEVFN_HDA:
151 return "HDAS";
152 /* DSDT: acpi/lpss.asl */
153 case PCH_DEVFN_UART0:
154 return "URT1";
155 case PCH_DEVFN_UART1:
156 return "URT2";
157 case PCH_DEVFN_UART2:
158 return "URT3";
159 case PCH_DEVFN_UART3:
160 return "URT4";
161 case PCH_DEVFN_SPI0:
162 return "SPI1";
163 case PCH_DEVFN_SPI1:
164 return "SPI2";
165 case PCH_DEVFN_SPI2:
166 return "SPI3";
167 case PCH_DEVFN_PWM:
168 return "PWM";
169 case PCH_DEVFN_I2C0:
170 return "I2C0";
171 case PCH_DEVFN_I2C1:
172 return "I2C1";
173 case PCH_DEVFN_I2C2:
174 return "I2C2";
175 case PCH_DEVFN_I2C3:
176 return "I2C3";
177 case PCH_DEVFN_I2C4:
178 return "I2C4";
179 case PCH_DEVFN_I2C5:
180 return "I2C5";
181 case PCH_DEVFN_I2C6:
182 return "I2C6";
183 case PCH_DEVFN_I2C7:
184 return "I2C7";
185 /* Storage */
186 case PCH_DEVFN_SDCARD:
187 return "SDCD";
188 case PCH_DEVFN_EMMC:
189 return "EMMC";
190 case PCH_DEVFN_SDIO:
191 return "SDIO";
192 /* PCIe */
193 case PCH_DEVFN_PCIE1:
194 return "RP03";
195 case PCH_DEVFN_PCIE5:
196 return "RP01";
197 }
198
199 return NULL;
200 }
201
202 static struct device_operations pci_domain_ops = {
203 .read_resources = pci_domain_read_resources,
204 .set_resources = pci_domain_set_resources,
205 .scan_bus = pci_host_bridge_scan_bus,
206 .acpi_name = &soc_acpi_name,
207 .acpi_fill_ssdt = ssdt_set_above_4g_pci,
208 };
209
210 struct device_operations apl_cpu_bus_ops = {
211 .read_resources = noop_read_resources,
212 .set_resources = noop_set_resources,
213 .init = mp_cpu_bus_init,
214 .acpi_fill_ssdt = generate_cpu_entries,
215 };
216
217 struct device_operations glk_cpu_bus_ops = {
218 .read_resources = noop_read_resources,
219 .set_resources = noop_set_resources,
220 .acpi_fill_ssdt = generate_cpu_entries,
221 };
222
enable_dev(struct device * dev)223 static void enable_dev(struct device *dev)
224 {
225 /* Set the operations if it is a special bus type */
226 if (dev->path.type == DEVICE_PATH_DOMAIN)
227 dev->ops = &pci_domain_ops;
228 else if (dev->path.type == DEVICE_PATH_GPIO)
229 block_gpio_enable(dev);
230 }
231
232 /*
233 * If the PCIe root port at function 0 is disabled,
234 * the PCIe root ports might be coalesced after FSP silicon init.
235 * The below function will swap the devfn of the first enabled device
236 * in devicetree and function 0 resides a pci device
237 * so that it won't confuse coreboot.
238 */
pcie_update_device_tree(unsigned int devfn0,int num_funcs)239 static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
240 {
241 struct device *func0;
242 unsigned int devfn;
243 int i;
244 unsigned int inc = PCI_DEVFN(0, 1);
245
246 func0 = pcidev_path_on_root(devfn0);
247 if (func0 == NULL)
248 return;
249
250 /* No more functions if function 0 is disabled. */
251 if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff)
252 return;
253
254 devfn = devfn0 + inc;
255
256 /*
257 * Increase function by 1.
258 * Then find first enabled device to replace func0
259 * as that port was move to func0.
260 */
261 for (i = 1; i < num_funcs; i++, devfn += inc) {
262 struct device *dev = pcidev_path_on_root(devfn);
263 if (dev == NULL)
264 continue;
265
266 if (!dev->enabled)
267 continue;
268 /* Found the first enabled device in given dev number */
269 func0->path.pci.devfn = dev->path.pci.devfn;
270 dev->path.pci.devfn = devfn0;
271 break;
272 }
273 }
274
pcie_override_devicetree_after_silicon_init(void)275 static void pcie_override_devicetree_after_silicon_init(void)
276 {
277 pcie_update_device_tree(PCH_DEVFN_PCIE1, 4);
278 pcie_update_device_tree(PCH_DEVFN_PCIE5, 2);
279 }
280
281 /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */
set_sci_irq(void)282 static void set_sci_irq(void)
283 {
284 struct soc_intel_apollolake_config *cfg;
285 uint32_t scis;
286
287 cfg = config_of_soc();
288
289 /* Change only if a device tree entry exists. */
290 if (cfg->sci_irq) {
291 scis = soc_read_sci_irq_select();
292 scis &= ~SCI_IRQ_SEL;
293 scis |= (cfg->sci_irq << SCI_IRQ_ADJUST) & SCI_IRQ_SEL;
294 soc_write_sci_irq_select(scis);
295 }
296 }
297
soc_init(void * data)298 static void soc_init(void *data)
299 {
300 struct soc_power_limits_config *soc_config;
301 config_t *config;
302
303 /* Snapshot the current GPIO IRQ polarities. FSP is setting a
304 * default policy that doesn't honor boards' requirements. */
305 itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
306
307 /*
308 * Clear the GPI interrupt status and enable registers. These
309 * registers do not get reset to default state when booting from S5.
310 */
311 gpi_clear_int_cfg();
312
313 fsp_silicon_init();
314
315 /* Restore GPIO IRQ polarities back to previous settings. */
316 itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
317
318 /* override 'enabled' setting in device tree if needed */
319 pcie_override_devicetree_after_silicon_init();
320
321 /*
322 * Keep the P2SB device visible so it and the other devices are
323 * visible in coreboot for driver support and PCI resource allocation.
324 * There is a UPD setting for this, but it's more consistent to use
325 * hide and unhide symmetrically.
326 */
327 p2sb_unhide();
328
329 config = config_of_soc();
330 /* Set RAPL MSR for Package power limits */
331 soc_config = &config->power_limits_config;
332 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
333
334 /*
335 * FSP-S routes SCI to IRQ 9. With the help of this function you can
336 * select another IRQ for SCI.
337 */
338 set_sci_irq();
339 }
340
soc_final(void * data)341 static void soc_final(void *data)
342 {
343 /* Make sure payload/OS can't trigger global reset */
344 pmc_global_reset_disable_and_lock();
345 }
346
disable_dev(struct device * dev,FSP_S_CONFIG * silconfig)347 static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
348 {
349 switch (dev->path.pci.devfn) {
350 case PCH_DEVFN_NPK:
351 /*
352 * Disable this device in the parse_devicetree_setting() function
353 * in romstage.c
354 */
355 break;
356 case PCH_DEVFN_ISH:
357 silconfig->IshEnable = 0;
358 break;
359 case PCH_DEVFN_SATA:
360 silconfig->EnableSata = 0;
361 break;
362 case PCH_DEVFN_PCIE5:
363 silconfig->PcieRootPortEn[0] = 0;
364 silconfig->PcieRpHotPlug[0] = 0;
365 break;
366 case PCH_DEVFN_PCIE6:
367 silconfig->PcieRootPortEn[1] = 0;
368 silconfig->PcieRpHotPlug[1] = 0;
369 break;
370 case PCH_DEVFN_PCIE1:
371 silconfig->PcieRootPortEn[2] = 0;
372 silconfig->PcieRpHotPlug[2] = 0;
373 break;
374 case PCH_DEVFN_PCIE2:
375 silconfig->PcieRootPortEn[3] = 0;
376 silconfig->PcieRpHotPlug[3] = 0;
377 break;
378 case PCH_DEVFN_PCIE3:
379 silconfig->PcieRootPortEn[4] = 0;
380 silconfig->PcieRpHotPlug[4] = 0;
381 break;
382 case PCH_DEVFN_PCIE4:
383 silconfig->PcieRootPortEn[5] = 0;
384 silconfig->PcieRpHotPlug[5] = 0;
385 break;
386 case PCH_DEVFN_XHCI:
387 silconfig->Usb30Mode = 0;
388 break;
389 case PCH_DEVFN_XDCI:
390 silconfig->UsbOtg = 0;
391 break;
392 case PCH_DEVFN_I2C0:
393 silconfig->I2c0Enable = 0;
394 break;
395 case PCH_DEVFN_I2C1:
396 silconfig->I2c1Enable = 0;
397 break;
398 case PCH_DEVFN_I2C2:
399 silconfig->I2c2Enable = 0;
400 break;
401 case PCH_DEVFN_I2C3:
402 silconfig->I2c3Enable = 0;
403 break;
404 case PCH_DEVFN_I2C4:
405 silconfig->I2c4Enable = 0;
406 break;
407 case PCH_DEVFN_I2C5:
408 silconfig->I2c5Enable = 0;
409 break;
410 case PCH_DEVFN_I2C6:
411 silconfig->I2c6Enable = 0;
412 break;
413 case PCH_DEVFN_I2C7:
414 silconfig->I2c7Enable = 0;
415 break;
416 case PCH_DEVFN_UART0:
417 silconfig->Hsuart0Enable = 0;
418 break;
419 case PCH_DEVFN_UART1:
420 silconfig->Hsuart1Enable = 0;
421 break;
422 case PCH_DEVFN_UART2:
423 silconfig->Hsuart2Enable = 0;
424 break;
425 case PCH_DEVFN_UART3:
426 silconfig->Hsuart3Enable = 0;
427 break;
428 case PCH_DEVFN_SPI0:
429 silconfig->Spi0Enable = 0;
430 break;
431 case PCH_DEVFN_SPI1:
432 silconfig->Spi1Enable = 0;
433 break;
434 case PCH_DEVFN_SPI2:
435 silconfig->Spi2Enable = 0;
436 break;
437 case PCH_DEVFN_SDCARD:
438 silconfig->SdcardEnabled = 0;
439 break;
440 case PCH_DEVFN_EMMC:
441 silconfig->eMMCEnabled = 0;
442 break;
443 case PCH_DEVFN_SDIO:
444 silconfig->SdioEnabled = 0;
445 break;
446 case PCH_DEVFN_SMBUS:
447 silconfig->SmbusEnable = 0;
448 break;
449 #if !CONFIG(SOC_INTEL_GEMINILAKE)
450 case SA_DEVFN_IPU:
451 silconfig->IpuEn = 0;
452 break;
453 #else
454 case PCH_DEVFN_CNVI:
455 silconfig->CnviMode = 0;
456 break;
457 case PCH_DEVFN_UFS:
458 silconfig->UfsEnabled = 0;
459 break;
460 #endif
461 case PCH_DEVFN_HDA:
462 silconfig->HdaEnable = 0;
463 break;
464 default:
465 printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n",
466 PCI_SLOT(dev->path.pci.devfn),
467 PCI_FUNC(dev->path.pci.devfn));
468 break;
469 }
470 }
471
parse_devicetree(FSP_S_CONFIG * silconfig)472 static void parse_devicetree(FSP_S_CONFIG *silconfig)
473 {
474 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
475
476 if (!dev) {
477 printk(BIOS_ERR, "Could not find root device\n");
478 return;
479 }
480 /* Only disable bus 0 devices. */
481 for (dev = dev->upstream->children; dev; dev = dev->sibling) {
482 if (!dev->enabled)
483 disable_dev(dev, silconfig);
484 }
485 }
486
apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config * cfg,FSP_S_CONFIG * silconfig)487 static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
488 *cfg, FSP_S_CONFIG *silconfig)
489 {
490 #if !CONFIG(SOC_INTEL_GEMINILAKE) /* GLK FSP does not have these fields in FspsUpd.h yet */
491 uint8_t port;
492
493 for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
494 if (cfg->usb_config_override) {
495 if (!cfg->usb2_port[port].enable)
496 continue;
497
498 silconfig->PortUsb20Enable[port] = 1;
499 silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin;
500 }
501
502 if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
503 silconfig->PortUsb20PerPortTxPeHalf[port] =
504 cfg->usb2eye[port].Usb20PerPortTxPeHalf;
505
506 if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0)
507 silconfig->PortUsb20PerPortPeTxiSet[port] =
508 cfg->usb2eye[port].Usb20PerPortPeTxiSet;
509
510 if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0)
511 silconfig->PortUsb20PerPortTxiSet[port] =
512 cfg->usb2eye[port].Usb20PerPortTxiSet;
513
514 if (cfg->usb2eye[port].Usb20HsSkewSel != 0)
515 silconfig->PortUsb20HsSkewSel[port] =
516 cfg->usb2eye[port].Usb20HsSkewSel;
517
518 if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0)
519 silconfig->PortUsb20IUsbTxEmphasisEn[port] =
520 cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
521
522 if (cfg->usb2eye[port].Usb20PerPortRXISet != 0)
523 silconfig->PortUsb20PerPortRXISet[port] =
524 cfg->usb2eye[port].Usb20PerPortRXISet;
525
526 if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0)
527 silconfig->PortUsb20HsNpreDrvSel[port] =
528 cfg->usb2eye[port].Usb20HsNpreDrvSel;
529 }
530
531 if (cfg->usb_config_override) {
532 for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) {
533 if (!cfg->usb3_port[port].enable)
534 continue;
535
536 silconfig->PortUsb30Enable[port] = 1;
537 silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin;
538 }
539 }
540 #endif
541 }
542
glk_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config * cfg,FSP_S_CONFIG * silconfig)543 static void glk_fsp_silicon_init_params_cb(
544 struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
545 {
546 #if CONFIG(SOC_INTEL_GEMINILAKE)
547 uint8_t port;
548
549 /*
550 * UsbPerPortCtl was retired in Fsp 2.0.0+, so PDO programming must be
551 * enabled to configure individual ports in what Fsp thinks is PEI.
552 */
553 silconfig->UsbPdoProgramming = cfg->usb_config_override;
554
555 for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
556 if (cfg->usb_config_override) {
557 silconfig->PortUsb20Enable[port] = cfg->usb2_port[port].enable;
558 silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin;
559 }
560
561 if (!cfg->usb2eye[port].Usb20OverrideEn)
562 continue;
563
564 silconfig->Usb2AfePehalfbit[port] =
565 cfg->usb2eye[port].Usb20PerPortTxPeHalf;
566 silconfig->Usb2AfePetxiset[port] =
567 cfg->usb2eye[port].Usb20PerPortPeTxiSet;
568 silconfig->Usb2AfeTxiset[port] =
569 cfg->usb2eye[port].Usb20PerPortTxiSet;
570 silconfig->Usb2AfePredeemp[port] =
571 cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
572 }
573
574 if (cfg->usb_config_override) {
575 for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) {
576 silconfig->PortUsb30Enable[port] = cfg->usb3_port[port].enable;
577 silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin;
578 }
579 }
580
581 silconfig->Gmm = is_devfn_enabled(SA_GLK_DEVFN_GMM);
582
583 /* On Geminilake, we need to override the default FSP PCIe de-emphasis
584 * settings using the device tree settings. This is because PCIe
585 * de-emphasis is enabled by default and Thunderpeak PCIe WiFi detection
586 * requires de-emphasis disabled. If we make this change common to both
587 * Apollolake and Geminilake, then we need to add mainboard device tree
588 * de-emphasis settings of 1 to Apollolake systems.
589 */
590 memcpy(silconfig->PcieRpSelectableDeemphasis,
591 cfg->pcie_rp_deemphasis_enable,
592 sizeof(silconfig->PcieRpSelectableDeemphasis));
593 /*
594 * FSP does not know what the clock requirements are for the
595 * device on SPI bus, hence it should not modify what coreboot
596 * has set up. Hence skipping in FSP.
597 */
598 silconfig->SkipSpiPCP = 1;
599
600 /*
601 * FSP provides UPD interface to execute IPC command. In order to
602 * improve boot performance, configure PmicPmcIpcCtrl for PMC to program
603 * PMIC PCH_PWROK delay.
604 */
605 silconfig->PmicPmcIpcCtrl = cfg->pmic_pmc_ipc_ctrl;
606
607 /*
608 * Options to disable XHCI Link Compliance Mode.
609 */
610 silconfig->DisableComplianceMode = cfg->disable_compliance_mode;
611
612 /*
613 * Options to change USB3 ModPhy setting for Integrated Filter value.
614 */
615 silconfig->ModPhyIfValue = cfg->mod_phy_if_value;
616
617 /*
618 * Options to bump USB3 LDO voltage with 40mv.
619 */
620 silconfig->ModPhyVoltageBump = cfg->mod_phy_voltage_bump;
621
622 /*
623 * Options to adjust PMIC Vdd2 voltage.
624 */
625 silconfig->PmicVdd2Voltage = cfg->pmic_vdd2_voltage;
626
627 /* FSP should let coreboot set subsystem IDs, which are read/write-once */
628 silconfig->SiSVID = 0;
629 silconfig->SiSSID = 0;
630 silconfig->HgSubSystemId = 0;
631 #endif
632 }
633
mainboard_devtree_update(struct device * dev)634 void __weak mainboard_devtree_update(struct device *dev)
635 {
636 /* Override dev tree settings per board */
637 }
638
platform_fsp_silicon_init_params_cb(FSPS_UPD * silupd)639 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
640 {
641 FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
642 struct soc_intel_apollolake_config *cfg;
643 struct device *dev;
644
645 /* Load VBT before devicetree-specific config. */
646 silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get();
647
648 dev = pcidev_path_on_root(SA_DEVFN_ROOT);
649 cfg = config_of(dev);
650
651 mainboard_devtree_update(dev);
652
653 /* Parse device tree and disable unused device*/
654 parse_devicetree(silconfig);
655
656 memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin,
657 sizeof(silconfig->PcieRpClkReqNumber));
658
659 memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable,
660 sizeof(silconfig->PcieRpHotPlug));
661
662 switch (cfg->serirq_mode) {
663 case SERIRQ_QUIET:
664 silconfig->SirqEnable = 1;
665 silconfig->SirqMode = 0;
666 break;
667 case SERIRQ_CONTINUOUS:
668 silconfig->SirqEnable = 1;
669 silconfig->SirqMode = 1;
670 break;
671 case SERIRQ_OFF:
672 default:
673 silconfig->SirqEnable = 0;
674 break;
675 }
676
677 if (cfg->emmc_tx_cmd_cntl != 0)
678 silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
679 if (cfg->emmc_tx_data_cntl1 != 0)
680 silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
681 if (cfg->emmc_tx_data_cntl2 != 0)
682 silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2;
683 if (cfg->emmc_rx_cmd_data_cntl1 != 0)
684 silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1;
685 if (cfg->emmc_rx_strobe_cntl != 0)
686 silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
687 if (cfg->emmc_rx_cmd_data_cntl2 != 0)
688 silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
689 if (cfg->emmc_host_max_speed != 0)
690 silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed;
691
692 memcpy(silconfig->SataPortsHotPlug, cfg->sata_ports_hot_plug,
693 sizeof(silconfig->SataPortsHotPlug));
694
695 silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
696
697 /* Disable monitor mwait since it is broken due to a hardware bug
698 * without a fix. Specific to Apollolake.
699 */
700 if (!CONFIG(SOC_INTEL_GEMINILAKE))
701 silconfig->MonitorMwaitEnable = 0;
702
703 silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
704
705 /* coreboot handles the lockdown */
706 silconfig->LockDownGlobalSmi = 0;
707 silconfig->BiosLock = 0;
708 silconfig->BiosInterface = 0;
709 silconfig->WriteProtectionEnable[0] = 0;
710 silconfig->SpiEiss = 0;
711 silconfig->RtcLock = 0;
712
713 /* Enable Audio clk gate and power gate */
714 silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
715 silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
716 /* BIOS config lockdown Audio clk and power gate */
717 silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
718 if (CONFIG(SOC_INTEL_GEMINILAKE))
719 glk_fsp_silicon_init_params_cb(cfg, silconfig);
720 else
721 apl_fsp_silicon_init_params_cb(cfg, silconfig);
722
723 silconfig->UsbOtg = xdci_can_enable(PCH_DEVFN_XDCI);
724
725 silconfig->VmxEnable = CONFIG(ENABLE_VMX);
726
727 /* Enable enhanced C-states */
728 silconfig->C1e = cfg->enhanced_cstates;
729
730 /* Set VTD feature according to devicetree */
731 silconfig->VtdEnable = get_uint_option("vtd", cfg->enable_vtd);
732
733 silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
734
735 silconfig->PavpEnable = CONFIG(PAVP);
736
737 /* SATA config */
738 if (is_devfn_enabled(PCH_DEVFN_SATA)) {
739 silconfig->SataSalpSupport = !(cfg->disable_sata_salp_support);
740 ahci_set_speed(cfg->sata_speed);
741 memcpy(silconfig->SataPortsEnable, cfg->sata_ports_enable,
742 sizeof(silconfig->SataPortsEnable));
743 memcpy(silconfig->SataPortsSolidStateDrive, cfg->sata_ports_ssd,
744 sizeof(silconfig->SataPortsSolidStateDrive));
745 }
746
747 /* Sata Power Optimisation */
748 silconfig->SataPwrOptEnable = !(cfg->sata_pwr_optimize_disable);
749
750 /* 8254 Timer */
751 bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
752 silconfig->Timer8254ClkSetting = !use_8254;
753
754 /* FSP should let coreboot set subsystem IDs, which are read/write-once */
755 silconfig->SubSystemVendorId = 0;
756 silconfig->SubSystemId = 0;
757
758 mainboard_silicon_init_params(silconfig);
759 }
760
761 struct chip_operations soc_intel_apollolake_ops = {
762 .name = "Intel Apollolake SOC",
763 .enable_dev = &enable_dev,
764 .init = &soc_init,
765 .final = &soc_final
766 };
767
soc_enable_untrusted_mode(void * unused)768 static void soc_enable_untrusted_mode(void *unused)
769 {
770 /*
771 * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120
772 * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.
773 */
774 msr_set(MSR_POWER_MISC, ENABLE_IA_UNTRUSTED);
775 }
776
drop_privilege_all(void)777 static void drop_privilege_all(void)
778 {
779 /* Drop privilege level on all the CPUs */
780 if (mp_run_on_all_cpus(&soc_enable_untrusted_mode, NULL) != CB_SUCCESS)
781 printk(BIOS_ERR, "failed to enable untrusted mode\n");
782 }
783
configure_xhci_host_mode_port0(void)784 static void configure_xhci_host_mode_port0(void)
785 {
786 uint32_t *cfg0;
787 uint32_t *cfg1;
788 const struct resource *res;
789 uint32_t reg;
790 struct stopwatch sw;
791 struct device *xhci_dev = PCH_DEV_XHCI;
792
793 printk(BIOS_INFO, "Putting xHCI port 0 into host mode.\n");
794 res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
795 cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0);
796 cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1);
797 reg = read32(cfg0);
798 if (!(reg & SW_IDPIN_EN_MASK))
799 return;
800
801 reg &= ~(SW_IDPIN_MASK | SW_VBUS_VALID_MASK);
802 write32(cfg0, reg);
803
804 stopwatch_init_msecs_expire(&sw, 10);
805 /* Wait for the host mode status bit. */
806 while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) {
807 if (stopwatch_expired(&sw)) {
808 printk(BIOS_ERR, "Timed out waiting for host mode.\n");
809 return;
810 }
811 }
812
813 printk(BIOS_INFO, "xHCI port 0 host switch over took %lld ms\n",
814 stopwatch_duration_msecs(&sw));
815 }
816
check_xdci_enable(void)817 static int check_xdci_enable(void)
818 {
819 return is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_XDCI));
820 }
821
disable_xhci_lfps_pm(void)822 static void disable_xhci_lfps_pm(void)
823 {
824 struct soc_intel_apollolake_config *cfg;
825
826 cfg = config_of_soc();
827
828 if (cfg->disable_xhci_lfps_pm) {
829 void *addr;
830 const struct resource *res;
831 uint32_t reg;
832 struct device *xhci_dev = PCH_DEV_XHCI;
833
834 res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
835 addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL);
836 reg = read32(addr);
837 printk(BIOS_DEBUG, "XHCI PM: control reg=0x%x.\n", reg);
838 if (reg) {
839 reg &= LFPS_PM_DISABLE_MASK;
840 write32(addr, reg);
841 printk(BIOS_INFO, "XHCI PM: Disable xHCI LFPS as configured in devicetree.\n");
842 }
843 }
844 }
845
platform_fsp_notify_status(enum fsp_notify_phase phase)846 void platform_fsp_notify_status(enum fsp_notify_phase phase)
847 {
848 if (phase == END_OF_FIRMWARE) {
849 /*
850 * Before hiding P2SB device and dropping privilege level,
851 * dump CSE status and disable HECI1 interface.
852 */
853 heci_cse_lockdown();
854
855 /* Hide the P2SB device to align with previous behavior. */
856 p2sb_hide();
857
858 /*
859 * As per guidelines BIOS is recommended to drop CPU privilege
860 * level to IA_UNTRUSTED. After that certain device registers
861 * and MSRs become inaccessible supposedly increasing system
862 * security.
863 */
864 drop_privilege_all();
865
866 /*
867 * When USB OTG is set, GLK FSP enables xHCI SW ID pin and
868 * configures USB-C as device mode. Force USB-C into host mode.
869 */
870 if (check_xdci_enable())
871 configure_xhci_host_mode_port0();
872
873 /*
874 * Override GLK xhci clock gating register(XHCLKGTEN) to
875 * mitigate USB device suspend and resume failure.
876 */
877 if (CONFIG(SOC_INTEL_GEMINILAKE)) {
878 uint32_t *cfg;
879 const struct resource *res;
880 uint32_t reg;
881 struct device *xhci_dev = PCH_DEV_XHCI;
882
883 res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
884 cfg = (void *)(uintptr_t)(res->base + CFG_XHCLKGTEN);
885 reg = SRAMPGTEN | SSLSE | USB2PLLSE | IOSFSTCGE |
886 HSTCGE | HSUXDMIPLLSE | SSTCGE | XHCFTCLKSE |
887 XHCBBTCGIPISO | XHCUSB2PLLSDLE | SSPLLSUE |
888 XHCBLCGE | HSLTCGE | SSLTCGE | IOSFBTCGE |
889 IOSFGBLCGE;
890 write32(cfg, reg);
891 }
892
893 /* Disable XHCI LFPS power management if the option in dev tree is set. */
894 disable_xhci_lfps_pm();
895 }
896 }
897
898 /*
899 * spi_flash init() needs to run unconditionally on every boot (including
900 * resume) to allow write protect to be disabled for eventlog and nvram
901 * updates. This needs to be done as early as possible in ramstage. Thus, add a
902 * callback for entry into BS_PRE_DEVICE.
903 */
spi_flash_init_cb(void * unused)904 static void spi_flash_init_cb(void *unused)
905 {
906 fast_spi_init();
907 }
908
909 __weak
mainboard_silicon_init_params(FSP_S_CONFIG * silconfig)910 void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
911 {
912 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
913 }
914
915 /* Handle FSP logo params */
soc_load_logo(FSPS_UPD * supd)916 void soc_load_logo(FSPS_UPD *supd)
917 {
918 size_t logo_size;
919 supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size);
920 supd->FspsConfig.LogoSize = (uint32_t)logo_size;
921 }
922
923 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
924