1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpi.h>
4 #include <device/mmio.h>
5 #include <device/pci_ops.h>
6 #include <bootmode.h>
7 #include <commonlib/helpers.h>
8 #include <console/console.h>
9 #include <cpu/intel/haswell/haswell.h>
10 #include <delay.h>
11 #include <device/device.h>
12 #include <device/pci.h>
13 #include <device/pci_ids.h>
14 #include <string.h>
15 #include <reg_script.h>
16 #include <drivers/intel/gma/i915.h>
17 #include <drivers/intel/gma/i915_reg.h>
18 #include <drivers/intel/gma/libgfxinit.h>
19 #include <drivers/intel/gma/opregion.h>
20 #include <soc/pm.h>
21 #include <soc/systemagent.h>
22 #include <soc/intel/broadwell/chip.h>
23 #include <security/vboot/vbnv.h>
24 #include <soc/igd.h>
25 #include <types.h>
26
27 #define GT_RETRY 1000
28 enum {
29 GT_CDCLK_DEFAULT = 0,
30 GT_CDCLK_337,
31 GT_CDCLK_450,
32 GT_CDCLK_540,
33 GT_CDCLK_675,
34 };
35
36 static u32 reg_em4;
37 static u32 reg_em5;
38
igd_get_reg_em4(void)39 u32 igd_get_reg_em4(void) { return reg_em4; }
igd_get_reg_em5(void)40 u32 igd_get_reg_em5(void) { return reg_em5; }
41
42 struct reg_script haswell_early_init_script[] = {
43 /* Enable Force Wake */
44 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
45 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
46 REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
47
48 /* Enable Counters */
49 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
50
51 /* GFXPAUSE settings */
52 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020),
53
54 /* ECO Settings */
55 REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000),
56
57 /* Enable DOP Clock Gating */
58 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd),
59
60 /* Enable Unit Level Clock Gating */
61 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080),
62 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
63 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
64 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
65
66 /*
67 * RC6 Settings
68 */
69
70 /* Wake Rate Limits */
71 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa090, 0x00000000),
72 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa098, 0x03e80000),
73 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa09c, 0x00280000),
74 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0a8, 0x0001e848),
75 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0ac, 0x00000019),
76
77 /* Render/Video/Blitter Idle Max Count */
78 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a),
79 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a),
80 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a),
81 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a),
82
83 /* RC Sleep / RCx Thresholds */
84 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b0, 0x00000000),
85 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b4, 0x000003e8),
86 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b8, 0x0000c350),
87
88 /* RP Settings */
89 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa010, 0x000f4240),
90 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa014, 0x12060000),
91 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa02c, 0x0000e808),
92 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa030, 0x0003bd08),
93 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa068, 0x000101d0),
94 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa06c, 0x00055730),
95 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a),
96
97 /* RP Control */
98 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92),
99
100 /* HW RC6 Control */
101 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x88040000),
102
103 /* Video Frequency Request */
104 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
105
106 /* Set RC6 VIDs */
107 REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
108 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
109 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
110 REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
111
112 /* Enable PM Interrupts */
113 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
114
115 /* Enable RC6 in idle */
116 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000),
117
118 REG_SCRIPT_END
119 };
120
121 static const struct reg_script haswell_late_init_script[] = {
122 /* Lock settings */
123 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)),
124 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a004, (1 << 4)),
125 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a080, (1 << 2)),
126 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)),
127
128 /* Disable Force Wake */
129 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
130 REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
131 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
132
133 /* Enable power well for DP and Audio */
134 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
135 REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
136 (1 << 30), (1 << 30), GT_RETRY),
137
138 REG_SCRIPT_END
139 };
140
141 static const struct reg_script broadwell_early_init_script[] = {
142 /* Enable Force Wake */
143 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
144 REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
145
146 /* Enable push bus metric control and shift */
147 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004),
148 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff),
149 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010),
150
151 /* GFXPAUSE settings (set based on stepping) */
152
153 /* ECO Settings */
154 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000),
155
156 /* Enable DOP Clock Gating */
157 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000000fd),
158
159 /* Enable Unit Level Clock Gating */
160 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000000),
161 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
162 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
163 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
164 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a),
165
166 /* Video Frequency Request */
167 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
168
169 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138158, 0x00000009),
170 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x13815c, 0x0000000d),
171
172 /*
173 * RC6 Settings
174 */
175
176 /* Wake Rate Limits */
177 REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0a090, 0, 0),
178 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a098, 0x03e80000),
179 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a09c, 0x00280000),
180 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0a8, 0x0001e848),
181 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0ac, 0x00000019),
182
183 /* Render/Video/Blitter Idle Max Count */
184 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a),
185 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a),
186 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a),
187
188 /* RC Sleep / RCx Thresholds */
189 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b0, 0x00000000),
190 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b8, 0x00000271),
191
192 /* RP Settings */
193 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a010, 0x000f4240),
194 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a014, 0x12060000),
195 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a02c, 0x0000e808),
196 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a030, 0x0003bd08),
197 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a068, 0x000101d0),
198 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a06c, 0x00055730),
199 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a070, 0x0000000a),
200 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a168, 0x00000006),
201
202 /* RP Control */
203 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92),
204
205 /* HW RC6 Control */
206 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
207
208 /* Set RC6 VIDs */
209 REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
210 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
211 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
212 REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
213
214 /* Enable PM Interrupts */
215 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
216
217 /* Enable RC6 in idle */
218 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000),
219
220 REG_SCRIPT_END
221 };
222
223 static const struct reg_script broadwell_late_init_script[] = {
224 /* Lock settings */
225 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)),
226 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a000, (1 << 18)),
227 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)),
228
229 /* Disable Force Wake */
230 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
231 REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
232
233 /* Enable power well for DP and Audio */
234 REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
235 REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
236 (1 << 30), (1 << 30), GT_RETRY),
237
238 REG_SCRIPT_END
239 };
240
map_oprom_vendev(u32 vendev)241 u32 map_oprom_vendev(u32 vendev)
242 {
243 if (vendev >> 16 == PCI_VID_INTEL)
244 return SA_IGD_OPROM_VENDEV;
245 else
246 return vendev;
247 }
248
249 static struct resource *gtt_res = NULL;
250
gtt_read(u32 reg)251 u32 gtt_read(u32 reg)
252 {
253 u32 val;
254 val = read32(res2mmio(gtt_res, reg, 0));
255 return val;
256 }
257
gtt_write(u32 reg,u32 data)258 void gtt_write(u32 reg, u32 data)
259 {
260 write32(res2mmio(gtt_res, reg, 0), data);
261 }
262
gtt_rmw(u32 reg,u32 andmask,u32 ormask)263 static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
264 {
265 u32 val = gtt_read(reg);
266 val &= andmask;
267 val |= ormask;
268 gtt_write(reg, val);
269 }
270
gtt_poll(u32 reg,u32 mask,u32 value)271 int gtt_poll(u32 reg, u32 mask, u32 value)
272 { unsigned int try = GT_RETRY;
273 u32 data;
274
275 while (try--) {
276 data = gtt_read(reg);
277 if ((data & mask) == value)
278 return 1;
279 udelay(10);
280 }
281
282 printk(BIOS_ERR, "GT init timeout\n");
283 return 0;
284 }
285
gma_setup_panel(struct device * dev)286 static void gma_setup_panel(struct device *dev)
287 {
288 struct soc_intel_broadwell_config *conf = config_of(dev);
289 const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg;
290 u32 reg32;
291
292 /* Setup Digital Port Hotplug */
293 reg32 = gtt_read(PCH_PORT_HOTPLUG);
294 if (!reg32) {
295 reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
296 reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
297 reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
298 gtt_write(PCH_PORT_HOTPLUG, reg32);
299 }
300
301 /* Setup Panel Power On Delays */
302 reg32 = gtt_read(PCH_PP_ON_DELAYS);
303 if (!reg32) {
304 reg32 |= ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
305 reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
306 gtt_write(PCH_PP_ON_DELAYS, reg32);
307 }
308
309 /* Setup Panel Power Off Delays */
310 reg32 = gtt_read(PCH_PP_OFF_DELAYS);
311 if (!reg32) {
312 reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
313 reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
314 gtt_write(PCH_PP_OFF_DELAYS, reg32);
315 }
316
317 /* Setup Panel Power Cycle Delay */
318 if (panel_cfg->cycle_delay_ms) {
319 reg32 = gtt_read(PCH_PP_DIVISOR);
320 reg32 &= ~0x1f;
321 reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f;
322 gtt_write(PCH_PP_DIVISOR, reg32);
323 }
324
325 /* So far all devices seem to use the PCH PWM function.
326 The CPU PWM registers are all zero after reset. */
327 if (panel_cfg->backlight_pwm_hz) {
328 /* For Lynx Point-LP:
329 Reference clock is 24MHz. We can choose either a 16
330 or a 128 step increment. Use 16 if we would have less
331 than 100 steps otherwise. */
332 const unsigned int refclock = 24 * MHz;
333 const unsigned int hz_limit = refclock / 128 / 100;
334 unsigned int pwm_increment, pwm_period;
335 u32 south_chicken2;
336
337 south_chicken2 = gtt_read(SOUTH_CHICKEN2);
338 if (panel_cfg->backlight_pwm_hz > hz_limit) {
339 pwm_increment = 16;
340 south_chicken2 |= 1 << 5;
341 } else {
342 pwm_increment = 128;
343 south_chicken2 &= ~(1 << 5);
344 }
345 gtt_write(SOUTH_CHICKEN2, south_chicken2);
346
347 pwm_period = refclock / pwm_increment / panel_cfg->backlight_pwm_hz;
348 printk(BIOS_INFO,
349 "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n",
350 refclock / MHz, pwm_increment, pwm_period,
351 DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period));
352
353 /* Start with a 50% duty cycle. */
354 gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
355
356 gtt_write(BLC_PWM_PCH_CTL1,
357 (panel_cfg->backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
358 BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
359 }
360 }
361
igd_get_cdclk_haswell(u32 * const cdsel,int * const inform_pc,struct device * const dev)362 static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
363 struct device *const dev)
364 {
365 const struct soc_intel_broadwell_config *const conf = config_of(dev);
366 int cdclk = conf->cdclk;
367
368 /* Check for ULX GT1 or GT2 */
369 const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
370 const int cpu_is_ult = cpu_family_model() == HASWELL_FAMILY_ULT;
371 const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 ||
372 devid == IGD_HASWELL_ULX_GT2;
373
374 /* Check for fixed fused clock */
375 if (gtt_read(0x42014) & 1 << 24)
376 cdclk = GT_CDCLK_450;
377
378 /*
379 * ULX defaults to 337MHz with possible override for 450MHz
380 * ULT is fixed at 450MHz
381 * others default to 540MHz with possible override for 450MHz
382 */
383 if (gpu_is_ulx && cdclk <= GT_CDCLK_337)
384 cdclk = GT_CDCLK_337;
385 else if (gpu_is_ulx || cpu_is_ult ||
386 cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450)
387 cdclk = GT_CDCLK_450;
388 else
389 cdclk = GT_CDCLK_540;
390
391 *cdsel = cdclk != GT_CDCLK_450;
392 *inform_pc = gpu_is_ulx;
393 return cdclk;
394 }
395
igd_get_cdclk_broadwell(u32 * const cdsel,int * const inform_pc,struct device * const dev)396 static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc,
397 struct device *const dev)
398 {
399 static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 };
400 const struct soc_intel_broadwell_config *const conf = config_of(dev);
401 int cdclk = conf->cdclk;
402
403 /* Check for ULX */
404 const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
405 const int cpu_is_ult = cpu_family_model() == BROADWELL_FAMILY_ULT;
406 const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2;
407
408 /* Inform power controller of upcoming frequency change */
409 gtt_write(0x138128, 0);
410 gtt_write(0x13812c, 0);
411 gtt_write(0x138124, 0x80000018);
412
413 /* Poll GT driver mailbox for run/busy clear */
414 if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
415 *inform_pc = 1;
416 } else {
417 cdclk = GT_CDCLK_450;
418 *inform_pc = 0;
419 }
420
421 /* Check for fixed fused clock */
422 if (gtt_read(0x42014) & 1 << 24)
423 cdclk = GT_CDCLK_450;
424
425 /*
426 * ULX defaults to 450MHz with possible override up to 540MHz
427 * ULT defaults to 540MHz with possible override up to 675MHz
428 * others default to 675MHz with possible override for lower freqs
429 */
430 if (cdclk == GT_CDCLK_337)
431 cdclk = GT_CDCLK_337;
432 else if (cdclk == GT_CDCLK_450 ||
433 (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT))
434 cdclk = GT_CDCLK_450;
435 else if (cdclk == GT_CDCLK_540 || gpu_is_ulx ||
436 (cpu_is_ult && cdclk == GT_CDCLK_DEFAULT))
437 cdclk = GT_CDCLK_540;
438 else
439 cdclk = GT_CDCLK_675;
440
441 *cdsel = cdsel_by_cdclk[cdclk];
442 return cdclk;
443 }
444
igd_cdclk_init(struct device * dev,const int is_broadwell)445 static void igd_cdclk_init(struct device *dev, const int is_broadwell)
446 {
447 u32 dpdiv, cdsel, cdval;
448 int cdclk, inform_pc;
449
450 if (is_broadwell)
451 cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev);
452 else
453 cdclk = igd_get_cdclk_haswell(&cdsel, &inform_pc, dev);
454
455 /* Set variables based on CD Clock setting */
456 switch (cdclk) {
457 case GT_CDCLK_337:
458 cdval = 337;
459 dpdiv = 169;
460 reg_em4 = 16;
461 reg_em5 = 225;
462 break;
463 case GT_CDCLK_450:
464 cdval = 449;
465 dpdiv = 225;
466 reg_em4 = 4;
467 reg_em5 = 75;
468 break;
469 case GT_CDCLK_540:
470 cdval = 539;
471 dpdiv = 270;
472 reg_em4 = 4;
473 reg_em5 = 90;
474 break;
475 case GT_CDCLK_675:
476 cdval = 674;
477 dpdiv = 338;
478 reg_em4 = 8;
479 reg_em5 = 225;
480 break;
481 default:
482 return;
483 }
484
485 /* Set LPCLL_CTL CD Clock Frequency Select */
486 gtt_rmw(0x130040, 0xf3ffffff, cdsel << 26);
487
488 if (inform_pc) {
489 /* Inform power controller of selected frequency */
490 gtt_write(0x138128, cdsel);
491 gtt_write(0x13812c, 0);
492 gtt_write(0x138124, 0x80000017);
493 }
494
495 /* Program CD Clock Frequency */
496 gtt_rmw(0x46200, 0xfffffc00, cdval);
497
498 /* Set CPU DP AUX 2X bit clock dividers */
499 gtt_rmw(0x64010, 0xfffff800, dpdiv);
500 gtt_rmw(0x64810, 0xfffff800, dpdiv);
501 }
502
igd_init(struct device * dev)503 static void igd_init(struct device *dev)
504 {
505 int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
506 u32 rp1_gfx_freq;
507
508 intel_gma_init_igd_opregion();
509
510 gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
511 if (!gtt_res || !gtt_res->base)
512 return;
513
514 if (!CONFIG(NO_GFX_INIT))
515 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
516
517 /* Early init steps */
518 if (is_broadwell) {
519 reg_script_run_on_dev(dev, broadwell_early_init_script);
520
521 /* Set GFXPAUSE based on stepping */
522 if (cpu_stepping() <= (CPUID_BROADWELL_ULT_E0 & 0xf) &&
523 systemagent_revision() <= 9) {
524 gtt_write(0xa000, 0x300ff);
525 } else {
526 gtt_write(0xa000, 0x30020);
527 }
528 } else {
529 reg_script_run_on_dev(dev, haswell_early_init_script);
530 }
531
532 /* Set RP1 graphics frequency */
533 rp1_gfx_freq = (mchbar_read32(0x5998) >> 8) & 0xff;
534 gtt_write(0xa008, rp1_gfx_freq << 24);
535
536 /* Post VBIOS panel setup */
537 gma_setup_panel(dev);
538
539 /* Initialize PCI device, load/execute BIOS Option ROM */
540 pci_dev_init(dev);
541
542 /* Late init steps */
543 igd_cdclk_init(dev, is_broadwell);
544 if (is_broadwell)
545 reg_script_run_on_dev(dev, broadwell_late_init_script);
546 else
547 reg_script_run_on_dev(dev, haswell_late_init_script);
548
549 if (gfx_get_init_done()) {
550 /*
551 * Work around VBIOS issue that is not clearing first 64
552 * bytes of the framebuffer during VBE mode set.
553 */
554 struct resource *fb = find_resource(dev, PCI_BASE_ADDRESS_2);
555 memset((void *)((u32)fb->base), 0, 64);
556 }
557
558 if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) {
559 /*
560 * Enable DDI-A if the Option ROM did not execute:
561 *
562 * bit 0: Display detected (RO)
563 * bit 4: DDI A supports 4 lanes and DDI E is not used
564 * bit 7: DDI buffer is idle
565 */
566 gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
567 DDI_INIT_DISPLAY_DETECTED);
568 }
569
570 if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
571 int lightup_ok;
572 gma_gfxinit(&lightup_ok);
573 gfx_set_init_done(lightup_ok);
574 }
575 }
576
gma_generate_ssdt(const struct device * dev)577 static void gma_generate_ssdt(const struct device *dev)
578 {
579 const struct soc_intel_broadwell_config *chip = dev->chip_info;
580
581 drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
582 }
583
584 static struct device_operations igd_ops = {
585 .read_resources = pci_dev_read_resources,
586 .set_resources = pci_dev_set_resources,
587 .enable_resources = pci_dev_enable_resources,
588 .init = igd_init,
589 .acpi_fill_ssdt = gma_generate_ssdt,
590 .ops_pci = &pci_dev_ops_pci,
591 };
592
593 static const unsigned short pci_device_ids[] = {
594 IGD_HASWELL_ULT_GT1,
595 IGD_HASWELL_ULT_GT2,
596 IGD_HASWELL_ULT_GT3,
597 IGD_BROADWELL_U_GT1,
598 IGD_BROADWELL_U_GT2,
599 IGD_BROADWELL_U_GT3_15W,
600 IGD_BROADWELL_U_GT3_28W,
601 IGD_BROADWELL_Y_GT2,
602 IGD_BROADWELL_H_GT2,
603 IGD_BROADWELL_H_GT3,
604 0,
605 };
606
607 static const struct pci_driver igd_driver __pci_driver = {
608 .ops = &igd_ops,
609 .vendor = PCI_VID_INTEL,
610 .devices = pci_device_ids,
611 };
612