1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DSI_REG_H_ 4 #define _DSI_REG_H_ 5 6 #include <soc/dsi_common.h> 7 #include <soc/dsi_register_v1.h> 8 #include <types.h> 9 10 /* DSI features */ 11 #define MTK_DSI_MIPI_RATIO_NUMERATOR 102 12 #define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 13 #define MTK_DSI_DATA_RATE_MIN_MHZ 50 14 #define MTK_DSI_HAVE_SIZE_CON 0 15 #define PIXEL_STREAM_CUSTOM_HEADER 0 16 17 /* MIPITX is SOC specific and cannot live in common. */ 18 19 /* MIPITX_REG */ 20 struct mipi_tx_regs { 21 u32 dsi_con; 22 u32 dsi_clock_lane; 23 u32 dsi_data_lane[4]; 24 u8 reserved0[40]; 25 u32 dsi_top_con; 26 u32 dsi_bg_con; 27 u8 reserved1[8]; 28 u32 dsi_pll_con0; 29 u32 dsi_pll_con1; 30 u32 dsi_pll_con2; 31 u32 dsi_pll_con3; 32 u32 dsi_pll_chg; 33 u32 dsi_pll_top; 34 u32 dsi_pll_pwr; 35 u8 reserved2[4]; 36 u32 dsi_rgs; 37 u32 dsi_gpi_en; 38 u32 dsi_gpi_pull; 39 u32 dsi_phy_sel; 40 u32 dsi_sw_ctrl_en; 41 u32 dsi_sw_ctrl_con0; 42 u32 dsi_sw_ctrl_con1; 43 u32 dsi_sw_ctrl_con2; 44 u32 dsi_dbg_con; 45 u32 dsi_dbg_out; 46 u32 dsi_apb_async_sta; 47 }; 48 49 check_member(mipi_tx_regs, dsi_top_con, 0x40); 50 check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); 51 52 static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE; 53 static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX0_BASE; 54 55 /* MIPITX_DSI0_CON */ 56 enum { 57 RG_DSI0_LDOCORE_EN = BIT(0), 58 RG_DSI0_CKG_LDOOUT_EN = BIT(1), 59 RG_DSI0_BCLK_SEL = (3 << 2), 60 RG_DSI0_LD_IDX_SEL = (7 << 4), 61 RG_DSI0_PHYCLK_SEL = (2 << 8), 62 RG_DSI0_DSICLK_FREQ_SEL = BIT(10), 63 RG_DSI0_LPTX_CLMP_EN = BIT(11) 64 }; 65 66 /* MIPITX_DSI0_CLOCK_LANE */ 67 enum { 68 LDOOUT_EN = BIT(0), 69 CKLANE_EN = BIT(1), 70 IPLUS1 = BIT(2), 71 LPTX_IPLUS2 = BIT(3), 72 LPTX_IMINUS = BIT(4), 73 LPCD_IPLUS = BIT(5), 74 LPCD_IMLUS = BIT(6), 75 RT_CODE = (0xf << 8) 76 }; 77 78 /* MIPITX_DSI_TOP_CON */ 79 enum { 80 RG_DSI_LNT_INTR_EN = BIT(0), 81 RG_DSI_LNT_HS_BIAS_EN = BIT(1), 82 RG_DSI_LNT_IMP_CAL_EN = BIT(2), 83 RG_DSI_LNT_TESTMODE_EN = BIT(3), 84 RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4), 85 RG_DSI_LNT_AIO_SEL = (7 << 8), 86 RG_DSI_PAD_TIE_LOW_EN = BIT(11), 87 RG_DSI_DEBUG_INPUT_EN = BIT(12), 88 RG_DSI_PRESERVE = (7 << 13) 89 }; 90 91 /* MIPITX_DSI_BG_CON */ 92 enum { 93 RG_DSI_BG_CORE_EN = BIT(0), 94 RG_DSI_BG_CKEN = BIT(1), 95 RG_DSI_BG_DIV = (0x3 << 2), 96 RG_DSI_BG_FAST_CHARGE = BIT(4), 97 RG_DSI_V12_SEL = (7 << 5), 98 RG_DSI_V10_SEL = (7 << 8), 99 RG_DSI_V072_SEL = (7 << 11), 100 RG_DSI_V04_SEL = (7 << 14), 101 RG_DSI_V032_SEL = (7 << 17), 102 RG_DSI_V02_SEL = (7 << 20), 103 rsv_23 = BIT(23), 104 RG_DSI_BG_R1_TRIM = (0xf << 24), 105 RG_DSI_BG_R2_TRIM = (0xf << 28) 106 }; 107 108 /* MIPITX_DSI_PLL_CON0 */ 109 enum { 110 RG_DSI0_MPPLL_PLL_EN = BIT(0), 111 RG_DSI0_MPPLL_PREDIV = (3 << 1), 112 RG_DSI0_MPPLL_TXDIV0 = (3 << 3), 113 RG_DSI0_MPPLL_TXDIV1 = (3 << 5), 114 RG_DSI0_MPPLL_POSDIV = (7 << 7), 115 RG_DSI0_MPPLL_MONVC_EN = BIT(10), 116 RG_DSI0_MPPLL_MONREF_EN = BIT(11), 117 RG_DSI0_MPPLL_VOD_EN = BIT(12) 118 }; 119 120 /* MIPITX_DSI_PLL_CON1 */ 121 enum { 122 RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0), 123 RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1), 124 RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2), 125 RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16) 126 }; 127 128 /* MIPITX_DSI_PLL_PWR */ 129 enum { 130 RG_DSI_MPPLL_SDM_PWR_ON = BIT(0), 131 RG_DSI_MPPLL_SDM_ISO_EN = BIT(1), 132 RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) 133 }; 134 135 /* LVDS_TX1_REG */ 136 struct lvds_tx1_regs { 137 u32 lvdstx1_ctl1; 138 u32 lvdstx1_ctl2; 139 u32 lvdstx1_ctl3; 140 u32 lvdstx1_ctl4; 141 u32 lvdstx1_ctl5; 142 u32 vopll_ctl1; 143 u32 vopll_ctl2; 144 u32 vopll_ctl3; 145 }; 146 147 static struct lvds_tx1_regs *const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800); 148 static struct lvds_tx1_regs *const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800); 149 150 /* LVDS_VOPLL_CTRL3 */ 151 enum { 152 RG_LVDSTX_21EDG = BIT(0), 153 RG_LVDSTX_21LEV = BIT(1), 154 RG_LVDSTX_51EDG = BIT(2), 155 RG_LVDSTX_51LEV = BIT(3), 156 RG_AD_LVDSTX_PWR_ACK = BIT(4), 157 RG_DA_LVDS_ISO_EN = BIT(8), 158 RG_DA_LVDSTX_PWR_ON = BIT(9) 159 }; 160 161 /* SOC specific functions */ 162 void mtk_dsi_pin_drv_ctrl(void); 163 164 #endif 165