1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <edid.h>
5 #include <soc/addressmap.h>
6 #include <soc/ddp.h>
7 #include <types.h>
8
disp_config_main_path_connection(void)9 static void disp_config_main_path_connection(void)
10 {
11 write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L);
12 write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0);
13 write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L);
14 write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR);
15 write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0);
16 write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT);
17 }
18
disp_config_main_path_mutex(void)19 static void disp_config_main_path_mutex(void)
20 {
21 write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
22
23 /* Clock source from DSI0 */
24 write32(&disp_mutex->mutex[0].ctl,
25 MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
26 write32(&disp_mutex->mutex[0].en, BIT(0));
27 }
28
ovl_bgclr_in_sel(u32 idx)29 static void ovl_bgclr_in_sel(u32 idx)
30 {
31 setbits32(&disp_ovl[idx]->datapath_con, BIT(2));
32 }
33
enable_pq(struct disp_pq_regs * const regs,u32 width,u32 height,int enable_relay)34 static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height,
35 int enable_relay)
36 {
37 write32(®s->size, width << 16 | height);
38 if (enable_relay)
39 write32(®s->cfg, PQ_RELAY_MODE);
40 write32(®s->en, PQ_EN);
41 }
42
main_disp_path_setup(u32 width,u32 height,u32 vrefresh)43 static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
44 {
45 u32 idx = 0;
46 u32 pixel_clk = width * height * vrefresh;
47
48 for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++)
49 ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff);
50
51 rdma_config(width, height, pixel_clk, 5 * KiB);
52 color_start(width, height);
53 enable_pq(disp_ccorr, width, height, 1);
54 enable_pq(disp_aal, width, height, 0);
55 enable_pq(disp_gamma, width, height, 0);
56 enable_pq(disp_dither, width, height, 1);
57 disp_config_main_path_connection();
58 disp_config_main_path_mutex();
59 }
60
disp_clock_on(void)61 static void disp_clock_on(void)
62 {
63 clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
64
65 clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
66 CG_CON1_DISP_DSI0_INTERFACE);
67 }
68
mtk_ddp_init(void)69 void mtk_ddp_init(void)
70 {
71 disp_clock_on();
72 /* Turn off M4U port. */
73 write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0);
74 }
75
mtk_ddp_mode_set(const struct edid * edid)76 void mtk_ddp_mode_set(const struct edid *edid)
77 {
78 u32 fmt = OVL_INFMT_RGBA8888;
79 u32 bpp = edid->framebuffer_bits_per_pixel / 8;
80 u32 width = edid->mode.ha;
81 u32 height = edid->mode.va;
82 u32 vrefresh = edid->mode.refresh;
83
84 main_disp_path_setup(width, height, vrefresh);
85 rdma_start();
86 ovl_layer_config(fmt, bpp, width, height);
87 ovl_bgclr_in_sel(1);
88 }
89