1 #ifndef __BDK_CSRS_SATA_H__
2 #define __BDK_CSRS_SATA_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
36 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
39 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium SATA.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration sata_bar_e
57 *
58 * SATA Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_SATA_BAR_E_SATAX_PF_BAR0(a) (0x810000000000ll + 0x1000000000ll * (a))
62 #define BDK_SATA_BAR_E_SATAX_PF_BAR0_SIZE 0x200000ull
63 #define BDK_SATA_BAR_E_SATAX_PF_BAR2(a) (0x810000200000ll + 0x1000000000ll * (a))
64 #define BDK_SATA_BAR_E_SATAX_PF_BAR2_SIZE 0x100000ull
65 #define BDK_SATA_BAR_E_SATAX_PF_BAR4_CN8(a) (0x810000200000ll + 0x1000000000ll * (a))
66 #define BDK_SATA_BAR_E_SATAX_PF_BAR4_CN8_SIZE 0x100000ull
67 #define BDK_SATA_BAR_E_SATAX_PF_BAR4_CN9(a) (0x810000000000ll + 0x1000000000ll * (a))
68 #define BDK_SATA_BAR_E_SATAX_PF_BAR4_CN9_SIZE 0x200000ull
69
70 /**
71 * Enumeration sata_int_vec_e
72 *
73 * SATA MSI-X Vector Enumeration
74 * Enumerates the MSI-X interrupt vectors.
75 */
76 #define BDK_SATA_INT_VEC_E_UAHC_INTRQ_IP (0)
77 #define BDK_SATA_INT_VEC_E_UAHC_INTRQ_IP_CLEAR (1)
78 #define BDK_SATA_INT_VEC_E_UAHC_PME_REQ_IP (2)
79 #define BDK_SATA_INT_VEC_E_UAHC_PME_REQ_IP_CLEAR (3)
80 #define BDK_SATA_INT_VEC_E_UCTL_INTSTAT_CN88XXP1 (4)
81 #define BDK_SATA_INT_VEC_E_UCTL_INTSTAT_CN9 (1)
82 #define BDK_SATA_INT_VEC_E_UCTL_INTSTAT_CN81XX (1)
83 #define BDK_SATA_INT_VEC_E_UCTL_INTSTAT_CN83XX (1)
84 #define BDK_SATA_INT_VEC_E_UCTL_INTSTAT_CN88XXP2 (1)
85 #define BDK_SATA_INT_VEC_E_UCTL_RAS (4)
86
87 /**
88 * Enumeration sata_uctl_dma_read_cmd_e
89 *
90 * SATA UCTL DMA Read Command Enumeration
91 * Enumerates NCB inbound command selections for DMA read operations.
92 */
93 #define BDK_SATA_UCTL_DMA_READ_CMD_E_LDI (0)
94 #define BDK_SATA_UCTL_DMA_READ_CMD_E_LDT (1)
95 #define BDK_SATA_UCTL_DMA_READ_CMD_E_LDY (2)
96
97 /**
98 * Enumeration sata_uctl_dma_write_cmd_e
99 *
100 * SATA UCTL DMA Write Command Enumeration
101 * Enumerate NCB inbound command selections for DMA writes.
102 */
103 #define BDK_SATA_UCTL_DMA_WRITE_CMD_E_RSTP (1)
104 #define BDK_SATA_UCTL_DMA_WRITE_CMD_E_STP (0)
105
106 /**
107 * Enumeration sata_uctl_ecc_err_source_e
108 *
109 * SATA UCTL ECC Error Source Enumeration
110 * Enumerate sources of ECC error log information.
111 */
112 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_FB_DBE (0xf)
113 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_FB_SBE (7)
114 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_NONE (0)
115 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_RX_DBE (0xd)
116 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_RX_SBE (5)
117 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_TX_DBE (0xe)
118 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_TX_SBE (6)
119 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_XM_R_DBE (0xa)
120 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_XM_R_SBE (2)
121 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_XM_W_DBE (9)
122 #define BDK_SATA_UCTL_ECC_ERR_SOURCE_E_XM_W_SBE (1)
123
124 /**
125 * Enumeration sata_uctl_xm_bad_dma_type_e
126 *
127 * SATA UCTL XM Bad DMA Type Enumeration
128 * Enumerates the type of DMA error seen.
129 */
130 #define BDK_SATA_UCTL_XM_BAD_DMA_TYPE_E_ADDR_OOB (1)
131 #define BDK_SATA_UCTL_XM_BAD_DMA_TYPE_E_LEN_GT_8 (2)
132 #define BDK_SATA_UCTL_XM_BAD_DMA_TYPE_E_MULTIBEAT_BYTE (3)
133 #define BDK_SATA_UCTL_XM_BAD_DMA_TYPE_E_MULTIBEAT_HALFWORD (4)
134 #define BDK_SATA_UCTL_XM_BAD_DMA_TYPE_E_MULTIBEAT_QWORD (6)
135 #define BDK_SATA_UCTL_XM_BAD_DMA_TYPE_E_MULTIBEAT_WORD (5)
136 #define BDK_SATA_UCTL_XM_BAD_DMA_TYPE_E_NONE (0)
137
138 /**
139 * Register (NCB) sata#_msix_pba#
140 *
141 * SATA MSI-X Pending Bit Array Registers
142 * This register is the MSI-X PBA table, the bit number is indexed by the SATA_INT_VEC_E enumeration.
143 */
144 union bdk_satax_msix_pbax
145 {
146 uint64_t u;
147 struct bdk_satax_msix_pbax_s
148 {
149 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
150 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated SATA()_MSIX_VEC()_CTL, enumerated by SATA_INT_VEC_E.
151 Bits that have no associated SATA_INT_VEC_E are zero. */
152 #else /* Word 0 - Little Endian */
153 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated SATA()_MSIX_VEC()_CTL, enumerated by SATA_INT_VEC_E.
154 Bits that have no associated SATA_INT_VEC_E are zero. */
155 #endif /* Word 0 - End */
156 } s;
157 /* struct bdk_satax_msix_pbax_s cn; */
158 };
159 typedef union bdk_satax_msix_pbax bdk_satax_msix_pbax_t;
160
161 static inline uint64_t BDK_SATAX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SATAX_MSIX_PBAX(unsigned long a,unsigned long b)162 static inline uint64_t BDK_SATAX_MSIX_PBAX(unsigned long a, unsigned long b)
163 {
164 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
165 return 0x8100002f0000ll + 0x1000000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
166 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=5) && (b==0)))
167 return 0x8100002f0000ll + 0x1000000000ll * ((a) & 0x7) + 8ll * ((b) & 0x0);
168 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=15) && (b==0)))
169 return 0x8100002f0000ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x0);
170 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=3) && (b==0)))
171 return 0x8100002f0000ll + 0x1000000000ll * ((a) & 0x3) + 8ll * ((b) & 0x0);
172 __bdk_csr_fatal("SATAX_MSIX_PBAX", 2, a, b, 0, 0);
173 }
174
175 #define typedef_BDK_SATAX_MSIX_PBAX(a,b) bdk_satax_msix_pbax_t
176 #define bustype_BDK_SATAX_MSIX_PBAX(a,b) BDK_CSR_TYPE_NCB
177 #define basename_BDK_SATAX_MSIX_PBAX(a,b) "SATAX_MSIX_PBAX"
178 #define device_bar_BDK_SATAX_MSIX_PBAX(a,b) 0x2 /* PF_BAR2 */
179 #define busnum_BDK_SATAX_MSIX_PBAX(a,b) (a)
180 #define arguments_BDK_SATAX_MSIX_PBAX(a,b) (a),(b),-1,-1
181
182 /**
183 * Register (NCB) sata#_msix_vec#_addr
184 *
185 * SATA MSI-X Vector Table Address Registers
186 * This register is the MSI-X vector table, indexed by the SATA_INT_VEC_E enumeration.
187 */
188 union bdk_satax_msix_vecx_addr
189 {
190 uint64_t u;
191 struct bdk_satax_msix_vecx_addr_s
192 {
193 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
194 uint64_t reserved_53_63 : 11;
195 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
196 uint64_t reserved_1 : 1;
197 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
198 0 = This vector may be read or written by either secure or nonsecure states.
199 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
200 corresponding
201 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
202 by the nonsecure world.
203
204 If PCCPF_SATA(0..15)_VSEC_SCTL[MSIX_SEC] (for documentation, see
205 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
206 set, all vectors are secure and function as if [SECVEC] was set. */
207 #else /* Word 0 - Little Endian */
208 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
209 0 = This vector may be read or written by either secure or nonsecure states.
210 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
211 corresponding
212 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
213 by the nonsecure world.
214
215 If PCCPF_SATA(0..15)_VSEC_SCTL[MSIX_SEC] (for documentation, see
216 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
217 set, all vectors are secure and function as if [SECVEC] was set. */
218 uint64_t reserved_1 : 1;
219 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
220 uint64_t reserved_53_63 : 11;
221 #endif /* Word 0 - End */
222 } s;
223 struct bdk_satax_msix_vecx_addr_cn9
224 {
225 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
226 uint64_t reserved_53_63 : 11;
227 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
228 uint64_t reserved_1 : 1;
229 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
230 0 = This vector may be read or written by either secure or nonsecure states.
231 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
232 corresponding
233 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
234 by the nonsecure world.
235
236 If PCCPF_SATA()_VSEC_SCTL[MSIX_SEC] (for documentation, see
237 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
238 set, all vectors are secure and function as if [SECVEC] was set. */
239 #else /* Word 0 - Little Endian */
240 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
241 0 = This vector may be read or written by either secure or nonsecure states.
242 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
243 corresponding
244 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
245 by the nonsecure world.
246
247 If PCCPF_SATA()_VSEC_SCTL[MSIX_SEC] (for documentation, see
248 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
249 set, all vectors are secure and function as if [SECVEC] was set. */
250 uint64_t reserved_1 : 1;
251 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
252 uint64_t reserved_53_63 : 11;
253 #endif /* Word 0 - End */
254 } cn9;
255 struct bdk_satax_msix_vecx_addr_cn81xx
256 {
257 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
258 uint64_t reserved_49_63 : 15;
259 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
260 uint64_t reserved_1 : 1;
261 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
262 0 = This vector may be read or written by either secure or nonsecure states.
263 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
264 corresponding
265 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
266 by the nonsecure world.
267
268 If PCCPF_SATA(0..1)_VSEC_SCTL[MSIX_SEC] (for documentation, see
269 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
270 set, all vectors are secure and function as if [SECVEC] was set. */
271 #else /* Word 0 - Little Endian */
272 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
273 0 = This vector may be read or written by either secure or nonsecure states.
274 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
275 corresponding
276 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
277 by the nonsecure world.
278
279 If PCCPF_SATA(0..1)_VSEC_SCTL[MSIX_SEC] (for documentation, see
280 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
281 set, all vectors are secure and function as if [SECVEC] was set. */
282 uint64_t reserved_1 : 1;
283 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
284 uint64_t reserved_49_63 : 15;
285 #endif /* Word 0 - End */
286 } cn81xx;
287 struct bdk_satax_msix_vecx_addr_cn88xx
288 {
289 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
290 uint64_t reserved_49_63 : 15;
291 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
292 uint64_t reserved_1 : 1;
293 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
294 0 = This vector may be read or written by either secure or nonsecure states.
295 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
296 corresponding
297 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
298 by the nonsecure world.
299
300 If PCCPF_SATA(0..15)_VSEC_SCTL[MSIX_SEC] (for documentation, see
301 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
302 set, all vectors are secure and function as if [SECVEC] was set. */
303 #else /* Word 0 - Little Endian */
304 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
305 0 = This vector may be read or written by either secure or nonsecure states.
306 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
307 corresponding
308 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
309 by the nonsecure world.
310
311 If PCCPF_SATA(0..15)_VSEC_SCTL[MSIX_SEC] (for documentation, see
312 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
313 set, all vectors are secure and function as if [SECVEC] was set. */
314 uint64_t reserved_1 : 1;
315 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
316 uint64_t reserved_49_63 : 15;
317 #endif /* Word 0 - End */
318 } cn88xx;
319 struct bdk_satax_msix_vecx_addr_cn83xx
320 {
321 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
322 uint64_t reserved_49_63 : 15;
323 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
324 uint64_t reserved_1 : 1;
325 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
326 0 = This vector may be read or written by either secure or nonsecure states.
327 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
328 corresponding
329 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
330 by the nonsecure world.
331
332 If PCCPF_SATA(0..5)_VSEC_SCTL[MSIX_SEC] (for documentation, see
333 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
334 set, all vectors are secure and function as if [SECVEC] was set. */
335 #else /* Word 0 - Little Endian */
336 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
337 0 = This vector may be read or written by either secure or nonsecure states.
338 1 = This vector's SATA()_MSIX_VEC()_ADDR, SATA()_MSIX_VEC()_CTL, and
339 corresponding
340 bit of SATA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
341 by the nonsecure world.
342
343 If PCCPF_SATA(0..5)_VSEC_SCTL[MSIX_SEC] (for documentation, see
344 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
345 set, all vectors are secure and function as if [SECVEC] was set. */
346 uint64_t reserved_1 : 1;
347 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
348 uint64_t reserved_49_63 : 15;
349 #endif /* Word 0 - End */
350 } cn83xx;
351 };
352 typedef union bdk_satax_msix_vecx_addr bdk_satax_msix_vecx_addr_t;
353
354 static inline uint64_t BDK_SATAX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SATAX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)355 static inline uint64_t BDK_SATAX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
356 {
357 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
358 return 0x810000200000ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
359 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=5) && (b<=3)))
360 return 0x810000200000ll + 0x1000000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x3);
361 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS1_X) && ((a<=15) && (b<=4)))
362 return 0x810000200000ll + 0x1000000000ll * ((a) & 0xf) + 0x10ll * ((b) & 0x7);
363 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && ((a<=15) && (b<=3)))
364 return 0x810000200000ll + 0x1000000000ll * ((a) & 0xf) + 0x10ll * ((b) & 0x3);
365 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=3) && (b<=4)))
366 return 0x810000200000ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x7);
367 __bdk_csr_fatal("SATAX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
368 }
369
370 #define typedef_BDK_SATAX_MSIX_VECX_ADDR(a,b) bdk_satax_msix_vecx_addr_t
371 #define bustype_BDK_SATAX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_NCB
372 #define basename_BDK_SATAX_MSIX_VECX_ADDR(a,b) "SATAX_MSIX_VECX_ADDR"
373 #define device_bar_BDK_SATAX_MSIX_VECX_ADDR(a,b) 0x2 /* PF_BAR2 */
374 #define busnum_BDK_SATAX_MSIX_VECX_ADDR(a,b) (a)
375 #define arguments_BDK_SATAX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
376
377 /**
378 * Register (NCB) sata#_msix_vec#_ctl
379 *
380 * SATA MSI-X Vector Table Control and Data Registers
381 * This register is the MSI-X vector table, indexed by the SATA_INT_VEC_E enumeration.
382 */
383 union bdk_satax_msix_vecx_ctl
384 {
385 uint64_t u;
386 struct bdk_satax_msix_vecx_ctl_s
387 {
388 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
389 uint64_t reserved_33_63 : 31;
390 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
391 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
392 #else /* Word 0 - Little Endian */
393 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
394 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
395 uint64_t reserved_33_63 : 31;
396 #endif /* Word 0 - End */
397 } s;
398 struct bdk_satax_msix_vecx_ctl_cn8
399 {
400 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
401 uint64_t reserved_33_63 : 31;
402 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
403 uint64_t reserved_20_31 : 12;
404 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
405 #else /* Word 0 - Little Endian */
406 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
407 uint64_t reserved_20_31 : 12;
408 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
409 uint64_t reserved_33_63 : 31;
410 #endif /* Word 0 - End */
411 } cn8;
412 /* struct bdk_satax_msix_vecx_ctl_s cn9; */
413 };
414 typedef union bdk_satax_msix_vecx_ctl bdk_satax_msix_vecx_ctl_t;
415
416 static inline uint64_t BDK_SATAX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_SATAX_MSIX_VECX_CTL(unsigned long a,unsigned long b)417 static inline uint64_t BDK_SATAX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
418 {
419 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
420 return 0x810000200008ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
421 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=5) && (b<=3)))
422 return 0x810000200008ll + 0x1000000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x3);
423 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS1_X) && ((a<=15) && (b<=4)))
424 return 0x810000200008ll + 0x1000000000ll * ((a) & 0xf) + 0x10ll * ((b) & 0x7);
425 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && ((a<=15) && (b<=3)))
426 return 0x810000200008ll + 0x1000000000ll * ((a) & 0xf) + 0x10ll * ((b) & 0x3);
427 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=3) && (b<=4)))
428 return 0x810000200008ll + 0x1000000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x7);
429 __bdk_csr_fatal("SATAX_MSIX_VECX_CTL", 2, a, b, 0, 0);
430 }
431
432 #define typedef_BDK_SATAX_MSIX_VECX_CTL(a,b) bdk_satax_msix_vecx_ctl_t
433 #define bustype_BDK_SATAX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_NCB
434 #define basename_BDK_SATAX_MSIX_VECX_CTL(a,b) "SATAX_MSIX_VECX_CTL"
435 #define device_bar_BDK_SATAX_MSIX_VECX_CTL(a,b) 0x2 /* PF_BAR2 */
436 #define busnum_BDK_SATAX_MSIX_VECX_CTL(a,b) (a)
437 #define arguments_BDK_SATAX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
438
439 /**
440 * Register (NCB32b) sata#_uahc_gbl_bistafr
441 *
442 * SATA UAHC BIST Activate FIS Register
443 * This register is shared between SATA ports. Before accessing this
444 * register, first select the required port by writing the port number
445 * to the SATA()_UAHC_GBL_TESTR[PSEL] field.
446 *
447 * This register contains the pattern definition (bits 23:16 of the
448 * first DWORD) and the data pattern (bits 7:0 of the second DWORD)
449 * fields of the received BIST activate FIS.
450 *
451 * Internal:
452 * See DWC_ahsata databook v5.00.
453 */
454 union bdk_satax_uahc_gbl_bistafr
455 {
456 uint32_t u;
457 struct bdk_satax_uahc_gbl_bistafr_s
458 {
459 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
460 uint32_t reserved_16_31 : 16;
461 uint32_t ncp : 8; /**< [ 15: 8](RO) Bits 7:0 of the second DWORD of BIST activate FIS.
462 0xF1 = Low transition density pattern (LTDP).
463 0xB5 = High transition density pattern (HTDP).
464 0xAB = Low frequency spectral component pattern (LFSCP).
465 0x7F = Simultaneous switching outputs pattern (SSOP).
466 0x78 = Mid frequency test pattern (MFTP).
467 0x4A = High frequency test pattern (HFTP).
468 0x7E = Low frequency test pattern (LFTP).
469 else = Lone bit pattern (LBP). */
470 uint32_t pd : 8; /**< [ 7: 0](RO) Bits 23:16 of the first DWORD of the BIST activate FIS. Only the following values are
471 supported:
472 0x10 = Far-end retimed.
473 0xC0 = Far-end transmit only.
474 0xE0 = Far-end transmit only with scrambler bypassed. */
475 #else /* Word 0 - Little Endian */
476 uint32_t pd : 8; /**< [ 7: 0](RO) Bits 23:16 of the first DWORD of the BIST activate FIS. Only the following values are
477 supported:
478 0x10 = Far-end retimed.
479 0xC0 = Far-end transmit only.
480 0xE0 = Far-end transmit only with scrambler bypassed. */
481 uint32_t ncp : 8; /**< [ 15: 8](RO) Bits 7:0 of the second DWORD of BIST activate FIS.
482 0xF1 = Low transition density pattern (LTDP).
483 0xB5 = High transition density pattern (HTDP).
484 0xAB = Low frequency spectral component pattern (LFSCP).
485 0x7F = Simultaneous switching outputs pattern (SSOP).
486 0x78 = Mid frequency test pattern (MFTP).
487 0x4A = High frequency test pattern (HFTP).
488 0x7E = Low frequency test pattern (LFTP).
489 else = Lone bit pattern (LBP). */
490 uint32_t reserved_16_31 : 16;
491 #endif /* Word 0 - End */
492 } s;
493 /* struct bdk_satax_uahc_gbl_bistafr_s cn; */
494 };
495 typedef union bdk_satax_uahc_gbl_bistafr bdk_satax_uahc_gbl_bistafr_t;
496
497 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTAFR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_BISTAFR(unsigned long a)498 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTAFR(unsigned long a)
499 {
500 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
501 return 0x8100000000a0ll + 0x1000000000ll * ((a) & 0x1);
502 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
503 return 0x8100000000a0ll + 0x1000000000ll * ((a) & 0x7);
504 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
505 return 0x8100000000a0ll + 0x1000000000ll * ((a) & 0xf);
506 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
507 return 0x8100000000a0ll + 0x1000000000ll * ((a) & 0x3);
508 __bdk_csr_fatal("SATAX_UAHC_GBL_BISTAFR", 1, a, 0, 0, 0);
509 }
510
511 #define typedef_BDK_SATAX_UAHC_GBL_BISTAFR(a) bdk_satax_uahc_gbl_bistafr_t
512 #define bustype_BDK_SATAX_UAHC_GBL_BISTAFR(a) BDK_CSR_TYPE_NCB32b
513 #define basename_BDK_SATAX_UAHC_GBL_BISTAFR(a) "SATAX_UAHC_GBL_BISTAFR"
514 #define device_bar_BDK_SATAX_UAHC_GBL_BISTAFR(a) 0x4 /* PF_BAR4 */
515 #define busnum_BDK_SATAX_UAHC_GBL_BISTAFR(a) (a)
516 #define arguments_BDK_SATAX_UAHC_GBL_BISTAFR(a) (a),-1,-1,-1
517
518 /**
519 * Register (NCB32b) sata#_uahc_gbl_bistcr
520 *
521 * SATA UAHC BIST Control Register
522 * This register is shared between SATA ports. Before accessing this
523 * register, first select the required port by writing the port number
524 * to the SATA()_UAHC_GBL_TESTR[PSEL] field.
525 *
526 * Internal:
527 * See DWC_ahsata databook v5.00.
528 */
529 union bdk_satax_uahc_gbl_bistcr
530 {
531 uint32_t u;
532 struct bdk_satax_uahc_gbl_bistcr_s
533 {
534 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
535 uint32_t reserved_26_31 : 6;
536 uint32_t old_phy_ready : 1; /**< [ 25: 25](R/W) Old phy_ready. Do not change the value of this bit. */
537 uint32_t late_phy_ready : 1; /**< [ 24: 24](R/W) Late phy_ready. */
538 uint32_t reserved_21_23 : 3;
539 uint32_t ferlib : 1; /**< [ 20: 20](WO) Far-end retimed loopback. */
540 uint32_t reserved_19 : 1;
541 uint32_t txo : 1; /**< [ 18: 18](WO) Transmit only. */
542 uint32_t cntclr : 1; /**< [ 17: 17](WO) Counter clear. */
543 uint32_t nealb : 1; /**< [ 16: 16](WO) Near-end analog loopback. */
544 uint32_t llb : 1; /**< [ 15: 15](R/W) Lab loopback mode. */
545 uint32_t reserved_14 : 1;
546 uint32_t errlossen : 1; /**< [ 13: 13](R/W) Error loss detect enable. */
547 uint32_t sdfe : 1; /**< [ 12: 12](R/W) Signal detect feature enable. */
548 uint32_t rsvd_1rsvd_11 : 1; /**< [ 11: 11](R/W) Reserved. */
549 uint32_t llc : 3; /**< [ 10: 8](R/W) Link layer control.
550 \<10\> = RPD - repeat primitive drop enable.
551 \<9\> = DESCRAM - descrambler enable.
552 \<8\> = SCRAM - scrambler enable. */
553 uint32_t reserved_7 : 1;
554 uint32_t erren : 1; /**< [ 6: 6](R/W) Error enable. */
555 uint32_t flip : 1; /**< [ 5: 5](R/W) Flip disparity. */
556 uint32_t pv : 1; /**< [ 4: 4](R/W) Pattern version. */
557 uint32_t pattern : 4; /**< [ 3: 0](RO) SATA compliant pattern selection. */
558 #else /* Word 0 - Little Endian */
559 uint32_t pattern : 4; /**< [ 3: 0](RO) SATA compliant pattern selection. */
560 uint32_t pv : 1; /**< [ 4: 4](R/W) Pattern version. */
561 uint32_t flip : 1; /**< [ 5: 5](R/W) Flip disparity. */
562 uint32_t erren : 1; /**< [ 6: 6](R/W) Error enable. */
563 uint32_t reserved_7 : 1;
564 uint32_t llc : 3; /**< [ 10: 8](R/W) Link layer control.
565 \<10\> = RPD - repeat primitive drop enable.
566 \<9\> = DESCRAM - descrambler enable.
567 \<8\> = SCRAM - scrambler enable. */
568 uint32_t rsvd_1rsvd_11 : 1; /**< [ 11: 11](R/W) Reserved. */
569 uint32_t sdfe : 1; /**< [ 12: 12](R/W) Signal detect feature enable. */
570 uint32_t errlossen : 1; /**< [ 13: 13](R/W) Error loss detect enable. */
571 uint32_t reserved_14 : 1;
572 uint32_t llb : 1; /**< [ 15: 15](R/W) Lab loopback mode. */
573 uint32_t nealb : 1; /**< [ 16: 16](WO) Near-end analog loopback. */
574 uint32_t cntclr : 1; /**< [ 17: 17](WO) Counter clear. */
575 uint32_t txo : 1; /**< [ 18: 18](WO) Transmit only. */
576 uint32_t reserved_19 : 1;
577 uint32_t ferlib : 1; /**< [ 20: 20](WO) Far-end retimed loopback. */
578 uint32_t reserved_21_23 : 3;
579 uint32_t late_phy_ready : 1; /**< [ 24: 24](R/W) Late phy_ready. */
580 uint32_t old_phy_ready : 1; /**< [ 25: 25](R/W) Old phy_ready. Do not change the value of this bit. */
581 uint32_t reserved_26_31 : 6;
582 #endif /* Word 0 - End */
583 } s;
584 /* struct bdk_satax_uahc_gbl_bistcr_s cn8; */
585 struct bdk_satax_uahc_gbl_bistcr_cn9
586 {
587 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
588 uint32_t reserved_26_31 : 6;
589 uint32_t old_phy_ready : 1; /**< [ 25: 25](R/W) Old phy_ready. Do not change the value of this bit. */
590 uint32_t late_phy_ready : 1; /**< [ 24: 24](R/W) Late phy_ready. */
591 uint32_t reserved_21_23 : 3;
592 uint32_t ferlib : 1; /**< [ 20: 20](WO) Far-end retimed loopback. */
593 uint32_t reserved_19 : 1;
594 uint32_t txo : 1; /**< [ 18: 18](WO) Transmit only. */
595 uint32_t cntclr : 1; /**< [ 17: 17](WO) Counter clear. */
596 uint32_t nealb : 1; /**< [ 16: 16](WO) Near-end analog loopback. */
597 uint32_t llb : 1; /**< [ 15: 15](R/W) Lab loopback mode. */
598 uint32_t reserved_14 : 1;
599 uint32_t errlossen : 1; /**< [ 13: 13](R/W) Error loss detect enable. */
600 uint32_t sdfe : 1; /**< [ 12: 12](R/W) Signal detect feature enable. */
601 uint32_t rsvd_1rsvd_11 : 1; /**< [ 11: 11](R/W) Reserved. */
602 uint32_t llc : 3; /**< [ 10: 8](R/W) Link layer control.
603 \<10\> = RPD - repeat primitive drop enable.
604 \<9\> = DESCRAM - descrambler enable.
605 \<8\> = SCRAM - scrambler enable. */
606 uint32_t reserved_7 : 1;
607 uint32_t erren : 1; /**< [ 6: 6](R/W) Error enable. */
608 uint32_t flip : 1; /**< [ 5: 5](R/W) Flip disparity. */
609 uint32_t pv : 1; /**< [ 4: 4](R/W) Pattern version. */
610 uint32_t pattern : 4; /**< [ 3: 0](R/W) SATA compliant pattern selection. */
611 #else /* Word 0 - Little Endian */
612 uint32_t pattern : 4; /**< [ 3: 0](R/W) SATA compliant pattern selection. */
613 uint32_t pv : 1; /**< [ 4: 4](R/W) Pattern version. */
614 uint32_t flip : 1; /**< [ 5: 5](R/W) Flip disparity. */
615 uint32_t erren : 1; /**< [ 6: 6](R/W) Error enable. */
616 uint32_t reserved_7 : 1;
617 uint32_t llc : 3; /**< [ 10: 8](R/W) Link layer control.
618 \<10\> = RPD - repeat primitive drop enable.
619 \<9\> = DESCRAM - descrambler enable.
620 \<8\> = SCRAM - scrambler enable. */
621 uint32_t rsvd_1rsvd_11 : 1; /**< [ 11: 11](R/W) Reserved. */
622 uint32_t sdfe : 1; /**< [ 12: 12](R/W) Signal detect feature enable. */
623 uint32_t errlossen : 1; /**< [ 13: 13](R/W) Error loss detect enable. */
624 uint32_t reserved_14 : 1;
625 uint32_t llb : 1; /**< [ 15: 15](R/W) Lab loopback mode. */
626 uint32_t nealb : 1; /**< [ 16: 16](WO) Near-end analog loopback. */
627 uint32_t cntclr : 1; /**< [ 17: 17](WO) Counter clear. */
628 uint32_t txo : 1; /**< [ 18: 18](WO) Transmit only. */
629 uint32_t reserved_19 : 1;
630 uint32_t ferlib : 1; /**< [ 20: 20](WO) Far-end retimed loopback. */
631 uint32_t reserved_21_23 : 3;
632 uint32_t late_phy_ready : 1; /**< [ 24: 24](R/W) Late phy_ready. */
633 uint32_t old_phy_ready : 1; /**< [ 25: 25](R/W) Old phy_ready. Do not change the value of this bit. */
634 uint32_t reserved_26_31 : 6;
635 #endif /* Word 0 - End */
636 } cn9;
637 };
638 typedef union bdk_satax_uahc_gbl_bistcr bdk_satax_uahc_gbl_bistcr_t;
639
640 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTCR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_BISTCR(unsigned long a)641 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTCR(unsigned long a)
642 {
643 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
644 return 0x8100000000a4ll + 0x1000000000ll * ((a) & 0x1);
645 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
646 return 0x8100000000a4ll + 0x1000000000ll * ((a) & 0x7);
647 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
648 return 0x8100000000a4ll + 0x1000000000ll * ((a) & 0xf);
649 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
650 return 0x8100000000a4ll + 0x1000000000ll * ((a) & 0x3);
651 __bdk_csr_fatal("SATAX_UAHC_GBL_BISTCR", 1, a, 0, 0, 0);
652 }
653
654 #define typedef_BDK_SATAX_UAHC_GBL_BISTCR(a) bdk_satax_uahc_gbl_bistcr_t
655 #define bustype_BDK_SATAX_UAHC_GBL_BISTCR(a) BDK_CSR_TYPE_NCB32b
656 #define basename_BDK_SATAX_UAHC_GBL_BISTCR(a) "SATAX_UAHC_GBL_BISTCR"
657 #define device_bar_BDK_SATAX_UAHC_GBL_BISTCR(a) 0x4 /* PF_BAR4 */
658 #define busnum_BDK_SATAX_UAHC_GBL_BISTCR(a) (a)
659 #define arguments_BDK_SATAX_UAHC_GBL_BISTCR(a) (a),-1,-1,-1
660
661 /**
662 * Register (NCB32b) sata#_uahc_gbl_bistdecr
663 *
664 * SATA UAHC BIST DWORD Error Count Register
665 * This register is shared between SATA ports. Before accessing this
666 * register, first select the required port by writing the port number
667 * to the SATA()_UAHC_GBL_TESTR[PSEL] field.
668 * Access to the register is disabled on power-on (system reset) or global
669 * SATA block reset, and when the TESTR.BSEL is set to 0.
670 *
671 * Internal:
672 * See DWC_ahsata databook v5.00.
673 */
674 union bdk_satax_uahc_gbl_bistdecr
675 {
676 uint32_t u;
677 struct bdk_satax_uahc_gbl_bistdecr_s
678 {
679 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
680 uint32_t dwerr : 32; /**< [ 31: 0](RO) DWORD error count. */
681 #else /* Word 0 - Little Endian */
682 uint32_t dwerr : 32; /**< [ 31: 0](RO) DWORD error count. */
683 #endif /* Word 0 - End */
684 } s;
685 /* struct bdk_satax_uahc_gbl_bistdecr_s cn; */
686 };
687 typedef union bdk_satax_uahc_gbl_bistdecr bdk_satax_uahc_gbl_bistdecr_t;
688
689 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTDECR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_BISTDECR(unsigned long a)690 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTDECR(unsigned long a)
691 {
692 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
693 return 0x8100000000b0ll + 0x1000000000ll * ((a) & 0x1);
694 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
695 return 0x8100000000b0ll + 0x1000000000ll * ((a) & 0x7);
696 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
697 return 0x8100000000b0ll + 0x1000000000ll * ((a) & 0xf);
698 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
699 return 0x8100000000b0ll + 0x1000000000ll * ((a) & 0x3);
700 __bdk_csr_fatal("SATAX_UAHC_GBL_BISTDECR", 1, a, 0, 0, 0);
701 }
702
703 #define typedef_BDK_SATAX_UAHC_GBL_BISTDECR(a) bdk_satax_uahc_gbl_bistdecr_t
704 #define bustype_BDK_SATAX_UAHC_GBL_BISTDECR(a) BDK_CSR_TYPE_NCB32b
705 #define basename_BDK_SATAX_UAHC_GBL_BISTDECR(a) "SATAX_UAHC_GBL_BISTDECR"
706 #define device_bar_BDK_SATAX_UAHC_GBL_BISTDECR(a) 0x4 /* PF_BAR4 */
707 #define busnum_BDK_SATAX_UAHC_GBL_BISTDECR(a) (a)
708 #define arguments_BDK_SATAX_UAHC_GBL_BISTDECR(a) (a),-1,-1,-1
709
710 /**
711 * Register (NCB32b) sata#_uahc_gbl_bistfctr
712 *
713 * SATA UAHC BIST FIS Count Register
714 * This register is shared between SATA ports. Before accessing this
715 * register, first select the required port by writing the port number
716 * to the SATA()_UAHC_GBL_TESTR[PSEL] field.
717 *
718 * Internal:
719 * See DWC_ahsata databook v5.00.
720 */
721 union bdk_satax_uahc_gbl_bistfctr
722 {
723 uint32_t u;
724 struct bdk_satax_uahc_gbl_bistfctr_s
725 {
726 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
727 uint32_t count : 32; /**< [ 31: 0](RO) Received BIST FIS count. */
728 #else /* Word 0 - Little Endian */
729 uint32_t count : 32; /**< [ 31: 0](RO) Received BIST FIS count. */
730 #endif /* Word 0 - End */
731 } s;
732 /* struct bdk_satax_uahc_gbl_bistfctr_s cn; */
733 };
734 typedef union bdk_satax_uahc_gbl_bistfctr bdk_satax_uahc_gbl_bistfctr_t;
735
736 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTFCTR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_BISTFCTR(unsigned long a)737 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTFCTR(unsigned long a)
738 {
739 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
740 return 0x8100000000a8ll + 0x1000000000ll * ((a) & 0x1);
741 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
742 return 0x8100000000a8ll + 0x1000000000ll * ((a) & 0x7);
743 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
744 return 0x8100000000a8ll + 0x1000000000ll * ((a) & 0xf);
745 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
746 return 0x8100000000a8ll + 0x1000000000ll * ((a) & 0x3);
747 __bdk_csr_fatal("SATAX_UAHC_GBL_BISTFCTR", 1, a, 0, 0, 0);
748 }
749
750 #define typedef_BDK_SATAX_UAHC_GBL_BISTFCTR(a) bdk_satax_uahc_gbl_bistfctr_t
751 #define bustype_BDK_SATAX_UAHC_GBL_BISTFCTR(a) BDK_CSR_TYPE_NCB32b
752 #define basename_BDK_SATAX_UAHC_GBL_BISTFCTR(a) "SATAX_UAHC_GBL_BISTFCTR"
753 #define device_bar_BDK_SATAX_UAHC_GBL_BISTFCTR(a) 0x4 /* PF_BAR4 */
754 #define busnum_BDK_SATAX_UAHC_GBL_BISTFCTR(a) (a)
755 #define arguments_BDK_SATAX_UAHC_GBL_BISTFCTR(a) (a),-1,-1,-1
756
757 /**
758 * Register (NCB32b) sata#_uahc_gbl_bistsr
759 *
760 * INTERNAL: SATA UAHC BIST Status Register
761 *
762 * Internal:
763 * See DWC_ahsata databook v5.00.
764 */
765 union bdk_satax_uahc_gbl_bistsr
766 {
767 uint32_t u;
768 struct bdk_satax_uahc_gbl_bistsr_s
769 {
770 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
771 uint32_t reserved_24_31 : 8;
772 uint32_t brsterr : 8; /**< [ 23: 16](RO) Burst error. */
773 uint32_t framerr : 16; /**< [ 15: 0](RO) Frame error. */
774 #else /* Word 0 - Little Endian */
775 uint32_t framerr : 16; /**< [ 15: 0](RO) Frame error. */
776 uint32_t brsterr : 8; /**< [ 23: 16](RO) Burst error. */
777 uint32_t reserved_24_31 : 8;
778 #endif /* Word 0 - End */
779 } s;
780 /* struct bdk_satax_uahc_gbl_bistsr_s cn; */
781 };
782 typedef union bdk_satax_uahc_gbl_bistsr bdk_satax_uahc_gbl_bistsr_t;
783
784 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTSR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_BISTSR(unsigned long a)785 static inline uint64_t BDK_SATAX_UAHC_GBL_BISTSR(unsigned long a)
786 {
787 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
788 return 0x8100000000acll + 0x1000000000ll * ((a) & 0x1);
789 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
790 return 0x8100000000acll + 0x1000000000ll * ((a) & 0x7);
791 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
792 return 0x8100000000acll + 0x1000000000ll * ((a) & 0xf);
793 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
794 return 0x8100000000acll + 0x1000000000ll * ((a) & 0x3);
795 __bdk_csr_fatal("SATAX_UAHC_GBL_BISTSR", 1, a, 0, 0, 0);
796 }
797
798 #define typedef_BDK_SATAX_UAHC_GBL_BISTSR(a) bdk_satax_uahc_gbl_bistsr_t
799 #define bustype_BDK_SATAX_UAHC_GBL_BISTSR(a) BDK_CSR_TYPE_NCB32b
800 #define basename_BDK_SATAX_UAHC_GBL_BISTSR(a) "SATAX_UAHC_GBL_BISTSR"
801 #define device_bar_BDK_SATAX_UAHC_GBL_BISTSR(a) 0x4 /* PF_BAR4 */
802 #define busnum_BDK_SATAX_UAHC_GBL_BISTSR(a) (a)
803 #define arguments_BDK_SATAX_UAHC_GBL_BISTSR(a) (a),-1,-1,-1
804
805 /**
806 * Register (NCB32b) sata#_uahc_gbl_cap
807 *
808 * SATA AHCI HBA Capabilities Register
809 * This register indicates basic capabilities of the SATA core to software.
810 */
811 union bdk_satax_uahc_gbl_cap
812 {
813 uint32_t u;
814 struct bdk_satax_uahc_gbl_cap_s
815 {
816 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
817 uint32_t s64a : 1; /**< [ 31: 31](RO) Supports 64-bit addressing. */
818 uint32_t sncq : 1; /**< [ 30: 30](RO) Supports native command queuing. */
819 uint32_t ssntf : 1; /**< [ 29: 29](RO) Supports SNotification register. */
820 uint32_t smps : 1; /**< [ 28: 28](R/W) Supports mechanical presence switch. */
821 uint32_t sss : 1; /**< [ 27: 27](R/W) Supports staggered spin-up. */
822 uint32_t salp : 1; /**< [ 26: 26](RO) Supports aggressive link power management. */
823 uint32_t sal : 1; /**< [ 25: 25](RO) Supports activity LED. */
824 uint32_t sclo : 1; /**< [ 24: 24](RO) Supports command list override. */
825 uint32_t iss : 4; /**< [ 23: 20](RO) Interface speed support. */
826 uint32_t snzo : 1; /**< [ 19: 19](RO) Supports nonzero DMA offsets. */
827 uint32_t sam : 1; /**< [ 18: 18](RO) Supports AHCI mode only. */
828 uint32_t spm : 1; /**< [ 17: 17](RO) Supports port multiplier. */
829 uint32_t fbss : 1; /**< [ 16: 16](RO) Supports FIS-based switching. */
830 uint32_t pmd : 1; /**< [ 15: 15](RO) PIO multiple DRQ block. */
831 uint32_t ssc : 1; /**< [ 14: 14](RO) Slumber state capable. */
832 uint32_t psc : 1; /**< [ 13: 13](RO) Partial state capable. */
833 uint32_t ncs : 5; /**< [ 12: 8](RO) Number of command slots. */
834 uint32_t cccs : 1; /**< [ 7: 7](RO) Command completion coalescing support. */
835 uint32_t ems : 1; /**< [ 6: 6](RO) Enclosure management support. */
836 uint32_t sxs : 1; /**< [ 5: 5](RO) Supports external SATA. */
837 uint32_t np : 5; /**< [ 4: 0](RO) Number of ports. 0x0 = 1 port. */
838 #else /* Word 0 - Little Endian */
839 uint32_t np : 5; /**< [ 4: 0](RO) Number of ports. 0x0 = 1 port. */
840 uint32_t sxs : 1; /**< [ 5: 5](RO) Supports external SATA. */
841 uint32_t ems : 1; /**< [ 6: 6](RO) Enclosure management support. */
842 uint32_t cccs : 1; /**< [ 7: 7](RO) Command completion coalescing support. */
843 uint32_t ncs : 5; /**< [ 12: 8](RO) Number of command slots. */
844 uint32_t psc : 1; /**< [ 13: 13](RO) Partial state capable. */
845 uint32_t ssc : 1; /**< [ 14: 14](RO) Slumber state capable. */
846 uint32_t pmd : 1; /**< [ 15: 15](RO) PIO multiple DRQ block. */
847 uint32_t fbss : 1; /**< [ 16: 16](RO) Supports FIS-based switching. */
848 uint32_t spm : 1; /**< [ 17: 17](RO) Supports port multiplier. */
849 uint32_t sam : 1; /**< [ 18: 18](RO) Supports AHCI mode only. */
850 uint32_t snzo : 1; /**< [ 19: 19](RO) Supports nonzero DMA offsets. */
851 uint32_t iss : 4; /**< [ 23: 20](RO) Interface speed support. */
852 uint32_t sclo : 1; /**< [ 24: 24](RO) Supports command list override. */
853 uint32_t sal : 1; /**< [ 25: 25](RO) Supports activity LED. */
854 uint32_t salp : 1; /**< [ 26: 26](RO) Supports aggressive link power management. */
855 uint32_t sss : 1; /**< [ 27: 27](R/W) Supports staggered spin-up. */
856 uint32_t smps : 1; /**< [ 28: 28](R/W) Supports mechanical presence switch. */
857 uint32_t ssntf : 1; /**< [ 29: 29](RO) Supports SNotification register. */
858 uint32_t sncq : 1; /**< [ 30: 30](RO) Supports native command queuing. */
859 uint32_t s64a : 1; /**< [ 31: 31](RO) Supports 64-bit addressing. */
860 #endif /* Word 0 - End */
861 } s;
862 /* struct bdk_satax_uahc_gbl_cap_s cn8; */
863 struct bdk_satax_uahc_gbl_cap_cn9
864 {
865 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
866 uint32_t s64a : 1; /**< [ 31: 31](RO) Supports 64-bit addressing. */
867 uint32_t sncq : 1; /**< [ 30: 30](RO) Supports native command queuing. */
868 uint32_t ssntf : 1; /**< [ 29: 29](RO) Supports SNotification register. */
869 uint32_t smps : 1; /**< [ 28: 28](R/W) Supports mechanical presence switch. */
870 uint32_t sss : 1; /**< [ 27: 27](R/W) Supports staggered spin-up. */
871 uint32_t salp : 1; /**< [ 26: 26](RO) Supports aggressive link power management. */
872 uint32_t sal : 1; /**< [ 25: 25](RO) Supports activity LED. */
873 uint32_t sclo : 1; /**< [ 24: 24](RO) Supports command list override. */
874 uint32_t iss : 4; /**< [ 23: 20](RO) Interface speed support. */
875 uint32_t snzo : 1; /**< [ 19: 19](RO) Supports nonzero DMA offsets. */
876 uint32_t sam : 1; /**< [ 18: 18](RO) Supports AHCI mode only. */
877 uint32_t spm : 1; /**< [ 17: 17](RO) Supports port multiplier. */
878 uint32_t fbss : 1; /**< [ 16: 16](RO) Supports FIS-based switching. */
879 uint32_t pmd : 1; /**< [ 15: 15](RO) PIO multiple DRQ block. */
880 uint32_t ssc : 1; /**< [ 14: 14](RO) Slumber state capable. */
881 uint32_t psc : 1; /**< [ 13: 13](RO) Partial state capable. */
882 uint32_t ncs : 5; /**< [ 12: 8](RO) Number of command slots. */
883 uint32_t cccs : 1; /**< [ 7: 7](RO) Command completion coalescing support. */
884 uint32_t ems : 1; /**< [ 6: 6](RO) Enclosure management support, as in termination of commands.
885 CNXXXX does not terminate enclosure management commands, but does support
886 passing enclosure management commands through to downstream controllers. */
887 uint32_t sxs : 1; /**< [ 5: 5](RO) Supports external SATA. */
888 uint32_t np : 5; /**< [ 4: 0](RO) Number of ports. 0x0 = 1 port. */
889 #else /* Word 0 - Little Endian */
890 uint32_t np : 5; /**< [ 4: 0](RO) Number of ports. 0x0 = 1 port. */
891 uint32_t sxs : 1; /**< [ 5: 5](RO) Supports external SATA. */
892 uint32_t ems : 1; /**< [ 6: 6](RO) Enclosure management support, as in termination of commands.
893 CNXXXX does not terminate enclosure management commands, but does support
894 passing enclosure management commands through to downstream controllers. */
895 uint32_t cccs : 1; /**< [ 7: 7](RO) Command completion coalescing support. */
896 uint32_t ncs : 5; /**< [ 12: 8](RO) Number of command slots. */
897 uint32_t psc : 1; /**< [ 13: 13](RO) Partial state capable. */
898 uint32_t ssc : 1; /**< [ 14: 14](RO) Slumber state capable. */
899 uint32_t pmd : 1; /**< [ 15: 15](RO) PIO multiple DRQ block. */
900 uint32_t fbss : 1; /**< [ 16: 16](RO) Supports FIS-based switching. */
901 uint32_t spm : 1; /**< [ 17: 17](RO) Supports port multiplier. */
902 uint32_t sam : 1; /**< [ 18: 18](RO) Supports AHCI mode only. */
903 uint32_t snzo : 1; /**< [ 19: 19](RO) Supports nonzero DMA offsets. */
904 uint32_t iss : 4; /**< [ 23: 20](RO) Interface speed support. */
905 uint32_t sclo : 1; /**< [ 24: 24](RO) Supports command list override. */
906 uint32_t sal : 1; /**< [ 25: 25](RO) Supports activity LED. */
907 uint32_t salp : 1; /**< [ 26: 26](RO) Supports aggressive link power management. */
908 uint32_t sss : 1; /**< [ 27: 27](R/W) Supports staggered spin-up. */
909 uint32_t smps : 1; /**< [ 28: 28](R/W) Supports mechanical presence switch. */
910 uint32_t ssntf : 1; /**< [ 29: 29](RO) Supports SNotification register. */
911 uint32_t sncq : 1; /**< [ 30: 30](RO) Supports native command queuing. */
912 uint32_t s64a : 1; /**< [ 31: 31](RO) Supports 64-bit addressing. */
913 #endif /* Word 0 - End */
914 } cn9;
915 };
916 typedef union bdk_satax_uahc_gbl_cap bdk_satax_uahc_gbl_cap_t;
917
918 static inline uint64_t BDK_SATAX_UAHC_GBL_CAP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_CAP(unsigned long a)919 static inline uint64_t BDK_SATAX_UAHC_GBL_CAP(unsigned long a)
920 {
921 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
922 return 0x810000000000ll + 0x1000000000ll * ((a) & 0x1);
923 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
924 return 0x810000000000ll + 0x1000000000ll * ((a) & 0x7);
925 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
926 return 0x810000000000ll + 0x1000000000ll * ((a) & 0xf);
927 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
928 return 0x810000000000ll + 0x1000000000ll * ((a) & 0x3);
929 __bdk_csr_fatal("SATAX_UAHC_GBL_CAP", 1, a, 0, 0, 0);
930 }
931
932 #define typedef_BDK_SATAX_UAHC_GBL_CAP(a) bdk_satax_uahc_gbl_cap_t
933 #define bustype_BDK_SATAX_UAHC_GBL_CAP(a) BDK_CSR_TYPE_NCB32b
934 #define basename_BDK_SATAX_UAHC_GBL_CAP(a) "SATAX_UAHC_GBL_CAP"
935 #define device_bar_BDK_SATAX_UAHC_GBL_CAP(a) 0x4 /* PF_BAR4 */
936 #define busnum_BDK_SATAX_UAHC_GBL_CAP(a) (a)
937 #define arguments_BDK_SATAX_UAHC_GBL_CAP(a) (a),-1,-1,-1
938
939 /**
940 * Register (NCB32b) sata#_uahc_gbl_cap2
941 *
942 * SATA AHCI HBA Capabilities Extended Register
943 * This register indicates capabilities of the SATA core to software.
944 */
945 union bdk_satax_uahc_gbl_cap2
946 {
947 uint32_t u;
948 struct bdk_satax_uahc_gbl_cap2_s
949 {
950 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
951 uint32_t reserved_6_31 : 26;
952 uint32_t deso : 1; /**< [ 5: 5](RO) Device sleep entrance from slumber only. */
953 uint32_t sadm : 1; /**< [ 4: 4](RO) Supports aggressive device sleep management. */
954 uint32_t sds : 1; /**< [ 3: 3](RO) Supports device sleep. */
955 uint32_t apst : 1; /**< [ 2: 2](RO) Automatic partial to slumber transitions. */
956 uint32_t nvmp : 1; /**< [ 1: 1](RO) NVMHCI present. */
957 uint32_t boh : 1; /**< [ 0: 0](RO) Supports BIOS/OS handoff. */
958 #else /* Word 0 - Little Endian */
959 uint32_t boh : 1; /**< [ 0: 0](RO) Supports BIOS/OS handoff. */
960 uint32_t nvmp : 1; /**< [ 1: 1](RO) NVMHCI present. */
961 uint32_t apst : 1; /**< [ 2: 2](RO) Automatic partial to slumber transitions. */
962 uint32_t sds : 1; /**< [ 3: 3](RO) Supports device sleep. */
963 uint32_t sadm : 1; /**< [ 4: 4](RO) Supports aggressive device sleep management. */
964 uint32_t deso : 1; /**< [ 5: 5](RO) Device sleep entrance from slumber only. */
965 uint32_t reserved_6_31 : 26;
966 #endif /* Word 0 - End */
967 } s;
968 /* struct bdk_satax_uahc_gbl_cap2_s cn; */
969 };
970 typedef union bdk_satax_uahc_gbl_cap2 bdk_satax_uahc_gbl_cap2_t;
971
972 static inline uint64_t BDK_SATAX_UAHC_GBL_CAP2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_CAP2(unsigned long a)973 static inline uint64_t BDK_SATAX_UAHC_GBL_CAP2(unsigned long a)
974 {
975 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
976 return 0x810000000024ll + 0x1000000000ll * ((a) & 0x1);
977 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
978 return 0x810000000024ll + 0x1000000000ll * ((a) & 0x7);
979 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
980 return 0x810000000024ll + 0x1000000000ll * ((a) & 0xf);
981 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
982 return 0x810000000024ll + 0x1000000000ll * ((a) & 0x3);
983 __bdk_csr_fatal("SATAX_UAHC_GBL_CAP2", 1, a, 0, 0, 0);
984 }
985
986 #define typedef_BDK_SATAX_UAHC_GBL_CAP2(a) bdk_satax_uahc_gbl_cap2_t
987 #define bustype_BDK_SATAX_UAHC_GBL_CAP2(a) BDK_CSR_TYPE_NCB32b
988 #define basename_BDK_SATAX_UAHC_GBL_CAP2(a) "SATAX_UAHC_GBL_CAP2"
989 #define device_bar_BDK_SATAX_UAHC_GBL_CAP2(a) 0x4 /* PF_BAR4 */
990 #define busnum_BDK_SATAX_UAHC_GBL_CAP2(a) (a)
991 #define arguments_BDK_SATAX_UAHC_GBL_CAP2(a) (a),-1,-1,-1
992
993 /**
994 * Register (NCB32b) sata#_uahc_gbl_ccc_ctl
995 *
996 * SATA AHCI CCC Control Register
997 * This register is used to configure the command completion coalescing (CCC) feature for the
998 * SATA core. It is reset on global reset.
999 */
1000 union bdk_satax_uahc_gbl_ccc_ctl
1001 {
1002 uint32_t u;
1003 struct bdk_satax_uahc_gbl_ccc_ctl_s
1004 {
1005 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1006 uint32_t tv : 16; /**< [ 31: 16](R/W) Time-out value. Writable only when [EN] = 0. */
1007 uint32_t cc : 8; /**< [ 15: 8](R/W) Command completions. Writable only when [EN] = 0. */
1008 uint32_t intr : 5; /**< [ 7: 3](RO) Specifies the port interrupt used by the CCC feature. */
1009 uint32_t reserved_1_2 : 2;
1010 uint32_t en : 1; /**< [ 0: 0](R/W) CCC enable. */
1011 #else /* Word 0 - Little Endian */
1012 uint32_t en : 1; /**< [ 0: 0](R/W) CCC enable. */
1013 uint32_t reserved_1_2 : 2;
1014 uint32_t intr : 5; /**< [ 7: 3](RO) Specifies the port interrupt used by the CCC feature. */
1015 uint32_t cc : 8; /**< [ 15: 8](R/W) Command completions. Writable only when [EN] = 0. */
1016 uint32_t tv : 16; /**< [ 31: 16](R/W) Time-out value. Writable only when [EN] = 0. */
1017 #endif /* Word 0 - End */
1018 } s;
1019 /* struct bdk_satax_uahc_gbl_ccc_ctl_s cn; */
1020 };
1021 typedef union bdk_satax_uahc_gbl_ccc_ctl bdk_satax_uahc_gbl_ccc_ctl_t;
1022
1023 static inline uint64_t BDK_SATAX_UAHC_GBL_CCC_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_CCC_CTL(unsigned long a)1024 static inline uint64_t BDK_SATAX_UAHC_GBL_CCC_CTL(unsigned long a)
1025 {
1026 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1027 return 0x810000000014ll + 0x1000000000ll * ((a) & 0x1);
1028 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1029 return 0x810000000014ll + 0x1000000000ll * ((a) & 0x7);
1030 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1031 return 0x810000000014ll + 0x1000000000ll * ((a) & 0xf);
1032 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1033 return 0x810000000014ll + 0x1000000000ll * ((a) & 0x3);
1034 __bdk_csr_fatal("SATAX_UAHC_GBL_CCC_CTL", 1, a, 0, 0, 0);
1035 }
1036
1037 #define typedef_BDK_SATAX_UAHC_GBL_CCC_CTL(a) bdk_satax_uahc_gbl_ccc_ctl_t
1038 #define bustype_BDK_SATAX_UAHC_GBL_CCC_CTL(a) BDK_CSR_TYPE_NCB32b
1039 #define basename_BDK_SATAX_UAHC_GBL_CCC_CTL(a) "SATAX_UAHC_GBL_CCC_CTL"
1040 #define device_bar_BDK_SATAX_UAHC_GBL_CCC_CTL(a) 0x4 /* PF_BAR4 */
1041 #define busnum_BDK_SATAX_UAHC_GBL_CCC_CTL(a) (a)
1042 #define arguments_BDK_SATAX_UAHC_GBL_CCC_CTL(a) (a),-1,-1,-1
1043
1044 /**
1045 * Register (NCB32b) sata#_uahc_gbl_ccc_ports
1046 *
1047 * SATA AHCI CCC Ports Register
1048 * This register specifies the ports that are coalesced as part of the command completion
1049 * coalescing
1050 * (CCC) feature when SATA()_UAHC_GBL_CCC_CTL[EN]=1. It is reset on global reset.
1051 */
1052 union bdk_satax_uahc_gbl_ccc_ports
1053 {
1054 uint32_t u;
1055 struct bdk_satax_uahc_gbl_ccc_ports_s
1056 {
1057 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1058 uint32_t reserved_1_31 : 31;
1059 uint32_t prt : 1; /**< [ 0: 0](R/W) Per port CCC enable. */
1060 #else /* Word 0 - Little Endian */
1061 uint32_t prt : 1; /**< [ 0: 0](R/W) Per port CCC enable. */
1062 uint32_t reserved_1_31 : 31;
1063 #endif /* Word 0 - End */
1064 } s;
1065 /* struct bdk_satax_uahc_gbl_ccc_ports_s cn; */
1066 };
1067 typedef union bdk_satax_uahc_gbl_ccc_ports bdk_satax_uahc_gbl_ccc_ports_t;
1068
1069 static inline uint64_t BDK_SATAX_UAHC_GBL_CCC_PORTS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_CCC_PORTS(unsigned long a)1070 static inline uint64_t BDK_SATAX_UAHC_GBL_CCC_PORTS(unsigned long a)
1071 {
1072 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1073 return 0x810000000018ll + 0x1000000000ll * ((a) & 0x1);
1074 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1075 return 0x810000000018ll + 0x1000000000ll * ((a) & 0x7);
1076 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1077 return 0x810000000018ll + 0x1000000000ll * ((a) & 0xf);
1078 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1079 return 0x810000000018ll + 0x1000000000ll * ((a) & 0x3);
1080 __bdk_csr_fatal("SATAX_UAHC_GBL_CCC_PORTS", 1, a, 0, 0, 0);
1081 }
1082
1083 #define typedef_BDK_SATAX_UAHC_GBL_CCC_PORTS(a) bdk_satax_uahc_gbl_ccc_ports_t
1084 #define bustype_BDK_SATAX_UAHC_GBL_CCC_PORTS(a) BDK_CSR_TYPE_NCB32b
1085 #define basename_BDK_SATAX_UAHC_GBL_CCC_PORTS(a) "SATAX_UAHC_GBL_CCC_PORTS"
1086 #define device_bar_BDK_SATAX_UAHC_GBL_CCC_PORTS(a) 0x4 /* PF_BAR4 */
1087 #define busnum_BDK_SATAX_UAHC_GBL_CCC_PORTS(a) (a)
1088 #define arguments_BDK_SATAX_UAHC_GBL_CCC_PORTS(a) (a),-1,-1,-1
1089
1090 /**
1091 * Register (NCB32b) sata#_uahc_gbl_diagnr3
1092 *
1093 * SATA UAHC DIAGNR3 Register
1094 * Internal:
1095 * See DWC_ahsata databook v5.00.
1096 */
1097 union bdk_satax_uahc_gbl_diagnr3
1098 {
1099 uint32_t u;
1100 struct bdk_satax_uahc_gbl_diagnr3_s
1101 {
1102 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1103 uint32_t fbcsw_cnt : 32; /**< [ 31: 0](R/W1C) FIS-based context switching counter. Any 32-bit write to this location clears the counter. */
1104 #else /* Word 0 - Little Endian */
1105 uint32_t fbcsw_cnt : 32; /**< [ 31: 0](R/W1C) FIS-based context switching counter. Any 32-bit write to this location clears the counter. */
1106 #endif /* Word 0 - End */
1107 } s;
1108 /* struct bdk_satax_uahc_gbl_diagnr3_s cn; */
1109 };
1110 typedef union bdk_satax_uahc_gbl_diagnr3 bdk_satax_uahc_gbl_diagnr3_t;
1111
1112 static inline uint64_t BDK_SATAX_UAHC_GBL_DIAGNR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_DIAGNR3(unsigned long a)1113 static inline uint64_t BDK_SATAX_UAHC_GBL_DIAGNR3(unsigned long a)
1114 {
1115 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1116 return 0x8100000000c4ll + 0x1000000000ll * ((a) & 0x3);
1117 __bdk_csr_fatal("SATAX_UAHC_GBL_DIAGNR3", 1, a, 0, 0, 0);
1118 }
1119
1120 #define typedef_BDK_SATAX_UAHC_GBL_DIAGNR3(a) bdk_satax_uahc_gbl_diagnr3_t
1121 #define bustype_BDK_SATAX_UAHC_GBL_DIAGNR3(a) BDK_CSR_TYPE_NCB32b
1122 #define basename_BDK_SATAX_UAHC_GBL_DIAGNR3(a) "SATAX_UAHC_GBL_DIAGNR3"
1123 #define device_bar_BDK_SATAX_UAHC_GBL_DIAGNR3(a) 0x4 /* PF_BAR4 */
1124 #define busnum_BDK_SATAX_UAHC_GBL_DIAGNR3(a) (a)
1125 #define arguments_BDK_SATAX_UAHC_GBL_DIAGNR3(a) (a),-1,-1,-1
1126
1127 /**
1128 * Register (NCB32b) sata#_uahc_gbl_ghc
1129 *
1130 * SATA AHCI Global HBA Control Register
1131 * This register controls various global actions of the SATA core.
1132 */
1133 union bdk_satax_uahc_gbl_ghc
1134 {
1135 uint32_t u;
1136 struct bdk_satax_uahc_gbl_ghc_s
1137 {
1138 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1139 uint32_t ae : 1; /**< [ 31: 31](RO) AHCI enable. */
1140 uint32_t reserved_2_30 : 29;
1141 uint32_t ie : 1; /**< [ 1: 1](R/W) Interrupt enable. */
1142 uint32_t hr : 1; /**< [ 0: 0](R/W1/H) HBA reset. Writing a 1 resets the UAHC. Hardware clears this bit once reset is complete. */
1143 #else /* Word 0 - Little Endian */
1144 uint32_t hr : 1; /**< [ 0: 0](R/W1/H) HBA reset. Writing a 1 resets the UAHC. Hardware clears this bit once reset is complete. */
1145 uint32_t ie : 1; /**< [ 1: 1](R/W) Interrupt enable. */
1146 uint32_t reserved_2_30 : 29;
1147 uint32_t ae : 1; /**< [ 31: 31](RO) AHCI enable. */
1148 #endif /* Word 0 - End */
1149 } s;
1150 /* struct bdk_satax_uahc_gbl_ghc_s cn; */
1151 };
1152 typedef union bdk_satax_uahc_gbl_ghc bdk_satax_uahc_gbl_ghc_t;
1153
1154 static inline uint64_t BDK_SATAX_UAHC_GBL_GHC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_GHC(unsigned long a)1155 static inline uint64_t BDK_SATAX_UAHC_GBL_GHC(unsigned long a)
1156 {
1157 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1158 return 0x810000000004ll + 0x1000000000ll * ((a) & 0x1);
1159 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1160 return 0x810000000004ll + 0x1000000000ll * ((a) & 0x7);
1161 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1162 return 0x810000000004ll + 0x1000000000ll * ((a) & 0xf);
1163 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1164 return 0x810000000004ll + 0x1000000000ll * ((a) & 0x3);
1165 __bdk_csr_fatal("SATAX_UAHC_GBL_GHC", 1, a, 0, 0, 0);
1166 }
1167
1168 #define typedef_BDK_SATAX_UAHC_GBL_GHC(a) bdk_satax_uahc_gbl_ghc_t
1169 #define bustype_BDK_SATAX_UAHC_GBL_GHC(a) BDK_CSR_TYPE_NCB32b
1170 #define basename_BDK_SATAX_UAHC_GBL_GHC(a) "SATAX_UAHC_GBL_GHC"
1171 #define device_bar_BDK_SATAX_UAHC_GBL_GHC(a) 0x4 /* PF_BAR4 */
1172 #define busnum_BDK_SATAX_UAHC_GBL_GHC(a) (a)
1173 #define arguments_BDK_SATAX_UAHC_GBL_GHC(a) (a),-1,-1,-1
1174
1175 /**
1176 * Register (NCB32b) sata#_uahc_gbl_gparam1r
1177 *
1178 * SATA UAHC Global Parameter Register 1
1179 * Internal:
1180 * See DWC_ahsata databook v5.00.
1181 */
1182 union bdk_satax_uahc_gbl_gparam1r
1183 {
1184 uint32_t u;
1185 struct bdk_satax_uahc_gbl_gparam1r_s
1186 {
1187 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1188 uint32_t align_m : 1; /**< [ 31: 31](RO) RX data alignment mode (ALIGN_MODE). */
1189 uint32_t rx_buffer : 1; /**< [ 30: 30](RO) RX data buffer mode (RX_BUFFER_MODE). */
1190 uint32_t phy_data : 2; /**< [ 29: 28](RO) PHY data width (PHY_DATA_WIDTH). */
1191 uint32_t phy_rst : 1; /**< [ 27: 27](RO) PHY reset mode (PHY_RST_MODE). */
1192 uint32_t phy_ctrl : 6; /**< [ 26: 21](RO) PHY control width (PHY_CTRL_W). */
1193 uint32_t phy_stat : 6; /**< [ 20: 15](RO) PHY status width (PHY_STAT_W). */
1194 uint32_t latch_m : 1; /**< [ 14: 14](RO) Latch mode (LATCH_MODE). */
1195 uint32_t phy_type : 3; /**< [ 13: 11](RO) PHY interface type (PHY_INTERFACE_TYPE). */
1196 uint32_t return_err : 1; /**< [ 10: 10](RO) AMBA error response (RETURN_ERR_RESP). */
1197 uint32_t ahb_endian : 2; /**< [ 9: 8](RO) AHB bus endianness (AHB_ENDIANNESS). */
1198 uint32_t s_haddr : 1; /**< [ 7: 7](RO) AMBA slave address bus width (S_HADDR_WIDTH). */
1199 uint32_t m_haddr : 1; /**< [ 6: 6](RO) AMBA master address bus width (M_HADDR_WIDTH). */
1200 uint32_t s_hdata : 3; /**< [ 5: 3](RO) AMBA slave data width (S_HDATA_WIDTH). */
1201 uint32_t m_hdata : 3; /**< [ 2: 0](RO) AMBA master data width (M_HDATA_WIDTH). */
1202 #else /* Word 0 - Little Endian */
1203 uint32_t m_hdata : 3; /**< [ 2: 0](RO) AMBA master data width (M_HDATA_WIDTH). */
1204 uint32_t s_hdata : 3; /**< [ 5: 3](RO) AMBA slave data width (S_HDATA_WIDTH). */
1205 uint32_t m_haddr : 1; /**< [ 6: 6](RO) AMBA master address bus width (M_HADDR_WIDTH). */
1206 uint32_t s_haddr : 1; /**< [ 7: 7](RO) AMBA slave address bus width (S_HADDR_WIDTH). */
1207 uint32_t ahb_endian : 2; /**< [ 9: 8](RO) AHB bus endianness (AHB_ENDIANNESS). */
1208 uint32_t return_err : 1; /**< [ 10: 10](RO) AMBA error response (RETURN_ERR_RESP). */
1209 uint32_t phy_type : 3; /**< [ 13: 11](RO) PHY interface type (PHY_INTERFACE_TYPE). */
1210 uint32_t latch_m : 1; /**< [ 14: 14](RO) Latch mode (LATCH_MODE). */
1211 uint32_t phy_stat : 6; /**< [ 20: 15](RO) PHY status width (PHY_STAT_W). */
1212 uint32_t phy_ctrl : 6; /**< [ 26: 21](RO) PHY control width (PHY_CTRL_W). */
1213 uint32_t phy_rst : 1; /**< [ 27: 27](RO) PHY reset mode (PHY_RST_MODE). */
1214 uint32_t phy_data : 2; /**< [ 29: 28](RO) PHY data width (PHY_DATA_WIDTH). */
1215 uint32_t rx_buffer : 1; /**< [ 30: 30](RO) RX data buffer mode (RX_BUFFER_MODE). */
1216 uint32_t align_m : 1; /**< [ 31: 31](RO) RX data alignment mode (ALIGN_MODE). */
1217 #endif /* Word 0 - End */
1218 } s;
1219 /* struct bdk_satax_uahc_gbl_gparam1r_s cn; */
1220 };
1221 typedef union bdk_satax_uahc_gbl_gparam1r bdk_satax_uahc_gbl_gparam1r_t;
1222
1223 static inline uint64_t BDK_SATAX_UAHC_GBL_GPARAM1R(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_GPARAM1R(unsigned long a)1224 static inline uint64_t BDK_SATAX_UAHC_GBL_GPARAM1R(unsigned long a)
1225 {
1226 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1227 return 0x8100000000e8ll + 0x1000000000ll * ((a) & 0x1);
1228 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1229 return 0x8100000000e8ll + 0x1000000000ll * ((a) & 0x7);
1230 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1231 return 0x8100000000e8ll + 0x1000000000ll * ((a) & 0xf);
1232 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1233 return 0x8100000000e8ll + 0x1000000000ll * ((a) & 0x3);
1234 __bdk_csr_fatal("SATAX_UAHC_GBL_GPARAM1R", 1, a, 0, 0, 0);
1235 }
1236
1237 #define typedef_BDK_SATAX_UAHC_GBL_GPARAM1R(a) bdk_satax_uahc_gbl_gparam1r_t
1238 #define bustype_BDK_SATAX_UAHC_GBL_GPARAM1R(a) BDK_CSR_TYPE_NCB32b
1239 #define basename_BDK_SATAX_UAHC_GBL_GPARAM1R(a) "SATAX_UAHC_GBL_GPARAM1R"
1240 #define device_bar_BDK_SATAX_UAHC_GBL_GPARAM1R(a) 0x4 /* PF_BAR4 */
1241 #define busnum_BDK_SATAX_UAHC_GBL_GPARAM1R(a) (a)
1242 #define arguments_BDK_SATAX_UAHC_GBL_GPARAM1R(a) (a),-1,-1,-1
1243
1244 /**
1245 * Register (NCB32b) sata#_uahc_gbl_gparam2r
1246 *
1247 * SATA UAHC Global Parameter Register 2
1248 * Internal:
1249 * See DWC_ahsata databook v5.00.
1250 */
1251 union bdk_satax_uahc_gbl_gparam2r
1252 {
1253 uint32_t u;
1254 struct bdk_satax_uahc_gbl_gparam2r_s
1255 {
1256 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1257 uint32_t fbs_mem_mode : 1; /**< [ 31: 31](RO) Selects FBS memory read port type. */
1258 uint32_t rxoob_clk_units : 1; /**< [ 30: 30](RO) RX OOB clock frequency units. */
1259 uint32_t rxoob_clk_upper : 10; /**< [ 29: 20](RO) Upper bits of RX OOB clock frequency. */
1260 uint32_t bist_m : 1; /**< [ 19: 19](RO) BIST loopback checking depth (BIST_MODE). */
1261 uint32_t fbs_mem_s : 1; /**< [ 18: 18](RO) Context RAM memory location. */
1262 uint32_t fbs_pmpn : 2; /**< [ 17: 16](RO) Maximum number of port multiplier ports (FBS_PMPN_MAX). */
1263 uint32_t fbs_support : 1; /**< [ 15: 15](RO) FIS-based switching support (FBS_SUPPORT). */
1264 uint32_t dev_cp : 1; /**< [ 14: 14](RO) Cold presence detect (DEV_CP_DET). */
1265 uint32_t dev_mp : 1; /**< [ 13: 13](RO) Mechanical presence switch (DEV_MP_SWITCH). */
1266 uint32_t encode_m : 1; /**< [ 12: 12](RO) 8/10 bit encoding/decoding (ENCODE_MODE). */
1267 uint32_t rxoob_clk_m : 1; /**< [ 11: 11](RO) RX OOB clock mode (RXOOB_CLK_MODE). */
1268 uint32_t rx_oob_m : 1; /**< [ 10: 10](RO) RX OOB mode (RX_OOB_MODE). */
1269 uint32_t tx_oob_m : 1; /**< [ 9: 9](RO) TX OOB mode (TX_OOB_MODE). */
1270 uint32_t rxoob_clk : 9; /**< [ 8: 0](RO) RX OOB clock frequency (RXOOB_CLK). */
1271 #else /* Word 0 - Little Endian */
1272 uint32_t rxoob_clk : 9; /**< [ 8: 0](RO) RX OOB clock frequency (RXOOB_CLK). */
1273 uint32_t tx_oob_m : 1; /**< [ 9: 9](RO) TX OOB mode (TX_OOB_MODE). */
1274 uint32_t rx_oob_m : 1; /**< [ 10: 10](RO) RX OOB mode (RX_OOB_MODE). */
1275 uint32_t rxoob_clk_m : 1; /**< [ 11: 11](RO) RX OOB clock mode (RXOOB_CLK_MODE). */
1276 uint32_t encode_m : 1; /**< [ 12: 12](RO) 8/10 bit encoding/decoding (ENCODE_MODE). */
1277 uint32_t dev_mp : 1; /**< [ 13: 13](RO) Mechanical presence switch (DEV_MP_SWITCH). */
1278 uint32_t dev_cp : 1; /**< [ 14: 14](RO) Cold presence detect (DEV_CP_DET). */
1279 uint32_t fbs_support : 1; /**< [ 15: 15](RO) FIS-based switching support (FBS_SUPPORT). */
1280 uint32_t fbs_pmpn : 2; /**< [ 17: 16](RO) Maximum number of port multiplier ports (FBS_PMPN_MAX). */
1281 uint32_t fbs_mem_s : 1; /**< [ 18: 18](RO) Context RAM memory location. */
1282 uint32_t bist_m : 1; /**< [ 19: 19](RO) BIST loopback checking depth (BIST_MODE). */
1283 uint32_t rxoob_clk_upper : 10; /**< [ 29: 20](RO) Upper bits of RX OOB clock frequency. */
1284 uint32_t rxoob_clk_units : 1; /**< [ 30: 30](RO) RX OOB clock frequency units. */
1285 uint32_t fbs_mem_mode : 1; /**< [ 31: 31](RO) Selects FBS memory read port type. */
1286 #endif /* Word 0 - End */
1287 } s;
1288 struct bdk_satax_uahc_gbl_gparam2r_cn8
1289 {
1290 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1291 uint32_t reserved_31 : 1;
1292 uint32_t rxoob_clk_units : 1; /**< [ 30: 30](RO) RX OOB clock frequency units. */
1293 uint32_t rxoob_clk_upper : 10; /**< [ 29: 20](RO) Upper bits of RX OOB clock frequency. */
1294 uint32_t bist_m : 1; /**< [ 19: 19](RO) BIST loopback checking depth (BIST_MODE). */
1295 uint32_t fbs_mem_s : 1; /**< [ 18: 18](RO) Context RAM memory location. */
1296 uint32_t fbs_pmpn : 2; /**< [ 17: 16](RO) Maximum number of port multiplier ports (FBS_PMPN_MAX). */
1297 uint32_t fbs_support : 1; /**< [ 15: 15](RO) FIS-based switching support (FBS_SUPPORT). */
1298 uint32_t dev_cp : 1; /**< [ 14: 14](RO) Cold presence detect (DEV_CP_DET). */
1299 uint32_t dev_mp : 1; /**< [ 13: 13](RO) Mechanical presence switch (DEV_MP_SWITCH). */
1300 uint32_t encode_m : 1; /**< [ 12: 12](RO) 8/10 bit encoding/decoding (ENCODE_MODE). */
1301 uint32_t rxoob_clk_m : 1; /**< [ 11: 11](RO) RX OOB clock mode (RXOOB_CLK_MODE). */
1302 uint32_t rx_oob_m : 1; /**< [ 10: 10](RO) RX OOB mode (RX_OOB_MODE). */
1303 uint32_t tx_oob_m : 1; /**< [ 9: 9](RO) TX OOB mode (TX_OOB_MODE). */
1304 uint32_t rxoob_clk : 9; /**< [ 8: 0](RO) RX OOB clock frequency (RXOOB_CLK). */
1305 #else /* Word 0 - Little Endian */
1306 uint32_t rxoob_clk : 9; /**< [ 8: 0](RO) RX OOB clock frequency (RXOOB_CLK). */
1307 uint32_t tx_oob_m : 1; /**< [ 9: 9](RO) TX OOB mode (TX_OOB_MODE). */
1308 uint32_t rx_oob_m : 1; /**< [ 10: 10](RO) RX OOB mode (RX_OOB_MODE). */
1309 uint32_t rxoob_clk_m : 1; /**< [ 11: 11](RO) RX OOB clock mode (RXOOB_CLK_MODE). */
1310 uint32_t encode_m : 1; /**< [ 12: 12](RO) 8/10 bit encoding/decoding (ENCODE_MODE). */
1311 uint32_t dev_mp : 1; /**< [ 13: 13](RO) Mechanical presence switch (DEV_MP_SWITCH). */
1312 uint32_t dev_cp : 1; /**< [ 14: 14](RO) Cold presence detect (DEV_CP_DET). */
1313 uint32_t fbs_support : 1; /**< [ 15: 15](RO) FIS-based switching support (FBS_SUPPORT). */
1314 uint32_t fbs_pmpn : 2; /**< [ 17: 16](RO) Maximum number of port multiplier ports (FBS_PMPN_MAX). */
1315 uint32_t fbs_mem_s : 1; /**< [ 18: 18](RO) Context RAM memory location. */
1316 uint32_t bist_m : 1; /**< [ 19: 19](RO) BIST loopback checking depth (BIST_MODE). */
1317 uint32_t rxoob_clk_upper : 10; /**< [ 29: 20](RO) Upper bits of RX OOB clock frequency. */
1318 uint32_t rxoob_clk_units : 1; /**< [ 30: 30](RO) RX OOB clock frequency units. */
1319 uint32_t reserved_31 : 1;
1320 #endif /* Word 0 - End */
1321 } cn8;
1322 struct bdk_satax_uahc_gbl_gparam2r_cn9
1323 {
1324 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1325 uint32_t fbs_mem_mode : 1; /**< [ 31: 31](RO) Selects FBS memory read port type. */
1326 uint32_t rxoob_clk_units : 1; /**< [ 30: 30](RO) RX OOB clock frequency units. */
1327 uint32_t rxoob_clk_upper : 10; /**< [ 29: 20](RO) Upper bits of RX OOB clock frequency. */
1328 uint32_t bist_m : 1; /**< [ 19: 19](RO) BIST loopback checking depth (BIST_MODE). */
1329 uint32_t fbs_mem_s : 1; /**< [ 18: 18](RO) Context RAM memory location. */
1330 uint32_t fbs_pmpn : 2; /**< [ 17: 16](RO) FBS RAM depth FBS_RAM_DEPTH. */
1331 uint32_t fbs_support : 1; /**< [ 15: 15](RO) FIS-based switching support (FBS_SUPPORT). */
1332 uint32_t dev_cp : 1; /**< [ 14: 14](RO) Cold presence detect (DEV_CP_DET). */
1333 uint32_t dev_mp : 1; /**< [ 13: 13](RO) Mechanical presence switch (DEV_MP_SWITCH). */
1334 uint32_t encode_m : 1; /**< [ 12: 12](RO) 8/10 bit encoding/decoding (ENCODE_MODE). */
1335 uint32_t rxoob_clk_m : 1; /**< [ 11: 11](RO) RX OOB clock mode (RXOOB_CLK_MODE). */
1336 uint32_t rx_oob_m : 1; /**< [ 10: 10](RO) RX OOB mode (RX_OOB_MODE). */
1337 uint32_t tx_oob_m : 1; /**< [ 9: 9](RO) TX OOB mode (TX_OOB_MODE). */
1338 uint32_t rxoob_clk : 9; /**< [ 8: 0](RO) RX OOB clock frequency (RXOOB_CLK_FREQ). */
1339 #else /* Word 0 - Little Endian */
1340 uint32_t rxoob_clk : 9; /**< [ 8: 0](RO) RX OOB clock frequency (RXOOB_CLK_FREQ). */
1341 uint32_t tx_oob_m : 1; /**< [ 9: 9](RO) TX OOB mode (TX_OOB_MODE). */
1342 uint32_t rx_oob_m : 1; /**< [ 10: 10](RO) RX OOB mode (RX_OOB_MODE). */
1343 uint32_t rxoob_clk_m : 1; /**< [ 11: 11](RO) RX OOB clock mode (RXOOB_CLK_MODE). */
1344 uint32_t encode_m : 1; /**< [ 12: 12](RO) 8/10 bit encoding/decoding (ENCODE_MODE). */
1345 uint32_t dev_mp : 1; /**< [ 13: 13](RO) Mechanical presence switch (DEV_MP_SWITCH). */
1346 uint32_t dev_cp : 1; /**< [ 14: 14](RO) Cold presence detect (DEV_CP_DET). */
1347 uint32_t fbs_support : 1; /**< [ 15: 15](RO) FIS-based switching support (FBS_SUPPORT). */
1348 uint32_t fbs_pmpn : 2; /**< [ 17: 16](RO) FBS RAM depth FBS_RAM_DEPTH. */
1349 uint32_t fbs_mem_s : 1; /**< [ 18: 18](RO) Context RAM memory location. */
1350 uint32_t bist_m : 1; /**< [ 19: 19](RO) BIST loopback checking depth (BIST_MODE). */
1351 uint32_t rxoob_clk_upper : 10; /**< [ 29: 20](RO) Upper bits of RX OOB clock frequency. */
1352 uint32_t rxoob_clk_units : 1; /**< [ 30: 30](RO) RX OOB clock frequency units. */
1353 uint32_t fbs_mem_mode : 1; /**< [ 31: 31](RO) Selects FBS memory read port type. */
1354 #endif /* Word 0 - End */
1355 } cn9;
1356 };
1357 typedef union bdk_satax_uahc_gbl_gparam2r bdk_satax_uahc_gbl_gparam2r_t;
1358
1359 static inline uint64_t BDK_SATAX_UAHC_GBL_GPARAM2R(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_GPARAM2R(unsigned long a)1360 static inline uint64_t BDK_SATAX_UAHC_GBL_GPARAM2R(unsigned long a)
1361 {
1362 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1363 return 0x8100000000ecll + 0x1000000000ll * ((a) & 0x1);
1364 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1365 return 0x8100000000ecll + 0x1000000000ll * ((a) & 0x7);
1366 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1367 return 0x8100000000ecll + 0x1000000000ll * ((a) & 0xf);
1368 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1369 return 0x8100000000ecll + 0x1000000000ll * ((a) & 0x3);
1370 __bdk_csr_fatal("SATAX_UAHC_GBL_GPARAM2R", 1, a, 0, 0, 0);
1371 }
1372
1373 #define typedef_BDK_SATAX_UAHC_GBL_GPARAM2R(a) bdk_satax_uahc_gbl_gparam2r_t
1374 #define bustype_BDK_SATAX_UAHC_GBL_GPARAM2R(a) BDK_CSR_TYPE_NCB32b
1375 #define basename_BDK_SATAX_UAHC_GBL_GPARAM2R(a) "SATAX_UAHC_GBL_GPARAM2R"
1376 #define device_bar_BDK_SATAX_UAHC_GBL_GPARAM2R(a) 0x4 /* PF_BAR4 */
1377 #define busnum_BDK_SATAX_UAHC_GBL_GPARAM2R(a) (a)
1378 #define arguments_BDK_SATAX_UAHC_GBL_GPARAM2R(a) (a),-1,-1,-1
1379
1380 /**
1381 * Register (NCB32b) sata#_uahc_gbl_gparam3
1382 *
1383 * SATA UAHC Global Parameter 3 Register
1384 * Internal:
1385 * See DWC_ahsata databook v5.00.
1386 */
1387 union bdk_satax_uahc_gbl_gparam3
1388 {
1389 uint32_t u;
1390 struct bdk_satax_uahc_gbl_gparam3_s
1391 {
1392 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1393 uint32_t reserved_9_31 : 23;
1394 uint32_t mem_ap_support : 1; /**< [ 8: 8](RO) Enable address protection. */
1395 uint32_t phy_type : 5; /**< [ 7: 3](RO) PHY interface type. */
1396 uint32_t mem_ecc_cor_en : 1; /**< [ 2: 2](RO) Single-bit correction enable. */
1397 uint32_t mem_dp_type : 1; /**< [ 1: 1](RO) Data protection type. */
1398 uint32_t mem_dp_support : 1; /**< [ 0: 0](RO) Enable data protection. */
1399 #else /* Word 0 - Little Endian */
1400 uint32_t mem_dp_support : 1; /**< [ 0: 0](RO) Enable data protection. */
1401 uint32_t mem_dp_type : 1; /**< [ 1: 1](RO) Data protection type. */
1402 uint32_t mem_ecc_cor_en : 1; /**< [ 2: 2](RO) Single-bit correction enable. */
1403 uint32_t phy_type : 5; /**< [ 7: 3](RO) PHY interface type. */
1404 uint32_t mem_ap_support : 1; /**< [ 8: 8](RO) Enable address protection. */
1405 uint32_t reserved_9_31 : 23;
1406 #endif /* Word 0 - End */
1407 } s;
1408 /* struct bdk_satax_uahc_gbl_gparam3_s cn; */
1409 };
1410 typedef union bdk_satax_uahc_gbl_gparam3 bdk_satax_uahc_gbl_gparam3_t;
1411
1412 static inline uint64_t BDK_SATAX_UAHC_GBL_GPARAM3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_GPARAM3(unsigned long a)1413 static inline uint64_t BDK_SATAX_UAHC_GBL_GPARAM3(unsigned long a)
1414 {
1415 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1416 return 0x8100000000dcll + 0x1000000000ll * ((a) & 0x3);
1417 __bdk_csr_fatal("SATAX_UAHC_GBL_GPARAM3", 1, a, 0, 0, 0);
1418 }
1419
1420 #define typedef_BDK_SATAX_UAHC_GBL_GPARAM3(a) bdk_satax_uahc_gbl_gparam3_t
1421 #define bustype_BDK_SATAX_UAHC_GBL_GPARAM3(a) BDK_CSR_TYPE_NCB32b
1422 #define basename_BDK_SATAX_UAHC_GBL_GPARAM3(a) "SATAX_UAHC_GBL_GPARAM3"
1423 #define device_bar_BDK_SATAX_UAHC_GBL_GPARAM3(a) 0x4 /* PF_BAR4 */
1424 #define busnum_BDK_SATAX_UAHC_GBL_GPARAM3(a) (a)
1425 #define arguments_BDK_SATAX_UAHC_GBL_GPARAM3(a) (a),-1,-1,-1
1426
1427 /**
1428 * Register (NCB32b) sata#_uahc_gbl_idr
1429 *
1430 * SATA UAHC ID Register
1431 * Internal:
1432 * See DWC_ahsata databook v5.00.
1433 */
1434 union bdk_satax_uahc_gbl_idr
1435 {
1436 uint32_t u;
1437 struct bdk_satax_uahc_gbl_idr_s
1438 {
1439 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1440 uint32_t id : 32; /**< [ 31: 0](RO) Core ID. */
1441 #else /* Word 0 - Little Endian */
1442 uint32_t id : 32; /**< [ 31: 0](RO) Core ID. */
1443 #endif /* Word 0 - End */
1444 } s;
1445 /* struct bdk_satax_uahc_gbl_idr_s cn; */
1446 };
1447 typedef union bdk_satax_uahc_gbl_idr bdk_satax_uahc_gbl_idr_t;
1448
1449 static inline uint64_t BDK_SATAX_UAHC_GBL_IDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_IDR(unsigned long a)1450 static inline uint64_t BDK_SATAX_UAHC_GBL_IDR(unsigned long a)
1451 {
1452 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1453 return 0x8100000000fcll + 0x1000000000ll * ((a) & 0x1);
1454 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1455 return 0x8100000000fcll + 0x1000000000ll * ((a) & 0x7);
1456 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1457 return 0x8100000000fcll + 0x1000000000ll * ((a) & 0xf);
1458 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1459 return 0x8100000000fcll + 0x1000000000ll * ((a) & 0x3);
1460 __bdk_csr_fatal("SATAX_UAHC_GBL_IDR", 1, a, 0, 0, 0);
1461 }
1462
1463 #define typedef_BDK_SATAX_UAHC_GBL_IDR(a) bdk_satax_uahc_gbl_idr_t
1464 #define bustype_BDK_SATAX_UAHC_GBL_IDR(a) BDK_CSR_TYPE_NCB32b
1465 #define basename_BDK_SATAX_UAHC_GBL_IDR(a) "SATAX_UAHC_GBL_IDR"
1466 #define device_bar_BDK_SATAX_UAHC_GBL_IDR(a) 0x4 /* PF_BAR4 */
1467 #define busnum_BDK_SATAX_UAHC_GBL_IDR(a) (a)
1468 #define arguments_BDK_SATAX_UAHC_GBL_IDR(a) (a),-1,-1,-1
1469
1470 /**
1471 * Register (NCB32b) sata#_uahc_gbl_is
1472 *
1473 * SATA AHCI Interrupt Status Register
1474 * This register indicates which of the ports within the SATA core have an interrupt
1475 * pending and require service. This register is reset on global reset (GHC.HR=1).
1476 */
1477 union bdk_satax_uahc_gbl_is
1478 {
1479 uint32_t u;
1480 struct bdk_satax_uahc_gbl_is_s
1481 {
1482 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1483 uint32_t reserved_2_31 : 30;
1484 uint32_t ips : 2; /**< [ 1: 0](R/W1C/H) Interrupt pending status. */
1485 #else /* Word 0 - Little Endian */
1486 uint32_t ips : 2; /**< [ 1: 0](R/W1C/H) Interrupt pending status. */
1487 uint32_t reserved_2_31 : 30;
1488 #endif /* Word 0 - End */
1489 } s;
1490 /* struct bdk_satax_uahc_gbl_is_s cn; */
1491 };
1492 typedef union bdk_satax_uahc_gbl_is bdk_satax_uahc_gbl_is_t;
1493
1494 static inline uint64_t BDK_SATAX_UAHC_GBL_IS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_IS(unsigned long a)1495 static inline uint64_t BDK_SATAX_UAHC_GBL_IS(unsigned long a)
1496 {
1497 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1498 return 0x810000000008ll + 0x1000000000ll * ((a) & 0x1);
1499 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1500 return 0x810000000008ll + 0x1000000000ll * ((a) & 0x7);
1501 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1502 return 0x810000000008ll + 0x1000000000ll * ((a) & 0xf);
1503 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1504 return 0x810000000008ll + 0x1000000000ll * ((a) & 0x3);
1505 __bdk_csr_fatal("SATAX_UAHC_GBL_IS", 1, a, 0, 0, 0);
1506 }
1507
1508 #define typedef_BDK_SATAX_UAHC_GBL_IS(a) bdk_satax_uahc_gbl_is_t
1509 #define bustype_BDK_SATAX_UAHC_GBL_IS(a) BDK_CSR_TYPE_NCB32b
1510 #define basename_BDK_SATAX_UAHC_GBL_IS(a) "SATAX_UAHC_GBL_IS"
1511 #define device_bar_BDK_SATAX_UAHC_GBL_IS(a) 0x4 /* PF_BAR4 */
1512 #define busnum_BDK_SATAX_UAHC_GBL_IS(a) (a)
1513 #define arguments_BDK_SATAX_UAHC_GBL_IS(a) (a),-1,-1,-1
1514
1515 /**
1516 * Register (NCB32b) sata#_uahc_gbl_oobr
1517 *
1518 * SATA UAHC OOB Register
1519 * This register is shared between SATA ports. Before accessing this
1520 * register, first select the required port by writing the port number
1521 * to the SATA()_UAHC_GBL_TESTR[PSEL] field.
1522 *
1523 * Internal:
1524 * See DWC_ahsata databook v5.00.
1525 */
1526 union bdk_satax_uahc_gbl_oobr
1527 {
1528 uint32_t u;
1529 struct bdk_satax_uahc_gbl_oobr_s
1530 {
1531 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1532 uint32_t we : 1; /**< [ 31: 31](R/W/H) Write enable. */
1533 uint32_t cwmin : 7; /**< [ 30: 24](R/W/H) COMWAKE minimum value. Writable only if WE is set. */
1534 uint32_t cwmax : 8; /**< [ 23: 16](R/W/H) COMWAKE maximum value. Writable only if WE is set. */
1535 uint32_t cimin : 8; /**< [ 15: 8](R/W/H) COMINIT minimum value. Writable only if WE is set. */
1536 uint32_t cimax : 8; /**< [ 7: 0](R/W/H) COMINIT maximum value. Writable only if WE is set. */
1537 #else /* Word 0 - Little Endian */
1538 uint32_t cimax : 8; /**< [ 7: 0](R/W/H) COMINIT maximum value. Writable only if WE is set. */
1539 uint32_t cimin : 8; /**< [ 15: 8](R/W/H) COMINIT minimum value. Writable only if WE is set. */
1540 uint32_t cwmax : 8; /**< [ 23: 16](R/W/H) COMWAKE maximum value. Writable only if WE is set. */
1541 uint32_t cwmin : 7; /**< [ 30: 24](R/W/H) COMWAKE minimum value. Writable only if WE is set. */
1542 uint32_t we : 1; /**< [ 31: 31](R/W/H) Write enable. */
1543 #endif /* Word 0 - End */
1544 } s;
1545 /* struct bdk_satax_uahc_gbl_oobr_s cn; */
1546 };
1547 typedef union bdk_satax_uahc_gbl_oobr bdk_satax_uahc_gbl_oobr_t;
1548
1549 static inline uint64_t BDK_SATAX_UAHC_GBL_OOBR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_OOBR(unsigned long a)1550 static inline uint64_t BDK_SATAX_UAHC_GBL_OOBR(unsigned long a)
1551 {
1552 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1553 return 0x8100000000bcll + 0x1000000000ll * ((a) & 0x1);
1554 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1555 return 0x8100000000bcll + 0x1000000000ll * ((a) & 0x7);
1556 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1557 return 0x8100000000bcll + 0x1000000000ll * ((a) & 0xf);
1558 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1559 return 0x8100000000bcll + 0x1000000000ll * ((a) & 0x3);
1560 __bdk_csr_fatal("SATAX_UAHC_GBL_OOBR", 1, a, 0, 0, 0);
1561 }
1562
1563 #define typedef_BDK_SATAX_UAHC_GBL_OOBR(a) bdk_satax_uahc_gbl_oobr_t
1564 #define bustype_BDK_SATAX_UAHC_GBL_OOBR(a) BDK_CSR_TYPE_NCB32b
1565 #define basename_BDK_SATAX_UAHC_GBL_OOBR(a) "SATAX_UAHC_GBL_OOBR"
1566 #define device_bar_BDK_SATAX_UAHC_GBL_OOBR(a) 0x4 /* PF_BAR4 */
1567 #define busnum_BDK_SATAX_UAHC_GBL_OOBR(a) (a)
1568 #define arguments_BDK_SATAX_UAHC_GBL_OOBR(a) (a),-1,-1,-1
1569
1570 /**
1571 * Register (NCB32b) sata#_uahc_gbl_pi
1572 *
1573 * SATA AHCI Ports Implemented Register
1574 * This register indicates which ports are exposed by the SATA core and are available
1575 * for the software to use.
1576 */
1577 union bdk_satax_uahc_gbl_pi
1578 {
1579 uint32_t u;
1580 struct bdk_satax_uahc_gbl_pi_s
1581 {
1582 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1583 uint32_t reserved_1_31 : 31;
1584 uint32_t pi : 1; /**< [ 0: 0](R/W) Number of ports implemented. This field is one-time writable, then becomes read-only. */
1585 #else /* Word 0 - Little Endian */
1586 uint32_t pi : 1; /**< [ 0: 0](R/W) Number of ports implemented. This field is one-time writable, then becomes read-only. */
1587 uint32_t reserved_1_31 : 31;
1588 #endif /* Word 0 - End */
1589 } s;
1590 /* struct bdk_satax_uahc_gbl_pi_s cn; */
1591 };
1592 typedef union bdk_satax_uahc_gbl_pi bdk_satax_uahc_gbl_pi_t;
1593
1594 static inline uint64_t BDK_SATAX_UAHC_GBL_PI(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_PI(unsigned long a)1595 static inline uint64_t BDK_SATAX_UAHC_GBL_PI(unsigned long a)
1596 {
1597 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1598 return 0x81000000000cll + 0x1000000000ll * ((a) & 0x1);
1599 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1600 return 0x81000000000cll + 0x1000000000ll * ((a) & 0x7);
1601 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1602 return 0x81000000000cll + 0x1000000000ll * ((a) & 0xf);
1603 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1604 return 0x81000000000cll + 0x1000000000ll * ((a) & 0x3);
1605 __bdk_csr_fatal("SATAX_UAHC_GBL_PI", 1, a, 0, 0, 0);
1606 }
1607
1608 #define typedef_BDK_SATAX_UAHC_GBL_PI(a) bdk_satax_uahc_gbl_pi_t
1609 #define bustype_BDK_SATAX_UAHC_GBL_PI(a) BDK_CSR_TYPE_NCB32b
1610 #define basename_BDK_SATAX_UAHC_GBL_PI(a) "SATAX_UAHC_GBL_PI"
1611 #define device_bar_BDK_SATAX_UAHC_GBL_PI(a) 0x4 /* PF_BAR4 */
1612 #define busnum_BDK_SATAX_UAHC_GBL_PI(a) (a)
1613 #define arguments_BDK_SATAX_UAHC_GBL_PI(a) (a),-1,-1,-1
1614
1615 /**
1616 * Register (NCB32b) sata#_uahc_gbl_pparamr
1617 *
1618 * SATA UAHC Port Parameter Register
1619 * Port is selected by the SATA()_UAHC_GBL_TESTR[PSEL] field.
1620 * Internal:
1621 * See DWC_ahsata databook v5.00.
1622 */
1623 union bdk_satax_uahc_gbl_pparamr
1624 {
1625 uint32_t u;
1626 struct bdk_satax_uahc_gbl_pparamr_s
1627 {
1628 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1629 uint32_t reserved_12_31 : 20;
1630 uint32_t tx_mem_m : 1; /**< [ 11: 11](RO) TX FIFO memory read port type (Pn_TX_MEM_MODE). */
1631 uint32_t tx_mem_s : 1; /**< [ 10: 10](RO) TX FIFO memory type (Pn_TX_MEM_SELECT). */
1632 uint32_t rx_mem_m : 1; /**< [ 9: 9](RO) RX FIFO memory read port type (Pn_RX_MEM_MODE). */
1633 uint32_t rx_mem_s : 1; /**< [ 8: 8](RO) RX FIFO memory type (Pn_RX_MEM_SELECT). */
1634 uint32_t txfifo_depth : 4; /**< [ 7: 4](RO) TX FIFO depth in FIFO words. */
1635 uint32_t rxfifo_depth : 4; /**< [ 3: 0](RO) RX FIFO depth in FIFO words. */
1636 #else /* Word 0 - Little Endian */
1637 uint32_t rxfifo_depth : 4; /**< [ 3: 0](RO) RX FIFO depth in FIFO words. */
1638 uint32_t txfifo_depth : 4; /**< [ 7: 4](RO) TX FIFO depth in FIFO words. */
1639 uint32_t rx_mem_s : 1; /**< [ 8: 8](RO) RX FIFO memory type (Pn_RX_MEM_SELECT). */
1640 uint32_t rx_mem_m : 1; /**< [ 9: 9](RO) RX FIFO memory read port type (Pn_RX_MEM_MODE). */
1641 uint32_t tx_mem_s : 1; /**< [ 10: 10](RO) TX FIFO memory type (Pn_TX_MEM_SELECT). */
1642 uint32_t tx_mem_m : 1; /**< [ 11: 11](RO) TX FIFO memory read port type (Pn_TX_MEM_MODE). */
1643 uint32_t reserved_12_31 : 20;
1644 #endif /* Word 0 - End */
1645 } s;
1646 /* struct bdk_satax_uahc_gbl_pparamr_s cn; */
1647 };
1648 typedef union bdk_satax_uahc_gbl_pparamr bdk_satax_uahc_gbl_pparamr_t;
1649
1650 static inline uint64_t BDK_SATAX_UAHC_GBL_PPARAMR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_PPARAMR(unsigned long a)1651 static inline uint64_t BDK_SATAX_UAHC_GBL_PPARAMR(unsigned long a)
1652 {
1653 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1654 return 0x8100000000f0ll + 0x1000000000ll * ((a) & 0x1);
1655 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1656 return 0x8100000000f0ll + 0x1000000000ll * ((a) & 0x7);
1657 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1658 return 0x8100000000f0ll + 0x1000000000ll * ((a) & 0xf);
1659 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1660 return 0x8100000000f0ll + 0x1000000000ll * ((a) & 0x3);
1661 __bdk_csr_fatal("SATAX_UAHC_GBL_PPARAMR", 1, a, 0, 0, 0);
1662 }
1663
1664 #define typedef_BDK_SATAX_UAHC_GBL_PPARAMR(a) bdk_satax_uahc_gbl_pparamr_t
1665 #define bustype_BDK_SATAX_UAHC_GBL_PPARAMR(a) BDK_CSR_TYPE_NCB32b
1666 #define basename_BDK_SATAX_UAHC_GBL_PPARAMR(a) "SATAX_UAHC_GBL_PPARAMR"
1667 #define device_bar_BDK_SATAX_UAHC_GBL_PPARAMR(a) 0x4 /* PF_BAR4 */
1668 #define busnum_BDK_SATAX_UAHC_GBL_PPARAMR(a) (a)
1669 #define arguments_BDK_SATAX_UAHC_GBL_PPARAMR(a) (a),-1,-1,-1
1670
1671 /**
1672 * Register (NCB32b) sata#_uahc_gbl_testr
1673 *
1674 * SATA UAHC Test Register
1675 * Internal:
1676 * See DWC_ahsata databook v5.00.
1677 */
1678 union bdk_satax_uahc_gbl_testr
1679 {
1680 uint32_t u;
1681 struct bdk_satax_uahc_gbl_testr_s
1682 {
1683 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1684 uint32_t reserved_25_31 : 7;
1685 uint32_t bsel : 1; /**< [ 24: 24](R/W) Bank select. Always select 0 for BIST registers. */
1686 uint32_t reserved_19_23 : 5;
1687 uint32_t psel : 3; /**< [ 18: 16](R/W) Port select. */
1688 uint32_t reserved_1_15 : 15;
1689 uint32_t test_if : 1; /**< [ 0: 0](R/W) Test interface. */
1690 #else /* Word 0 - Little Endian */
1691 uint32_t test_if : 1; /**< [ 0: 0](R/W) Test interface. */
1692 uint32_t reserved_1_15 : 15;
1693 uint32_t psel : 3; /**< [ 18: 16](R/W) Port select. */
1694 uint32_t reserved_19_23 : 5;
1695 uint32_t bsel : 1; /**< [ 24: 24](R/W) Bank select. Always select 0 for BIST registers. */
1696 uint32_t reserved_25_31 : 7;
1697 #endif /* Word 0 - End */
1698 } s;
1699 struct bdk_satax_uahc_gbl_testr_cn8
1700 {
1701 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1702 uint32_t reserved_19_31 : 13;
1703 uint32_t psel : 3; /**< [ 18: 16](R/W) Port select. */
1704 uint32_t reserved_1_15 : 15;
1705 uint32_t test_if : 1; /**< [ 0: 0](R/W) Test interface. */
1706 #else /* Word 0 - Little Endian */
1707 uint32_t test_if : 1; /**< [ 0: 0](R/W) Test interface. */
1708 uint32_t reserved_1_15 : 15;
1709 uint32_t psel : 3; /**< [ 18: 16](R/W) Port select. */
1710 uint32_t reserved_19_31 : 13;
1711 #endif /* Word 0 - End */
1712 } cn8;
1713 /* struct bdk_satax_uahc_gbl_testr_s cn9; */
1714 };
1715 typedef union bdk_satax_uahc_gbl_testr bdk_satax_uahc_gbl_testr_t;
1716
1717 static inline uint64_t BDK_SATAX_UAHC_GBL_TESTR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_TESTR(unsigned long a)1718 static inline uint64_t BDK_SATAX_UAHC_GBL_TESTR(unsigned long a)
1719 {
1720 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1721 return 0x8100000000f4ll + 0x1000000000ll * ((a) & 0x1);
1722 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1723 return 0x8100000000f4ll + 0x1000000000ll * ((a) & 0x7);
1724 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1725 return 0x8100000000f4ll + 0x1000000000ll * ((a) & 0xf);
1726 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1727 return 0x8100000000f4ll + 0x1000000000ll * ((a) & 0x3);
1728 __bdk_csr_fatal("SATAX_UAHC_GBL_TESTR", 1, a, 0, 0, 0);
1729 }
1730
1731 #define typedef_BDK_SATAX_UAHC_GBL_TESTR(a) bdk_satax_uahc_gbl_testr_t
1732 #define bustype_BDK_SATAX_UAHC_GBL_TESTR(a) BDK_CSR_TYPE_NCB32b
1733 #define basename_BDK_SATAX_UAHC_GBL_TESTR(a) "SATAX_UAHC_GBL_TESTR"
1734 #define device_bar_BDK_SATAX_UAHC_GBL_TESTR(a) 0x4 /* PF_BAR4 */
1735 #define busnum_BDK_SATAX_UAHC_GBL_TESTR(a) (a)
1736 #define arguments_BDK_SATAX_UAHC_GBL_TESTR(a) (a),-1,-1,-1
1737
1738 /**
1739 * Register (NCB32b) sata#_uahc_gbl_timer1ms
1740 *
1741 * SATA UAHC Timer 1ms Register
1742 * Internal:
1743 * See DWC_ahsata databook v5.00.
1744 */
1745 union bdk_satax_uahc_gbl_timer1ms
1746 {
1747 uint32_t u;
1748 struct bdk_satax_uahc_gbl_timer1ms_s
1749 {
1750 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1751 uint32_t reserved_20_31 : 12;
1752 uint32_t timv : 20; /**< [ 19: 0](R/W) 1ms timer value. Writable only when SATA()_UAHC_GBL_CCC_CTL[EN] = 0. */
1753 #else /* Word 0 - Little Endian */
1754 uint32_t timv : 20; /**< [ 19: 0](R/W) 1ms timer value. Writable only when SATA()_UAHC_GBL_CCC_CTL[EN] = 0. */
1755 uint32_t reserved_20_31 : 12;
1756 #endif /* Word 0 - End */
1757 } s;
1758 /* struct bdk_satax_uahc_gbl_timer1ms_s cn; */
1759 };
1760 typedef union bdk_satax_uahc_gbl_timer1ms bdk_satax_uahc_gbl_timer1ms_t;
1761
1762 static inline uint64_t BDK_SATAX_UAHC_GBL_TIMER1MS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_TIMER1MS(unsigned long a)1763 static inline uint64_t BDK_SATAX_UAHC_GBL_TIMER1MS(unsigned long a)
1764 {
1765 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1766 return 0x8100000000e0ll + 0x1000000000ll * ((a) & 0x1);
1767 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1768 return 0x8100000000e0ll + 0x1000000000ll * ((a) & 0x7);
1769 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1770 return 0x8100000000e0ll + 0x1000000000ll * ((a) & 0xf);
1771 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1772 return 0x8100000000e0ll + 0x1000000000ll * ((a) & 0x3);
1773 __bdk_csr_fatal("SATAX_UAHC_GBL_TIMER1MS", 1, a, 0, 0, 0);
1774 }
1775
1776 #define typedef_BDK_SATAX_UAHC_GBL_TIMER1MS(a) bdk_satax_uahc_gbl_timer1ms_t
1777 #define bustype_BDK_SATAX_UAHC_GBL_TIMER1MS(a) BDK_CSR_TYPE_NCB32b
1778 #define basename_BDK_SATAX_UAHC_GBL_TIMER1MS(a) "SATAX_UAHC_GBL_TIMER1MS"
1779 #define device_bar_BDK_SATAX_UAHC_GBL_TIMER1MS(a) 0x4 /* PF_BAR4 */
1780 #define busnum_BDK_SATAX_UAHC_GBL_TIMER1MS(a) (a)
1781 #define arguments_BDK_SATAX_UAHC_GBL_TIMER1MS(a) (a),-1,-1,-1
1782
1783 /**
1784 * Register (NCB32b) sata#_uahc_gbl_versionr
1785 *
1786 * SATA UAHC Version Register
1787 * Internal:
1788 * See DWC_ahsata databook v5.00.
1789 */
1790 union bdk_satax_uahc_gbl_versionr
1791 {
1792 uint32_t u;
1793 struct bdk_satax_uahc_gbl_versionr_s
1794 {
1795 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1796 uint32_t ver : 32; /**< [ 31: 0](RO) SATA IP version number. */
1797 #else /* Word 0 - Little Endian */
1798 uint32_t ver : 32; /**< [ 31: 0](RO) SATA IP version number. */
1799 #endif /* Word 0 - End */
1800 } s;
1801 /* struct bdk_satax_uahc_gbl_versionr_s cn; */
1802 };
1803 typedef union bdk_satax_uahc_gbl_versionr bdk_satax_uahc_gbl_versionr_t;
1804
1805 static inline uint64_t BDK_SATAX_UAHC_GBL_VERSIONR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_VERSIONR(unsigned long a)1806 static inline uint64_t BDK_SATAX_UAHC_GBL_VERSIONR(unsigned long a)
1807 {
1808 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1809 return 0x8100000000f8ll + 0x1000000000ll * ((a) & 0x1);
1810 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1811 return 0x8100000000f8ll + 0x1000000000ll * ((a) & 0x7);
1812 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1813 return 0x8100000000f8ll + 0x1000000000ll * ((a) & 0xf);
1814 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1815 return 0x8100000000f8ll + 0x1000000000ll * ((a) & 0x3);
1816 __bdk_csr_fatal("SATAX_UAHC_GBL_VERSIONR", 1, a, 0, 0, 0);
1817 }
1818
1819 #define typedef_BDK_SATAX_UAHC_GBL_VERSIONR(a) bdk_satax_uahc_gbl_versionr_t
1820 #define bustype_BDK_SATAX_UAHC_GBL_VERSIONR(a) BDK_CSR_TYPE_NCB32b
1821 #define basename_BDK_SATAX_UAHC_GBL_VERSIONR(a) "SATAX_UAHC_GBL_VERSIONR"
1822 #define device_bar_BDK_SATAX_UAHC_GBL_VERSIONR(a) 0x4 /* PF_BAR4 */
1823 #define busnum_BDK_SATAX_UAHC_GBL_VERSIONR(a) (a)
1824 #define arguments_BDK_SATAX_UAHC_GBL_VERSIONR(a) (a),-1,-1,-1
1825
1826 /**
1827 * Register (NCB32b) sata#_uahc_gbl_vs
1828 *
1829 * SATA AHCI Version Register
1830 * This register indicates the major and minor version of the AHCI specification that
1831 * the SATA core supports.
1832 */
1833 union bdk_satax_uahc_gbl_vs
1834 {
1835 uint32_t u;
1836 struct bdk_satax_uahc_gbl_vs_s
1837 {
1838 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1839 uint32_t mjr : 16; /**< [ 31: 16](RO) Major version number. */
1840 uint32_t mnr : 16; /**< [ 15: 0](RO) Minor version number. No DevSleep support. */
1841 #else /* Word 0 - Little Endian */
1842 uint32_t mnr : 16; /**< [ 15: 0](RO) Minor version number. No DevSleep support. */
1843 uint32_t mjr : 16; /**< [ 31: 16](RO) Major version number. */
1844 #endif /* Word 0 - End */
1845 } s;
1846 /* struct bdk_satax_uahc_gbl_vs_s cn8; */
1847 struct bdk_satax_uahc_gbl_vs_cn9
1848 {
1849 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1850 uint32_t mjr : 16; /**< [ 31: 16](RO) Major version number. */
1851 uint32_t mnr : 16; /**< [ 15: 0](RO) Minor version number. DevSleep is supported. */
1852 #else /* Word 0 - Little Endian */
1853 uint32_t mnr : 16; /**< [ 15: 0](RO) Minor version number. DevSleep is supported. */
1854 uint32_t mjr : 16; /**< [ 31: 16](RO) Major version number. */
1855 #endif /* Word 0 - End */
1856 } cn9;
1857 };
1858 typedef union bdk_satax_uahc_gbl_vs bdk_satax_uahc_gbl_vs_t;
1859
1860 static inline uint64_t BDK_SATAX_UAHC_GBL_VS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_GBL_VS(unsigned long a)1861 static inline uint64_t BDK_SATAX_UAHC_GBL_VS(unsigned long a)
1862 {
1863 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1864 return 0x810000000010ll + 0x1000000000ll * ((a) & 0x1);
1865 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1866 return 0x810000000010ll + 0x1000000000ll * ((a) & 0x7);
1867 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1868 return 0x810000000010ll + 0x1000000000ll * ((a) & 0xf);
1869 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1870 return 0x810000000010ll + 0x1000000000ll * ((a) & 0x3);
1871 __bdk_csr_fatal("SATAX_UAHC_GBL_VS", 1, a, 0, 0, 0);
1872 }
1873
1874 #define typedef_BDK_SATAX_UAHC_GBL_VS(a) bdk_satax_uahc_gbl_vs_t
1875 #define bustype_BDK_SATAX_UAHC_GBL_VS(a) BDK_CSR_TYPE_NCB32b
1876 #define basename_BDK_SATAX_UAHC_GBL_VS(a) "SATAX_UAHC_GBL_VS"
1877 #define device_bar_BDK_SATAX_UAHC_GBL_VS(a) 0x4 /* PF_BAR4 */
1878 #define busnum_BDK_SATAX_UAHC_GBL_VS(a) (a)
1879 #define arguments_BDK_SATAX_UAHC_GBL_VS(a) (a),-1,-1,-1
1880
1881 /**
1882 * Register (NCB32b) sata#_uahc_p0_ci
1883 *
1884 * SATA UAHC Command Issue Registers
1885 * Internal:
1886 * See DWC_ahsata databook v5.00.
1887 */
1888 union bdk_satax_uahc_p0_ci
1889 {
1890 uint32_t u;
1891 struct bdk_satax_uahc_p0_ci_s
1892 {
1893 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1894 uint32_t ci : 32; /**< [ 31: 0](R/W1S/H) Command issued. */
1895 #else /* Word 0 - Little Endian */
1896 uint32_t ci : 32; /**< [ 31: 0](R/W1S/H) Command issued. */
1897 #endif /* Word 0 - End */
1898 } s;
1899 /* struct bdk_satax_uahc_p0_ci_s cn; */
1900 };
1901 typedef union bdk_satax_uahc_p0_ci bdk_satax_uahc_p0_ci_t;
1902
1903 static inline uint64_t BDK_SATAX_UAHC_P0_CI(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_CI(unsigned long a)1904 static inline uint64_t BDK_SATAX_UAHC_P0_CI(unsigned long a)
1905 {
1906 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1907 return 0x810000000138ll + 0x1000000000ll * ((a) & 0x1);
1908 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1909 return 0x810000000138ll + 0x1000000000ll * ((a) & 0x7);
1910 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1911 return 0x810000000138ll + 0x1000000000ll * ((a) & 0xf);
1912 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1913 return 0x810000000138ll + 0x1000000000ll * ((a) & 0x3);
1914 __bdk_csr_fatal("SATAX_UAHC_P0_CI", 1, a, 0, 0, 0);
1915 }
1916
1917 #define typedef_BDK_SATAX_UAHC_P0_CI(a) bdk_satax_uahc_p0_ci_t
1918 #define bustype_BDK_SATAX_UAHC_P0_CI(a) BDK_CSR_TYPE_NCB32b
1919 #define basename_BDK_SATAX_UAHC_P0_CI(a) "SATAX_UAHC_P0_CI"
1920 #define device_bar_BDK_SATAX_UAHC_P0_CI(a) 0x4 /* PF_BAR4 */
1921 #define busnum_BDK_SATAX_UAHC_P0_CI(a) (a)
1922 #define arguments_BDK_SATAX_UAHC_P0_CI(a) (a),-1,-1,-1
1923
1924 /**
1925 * Register (NCB) sata#_uahc_p0_clb
1926 *
1927 * SATA UAHC Command-List Base-Address Registers
1928 * Internal:
1929 * See DWC_ahsata databook v5.00.
1930 */
1931 union bdk_satax_uahc_p0_clb
1932 {
1933 uint64_t u;
1934 struct bdk_satax_uahc_p0_clb_s
1935 {
1936 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1937 uint64_t clb : 54; /**< [ 63: 10](R/W) Command-list base address. */
1938 uint64_t reserved_0_9 : 10;
1939 #else /* Word 0 - Little Endian */
1940 uint64_t reserved_0_9 : 10;
1941 uint64_t clb : 54; /**< [ 63: 10](R/W) Command-list base address. */
1942 #endif /* Word 0 - End */
1943 } s;
1944 /* struct bdk_satax_uahc_p0_clb_s cn; */
1945 };
1946 typedef union bdk_satax_uahc_p0_clb bdk_satax_uahc_p0_clb_t;
1947
1948 static inline uint64_t BDK_SATAX_UAHC_P0_CLB(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_CLB(unsigned long a)1949 static inline uint64_t BDK_SATAX_UAHC_P0_CLB(unsigned long a)
1950 {
1951 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1952 return 0x810000000100ll + 0x1000000000ll * ((a) & 0x1);
1953 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
1954 return 0x810000000100ll + 0x1000000000ll * ((a) & 0x7);
1955 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
1956 return 0x810000000100ll + 0x1000000000ll * ((a) & 0xf);
1957 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
1958 return 0x810000000100ll + 0x1000000000ll * ((a) & 0x3);
1959 __bdk_csr_fatal("SATAX_UAHC_P0_CLB", 1, a, 0, 0, 0);
1960 }
1961
1962 #define typedef_BDK_SATAX_UAHC_P0_CLB(a) bdk_satax_uahc_p0_clb_t
1963 #define bustype_BDK_SATAX_UAHC_P0_CLB(a) BDK_CSR_TYPE_NCB
1964 #define basename_BDK_SATAX_UAHC_P0_CLB(a) "SATAX_UAHC_P0_CLB"
1965 #define device_bar_BDK_SATAX_UAHC_P0_CLB(a) 0x4 /* PF_BAR4 */
1966 #define busnum_BDK_SATAX_UAHC_P0_CLB(a) (a)
1967 #define arguments_BDK_SATAX_UAHC_P0_CLB(a) (a),-1,-1,-1
1968
1969 /**
1970 * Register (NCB32b) sata#_uahc_p0_cmd
1971 *
1972 * SATA UAHC Command Registers
1973 * Internal:
1974 * See DWC_ahsata databook v5.00.
1975 */
1976 union bdk_satax_uahc_p0_cmd
1977 {
1978 uint32_t u;
1979 struct bdk_satax_uahc_p0_cmd_s
1980 {
1981 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1982 uint32_t icc : 4; /**< [ 31: 28](R/W) Interface communication control. */
1983 uint32_t asp : 1; /**< [ 27: 27](R/W) Aggressive slumber/partial. */
1984 uint32_t alpe : 1; /**< [ 26: 26](R/W) Aggressive link-power-management enable. */
1985 uint32_t dlae : 1; /**< [ 25: 25](R/W) Drive LED on ATAPI enable. */
1986 uint32_t atapi : 1; /**< [ 24: 24](R/W) Device is ATAPI. */
1987 uint32_t apste : 1; /**< [ 23: 23](R/W) Automatic partial to slumber transitions enable. */
1988 uint32_t fbscp : 1; /**< [ 22: 22](R/W) FIS-based switching capable port. Write-once. */
1989 uint32_t esp : 1; /**< [ 21: 21](R/W) External SATA port. Write-once. */
1990 uint32_t cpd : 1; /**< [ 20: 20](R/W) Cold-presence detection. Write-once. */
1991 uint32_t mpsp : 1; /**< [ 19: 19](R/W) Mechanical presence switch attached to port. Write-once. */
1992 uint32_t hpcp : 1; /**< [ 18: 18](R/W) Hot-plug-capable support. Write-once. */
1993 uint32_t pma : 1; /**< [ 17: 17](R/W) Port multiplier attached. */
1994 uint32_t cps : 1; /**< [ 16: 16](RO) Cold presence state. */
1995 uint32_t cr : 1; /**< [ 15: 15](RO) Command list running. */
1996 uint32_t fr : 1; /**< [ 14: 14](RO/H) FIS receive running. */
1997 uint32_t mpss : 1; /**< [ 13: 13](RO) Mechanical presence switch state. */
1998 uint32_t ccs : 5; /**< [ 12: 8](RO) Current-command slot. */
1999 uint32_t reserved_5_7 : 3;
2000 uint32_t fre : 1; /**< [ 4: 4](R/W) FIS-receive enable. */
2001 uint32_t clo : 1; /**< [ 3: 3](WO) Command-list override. */
2002 uint32_t pod : 1; /**< [ 2: 2](R/W) Power-on device. R/W only if CPD = 1, else read only. */
2003 uint32_t sud : 1; /**< [ 1: 1](R/W) Spin-up device. R/W only if SATA()_UAHC_GBL_CAP[SSS]=1, else read only.
2004 Setting this bit triggers a COMRESET initialization sequence. */
2005 uint32_t st : 1; /**< [ 0: 0](R/W) Start. */
2006 #else /* Word 0 - Little Endian */
2007 uint32_t st : 1; /**< [ 0: 0](R/W) Start. */
2008 uint32_t sud : 1; /**< [ 1: 1](R/W) Spin-up device. R/W only if SATA()_UAHC_GBL_CAP[SSS]=1, else read only.
2009 Setting this bit triggers a COMRESET initialization sequence. */
2010 uint32_t pod : 1; /**< [ 2: 2](R/W) Power-on device. R/W only if CPD = 1, else read only. */
2011 uint32_t clo : 1; /**< [ 3: 3](WO) Command-list override. */
2012 uint32_t fre : 1; /**< [ 4: 4](R/W) FIS-receive enable. */
2013 uint32_t reserved_5_7 : 3;
2014 uint32_t ccs : 5; /**< [ 12: 8](RO) Current-command slot. */
2015 uint32_t mpss : 1; /**< [ 13: 13](RO) Mechanical presence switch state. */
2016 uint32_t fr : 1; /**< [ 14: 14](RO/H) FIS receive running. */
2017 uint32_t cr : 1; /**< [ 15: 15](RO) Command list running. */
2018 uint32_t cps : 1; /**< [ 16: 16](RO) Cold presence state. */
2019 uint32_t pma : 1; /**< [ 17: 17](R/W) Port multiplier attached. */
2020 uint32_t hpcp : 1; /**< [ 18: 18](R/W) Hot-plug-capable support. Write-once. */
2021 uint32_t mpsp : 1; /**< [ 19: 19](R/W) Mechanical presence switch attached to port. Write-once. */
2022 uint32_t cpd : 1; /**< [ 20: 20](R/W) Cold-presence detection. Write-once. */
2023 uint32_t esp : 1; /**< [ 21: 21](R/W) External SATA port. Write-once. */
2024 uint32_t fbscp : 1; /**< [ 22: 22](R/W) FIS-based switching capable port. Write-once. */
2025 uint32_t apste : 1; /**< [ 23: 23](R/W) Automatic partial to slumber transitions enable. */
2026 uint32_t atapi : 1; /**< [ 24: 24](R/W) Device is ATAPI. */
2027 uint32_t dlae : 1; /**< [ 25: 25](R/W) Drive LED on ATAPI enable. */
2028 uint32_t alpe : 1; /**< [ 26: 26](R/W) Aggressive link-power-management enable. */
2029 uint32_t asp : 1; /**< [ 27: 27](R/W) Aggressive slumber/partial. */
2030 uint32_t icc : 4; /**< [ 31: 28](R/W) Interface communication control. */
2031 #endif /* Word 0 - End */
2032 } s;
2033 /* struct bdk_satax_uahc_p0_cmd_s cn; */
2034 };
2035 typedef union bdk_satax_uahc_p0_cmd bdk_satax_uahc_p0_cmd_t;
2036
2037 static inline uint64_t BDK_SATAX_UAHC_P0_CMD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_CMD(unsigned long a)2038 static inline uint64_t BDK_SATAX_UAHC_P0_CMD(unsigned long a)
2039 {
2040 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2041 return 0x810000000118ll + 0x1000000000ll * ((a) & 0x1);
2042 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2043 return 0x810000000118ll + 0x1000000000ll * ((a) & 0x7);
2044 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2045 return 0x810000000118ll + 0x1000000000ll * ((a) & 0xf);
2046 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2047 return 0x810000000118ll + 0x1000000000ll * ((a) & 0x3);
2048 __bdk_csr_fatal("SATAX_UAHC_P0_CMD", 1, a, 0, 0, 0);
2049 }
2050
2051 #define typedef_BDK_SATAX_UAHC_P0_CMD(a) bdk_satax_uahc_p0_cmd_t
2052 #define bustype_BDK_SATAX_UAHC_P0_CMD(a) BDK_CSR_TYPE_NCB32b
2053 #define basename_BDK_SATAX_UAHC_P0_CMD(a) "SATAX_UAHC_P0_CMD"
2054 #define device_bar_BDK_SATAX_UAHC_P0_CMD(a) 0x4 /* PF_BAR4 */
2055 #define busnum_BDK_SATAX_UAHC_P0_CMD(a) (a)
2056 #define arguments_BDK_SATAX_UAHC_P0_CMD(a) (a),-1,-1,-1
2057
2058 /**
2059 * Register (NCB32b) sata#_uahc_p0_devslp
2060 *
2061 * SATA UAHC Device Sleep Register
2062 * Internal:
2063 * See DWC_ahsata databook v5.00.
2064 */
2065 union bdk_satax_uahc_p0_devslp
2066 {
2067 uint32_t u;
2068 struct bdk_satax_uahc_p0_devslp_s
2069 {
2070 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2071 uint32_t reserved_29_31 : 3;
2072 uint32_t dm : 4; /**< [ 28: 25](R/W) DITO multiplier. Write once only. */
2073 uint32_t dito : 10; /**< [ 24: 15](R/W) Device sleep idle timeout.
2074 If [DSP]=0, then these bits are read-only zero and software should treat them as reserved.
2075 If [DSP]=1, then these bits are read-write and reset to 0xA on powerup only. */
2076 uint32_t mdat : 5; /**< [ 14: 10](R/W) Minimum device sleep assertion time.
2077 If [DSP]=0, then these bits are read-only zero and software should treat them as reserved.
2078 If [DSP]=1, then these bits are read-write and reset to 0xA on powerup only. */
2079 uint32_t deto : 8; /**< [ 9: 2](R/W) Device sleep exit timeout.
2080 If [DSP]=0, then these bits are read-only zero and software should treat them as reserved.
2081 If [DSP]=1, then these bits are read-write and reset to 0x14 on powerup only. */
2082 uint32_t dsp : 1; /**< [ 1: 1](R/W) Device sleep present. Write once only. */
2083 uint32_t adse : 1; /**< [ 0: 0](R/W) Aggressive device sleep enable.
2084 If [DSP]=0, then this bit is read-only zero and software should treat it as reserved.
2085 If [DSP]=1, then this bit is read-write. */
2086 #else /* Word 0 - Little Endian */
2087 uint32_t adse : 1; /**< [ 0: 0](R/W) Aggressive device sleep enable.
2088 If [DSP]=0, then this bit is read-only zero and software should treat it as reserved.
2089 If [DSP]=1, then this bit is read-write. */
2090 uint32_t dsp : 1; /**< [ 1: 1](R/W) Device sleep present. Write once only. */
2091 uint32_t deto : 8; /**< [ 9: 2](R/W) Device sleep exit timeout.
2092 If [DSP]=0, then these bits are read-only zero and software should treat them as reserved.
2093 If [DSP]=1, then these bits are read-write and reset to 0x14 on powerup only. */
2094 uint32_t mdat : 5; /**< [ 14: 10](R/W) Minimum device sleep assertion time.
2095 If [DSP]=0, then these bits are read-only zero and software should treat them as reserved.
2096 If [DSP]=1, then these bits are read-write and reset to 0xA on powerup only. */
2097 uint32_t dito : 10; /**< [ 24: 15](R/W) Device sleep idle timeout.
2098 If [DSP]=0, then these bits are read-only zero and software should treat them as reserved.
2099 If [DSP]=1, then these bits are read-write and reset to 0xA on powerup only. */
2100 uint32_t dm : 4; /**< [ 28: 25](R/W) DITO multiplier. Write once only. */
2101 uint32_t reserved_29_31 : 3;
2102 #endif /* Word 0 - End */
2103 } s;
2104 /* struct bdk_satax_uahc_p0_devslp_s cn; */
2105 };
2106 typedef union bdk_satax_uahc_p0_devslp bdk_satax_uahc_p0_devslp_t;
2107
2108 static inline uint64_t BDK_SATAX_UAHC_P0_DEVSLP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_DEVSLP(unsigned long a)2109 static inline uint64_t BDK_SATAX_UAHC_P0_DEVSLP(unsigned long a)
2110 {
2111 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2112 return 0x810000000144ll + 0x1000000000ll * ((a) & 0x3);
2113 __bdk_csr_fatal("SATAX_UAHC_P0_DEVSLP", 1, a, 0, 0, 0);
2114 }
2115
2116 #define typedef_BDK_SATAX_UAHC_P0_DEVSLP(a) bdk_satax_uahc_p0_devslp_t
2117 #define bustype_BDK_SATAX_UAHC_P0_DEVSLP(a) BDK_CSR_TYPE_NCB32b
2118 #define basename_BDK_SATAX_UAHC_P0_DEVSLP(a) "SATAX_UAHC_P0_DEVSLP"
2119 #define device_bar_BDK_SATAX_UAHC_P0_DEVSLP(a) 0x4 /* PF_BAR4 */
2120 #define busnum_BDK_SATAX_UAHC_P0_DEVSLP(a) (a)
2121 #define arguments_BDK_SATAX_UAHC_P0_DEVSLP(a) (a),-1,-1,-1
2122
2123 /**
2124 * Register (NCB32b) sata#_uahc_p0_dmacr
2125 *
2126 * SATA UAHC DMA Control Registers
2127 * Internal:
2128 * See DWC_ahsata databook v5.00.
2129 */
2130 union bdk_satax_uahc_p0_dmacr
2131 {
2132 uint32_t u;
2133 struct bdk_satax_uahc_p0_dmacr_s
2134 {
2135 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2136 uint32_t reserved_8_31 : 24;
2137 uint32_t rxts : 4; /**< [ 7: 4](R/W) Receive transaction size. This field is R/W when SATA()_UAHC_P0_CMD[ST] = 0
2138 and read only when SATA()_UAHC_P0_CMD[ST] = 1. */
2139 uint32_t txts : 4; /**< [ 3: 0](R/W) Transmit transaction size. This field is R/W when SATA()_UAHC_P0_CMD[ST] = 0
2140 and read only when SATA()_UAHC_P0_CMD[ST] = 1. */
2141 #else /* Word 0 - Little Endian */
2142 uint32_t txts : 4; /**< [ 3: 0](R/W) Transmit transaction size. This field is R/W when SATA()_UAHC_P0_CMD[ST] = 0
2143 and read only when SATA()_UAHC_P0_CMD[ST] = 1. */
2144 uint32_t rxts : 4; /**< [ 7: 4](R/W) Receive transaction size. This field is R/W when SATA()_UAHC_P0_CMD[ST] = 0
2145 and read only when SATA()_UAHC_P0_CMD[ST] = 1. */
2146 uint32_t reserved_8_31 : 24;
2147 #endif /* Word 0 - End */
2148 } s;
2149 /* struct bdk_satax_uahc_p0_dmacr_s cn; */
2150 };
2151 typedef union bdk_satax_uahc_p0_dmacr bdk_satax_uahc_p0_dmacr_t;
2152
2153 static inline uint64_t BDK_SATAX_UAHC_P0_DMACR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_DMACR(unsigned long a)2154 static inline uint64_t BDK_SATAX_UAHC_P0_DMACR(unsigned long a)
2155 {
2156 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2157 return 0x810000000170ll + 0x1000000000ll * ((a) & 0x1);
2158 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2159 return 0x810000000170ll + 0x1000000000ll * ((a) & 0x7);
2160 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2161 return 0x810000000170ll + 0x1000000000ll * ((a) & 0xf);
2162 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2163 return 0x810000000170ll + 0x1000000000ll * ((a) & 0x3);
2164 __bdk_csr_fatal("SATAX_UAHC_P0_DMACR", 1, a, 0, 0, 0);
2165 }
2166
2167 #define typedef_BDK_SATAX_UAHC_P0_DMACR(a) bdk_satax_uahc_p0_dmacr_t
2168 #define bustype_BDK_SATAX_UAHC_P0_DMACR(a) BDK_CSR_TYPE_NCB32b
2169 #define basename_BDK_SATAX_UAHC_P0_DMACR(a) "SATAX_UAHC_P0_DMACR"
2170 #define device_bar_BDK_SATAX_UAHC_P0_DMACR(a) 0x4 /* PF_BAR4 */
2171 #define busnum_BDK_SATAX_UAHC_P0_DMACR(a) (a)
2172 #define arguments_BDK_SATAX_UAHC_P0_DMACR(a) (a),-1,-1,-1
2173
2174 /**
2175 * Register (NCB) sata#_uahc_p0_fb
2176 *
2177 * SATA UAHC FIS Base-Address Registers
2178 * Internal:
2179 * See DWC_ahsata databook v5.00.
2180 */
2181 union bdk_satax_uahc_p0_fb
2182 {
2183 uint64_t u;
2184 struct bdk_satax_uahc_p0_fb_s
2185 {
2186 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2187 uint64_t fb : 56; /**< [ 63: 8](R/W) FIS base address. */
2188 uint64_t reserved_0_7 : 8;
2189 #else /* Word 0 - Little Endian */
2190 uint64_t reserved_0_7 : 8;
2191 uint64_t fb : 56; /**< [ 63: 8](R/W) FIS base address. */
2192 #endif /* Word 0 - End */
2193 } s;
2194 /* struct bdk_satax_uahc_p0_fb_s cn; */
2195 };
2196 typedef union bdk_satax_uahc_p0_fb bdk_satax_uahc_p0_fb_t;
2197
2198 static inline uint64_t BDK_SATAX_UAHC_P0_FB(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_FB(unsigned long a)2199 static inline uint64_t BDK_SATAX_UAHC_P0_FB(unsigned long a)
2200 {
2201 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2202 return 0x810000000108ll + 0x1000000000ll * ((a) & 0x1);
2203 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2204 return 0x810000000108ll + 0x1000000000ll * ((a) & 0x7);
2205 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2206 return 0x810000000108ll + 0x1000000000ll * ((a) & 0xf);
2207 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2208 return 0x810000000108ll + 0x1000000000ll * ((a) & 0x3);
2209 __bdk_csr_fatal("SATAX_UAHC_P0_FB", 1, a, 0, 0, 0);
2210 }
2211
2212 #define typedef_BDK_SATAX_UAHC_P0_FB(a) bdk_satax_uahc_p0_fb_t
2213 #define bustype_BDK_SATAX_UAHC_P0_FB(a) BDK_CSR_TYPE_NCB
2214 #define basename_BDK_SATAX_UAHC_P0_FB(a) "SATAX_UAHC_P0_FB"
2215 #define device_bar_BDK_SATAX_UAHC_P0_FB(a) 0x4 /* PF_BAR4 */
2216 #define busnum_BDK_SATAX_UAHC_P0_FB(a) (a)
2217 #define arguments_BDK_SATAX_UAHC_P0_FB(a) (a),-1,-1,-1
2218
2219 /**
2220 * Register (NCB32b) sata#_uahc_p0_fbs
2221 *
2222 * SATA UAHC FIS-Based Switching Control Registers
2223 * Internal:
2224 * See DWC_ahsata databook v5.00.
2225 */
2226 union bdk_satax_uahc_p0_fbs
2227 {
2228 uint32_t u;
2229 struct bdk_satax_uahc_p0_fbs_s
2230 {
2231 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2232 uint32_t reserved_20_31 : 12;
2233 uint32_t dwe : 4; /**< [ 19: 16](RO) Device with error. */
2234 uint32_t ado : 4; /**< [ 15: 12](RO) Active device optimization. */
2235 uint32_t dev : 4; /**< [ 11: 8](R/W) Device to issue. */
2236 uint32_t reserved_3_7 : 5;
2237 uint32_t sde : 1; /**< [ 2: 2](RO) Single device error. */
2238 uint32_t dec : 1; /**< [ 1: 1](R/W1C/H) Device error clear. */
2239 uint32_t en : 1; /**< [ 0: 0](R/W) Enable. */
2240 #else /* Word 0 - Little Endian */
2241 uint32_t en : 1; /**< [ 0: 0](R/W) Enable. */
2242 uint32_t dec : 1; /**< [ 1: 1](R/W1C/H) Device error clear. */
2243 uint32_t sde : 1; /**< [ 2: 2](RO) Single device error. */
2244 uint32_t reserved_3_7 : 5;
2245 uint32_t dev : 4; /**< [ 11: 8](R/W) Device to issue. */
2246 uint32_t ado : 4; /**< [ 15: 12](RO) Active device optimization. */
2247 uint32_t dwe : 4; /**< [ 19: 16](RO) Device with error. */
2248 uint32_t reserved_20_31 : 12;
2249 #endif /* Word 0 - End */
2250 } s;
2251 /* struct bdk_satax_uahc_p0_fbs_s cn; */
2252 };
2253 typedef union bdk_satax_uahc_p0_fbs bdk_satax_uahc_p0_fbs_t;
2254
2255 static inline uint64_t BDK_SATAX_UAHC_P0_FBS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_FBS(unsigned long a)2256 static inline uint64_t BDK_SATAX_UAHC_P0_FBS(unsigned long a)
2257 {
2258 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2259 return 0x810000000140ll + 0x1000000000ll * ((a) & 0x1);
2260 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2261 return 0x810000000140ll + 0x1000000000ll * ((a) & 0x7);
2262 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2263 return 0x810000000140ll + 0x1000000000ll * ((a) & 0xf);
2264 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2265 return 0x810000000140ll + 0x1000000000ll * ((a) & 0x3);
2266 __bdk_csr_fatal("SATAX_UAHC_P0_FBS", 1, a, 0, 0, 0);
2267 }
2268
2269 #define typedef_BDK_SATAX_UAHC_P0_FBS(a) bdk_satax_uahc_p0_fbs_t
2270 #define bustype_BDK_SATAX_UAHC_P0_FBS(a) BDK_CSR_TYPE_NCB32b
2271 #define basename_BDK_SATAX_UAHC_P0_FBS(a) "SATAX_UAHC_P0_FBS"
2272 #define device_bar_BDK_SATAX_UAHC_P0_FBS(a) 0x4 /* PF_BAR4 */
2273 #define busnum_BDK_SATAX_UAHC_P0_FBS(a) (a)
2274 #define arguments_BDK_SATAX_UAHC_P0_FBS(a) (a),-1,-1,-1
2275
2276 /**
2277 * Register (NCB32b) sata#_uahc_p0_ie
2278 *
2279 * SATA UAHC Interrupt Enable Registers
2280 * Internal:
2281 * See DWC_ahsata databook v5.00.
2282 */
2283 union bdk_satax_uahc_p0_ie
2284 {
2285 uint32_t u;
2286 struct bdk_satax_uahc_p0_ie_s
2287 {
2288 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2289 uint32_t cpde : 1; /**< [ 31: 31](R/W) Cold-port-detect enable. */
2290 uint32_t tfee : 1; /**< [ 30: 30](R/W) Task-file-error enable. */
2291 uint32_t hbfe : 1; /**< [ 29: 29](R/W) Host-bus fatal-error enable. */
2292 uint32_t hbde : 1; /**< [ 28: 28](R/W) Host-bus data-error enable. */
2293 uint32_t ife : 1; /**< [ 27: 27](R/W) Interface fatal-error enable. */
2294 uint32_t infe : 1; /**< [ 26: 26](R/W) Interface non-fatal-error enable. */
2295 uint32_t reserved_25 : 1;
2296 uint32_t ofe : 1; /**< [ 24: 24](R/W) Overflow enable. */
2297 uint32_t impe : 1; /**< [ 23: 23](R/W) Incorrect port-multiplier enable. */
2298 uint32_t prce : 1; /**< [ 22: 22](R/W) PHY-ready-change enable. */
2299 uint32_t reserved_8_21 : 14;
2300 uint32_t dmpe : 1; /**< [ 7: 7](R/W) Device mechanical-presence enable. */
2301 uint32_t pce : 1; /**< [ 6: 6](R/W) Port-connect-change enable. */
2302 uint32_t dpe : 1; /**< [ 5: 5](R/W) Descriptor-processed enable. */
2303 uint32_t ufe : 1; /**< [ 4: 4](R/W) Unknown-FIS-interrupt enable. */
2304 uint32_t sdbe : 1; /**< [ 3: 3](R/W) Set device-bits-interrupt enable. */
2305 uint32_t dse : 1; /**< [ 2: 2](R/W) DMA-setup FIS interrupt enable. */
2306 uint32_t pse : 1; /**< [ 1: 1](R/W) PIO-setup FIS interrupt enable. */
2307 uint32_t dhre : 1; /**< [ 0: 0](R/W) Device-to-host register FIS interrupt enable. */
2308 #else /* Word 0 - Little Endian */
2309 uint32_t dhre : 1; /**< [ 0: 0](R/W) Device-to-host register FIS interrupt enable. */
2310 uint32_t pse : 1; /**< [ 1: 1](R/W) PIO-setup FIS interrupt enable. */
2311 uint32_t dse : 1; /**< [ 2: 2](R/W) DMA-setup FIS interrupt enable. */
2312 uint32_t sdbe : 1; /**< [ 3: 3](R/W) Set device-bits-interrupt enable. */
2313 uint32_t ufe : 1; /**< [ 4: 4](R/W) Unknown-FIS-interrupt enable. */
2314 uint32_t dpe : 1; /**< [ 5: 5](R/W) Descriptor-processed enable. */
2315 uint32_t pce : 1; /**< [ 6: 6](R/W) Port-connect-change enable. */
2316 uint32_t dmpe : 1; /**< [ 7: 7](R/W) Device mechanical-presence enable. */
2317 uint32_t reserved_8_21 : 14;
2318 uint32_t prce : 1; /**< [ 22: 22](R/W) PHY-ready-change enable. */
2319 uint32_t impe : 1; /**< [ 23: 23](R/W) Incorrect port-multiplier enable. */
2320 uint32_t ofe : 1; /**< [ 24: 24](R/W) Overflow enable. */
2321 uint32_t reserved_25 : 1;
2322 uint32_t infe : 1; /**< [ 26: 26](R/W) Interface non-fatal-error enable. */
2323 uint32_t ife : 1; /**< [ 27: 27](R/W) Interface fatal-error enable. */
2324 uint32_t hbde : 1; /**< [ 28: 28](R/W) Host-bus data-error enable. */
2325 uint32_t hbfe : 1; /**< [ 29: 29](R/W) Host-bus fatal-error enable. */
2326 uint32_t tfee : 1; /**< [ 30: 30](R/W) Task-file-error enable. */
2327 uint32_t cpde : 1; /**< [ 31: 31](R/W) Cold-port-detect enable. */
2328 #endif /* Word 0 - End */
2329 } s;
2330 /* struct bdk_satax_uahc_p0_ie_s cn; */
2331 };
2332 typedef union bdk_satax_uahc_p0_ie bdk_satax_uahc_p0_ie_t;
2333
2334 static inline uint64_t BDK_SATAX_UAHC_P0_IE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_IE(unsigned long a)2335 static inline uint64_t BDK_SATAX_UAHC_P0_IE(unsigned long a)
2336 {
2337 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2338 return 0x810000000114ll + 0x1000000000ll * ((a) & 0x1);
2339 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2340 return 0x810000000114ll + 0x1000000000ll * ((a) & 0x7);
2341 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2342 return 0x810000000114ll + 0x1000000000ll * ((a) & 0xf);
2343 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2344 return 0x810000000114ll + 0x1000000000ll * ((a) & 0x3);
2345 __bdk_csr_fatal("SATAX_UAHC_P0_IE", 1, a, 0, 0, 0);
2346 }
2347
2348 #define typedef_BDK_SATAX_UAHC_P0_IE(a) bdk_satax_uahc_p0_ie_t
2349 #define bustype_BDK_SATAX_UAHC_P0_IE(a) BDK_CSR_TYPE_NCB32b
2350 #define basename_BDK_SATAX_UAHC_P0_IE(a) "SATAX_UAHC_P0_IE"
2351 #define device_bar_BDK_SATAX_UAHC_P0_IE(a) 0x4 /* PF_BAR4 */
2352 #define busnum_BDK_SATAX_UAHC_P0_IE(a) (a)
2353 #define arguments_BDK_SATAX_UAHC_P0_IE(a) (a),-1,-1,-1
2354
2355 /**
2356 * Register (NCB32b) sata#_uahc_p0_is
2357 *
2358 * SATA UAHC Interrupt Status Registers
2359 * Internal:
2360 * See DWC_ahsata databook v5.00.
2361 */
2362 union bdk_satax_uahc_p0_is
2363 {
2364 uint32_t u;
2365 struct bdk_satax_uahc_p0_is_s
2366 {
2367 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2368 uint32_t cpds : 1; /**< [ 31: 31](R/W1C/H) Cold-port detect status. */
2369 uint32_t tfes : 1; /**< [ 30: 30](R/W1C/H) Task-file error status. */
2370 uint32_t hbfs : 1; /**< [ 29: 29](R/W1C/H) Host-bus fatal-error status. */
2371 uint32_t hbds : 1; /**< [ 28: 28](R/W1C/H) Host-bus data-error status. */
2372 uint32_t ifs : 1; /**< [ 27: 27](R/W1C/H) Interface fatal-error status. */
2373 uint32_t infs : 1; /**< [ 26: 26](R/W1C/H) Interface non-fatal-error status. */
2374 uint32_t reserved_25 : 1;
2375 uint32_t ofs : 1; /**< [ 24: 24](R/W1C/H) Overflow status. */
2376 uint32_t imps : 1; /**< [ 23: 23](R/W1C/H) Incorrect port-multiplier status. */
2377 uint32_t prcs : 1; /**< [ 22: 22](RO/H) PHY-ready change status. */
2378 uint32_t reserved_8_21 : 14;
2379 uint32_t dmps : 1; /**< [ 7: 7](R/W1C/H) Device mechanical-presence status. */
2380 uint32_t pcs : 1; /**< [ 6: 6](RO/H) Port-connect-change status. */
2381 uint32_t dps : 1; /**< [ 5: 5](R/W1C/H) Descriptor processed. */
2382 uint32_t ufs : 1; /**< [ 4: 4](RO) Unknown FIS interrupt. */
2383 uint32_t sdbs : 1; /**< [ 3: 3](R/W1C/H) Set device bits interrupt. */
2384 uint32_t dss : 1; /**< [ 2: 2](R/W1C/H) DMA setup FIS interrupt. */
2385 uint32_t pss : 1; /**< [ 1: 1](R/W1C/H) PIO setup FIS interrupt. */
2386 uint32_t dhrs : 1; /**< [ 0: 0](R/W1C/H) Device-to-host register FIS interrupt. */
2387 #else /* Word 0 - Little Endian */
2388 uint32_t dhrs : 1; /**< [ 0: 0](R/W1C/H) Device-to-host register FIS interrupt. */
2389 uint32_t pss : 1; /**< [ 1: 1](R/W1C/H) PIO setup FIS interrupt. */
2390 uint32_t dss : 1; /**< [ 2: 2](R/W1C/H) DMA setup FIS interrupt. */
2391 uint32_t sdbs : 1; /**< [ 3: 3](R/W1C/H) Set device bits interrupt. */
2392 uint32_t ufs : 1; /**< [ 4: 4](RO) Unknown FIS interrupt. */
2393 uint32_t dps : 1; /**< [ 5: 5](R/W1C/H) Descriptor processed. */
2394 uint32_t pcs : 1; /**< [ 6: 6](RO/H) Port-connect-change status. */
2395 uint32_t dmps : 1; /**< [ 7: 7](R/W1C/H) Device mechanical-presence status. */
2396 uint32_t reserved_8_21 : 14;
2397 uint32_t prcs : 1; /**< [ 22: 22](RO/H) PHY-ready change status. */
2398 uint32_t imps : 1; /**< [ 23: 23](R/W1C/H) Incorrect port-multiplier status. */
2399 uint32_t ofs : 1; /**< [ 24: 24](R/W1C/H) Overflow status. */
2400 uint32_t reserved_25 : 1;
2401 uint32_t infs : 1; /**< [ 26: 26](R/W1C/H) Interface non-fatal-error status. */
2402 uint32_t ifs : 1; /**< [ 27: 27](R/W1C/H) Interface fatal-error status. */
2403 uint32_t hbds : 1; /**< [ 28: 28](R/W1C/H) Host-bus data-error status. */
2404 uint32_t hbfs : 1; /**< [ 29: 29](R/W1C/H) Host-bus fatal-error status. */
2405 uint32_t tfes : 1; /**< [ 30: 30](R/W1C/H) Task-file error status. */
2406 uint32_t cpds : 1; /**< [ 31: 31](R/W1C/H) Cold-port detect status. */
2407 #endif /* Word 0 - End */
2408 } s;
2409 /* struct bdk_satax_uahc_p0_is_s cn; */
2410 };
2411 typedef union bdk_satax_uahc_p0_is bdk_satax_uahc_p0_is_t;
2412
2413 static inline uint64_t BDK_SATAX_UAHC_P0_IS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_IS(unsigned long a)2414 static inline uint64_t BDK_SATAX_UAHC_P0_IS(unsigned long a)
2415 {
2416 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2417 return 0x810000000110ll + 0x1000000000ll * ((a) & 0x1);
2418 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2419 return 0x810000000110ll + 0x1000000000ll * ((a) & 0x7);
2420 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2421 return 0x810000000110ll + 0x1000000000ll * ((a) & 0xf);
2422 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2423 return 0x810000000110ll + 0x1000000000ll * ((a) & 0x3);
2424 __bdk_csr_fatal("SATAX_UAHC_P0_IS", 1, a, 0, 0, 0);
2425 }
2426
2427 #define typedef_BDK_SATAX_UAHC_P0_IS(a) bdk_satax_uahc_p0_is_t
2428 #define bustype_BDK_SATAX_UAHC_P0_IS(a) BDK_CSR_TYPE_NCB32b
2429 #define basename_BDK_SATAX_UAHC_P0_IS(a) "SATAX_UAHC_P0_IS"
2430 #define device_bar_BDK_SATAX_UAHC_P0_IS(a) 0x4 /* PF_BAR4 */
2431 #define busnum_BDK_SATAX_UAHC_P0_IS(a) (a)
2432 #define arguments_BDK_SATAX_UAHC_P0_IS(a) (a),-1,-1,-1
2433
2434 /**
2435 * Register (NCB32b) sata#_uahc_p0_phycr
2436 *
2437 * SATA UAHC PHY Control Registers
2438 * Internal:
2439 * See DWC_ahsata databook v5.00.
2440 */
2441 union bdk_satax_uahc_p0_phycr
2442 {
2443 uint32_t u;
2444 struct bdk_satax_uahc_p0_phycr_s
2445 {
2446 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2447 uint32_t ctrl : 32; /**< [ 31: 0](R/W) Port PHY control. */
2448 #else /* Word 0 - Little Endian */
2449 uint32_t ctrl : 32; /**< [ 31: 0](R/W) Port PHY control. */
2450 #endif /* Word 0 - End */
2451 } s;
2452 /* struct bdk_satax_uahc_p0_phycr_s cn; */
2453 };
2454 typedef union bdk_satax_uahc_p0_phycr bdk_satax_uahc_p0_phycr_t;
2455
2456 static inline uint64_t BDK_SATAX_UAHC_P0_PHYCR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_PHYCR(unsigned long a)2457 static inline uint64_t BDK_SATAX_UAHC_P0_PHYCR(unsigned long a)
2458 {
2459 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2460 return 0x810000000178ll + 0x1000000000ll * ((a) & 0x1);
2461 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2462 return 0x810000000178ll + 0x1000000000ll * ((a) & 0x7);
2463 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2464 return 0x810000000178ll + 0x1000000000ll * ((a) & 0xf);
2465 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2466 return 0x810000000178ll + 0x1000000000ll * ((a) & 0x3);
2467 __bdk_csr_fatal("SATAX_UAHC_P0_PHYCR", 1, a, 0, 0, 0);
2468 }
2469
2470 #define typedef_BDK_SATAX_UAHC_P0_PHYCR(a) bdk_satax_uahc_p0_phycr_t
2471 #define bustype_BDK_SATAX_UAHC_P0_PHYCR(a) BDK_CSR_TYPE_NCB32b
2472 #define basename_BDK_SATAX_UAHC_P0_PHYCR(a) "SATAX_UAHC_P0_PHYCR"
2473 #define device_bar_BDK_SATAX_UAHC_P0_PHYCR(a) 0x4 /* PF_BAR4 */
2474 #define busnum_BDK_SATAX_UAHC_P0_PHYCR(a) (a)
2475 #define arguments_BDK_SATAX_UAHC_P0_PHYCR(a) (a),-1,-1,-1
2476
2477 /**
2478 * Register (NCB32b) sata#_uahc_p0_physr
2479 *
2480 * SATA UAHC PHY Status Registers
2481 * Internal:
2482 * See DWC_ahsata databook v5.00.
2483 */
2484 union bdk_satax_uahc_p0_physr
2485 {
2486 uint32_t u;
2487 struct bdk_satax_uahc_p0_physr_s
2488 {
2489 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2490 uint32_t stat : 32; /**< [ 31: 0](RO) Port PHY status. */
2491 #else /* Word 0 - Little Endian */
2492 uint32_t stat : 32; /**< [ 31: 0](RO) Port PHY status. */
2493 #endif /* Word 0 - End */
2494 } s;
2495 /* struct bdk_satax_uahc_p0_physr_s cn; */
2496 };
2497 typedef union bdk_satax_uahc_p0_physr bdk_satax_uahc_p0_physr_t;
2498
2499 static inline uint64_t BDK_SATAX_UAHC_P0_PHYSR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_PHYSR(unsigned long a)2500 static inline uint64_t BDK_SATAX_UAHC_P0_PHYSR(unsigned long a)
2501 {
2502 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2503 return 0x81000000017cll + 0x1000000000ll * ((a) & 0x1);
2504 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2505 return 0x81000000017cll + 0x1000000000ll * ((a) & 0x7);
2506 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2507 return 0x81000000017cll + 0x1000000000ll * ((a) & 0xf);
2508 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2509 return 0x81000000017cll + 0x1000000000ll * ((a) & 0x3);
2510 __bdk_csr_fatal("SATAX_UAHC_P0_PHYSR", 1, a, 0, 0, 0);
2511 }
2512
2513 #define typedef_BDK_SATAX_UAHC_P0_PHYSR(a) bdk_satax_uahc_p0_physr_t
2514 #define bustype_BDK_SATAX_UAHC_P0_PHYSR(a) BDK_CSR_TYPE_NCB32b
2515 #define basename_BDK_SATAX_UAHC_P0_PHYSR(a) "SATAX_UAHC_P0_PHYSR"
2516 #define device_bar_BDK_SATAX_UAHC_P0_PHYSR(a) 0x4 /* PF_BAR4 */
2517 #define busnum_BDK_SATAX_UAHC_P0_PHYSR(a) (a)
2518 #define arguments_BDK_SATAX_UAHC_P0_PHYSR(a) (a),-1,-1,-1
2519
2520 /**
2521 * Register (NCB32b) sata#_uahc_p0_sact
2522 *
2523 * SATA UAHC SATA Active Registers
2524 * Internal:
2525 * See DWC_ahsata databook v5.00.
2526 */
2527 union bdk_satax_uahc_p0_sact
2528 {
2529 uint32_t u;
2530 struct bdk_satax_uahc_p0_sact_s
2531 {
2532 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2533 uint32_t ds : 32; /**< [ 31: 0](R/W1S/H) Device status. */
2534 #else /* Word 0 - Little Endian */
2535 uint32_t ds : 32; /**< [ 31: 0](R/W1S/H) Device status. */
2536 #endif /* Word 0 - End */
2537 } s;
2538 /* struct bdk_satax_uahc_p0_sact_s cn; */
2539 };
2540 typedef union bdk_satax_uahc_p0_sact bdk_satax_uahc_p0_sact_t;
2541
2542 static inline uint64_t BDK_SATAX_UAHC_P0_SACT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_SACT(unsigned long a)2543 static inline uint64_t BDK_SATAX_UAHC_P0_SACT(unsigned long a)
2544 {
2545 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2546 return 0x810000000134ll + 0x1000000000ll * ((a) & 0x1);
2547 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2548 return 0x810000000134ll + 0x1000000000ll * ((a) & 0x7);
2549 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2550 return 0x810000000134ll + 0x1000000000ll * ((a) & 0xf);
2551 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2552 return 0x810000000134ll + 0x1000000000ll * ((a) & 0x3);
2553 __bdk_csr_fatal("SATAX_UAHC_P0_SACT", 1, a, 0, 0, 0);
2554 }
2555
2556 #define typedef_BDK_SATAX_UAHC_P0_SACT(a) bdk_satax_uahc_p0_sact_t
2557 #define bustype_BDK_SATAX_UAHC_P0_SACT(a) BDK_CSR_TYPE_NCB32b
2558 #define basename_BDK_SATAX_UAHC_P0_SACT(a) "SATAX_UAHC_P0_SACT"
2559 #define device_bar_BDK_SATAX_UAHC_P0_SACT(a) 0x4 /* PF_BAR4 */
2560 #define busnum_BDK_SATAX_UAHC_P0_SACT(a) (a)
2561 #define arguments_BDK_SATAX_UAHC_P0_SACT(a) (a),-1,-1,-1
2562
2563 /**
2564 * Register (NCB32b) sata#_uahc_p0_sctl
2565 *
2566 * SATA UAHC SATA Control Registers
2567 * Internal:
2568 * See DWC_ahsata databook v5.00.
2569 */
2570 union bdk_satax_uahc_p0_sctl
2571 {
2572 uint32_t u;
2573 struct bdk_satax_uahc_p0_sctl_s
2574 {
2575 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2576 uint32_t reserved_11_31 : 21;
2577 uint32_t ipm : 3; /**< [ 10: 8](R/W) Interface power-management transitions allowed. */
2578 uint32_t reserved_6_7 : 2;
2579 uint32_t spd : 2; /**< [ 5: 4](R/W) Speed allowed. */
2580 uint32_t reserved_3 : 1;
2581 uint32_t det : 3; /**< [ 2: 0](R/W) Device-detection initialization. */
2582 #else /* Word 0 - Little Endian */
2583 uint32_t det : 3; /**< [ 2: 0](R/W) Device-detection initialization. */
2584 uint32_t reserved_3 : 1;
2585 uint32_t spd : 2; /**< [ 5: 4](R/W) Speed allowed. */
2586 uint32_t reserved_6_7 : 2;
2587 uint32_t ipm : 3; /**< [ 10: 8](R/W) Interface power-management transitions allowed. */
2588 uint32_t reserved_11_31 : 21;
2589 #endif /* Word 0 - End */
2590 } s;
2591 struct bdk_satax_uahc_p0_sctl_cn8
2592 {
2593 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2594 uint32_t reserved_10_31 : 22;
2595 uint32_t ipm : 2; /**< [ 9: 8](R/W) Interface power-management transitions allowed. */
2596 uint32_t reserved_6_7 : 2;
2597 uint32_t spd : 2; /**< [ 5: 4](R/W) Speed allowed. */
2598 uint32_t reserved_3 : 1;
2599 uint32_t det : 3; /**< [ 2: 0](R/W) Device-detection initialization. */
2600 #else /* Word 0 - Little Endian */
2601 uint32_t det : 3; /**< [ 2: 0](R/W) Device-detection initialization. */
2602 uint32_t reserved_3 : 1;
2603 uint32_t spd : 2; /**< [ 5: 4](R/W) Speed allowed. */
2604 uint32_t reserved_6_7 : 2;
2605 uint32_t ipm : 2; /**< [ 9: 8](R/W) Interface power-management transitions allowed. */
2606 uint32_t reserved_10_31 : 22;
2607 #endif /* Word 0 - End */
2608 } cn8;
2609 /* struct bdk_satax_uahc_p0_sctl_s cn9; */
2610 };
2611 typedef union bdk_satax_uahc_p0_sctl bdk_satax_uahc_p0_sctl_t;
2612
2613 static inline uint64_t BDK_SATAX_UAHC_P0_SCTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_SCTL(unsigned long a)2614 static inline uint64_t BDK_SATAX_UAHC_P0_SCTL(unsigned long a)
2615 {
2616 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2617 return 0x81000000012cll + 0x1000000000ll * ((a) & 0x1);
2618 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2619 return 0x81000000012cll + 0x1000000000ll * ((a) & 0x7);
2620 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2621 return 0x81000000012cll + 0x1000000000ll * ((a) & 0xf);
2622 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2623 return 0x81000000012cll + 0x1000000000ll * ((a) & 0x3);
2624 __bdk_csr_fatal("SATAX_UAHC_P0_SCTL", 1, a, 0, 0, 0);
2625 }
2626
2627 #define typedef_BDK_SATAX_UAHC_P0_SCTL(a) bdk_satax_uahc_p0_sctl_t
2628 #define bustype_BDK_SATAX_UAHC_P0_SCTL(a) BDK_CSR_TYPE_NCB32b
2629 #define basename_BDK_SATAX_UAHC_P0_SCTL(a) "SATAX_UAHC_P0_SCTL"
2630 #define device_bar_BDK_SATAX_UAHC_P0_SCTL(a) 0x4 /* PF_BAR4 */
2631 #define busnum_BDK_SATAX_UAHC_P0_SCTL(a) (a)
2632 #define arguments_BDK_SATAX_UAHC_P0_SCTL(a) (a),-1,-1,-1
2633
2634 /**
2635 * Register (NCB32b) sata#_uahc_p0_serr
2636 *
2637 * SATA UAHC SATA Error Registers
2638 * Internal:
2639 * See DWC_ahsata databook v5.00.
2640 */
2641 union bdk_satax_uahc_p0_serr
2642 {
2643 uint32_t u;
2644 struct bdk_satax_uahc_p0_serr_s
2645 {
2646 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2647 uint32_t reserved_27_31 : 5;
2648 uint32_t diag_x : 1; /**< [ 26: 26](R/W1C/H) Exchanged. */
2649 uint32_t diag_f : 1; /**< [ 25: 25](R/W1C/H) Unknown FIS type. */
2650 uint32_t diag_t : 1; /**< [ 24: 24](R/W1C/H) Transport state transition error. */
2651 uint32_t diag_s : 1; /**< [ 23: 23](R/W1C/H) Link sequence error. */
2652 uint32_t diag_h : 1; /**< [ 22: 22](R/W1C/H) Handshake error. */
2653 uint32_t diag_c : 1; /**< [ 21: 21](R/W1C/H) CRC error. */
2654 uint32_t diag_d : 1; /**< [ 20: 20](R/W1C/H) Disparity error. */
2655 uint32_t diag_b : 1; /**< [ 19: 19](R/W1C/H) 10/8 bit decode error. */
2656 uint32_t diag_w : 1; /**< [ 18: 18](R/W1C/H) COMWAKE detected. */
2657 uint32_t diag_i : 1; /**< [ 17: 17](R/W1C/H) PHY internal error. */
2658 uint32_t diag_n : 1; /**< [ 16: 16](R/W1C/H) PHY ready change. */
2659 uint32_t reserved_12_15 : 4;
2660 uint32_t err_e : 1; /**< [ 11: 11](R/W1C/H) Internal error. */
2661 uint32_t err_p : 1; /**< [ 10: 10](R/W1C/H) Protocol error. */
2662 uint32_t err_c : 1; /**< [ 9: 9](R/W1C/H) Non-recovered persistent communication error. */
2663 uint32_t err_t : 1; /**< [ 8: 8](R/W1C/H) Non-recovered transient data integrity error. */
2664 uint32_t reserved_2_7 : 6;
2665 uint32_t err_m : 1; /**< [ 1: 1](R/W1C/H) Recovered communication error. */
2666 uint32_t err_i : 1; /**< [ 0: 0](R/W1C/H) Recovered data integrity. */
2667 #else /* Word 0 - Little Endian */
2668 uint32_t err_i : 1; /**< [ 0: 0](R/W1C/H) Recovered data integrity. */
2669 uint32_t err_m : 1; /**< [ 1: 1](R/W1C/H) Recovered communication error. */
2670 uint32_t reserved_2_7 : 6;
2671 uint32_t err_t : 1; /**< [ 8: 8](R/W1C/H) Non-recovered transient data integrity error. */
2672 uint32_t err_c : 1; /**< [ 9: 9](R/W1C/H) Non-recovered persistent communication error. */
2673 uint32_t err_p : 1; /**< [ 10: 10](R/W1C/H) Protocol error. */
2674 uint32_t err_e : 1; /**< [ 11: 11](R/W1C/H) Internal error. */
2675 uint32_t reserved_12_15 : 4;
2676 uint32_t diag_n : 1; /**< [ 16: 16](R/W1C/H) PHY ready change. */
2677 uint32_t diag_i : 1; /**< [ 17: 17](R/W1C/H) PHY internal error. */
2678 uint32_t diag_w : 1; /**< [ 18: 18](R/W1C/H) COMWAKE detected. */
2679 uint32_t diag_b : 1; /**< [ 19: 19](R/W1C/H) 10/8 bit decode error. */
2680 uint32_t diag_d : 1; /**< [ 20: 20](R/W1C/H) Disparity error. */
2681 uint32_t diag_c : 1; /**< [ 21: 21](R/W1C/H) CRC error. */
2682 uint32_t diag_h : 1; /**< [ 22: 22](R/W1C/H) Handshake error. */
2683 uint32_t diag_s : 1; /**< [ 23: 23](R/W1C/H) Link sequence error. */
2684 uint32_t diag_t : 1; /**< [ 24: 24](R/W1C/H) Transport state transition error. */
2685 uint32_t diag_f : 1; /**< [ 25: 25](R/W1C/H) Unknown FIS type. */
2686 uint32_t diag_x : 1; /**< [ 26: 26](R/W1C/H) Exchanged. */
2687 uint32_t reserved_27_31 : 5;
2688 #endif /* Word 0 - End */
2689 } s;
2690 /* struct bdk_satax_uahc_p0_serr_s cn; */
2691 };
2692 typedef union bdk_satax_uahc_p0_serr bdk_satax_uahc_p0_serr_t;
2693
2694 static inline uint64_t BDK_SATAX_UAHC_P0_SERR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_SERR(unsigned long a)2695 static inline uint64_t BDK_SATAX_UAHC_P0_SERR(unsigned long a)
2696 {
2697 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2698 return 0x810000000130ll + 0x1000000000ll * ((a) & 0x1);
2699 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2700 return 0x810000000130ll + 0x1000000000ll * ((a) & 0x7);
2701 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2702 return 0x810000000130ll + 0x1000000000ll * ((a) & 0xf);
2703 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2704 return 0x810000000130ll + 0x1000000000ll * ((a) & 0x3);
2705 __bdk_csr_fatal("SATAX_UAHC_P0_SERR", 1, a, 0, 0, 0);
2706 }
2707
2708 #define typedef_BDK_SATAX_UAHC_P0_SERR(a) bdk_satax_uahc_p0_serr_t
2709 #define bustype_BDK_SATAX_UAHC_P0_SERR(a) BDK_CSR_TYPE_NCB32b
2710 #define basename_BDK_SATAX_UAHC_P0_SERR(a) "SATAX_UAHC_P0_SERR"
2711 #define device_bar_BDK_SATAX_UAHC_P0_SERR(a) 0x4 /* PF_BAR4 */
2712 #define busnum_BDK_SATAX_UAHC_P0_SERR(a) (a)
2713 #define arguments_BDK_SATAX_UAHC_P0_SERR(a) (a),-1,-1,-1
2714
2715 /**
2716 * Register (NCB32b) sata#_uahc_p0_sig
2717 *
2718 * SATA UAHC Signature Registers
2719 * Internal:
2720 * See DWC_ahsata databook v5.00.
2721 */
2722 union bdk_satax_uahc_p0_sig
2723 {
2724 uint32_t u;
2725 struct bdk_satax_uahc_p0_sig_s
2726 {
2727 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2728 uint32_t sig : 32; /**< [ 31: 0](RO/H) Signature. */
2729 #else /* Word 0 - Little Endian */
2730 uint32_t sig : 32; /**< [ 31: 0](RO/H) Signature. */
2731 #endif /* Word 0 - End */
2732 } s;
2733 /* struct bdk_satax_uahc_p0_sig_s cn; */
2734 };
2735 typedef union bdk_satax_uahc_p0_sig bdk_satax_uahc_p0_sig_t;
2736
2737 static inline uint64_t BDK_SATAX_UAHC_P0_SIG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_SIG(unsigned long a)2738 static inline uint64_t BDK_SATAX_UAHC_P0_SIG(unsigned long a)
2739 {
2740 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2741 return 0x810000000124ll + 0x1000000000ll * ((a) & 0x1);
2742 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2743 return 0x810000000124ll + 0x1000000000ll * ((a) & 0x7);
2744 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2745 return 0x810000000124ll + 0x1000000000ll * ((a) & 0xf);
2746 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2747 return 0x810000000124ll + 0x1000000000ll * ((a) & 0x3);
2748 __bdk_csr_fatal("SATAX_UAHC_P0_SIG", 1, a, 0, 0, 0);
2749 }
2750
2751 #define typedef_BDK_SATAX_UAHC_P0_SIG(a) bdk_satax_uahc_p0_sig_t
2752 #define bustype_BDK_SATAX_UAHC_P0_SIG(a) BDK_CSR_TYPE_NCB32b
2753 #define basename_BDK_SATAX_UAHC_P0_SIG(a) "SATAX_UAHC_P0_SIG"
2754 #define device_bar_BDK_SATAX_UAHC_P0_SIG(a) 0x4 /* PF_BAR4 */
2755 #define busnum_BDK_SATAX_UAHC_P0_SIG(a) (a)
2756 #define arguments_BDK_SATAX_UAHC_P0_SIG(a) (a),-1,-1,-1
2757
2758 /**
2759 * Register (NCB32b) sata#_uahc_p0_sntf
2760 *
2761 * SATA UAHC SATA Notification Registers
2762 * Internal:
2763 * See DWC_ahsata databook v5.00.
2764 */
2765 union bdk_satax_uahc_p0_sntf
2766 {
2767 uint32_t u;
2768 struct bdk_satax_uahc_p0_sntf_s
2769 {
2770 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2771 uint32_t reserved_16_31 : 16;
2772 uint32_t pmn : 16; /**< [ 15: 0](R/W1C/H) PM notify. */
2773 #else /* Word 0 - Little Endian */
2774 uint32_t pmn : 16; /**< [ 15: 0](R/W1C/H) PM notify. */
2775 uint32_t reserved_16_31 : 16;
2776 #endif /* Word 0 - End */
2777 } s;
2778 /* struct bdk_satax_uahc_p0_sntf_s cn; */
2779 };
2780 typedef union bdk_satax_uahc_p0_sntf bdk_satax_uahc_p0_sntf_t;
2781
2782 static inline uint64_t BDK_SATAX_UAHC_P0_SNTF(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_SNTF(unsigned long a)2783 static inline uint64_t BDK_SATAX_UAHC_P0_SNTF(unsigned long a)
2784 {
2785 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2786 return 0x81000000013cll + 0x1000000000ll * ((a) & 0x1);
2787 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2788 return 0x81000000013cll + 0x1000000000ll * ((a) & 0x7);
2789 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2790 return 0x81000000013cll + 0x1000000000ll * ((a) & 0xf);
2791 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2792 return 0x81000000013cll + 0x1000000000ll * ((a) & 0x3);
2793 __bdk_csr_fatal("SATAX_UAHC_P0_SNTF", 1, a, 0, 0, 0);
2794 }
2795
2796 #define typedef_BDK_SATAX_UAHC_P0_SNTF(a) bdk_satax_uahc_p0_sntf_t
2797 #define bustype_BDK_SATAX_UAHC_P0_SNTF(a) BDK_CSR_TYPE_NCB32b
2798 #define basename_BDK_SATAX_UAHC_P0_SNTF(a) "SATAX_UAHC_P0_SNTF"
2799 #define device_bar_BDK_SATAX_UAHC_P0_SNTF(a) 0x4 /* PF_BAR4 */
2800 #define busnum_BDK_SATAX_UAHC_P0_SNTF(a) (a)
2801 #define arguments_BDK_SATAX_UAHC_P0_SNTF(a) (a),-1,-1,-1
2802
2803 /**
2804 * Register (NCB32b) sata#_uahc_p0_ssts
2805 *
2806 * SATA UAHC SATA Status Registers
2807 * Internal:
2808 * See DWC_ahsata databook v5.00.
2809 */
2810 union bdk_satax_uahc_p0_ssts
2811 {
2812 uint32_t u;
2813 struct bdk_satax_uahc_p0_ssts_s
2814 {
2815 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2816 uint32_t reserved_12_31 : 20;
2817 uint32_t ipm : 4; /**< [ 11: 8](RO/H) Interface power management. */
2818 uint32_t spd : 4; /**< [ 7: 4](RO/H) Current interface speed. */
2819 uint32_t det : 4; /**< [ 3: 0](RO/H) Device detection. */
2820 #else /* Word 0 - Little Endian */
2821 uint32_t det : 4; /**< [ 3: 0](RO/H) Device detection. */
2822 uint32_t spd : 4; /**< [ 7: 4](RO/H) Current interface speed. */
2823 uint32_t ipm : 4; /**< [ 11: 8](RO/H) Interface power management. */
2824 uint32_t reserved_12_31 : 20;
2825 #endif /* Word 0 - End */
2826 } s;
2827 /* struct bdk_satax_uahc_p0_ssts_s cn; */
2828 };
2829 typedef union bdk_satax_uahc_p0_ssts bdk_satax_uahc_p0_ssts_t;
2830
2831 static inline uint64_t BDK_SATAX_UAHC_P0_SSTS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_SSTS(unsigned long a)2832 static inline uint64_t BDK_SATAX_UAHC_P0_SSTS(unsigned long a)
2833 {
2834 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2835 return 0x810000000128ll + 0x1000000000ll * ((a) & 0x1);
2836 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2837 return 0x810000000128ll + 0x1000000000ll * ((a) & 0x7);
2838 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2839 return 0x810000000128ll + 0x1000000000ll * ((a) & 0xf);
2840 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2841 return 0x810000000128ll + 0x1000000000ll * ((a) & 0x3);
2842 __bdk_csr_fatal("SATAX_UAHC_P0_SSTS", 1, a, 0, 0, 0);
2843 }
2844
2845 #define typedef_BDK_SATAX_UAHC_P0_SSTS(a) bdk_satax_uahc_p0_ssts_t
2846 #define bustype_BDK_SATAX_UAHC_P0_SSTS(a) BDK_CSR_TYPE_NCB32b
2847 #define basename_BDK_SATAX_UAHC_P0_SSTS(a) "SATAX_UAHC_P0_SSTS"
2848 #define device_bar_BDK_SATAX_UAHC_P0_SSTS(a) 0x4 /* PF_BAR4 */
2849 #define busnum_BDK_SATAX_UAHC_P0_SSTS(a) (a)
2850 #define arguments_BDK_SATAX_UAHC_P0_SSTS(a) (a),-1,-1,-1
2851
2852 /**
2853 * Register (NCB32b) sata#_uahc_p0_tfd
2854 *
2855 * SATA UAHC Task File Data Registers
2856 * Internal:
2857 * See DWC_ahsata databook v5.00.
2858 */
2859 union bdk_satax_uahc_p0_tfd
2860 {
2861 uint32_t u;
2862 struct bdk_satax_uahc_p0_tfd_s
2863 {
2864 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2865 uint32_t reserved_16_31 : 16;
2866 uint32_t tferr : 8; /**< [ 15: 8](RO) Copy of task-file error register. */
2867 uint32_t sts : 8; /**< [ 7: 0](RO/H) Copy of task-file status register.
2868 \<7\> = BSY: Indicates the interface is busy.
2869 \<6:4\> = Command specific.
2870 \<3\> = DRQ: Indicates a data transfer is requested.
2871 \<2:1\> = Command specific.
2872 \<0\> = ERR: Indicates an error during the transfer. */
2873 #else /* Word 0 - Little Endian */
2874 uint32_t sts : 8; /**< [ 7: 0](RO/H) Copy of task-file status register.
2875 \<7\> = BSY: Indicates the interface is busy.
2876 \<6:4\> = Command specific.
2877 \<3\> = DRQ: Indicates a data transfer is requested.
2878 \<2:1\> = Command specific.
2879 \<0\> = ERR: Indicates an error during the transfer. */
2880 uint32_t tferr : 8; /**< [ 15: 8](RO) Copy of task-file error register. */
2881 uint32_t reserved_16_31 : 16;
2882 #endif /* Word 0 - End */
2883 } s;
2884 /* struct bdk_satax_uahc_p0_tfd_s cn; */
2885 };
2886 typedef union bdk_satax_uahc_p0_tfd bdk_satax_uahc_p0_tfd_t;
2887
2888 static inline uint64_t BDK_SATAX_UAHC_P0_TFD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UAHC_P0_TFD(unsigned long a)2889 static inline uint64_t BDK_SATAX_UAHC_P0_TFD(unsigned long a)
2890 {
2891 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2892 return 0x810000000120ll + 0x1000000000ll * ((a) & 0x1);
2893 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2894 return 0x810000000120ll + 0x1000000000ll * ((a) & 0x7);
2895 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2896 return 0x810000000120ll + 0x1000000000ll * ((a) & 0xf);
2897 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2898 return 0x810000000120ll + 0x1000000000ll * ((a) & 0x3);
2899 __bdk_csr_fatal("SATAX_UAHC_P0_TFD", 1, a, 0, 0, 0);
2900 }
2901
2902 #define typedef_BDK_SATAX_UAHC_P0_TFD(a) bdk_satax_uahc_p0_tfd_t
2903 #define bustype_BDK_SATAX_UAHC_P0_TFD(a) BDK_CSR_TYPE_NCB32b
2904 #define basename_BDK_SATAX_UAHC_P0_TFD(a) "SATAX_UAHC_P0_TFD"
2905 #define device_bar_BDK_SATAX_UAHC_P0_TFD(a) 0x4 /* PF_BAR4 */
2906 #define busnum_BDK_SATAX_UAHC_P0_TFD(a) (a)
2907 #define arguments_BDK_SATAX_UAHC_P0_TFD(a) (a),-1,-1,-1
2908
2909 /**
2910 * Register (NCB) sata#_uctl_bist_status
2911 *
2912 * SATA UCTL BIST Status Register
2913 * Results from BIST runs of SATA's memories.
2914 * Wait for NDONE==0, then look at defect indication.
2915 *
2916 * Accessible always.
2917 *
2918 * Reset by NCB reset.
2919 */
2920 union bdk_satax_uctl_bist_status
2921 {
2922 uint64_t u;
2923 struct bdk_satax_uctl_bist_status_s
2924 {
2925 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2926 uint64_t reserved_42_63 : 22;
2927 uint64_t uctl_xm_r_bist_ndone : 1; /**< [ 41: 41](RO/H) BIST is not complete for the UCTL AxiMaster read-data FIFO. */
2928 uint64_t uctl_xm_w_bist_ndone : 1; /**< [ 40: 40](RO/H) BIST is not complete for the UCTL AxiMaster write-data FIFO. */
2929 uint64_t reserved_36_39 : 4;
2930 uint64_t uahc_p0_rxram_bist_ndone : 1;/**< [ 35: 35](RO/H) BIST is not complete for the UAHC Port 0 RxFIFO RAM. */
2931 uint64_t reserved_34 : 1;
2932 uint64_t uahc_p0_txram_bist_ndone : 1;/**< [ 33: 33](RO/H) BIST is not complete for the UAHC Port 0 TxFIFO RAM. */
2933 uint64_t reserved_10_32 : 23;
2934 uint64_t uctl_xm_r_bist_status : 1; /**< [ 9: 9](RO/H) BIST status of the UCTL AxiMaster read-data FIFO. */
2935 uint64_t uctl_xm_w_bist_status : 1; /**< [ 8: 8](RO/H) BIST status of the UCTL AxiMaster write-data FIFO. */
2936 uint64_t reserved_4_7 : 4;
2937 uint64_t uahc_p0_rxram_bist_status : 1;/**< [ 3: 3](RO/H) BIST status of the UAHC Port0 RxFIFO RAM. */
2938 uint64_t reserved_2 : 1;
2939 uint64_t uahc_p0_txram_bist_status : 1;/**< [ 1: 1](RO/H) BIST status of the UAHC Port0 TxFIFO RAM. */
2940 uint64_t reserved_0 : 1;
2941 #else /* Word 0 - Little Endian */
2942 uint64_t reserved_0 : 1;
2943 uint64_t uahc_p0_txram_bist_status : 1;/**< [ 1: 1](RO/H) BIST status of the UAHC Port0 TxFIFO RAM. */
2944 uint64_t reserved_2 : 1;
2945 uint64_t uahc_p0_rxram_bist_status : 1;/**< [ 3: 3](RO/H) BIST status of the UAHC Port0 RxFIFO RAM. */
2946 uint64_t reserved_4_7 : 4;
2947 uint64_t uctl_xm_w_bist_status : 1; /**< [ 8: 8](RO/H) BIST status of the UCTL AxiMaster write-data FIFO. */
2948 uint64_t uctl_xm_r_bist_status : 1; /**< [ 9: 9](RO/H) BIST status of the UCTL AxiMaster read-data FIFO. */
2949 uint64_t reserved_10_32 : 23;
2950 uint64_t uahc_p0_txram_bist_ndone : 1;/**< [ 33: 33](RO/H) BIST is not complete for the UAHC Port 0 TxFIFO RAM. */
2951 uint64_t reserved_34 : 1;
2952 uint64_t uahc_p0_rxram_bist_ndone : 1;/**< [ 35: 35](RO/H) BIST is not complete for the UAHC Port 0 RxFIFO RAM. */
2953 uint64_t reserved_36_39 : 4;
2954 uint64_t uctl_xm_w_bist_ndone : 1; /**< [ 40: 40](RO/H) BIST is not complete for the UCTL AxiMaster write-data FIFO. */
2955 uint64_t uctl_xm_r_bist_ndone : 1; /**< [ 41: 41](RO/H) BIST is not complete for the UCTL AxiMaster read-data FIFO. */
2956 uint64_t reserved_42_63 : 22;
2957 #endif /* Word 0 - End */
2958 } s;
2959 /* struct bdk_satax_uctl_bist_status_s cn; */
2960 };
2961 typedef union bdk_satax_uctl_bist_status bdk_satax_uctl_bist_status_t;
2962
2963 static inline uint64_t BDK_SATAX_UCTL_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_BIST_STATUS(unsigned long a)2964 static inline uint64_t BDK_SATAX_UCTL_BIST_STATUS(unsigned long a)
2965 {
2966 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2967 return 0x810000100008ll + 0x1000000000ll * ((a) & 0x1);
2968 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
2969 return 0x810000100008ll + 0x1000000000ll * ((a) & 0x7);
2970 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
2971 return 0x810000100008ll + 0x1000000000ll * ((a) & 0xf);
2972 __bdk_csr_fatal("SATAX_UCTL_BIST_STATUS", 1, a, 0, 0, 0);
2973 }
2974
2975 #define typedef_BDK_SATAX_UCTL_BIST_STATUS(a) bdk_satax_uctl_bist_status_t
2976 #define bustype_BDK_SATAX_UCTL_BIST_STATUS(a) BDK_CSR_TYPE_NCB
2977 #define basename_BDK_SATAX_UCTL_BIST_STATUS(a) "SATAX_UCTL_BIST_STATUS"
2978 #define device_bar_BDK_SATAX_UCTL_BIST_STATUS(a) 0x0 /* PF_BAR0 */
2979 #define busnum_BDK_SATAX_UCTL_BIST_STATUS(a) (a)
2980 #define arguments_BDK_SATAX_UCTL_BIST_STATUS(a) (a),-1,-1,-1
2981
2982 /**
2983 * Register (NCB) sata#_uctl_bp_test
2984 *
2985 * INTERNAL: SATA UCTL Backpressure Test Register
2986 */
2987 union bdk_satax_uctl_bp_test
2988 {
2989 uint64_t u;
2990 struct bdk_satax_uctl_bp_test_s
2991 {
2992 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2993 uint64_t enable : 4; /**< [ 63: 60](R/W) Enable test mode. For diagnostic use only.
2994 Internal:
2995 Once a bit is set, random backpressure is generated
2996 at the corresponding point to allow for more frequent backpressure.
2997 \<63\> = Reserved.
2998 \<62\> = When set, disables popping of NCBO FIFO, also credits won't be returned.
2999 \<61\> = When set, disables popping of NCBI FIFO, also credits won't be returned.
3000 \<60\> = When set, enables backpressure on the FPA(XPD) interface. */
3001 uint64_t reserved_24_59 : 36;
3002 uint64_t bp_cfg : 8; /**< [ 23: 16](R/W) Backpressure weight. For diagnostic use only.
3003 Internal:
3004 There are 2 backpressure configuration bits per enable, with the two bits
3005 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
3006 0x3=25% of the time.
3007 \<23:22\> = Reserved.
3008 \<21:20\> = Config 2.
3009 \<19:18\> = Config 1.
3010 \<17:16\> = Config 0. */
3011 uint64_t reserved_12_15 : 4;
3012 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
3013 #else /* Word 0 - Little Endian */
3014 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
3015 uint64_t reserved_12_15 : 4;
3016 uint64_t bp_cfg : 8; /**< [ 23: 16](R/W) Backpressure weight. For diagnostic use only.
3017 Internal:
3018 There are 2 backpressure configuration bits per enable, with the two bits
3019 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
3020 0x3=25% of the time.
3021 \<23:22\> = Reserved.
3022 \<21:20\> = Config 2.
3023 \<19:18\> = Config 1.
3024 \<17:16\> = Config 0. */
3025 uint64_t reserved_24_59 : 36;
3026 uint64_t enable : 4; /**< [ 63: 60](R/W) Enable test mode. For diagnostic use only.
3027 Internal:
3028 Once a bit is set, random backpressure is generated
3029 at the corresponding point to allow for more frequent backpressure.
3030 \<63\> = Reserved.
3031 \<62\> = When set, disables popping of NCBO FIFO, also credits won't be returned.
3032 \<61\> = When set, disables popping of NCBI FIFO, also credits won't be returned.
3033 \<60\> = When set, enables backpressure on the FPA(XPD) interface. */
3034 #endif /* Word 0 - End */
3035 } s;
3036 /* struct bdk_satax_uctl_bp_test_s cn; */
3037 };
3038 typedef union bdk_satax_uctl_bp_test bdk_satax_uctl_bp_test_t;
3039
3040 static inline uint64_t BDK_SATAX_UCTL_BP_TEST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_BP_TEST(unsigned long a)3041 static inline uint64_t BDK_SATAX_UCTL_BP_TEST(unsigned long a)
3042 {
3043 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
3044 return 0x810000100020ll + 0x1000000000ll * ((a) & 0x3);
3045 __bdk_csr_fatal("SATAX_UCTL_BP_TEST", 1, a, 0, 0, 0);
3046 }
3047
3048 #define typedef_BDK_SATAX_UCTL_BP_TEST(a) bdk_satax_uctl_bp_test_t
3049 #define bustype_BDK_SATAX_UCTL_BP_TEST(a) BDK_CSR_TYPE_NCB
3050 #define basename_BDK_SATAX_UCTL_BP_TEST(a) "SATAX_UCTL_BP_TEST"
3051 #define device_bar_BDK_SATAX_UCTL_BP_TEST(a) 0x4 /* PF_BAR4 */
3052 #define busnum_BDK_SATAX_UCTL_BP_TEST(a) (a)
3053 #define arguments_BDK_SATAX_UCTL_BP_TEST(a) (a),-1,-1,-1
3054
3055 /**
3056 * Register (NCB) sata#_uctl_cap_cfg
3057 *
3058 * SATA UCTL Capability Configuration Register
3059 * This register allows for overriding the advertised AHCI power management
3060 * capabilities, configuration registers, and unplug notifications to work around
3061 * hardware issues without modifying standard drivers. For diagnostic use only.
3062 */
3063 union bdk_satax_uctl_cap_cfg
3064 {
3065 uint64_t u;
3066 struct bdk_satax_uctl_cap_cfg_s
3067 {
3068 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3069 uint64_t or_ahci_cap_en : 1; /**< [ 63: 63](R/W) Enable overriding advertised AHCI power management capabilities. */
3070 uint64_t gbl_cap_salp : 1; /**< [ 62: 62](R/W) Override SATA()_UAHC_GBL_CAP[SALP]. */
3071 uint64_t gbl_cap_ssc : 1; /**< [ 61: 61](R/W) Override SATA()_UAHC_GBL_CAP[SSC]. */
3072 uint64_t gbl_cap2_sadm : 1; /**< [ 60: 60](R/W) Override SATA()_UAHC_GBL_CAP2[SADM]. */
3073 uint64_t gbl_cap2_sds : 1; /**< [ 59: 59](R/W) Override SATA()_UAHC_GBL_CAP2[SDS]. */
3074 uint64_t gbl_cap2_apst : 1; /**< [ 58: 58](R/W) Override SATA()_UAHC_GBL_CAP2[APST]. */
3075 uint64_t reserved_56_57 : 2;
3076 uint64_t or_ahci_pwr_en : 1; /**< [ 55: 55](R/W) Enable overriding programmed setting to AHCI power management config registers. */
3077 uint64_t sctl_ipm : 3; /**< [ 54: 52](R/W) Override SATA()_UAHC_P0_SCTL[IPM]. */
3078 uint64_t cmd_icc : 4; /**< [ 51: 48](R/W) Override SATA()_UAHC_P0_CMD[ICC]. */
3079 uint64_t cmd_asp : 1; /**< [ 47: 47](R/W) Override SATA()_UAHC_P0_CMD[ASP]. */
3080 uint64_t cmd_alpe : 1; /**< [ 46: 46](R/W) Override SATA()_UAHC_P0_CMD[ALPE]. */
3081 uint64_t cmd_apste : 1; /**< [ 45: 45](R/W) Override SATA()_UAHC_P0_CMD[APSTE]. */
3082 uint64_t reserved_40_44 : 5;
3083 uint64_t or_uahc_int_en : 1; /**< [ 39: 39](R/W) Enable overriding notification of unplug event to force the interrupts. */
3084 uint64_t p0_is_prcs : 1; /**< [ 38: 38](R/W) Override SATA()_UAHC_P0_IS[PRCS]. */
3085 uint64_t p0_serr_diag_n : 1; /**< [ 37: 37](R/W) Override SATA()_UAHC_P0_SERR[DIAG_N]. */
3086 uint64_t reserved_0_36 : 37;
3087 #else /* Word 0 - Little Endian */
3088 uint64_t reserved_0_36 : 37;
3089 uint64_t p0_serr_diag_n : 1; /**< [ 37: 37](R/W) Override SATA()_UAHC_P0_SERR[DIAG_N]. */
3090 uint64_t p0_is_prcs : 1; /**< [ 38: 38](R/W) Override SATA()_UAHC_P0_IS[PRCS]. */
3091 uint64_t or_uahc_int_en : 1; /**< [ 39: 39](R/W) Enable overriding notification of unplug event to force the interrupts. */
3092 uint64_t reserved_40_44 : 5;
3093 uint64_t cmd_apste : 1; /**< [ 45: 45](R/W) Override SATA()_UAHC_P0_CMD[APSTE]. */
3094 uint64_t cmd_alpe : 1; /**< [ 46: 46](R/W) Override SATA()_UAHC_P0_CMD[ALPE]. */
3095 uint64_t cmd_asp : 1; /**< [ 47: 47](R/W) Override SATA()_UAHC_P0_CMD[ASP]. */
3096 uint64_t cmd_icc : 4; /**< [ 51: 48](R/W) Override SATA()_UAHC_P0_CMD[ICC]. */
3097 uint64_t sctl_ipm : 3; /**< [ 54: 52](R/W) Override SATA()_UAHC_P0_SCTL[IPM]. */
3098 uint64_t or_ahci_pwr_en : 1; /**< [ 55: 55](R/W) Enable overriding programmed setting to AHCI power management config registers. */
3099 uint64_t reserved_56_57 : 2;
3100 uint64_t gbl_cap2_apst : 1; /**< [ 58: 58](R/W) Override SATA()_UAHC_GBL_CAP2[APST]. */
3101 uint64_t gbl_cap2_sds : 1; /**< [ 59: 59](R/W) Override SATA()_UAHC_GBL_CAP2[SDS]. */
3102 uint64_t gbl_cap2_sadm : 1; /**< [ 60: 60](R/W) Override SATA()_UAHC_GBL_CAP2[SADM]. */
3103 uint64_t gbl_cap_ssc : 1; /**< [ 61: 61](R/W) Override SATA()_UAHC_GBL_CAP[SSC]. */
3104 uint64_t gbl_cap_salp : 1; /**< [ 62: 62](R/W) Override SATA()_UAHC_GBL_CAP[SALP]. */
3105 uint64_t or_ahci_cap_en : 1; /**< [ 63: 63](R/W) Enable overriding advertised AHCI power management capabilities. */
3106 #endif /* Word 0 - End */
3107 } s;
3108 /* struct bdk_satax_uctl_cap_cfg_s cn; */
3109 };
3110 typedef union bdk_satax_uctl_cap_cfg bdk_satax_uctl_cap_cfg_t;
3111
3112 static inline uint64_t BDK_SATAX_UCTL_CAP_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_CAP_CFG(unsigned long a)3113 static inline uint64_t BDK_SATAX_UCTL_CAP_CFG(unsigned long a)
3114 {
3115 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
3116 return 0x8100001000e0ll + 0x1000000000ll * ((a) & 0x3);
3117 __bdk_csr_fatal("SATAX_UCTL_CAP_CFG", 1, a, 0, 0, 0);
3118 }
3119
3120 #define typedef_BDK_SATAX_UCTL_CAP_CFG(a) bdk_satax_uctl_cap_cfg_t
3121 #define bustype_BDK_SATAX_UCTL_CAP_CFG(a) BDK_CSR_TYPE_NCB
3122 #define basename_BDK_SATAX_UCTL_CAP_CFG(a) "SATAX_UCTL_CAP_CFG"
3123 #define device_bar_BDK_SATAX_UCTL_CAP_CFG(a) 0x4 /* PF_BAR4 */
3124 #define busnum_BDK_SATAX_UCTL_CAP_CFG(a) (a)
3125 #define arguments_BDK_SATAX_UCTL_CAP_CFG(a) (a),-1,-1,-1
3126
3127 /**
3128 * Register (NCB) sata#_uctl_const
3129 *
3130 * SATA UCTL Constants Register
3131 * This register contains constants for software discovery.
3132 */
3133 union bdk_satax_uctl_const
3134 {
3135 uint64_t u;
3136 struct bdk_satax_uctl_const_s
3137 {
3138 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3139 uint64_t reserved_0_63 : 64;
3140 #else /* Word 0 - Little Endian */
3141 uint64_t reserved_0_63 : 64;
3142 #endif /* Word 0 - End */
3143 } s;
3144 /* struct bdk_satax_uctl_const_s cn; */
3145 };
3146 typedef union bdk_satax_uctl_const bdk_satax_uctl_const_t;
3147
3148 static inline uint64_t BDK_SATAX_UCTL_CONST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_CONST(unsigned long a)3149 static inline uint64_t BDK_SATAX_UCTL_CONST(unsigned long a)
3150 {
3151 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
3152 return 0x810000100028ll + 0x1000000000ll * ((a) & 0x3);
3153 __bdk_csr_fatal("SATAX_UCTL_CONST", 1, a, 0, 0, 0);
3154 }
3155
3156 #define typedef_BDK_SATAX_UCTL_CONST(a) bdk_satax_uctl_const_t
3157 #define bustype_BDK_SATAX_UCTL_CONST(a) BDK_CSR_TYPE_NCB
3158 #define basename_BDK_SATAX_UCTL_CONST(a) "SATAX_UCTL_CONST"
3159 #define device_bar_BDK_SATAX_UCTL_CONST(a) 0x4 /* PF_BAR4 */
3160 #define busnum_BDK_SATAX_UCTL_CONST(a) (a)
3161 #define arguments_BDK_SATAX_UCTL_CONST(a) (a),-1,-1,-1
3162
3163 /**
3164 * Register (NCB) sata#_uctl_csclk_active_pc
3165 *
3166 * SATA UCTL Conditional Sclk Clock Counter Register
3167 * This register count csclk clock cycle.
3168 * Reset by NCB reset.
3169 */
3170 union bdk_satax_uctl_csclk_active_pc
3171 {
3172 uint64_t u;
3173 struct bdk_satax_uctl_csclk_active_pc_s
3174 {
3175 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3176 uint64_t count : 64; /**< [ 63: 0](R/W/H) Counts conditional clock active cycles since reset. */
3177 #else /* Word 0 - Little Endian */
3178 uint64_t count : 64; /**< [ 63: 0](R/W/H) Counts conditional clock active cycles since reset. */
3179 #endif /* Word 0 - End */
3180 } s;
3181 /* struct bdk_satax_uctl_csclk_active_pc_s cn; */
3182 };
3183 typedef union bdk_satax_uctl_csclk_active_pc bdk_satax_uctl_csclk_active_pc_t;
3184
3185 static inline uint64_t BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(unsigned long a)3186 static inline uint64_t BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(unsigned long a)
3187 {
3188 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
3189 return 0x810000100018ll + 0x1000000000ll * ((a) & 0x3);
3190 __bdk_csr_fatal("SATAX_UCTL_CSCLK_ACTIVE_PC", 1, a, 0, 0, 0);
3191 }
3192
3193 #define typedef_BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(a) bdk_satax_uctl_csclk_active_pc_t
3194 #define bustype_BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(a) BDK_CSR_TYPE_NCB
3195 #define basename_BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(a) "SATAX_UCTL_CSCLK_ACTIVE_PC"
3196 #define device_bar_BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(a) 0x4 /* PF_BAR4 */
3197 #define busnum_BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(a) (a)
3198 #define arguments_BDK_SATAX_UCTL_CSCLK_ACTIVE_PC(a) (a),-1,-1,-1
3199
3200 /**
3201 * Register (NCB) sata#_uctl_ctl
3202 *
3203 * SATA UCTL Control Register
3204 * This register controls clocks, resets, power, and BIST for the SATA.
3205 *
3206 * Accessible always.
3207 *
3208 * Reset by NCB reset.
3209 */
3210 union bdk_satax_uctl_ctl
3211 {
3212 uint64_t u;
3213 struct bdk_satax_uctl_ctl_s
3214 {
3215 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3216 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. There are two major modes of BIST: FULL and CLEAR.
3217 0 = FULL BIST is run by the BIST state machine.
3218 1 = CLEAR BIST is run by the BIST state machine. A clear-BIST run clears all entries in
3219 SATA RAMs to 0x0.
3220
3221 To avoid race conditions, software must first perform a CSR write operation that puts
3222 [CLEAR_BIST] into the correct state and then perform another CSR write operation to set
3223 [START_BIST] (keeping [CLEAR_BIST] constant). CLEAR BIST completion is indicated by
3224 SATA()_UCTL_BIST_STATUS[NDONE*] clear.
3225
3226 A BIST clear operation takes almost 2,000 host-controller clock cycles for the largest
3227 RAM. */
3228 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Start BIST. The rising edge starts BIST on the memories in SATA. To run BIST, the host-
3229 controller clock must be both configured and enabled, and should be configured to the
3230 maximum available frequency given the available coprocessor clock and dividers.
3231
3232 Refer to Cold Reset for clock initialization procedures. BIST defect status can
3233 be checked after FULL BIST completion, both of which are indicated in
3234 SATA()_UCTL_BIST_STATUS. The FULL BIST run takes almost 80,000 host-controller
3235 clock cycles for the largest RAM. */
3236 uint64_t reserved_32_61 : 30;
3237 uint64_t cmd_flr_en : 1; /**< [ 31: 31](R/W) Select an option for doing SATA FLR based on finishing existing commands or DMA transactions.
3238 0 = DMA-base FLR.
3239 1 = Command-base FLR.
3240
3241 Command-base option will require AHCI software to read SATA()_UAHC_P0_CI to make sure there is
3242 no more command to process, then proceed FLR by negating PCC master enable signal.
3243
3244 This option has to be set before PCC master enable negates. Futher commands write to
3245 SATA()_UAHC_P0_CI after this bit is set will not be executed.
3246
3247 To check if commands have finished, read SATA()_UCTL_CTL[CMD_FLR_DONE]. */
3248 uint64_t a_clk_en : 1; /**< [ 30: 30](R/W) Host-controller clock enable. When set to one, the host-controller clock is generated. This
3249 also enables access to UCTL registers 0x30-0xF8. */
3250 uint64_t a_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the host-controller clock divider.
3251 0 = Use the divided coprocessor clock from the [A_CLKDIV_SEL] divider.
3252 1 = use the bypass clock from the GPIO pins (generally bypass is only used for scan
3253 purposes).
3254
3255 This signal is a multiplexer-select signal; it does not enable the host-controller clock.
3256 You must set [A_CLK_EN] separately. [A_CLK_BYP_SEL] select should not be changed unless
3257 [A_CLK_EN] is disabled. The bypass clock can be selected and running even if the host-
3258 controller clock dividers are not running. */
3259 uint64_t a_clkdiv_rst : 1; /**< [ 28: 28](R/W) Host-controller-clock divider reset. Divided clocks are not generated while the divider is
3260 being reset.
3261 This also resets the suspend-clock divider. */
3262 uint64_t cmd_flr_done : 1; /**< [ 27: 27](RO/H) This bit tells you if commands set before SATA()_UCTL_CTL[CMD_FLR_EN] are finished or not.
3263 This bit is only valid after SATA()_UCTL_CTL[CMD_FLR_EN] is set. */
3264 uint64_t a_clkdiv_sel : 3; /**< [ 26: 24](R/W) The host-controller clock frequency is the coprocessor-clock frequency divided by
3265 [A_CLKDIV_SEL]. The host-controller clock frequency must be at or below 333MHz.
3266 This field can be changed only when [A_CLKDIV_RST] = 1. The divider values are the
3267 following:
3268 0x0 = divide by 1.
3269 0x1 = divide by 2.
3270 0x2 = divide by 3.
3271 0x3 = divide by 4.
3272 0x4 = divide by 6.
3273 0x5 = divide by 8.
3274 0x6 = divide by 16.
3275 0x7 = divide by 24. */
3276 uint64_t reserved_6_23 : 18;
3277 uint64_t dma_psn_ign : 1; /**< [ 5: 5](R/W) Handling of poison indication on DMA read responses.
3278 0 = Treat poison data the same way as fault, sending an AXI error to the SATA
3279 controller.
3280 1 = Ignore poison and proceed with the transaction as if no problems. */
3281 uint64_t reserved_2_4 : 3;
3282 uint64_t sata_uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
3283 Internal:
3284 Note that soft-resetting the UAHC while it is active may cause violations of RSL
3285 or NCB protocols. */
3286 uint64_t sata_uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high. Resets UAHC DMA and register shims and the UCTL
3287 registers 0x10_0030-0x10_00F8.
3288
3289 It does not reset UCTL registers 0x10_0000-0x10_0028.
3290
3291 The UCTL registers starting from 0x10_0030 can be accessed only after the host-controller
3292 clock is active and [SATA_UCTL_RST] is deasserted.
3293
3294 Internal:
3295 Note that soft-resetting the UCTL while it is active may cause violations of
3296 RSL, NCB, and GIB protocols. */
3297 #else /* Word 0 - Little Endian */
3298 uint64_t sata_uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high. Resets UAHC DMA and register shims and the UCTL
3299 registers 0x10_0030-0x10_00F8.
3300
3301 It does not reset UCTL registers 0x10_0000-0x10_0028.
3302
3303 The UCTL registers starting from 0x10_0030 can be accessed only after the host-controller
3304 clock is active and [SATA_UCTL_RST] is deasserted.
3305
3306 Internal:
3307 Note that soft-resetting the UCTL while it is active may cause violations of
3308 RSL, NCB, and GIB protocols. */
3309 uint64_t sata_uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
3310 Internal:
3311 Note that soft-resetting the UAHC while it is active may cause violations of RSL
3312 or NCB protocols. */
3313 uint64_t reserved_2_4 : 3;
3314 uint64_t dma_psn_ign : 1; /**< [ 5: 5](R/W) Handling of poison indication on DMA read responses.
3315 0 = Treat poison data the same way as fault, sending an AXI error to the SATA
3316 controller.
3317 1 = Ignore poison and proceed with the transaction as if no problems. */
3318 uint64_t reserved_6_23 : 18;
3319 uint64_t a_clkdiv_sel : 3; /**< [ 26: 24](R/W) The host-controller clock frequency is the coprocessor-clock frequency divided by
3320 [A_CLKDIV_SEL]. The host-controller clock frequency must be at or below 333MHz.
3321 This field can be changed only when [A_CLKDIV_RST] = 1. The divider values are the
3322 following:
3323 0x0 = divide by 1.
3324 0x1 = divide by 2.
3325 0x2 = divide by 3.
3326 0x3 = divide by 4.
3327 0x4 = divide by 6.
3328 0x5 = divide by 8.
3329 0x6 = divide by 16.
3330 0x7 = divide by 24. */
3331 uint64_t cmd_flr_done : 1; /**< [ 27: 27](RO/H) This bit tells you if commands set before SATA()_UCTL_CTL[CMD_FLR_EN] are finished or not.
3332 This bit is only valid after SATA()_UCTL_CTL[CMD_FLR_EN] is set. */
3333 uint64_t a_clkdiv_rst : 1; /**< [ 28: 28](R/W) Host-controller-clock divider reset. Divided clocks are not generated while the divider is
3334 being reset.
3335 This also resets the suspend-clock divider. */
3336 uint64_t a_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the host-controller clock divider.
3337 0 = Use the divided coprocessor clock from the [A_CLKDIV_SEL] divider.
3338 1 = use the bypass clock from the GPIO pins (generally bypass is only used for scan
3339 purposes).
3340
3341 This signal is a multiplexer-select signal; it does not enable the host-controller clock.
3342 You must set [A_CLK_EN] separately. [A_CLK_BYP_SEL] select should not be changed unless
3343 [A_CLK_EN] is disabled. The bypass clock can be selected and running even if the host-
3344 controller clock dividers are not running. */
3345 uint64_t a_clk_en : 1; /**< [ 30: 30](R/W) Host-controller clock enable. When set to one, the host-controller clock is generated. This
3346 also enables access to UCTL registers 0x30-0xF8. */
3347 uint64_t cmd_flr_en : 1; /**< [ 31: 31](R/W) Select an option for doing SATA FLR based on finishing existing commands or DMA transactions.
3348 0 = DMA-base FLR.
3349 1 = Command-base FLR.
3350
3351 Command-base option will require AHCI software to read SATA()_UAHC_P0_CI to make sure there is
3352 no more command to process, then proceed FLR by negating PCC master enable signal.
3353
3354 This option has to be set before PCC master enable negates. Futher commands write to
3355 SATA()_UAHC_P0_CI after this bit is set will not be executed.
3356
3357 To check if commands have finished, read SATA()_UCTL_CTL[CMD_FLR_DONE]. */
3358 uint64_t reserved_32_61 : 30;
3359 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Start BIST. The rising edge starts BIST on the memories in SATA. To run BIST, the host-
3360 controller clock must be both configured and enabled, and should be configured to the
3361 maximum available frequency given the available coprocessor clock and dividers.
3362
3363 Refer to Cold Reset for clock initialization procedures. BIST defect status can
3364 be checked after FULL BIST completion, both of which are indicated in
3365 SATA()_UCTL_BIST_STATUS. The FULL BIST run takes almost 80,000 host-controller
3366 clock cycles for the largest RAM. */
3367 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. There are two major modes of BIST: FULL and CLEAR.
3368 0 = FULL BIST is run by the BIST state machine.
3369 1 = CLEAR BIST is run by the BIST state machine. A clear-BIST run clears all entries in
3370 SATA RAMs to 0x0.
3371
3372 To avoid race conditions, software must first perform a CSR write operation that puts
3373 [CLEAR_BIST] into the correct state and then perform another CSR write operation to set
3374 [START_BIST] (keeping [CLEAR_BIST] constant). CLEAR BIST completion is indicated by
3375 SATA()_UCTL_BIST_STATUS[NDONE*] clear.
3376
3377 A BIST clear operation takes almost 2,000 host-controller clock cycles for the largest
3378 RAM. */
3379 #endif /* Word 0 - End */
3380 } s;
3381 struct bdk_satax_uctl_ctl_cn8
3382 {
3383 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3384 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. There are two major modes of BIST: FULL and CLEAR.
3385 0 = FULL BIST is run by the BIST state machine.
3386 1 = CLEAR BIST is run by the BIST state machine. A clear-BIST run clears all entries in
3387 SATA RAMs to 0x0.
3388
3389 To avoid race conditions, software must first perform a CSR write operation that puts
3390 [CLEAR_BIST] into the correct state and then perform another CSR write operation to set
3391 [START_BIST] (keeping [CLEAR_BIST] constant). CLEAR BIST completion is indicated by
3392 SATA()_UCTL_BIST_STATUS[NDONE*] clear.
3393
3394 A BIST clear operation takes almost 2,000 host-controller clock cycles for the largest
3395 RAM. */
3396 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Start BIST. The rising edge starts BIST on the memories in SATA. To run BIST, the host-
3397 controller clock must be both configured and enabled, and should be configured to the
3398 maximum available frequency given the available coprocessor clock and dividers.
3399
3400 Refer to Cold Reset for clock initialization procedures. BIST defect status can
3401 be checked after FULL BIST completion, both of which are indicated in
3402 SATA()_UCTL_BIST_STATUS. The FULL BIST run takes almost 80,000 host-controller
3403 clock cycles for the largest RAM. */
3404 uint64_t reserved_31_61 : 31;
3405 uint64_t a_clk_en : 1; /**< [ 30: 30](R/W) Host-controller clock enable. When set to one, the host-controller clock is generated. This
3406 also enables access to UCTL registers 0x30-0xF8. */
3407 uint64_t a_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the host-controller clock divider.
3408 0 = Use the divided coprocessor clock from the [A_CLKDIV_SEL] divider.
3409 1 = use the bypass clock from the GPIO pins (generally bypass is only used for scan
3410 purposes).
3411
3412 This signal is a multiplexer-select signal; it does not enable the host-controller clock.
3413 You must set [A_CLK_EN] separately. [A_CLK_BYP_SEL] select should not be changed unless
3414 [A_CLK_EN] is disabled. The bypass clock can be selected and running even if the host-
3415 controller clock dividers are not running. */
3416 uint64_t a_clkdiv_rst : 1; /**< [ 28: 28](R/W) Host-controller-clock divider reset. Divided clocks are not generated while the divider is
3417 being reset.
3418 This also resets the suspend-clock divider. */
3419 uint64_t reserved_27 : 1;
3420 uint64_t a_clkdiv_sel : 3; /**< [ 26: 24](R/W) The host-controller clock frequency is the coprocessor-clock frequency divided by
3421 [A_CLKDIV_SEL]. The host-controller clock frequency must be at or below 333MHz.
3422 This field can be changed only when [A_CLKDIV_RST] = 1. The divider values are the
3423 following:
3424 0x0 = divide by 1.
3425 0x1 = divide by 2.
3426 0x2 = divide by 3.
3427 0x3 = divide by 4.
3428 0x4 = divide by 6.
3429 0x5 = divide by 8.
3430 0x6 = divide by 16.
3431 0x7 = divide by 24. */
3432 uint64_t reserved_5_23 : 19;
3433 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the SATA UCTL interface clock (coprocessor clock). This enables access to UAHC
3434 registers via the NCB, as well as UCTL registers starting from 0x10_0030. */
3435 uint64_t reserved_2_3 : 2;
3436 uint64_t sata_uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
3437 Internal:
3438 Note that soft-resetting the UAHC while it is active may cause violations of RSL
3439 or NCB protocols. */
3440 uint64_t sata_uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high. Resets UAHC DMA and register shims and the UCTL
3441 registers 0x10_0030-0x10_00F8.
3442
3443 It does not reset UCTL registers 0x10_0000-0x10_0028.
3444
3445 The UCTL registers starting from 0x10_0030 can be accessed only after the host-controller
3446 clock is active and [SATA_UCTL_RST] is deasserted.
3447
3448 Internal:
3449 Note that soft-resetting the UCTL while it is active may cause violations of
3450 RSL, NCB, and GIB protocols. */
3451 #else /* Word 0 - Little Endian */
3452 uint64_t sata_uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high. Resets UAHC DMA and register shims and the UCTL
3453 registers 0x10_0030-0x10_00F8.
3454
3455 It does not reset UCTL registers 0x10_0000-0x10_0028.
3456
3457 The UCTL registers starting from 0x10_0030 can be accessed only after the host-controller
3458 clock is active and [SATA_UCTL_RST] is deasserted.
3459
3460 Internal:
3461 Note that soft-resetting the UCTL while it is active may cause violations of
3462 RSL, NCB, and GIB protocols. */
3463 uint64_t sata_uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
3464 Internal:
3465 Note that soft-resetting the UAHC while it is active may cause violations of RSL
3466 or NCB protocols. */
3467 uint64_t reserved_2_3 : 2;
3468 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the SATA UCTL interface clock (coprocessor clock). This enables access to UAHC
3469 registers via the NCB, as well as UCTL registers starting from 0x10_0030. */
3470 uint64_t reserved_5_23 : 19;
3471 uint64_t a_clkdiv_sel : 3; /**< [ 26: 24](R/W) The host-controller clock frequency is the coprocessor-clock frequency divided by
3472 [A_CLKDIV_SEL]. The host-controller clock frequency must be at or below 333MHz.
3473 This field can be changed only when [A_CLKDIV_RST] = 1. The divider values are the
3474 following:
3475 0x0 = divide by 1.
3476 0x1 = divide by 2.
3477 0x2 = divide by 3.
3478 0x3 = divide by 4.
3479 0x4 = divide by 6.
3480 0x5 = divide by 8.
3481 0x6 = divide by 16.
3482 0x7 = divide by 24. */
3483 uint64_t reserved_27 : 1;
3484 uint64_t a_clkdiv_rst : 1; /**< [ 28: 28](R/W) Host-controller-clock divider reset. Divided clocks are not generated while the divider is
3485 being reset.
3486 This also resets the suspend-clock divider. */
3487 uint64_t a_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the host-controller clock divider.
3488 0 = Use the divided coprocessor clock from the [A_CLKDIV_SEL] divider.
3489 1 = use the bypass clock from the GPIO pins (generally bypass is only used for scan
3490 purposes).
3491
3492 This signal is a multiplexer-select signal; it does not enable the host-controller clock.
3493 You must set [A_CLK_EN] separately. [A_CLK_BYP_SEL] select should not be changed unless
3494 [A_CLK_EN] is disabled. The bypass clock can be selected and running even if the host-
3495 controller clock dividers are not running. */
3496 uint64_t a_clk_en : 1; /**< [ 30: 30](R/W) Host-controller clock enable. When set to one, the host-controller clock is generated. This
3497 also enables access to UCTL registers 0x30-0xF8. */
3498 uint64_t reserved_31_61 : 31;
3499 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Start BIST. The rising edge starts BIST on the memories in SATA. To run BIST, the host-
3500 controller clock must be both configured and enabled, and should be configured to the
3501 maximum available frequency given the available coprocessor clock and dividers.
3502
3503 Refer to Cold Reset for clock initialization procedures. BIST defect status can
3504 be checked after FULL BIST completion, both of which are indicated in
3505 SATA()_UCTL_BIST_STATUS. The FULL BIST run takes almost 80,000 host-controller
3506 clock cycles for the largest RAM. */
3507 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. There are two major modes of BIST: FULL and CLEAR.
3508 0 = FULL BIST is run by the BIST state machine.
3509 1 = CLEAR BIST is run by the BIST state machine. A clear-BIST run clears all entries in
3510 SATA RAMs to 0x0.
3511
3512 To avoid race conditions, software must first perform a CSR write operation that puts
3513 [CLEAR_BIST] into the correct state and then perform another CSR write operation to set
3514 [START_BIST] (keeping [CLEAR_BIST] constant). CLEAR BIST completion is indicated by
3515 SATA()_UCTL_BIST_STATUS[NDONE*] clear.
3516
3517 A BIST clear operation takes almost 2,000 host-controller clock cycles for the largest
3518 RAM. */
3519 #endif /* Word 0 - End */
3520 } cn8;
3521 struct bdk_satax_uctl_ctl_cn9
3522 {
3523 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3524 uint64_t reserved_32_63 : 32;
3525 uint64_t cmd_flr_en : 1; /**< [ 31: 31](R/W) Select an option for doing SATA FLR based on finishing existing commands or DMA transactions.
3526 0 = DMA-base FLR.
3527 1 = Command-base FLR.
3528
3529 Command-base option will require AHCI software to read SATA()_UAHC_P0_CI to make sure there is
3530 no more command to process, then proceed FLR by negating PCC master enable signal.
3531
3532 This option has to be set before PCC master enable negates. Futher commands write to
3533 SATA()_UAHC_P0_CI after this bit is set will not be executed.
3534
3535 To check if commands have finished, read SATA()_UCTL_CTL[CMD_FLR_DONE]. */
3536 uint64_t a_clk_en : 1; /**< [ 30: 30](R/W) Host-controller clock enable. When set to one, the host-controller clock is generated. This
3537 also enables access to UCTL registers 0x30-0xF8. */
3538 uint64_t a_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the host-controller clock divider.
3539 0 = Use the divided coprocessor clock from the [A_CLKDIV_SEL] divider.
3540 1 = use the bypass clock from the GPIO pins (generally bypass is only used for scan
3541 purposes).
3542
3543 This signal is a multiplexer-select signal; it does not enable the host-controller clock.
3544 You must set [A_CLK_EN] separately. [A_CLK_BYP_SEL] select should not be changed unless
3545 [A_CLK_EN] is disabled. The bypass clock can be selected and running even if the host-
3546 controller clock dividers are not running. */
3547 uint64_t a_clkdiv_rst : 1; /**< [ 28: 28](R/W) Host-controller-clock divider reset. Divided clocks are not generated while the divider is
3548 being reset.
3549 This also resets the suspend-clock divider. */
3550 uint64_t cmd_flr_done : 1; /**< [ 27: 27](RO/H) This bit tells you if commands set before SATA()_UCTL_CTL[CMD_FLR_EN] are finished or not.
3551 This bit is only valid after SATA()_UCTL_CTL[CMD_FLR_EN] is set. */
3552 uint64_t a_clkdiv_sel : 3; /**< [ 26: 24](R/W) The host-controller clock frequency is the coprocessor-clock frequency divided by
3553 [A_CLKDIV_SEL]. The host-controller clock frequency must be at or below 333MHz.
3554 This field can be changed only when [A_CLKDIV_RST] = 1. The divider values are the
3555 following:
3556 0x0 = divide by 1.
3557 0x1 = divide by 2.
3558 0x2 = divide by 3.
3559 0x3 = divide by 4.
3560 0x4 = divide by 6.
3561 0x5 = divide by 8.
3562 0x6 = divide by 16.
3563 0x7 = divide by 24. */
3564 uint64_t reserved_6_23 : 18;
3565 uint64_t dma_psn_ign : 1; /**< [ 5: 5](R/W) Handling of poison indication on DMA read responses.
3566 0 = Treat poison data the same way as fault, sending an AXI error to the SATA
3567 controller.
3568 1 = Ignore poison and proceed with the transaction as if no problems. */
3569 uint64_t csclk_force : 1; /**< [ 4: 4](R/W) Force conditional clock to be running. For diagnostic use only.
3570 0 = No override.
3571 1 = Override the enable of conditional clock to force it running. */
3572 uint64_t reserved_2_3 : 2;
3573 uint64_t sata_uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
3574 Internal:
3575 Note that soft-resetting the UAHC while it is active may cause violations of RSL
3576 or NCB protocols. */
3577 uint64_t sata_uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high. Resets UAHC DMA and register shims and the UCTL
3578 registers 0x10_0030-0x10_00F8.
3579
3580 It does not reset UCTL registers 0x10_0000-0x10_0028. These can be accessed when
3581 [SATA_UCTL_RST] is asserted.
3582
3583 The UCTL registers starting from 0x10_0030 can be accessed only after the host-controller
3584 clock is active and [SATA_UCTL_RST] is deasserted.
3585
3586 Internal:
3587 Note that soft-resetting the UCTL while it is active may cause violations of
3588 RSL, NCB, and GIB protocols. */
3589 #else /* Word 0 - Little Endian */
3590 uint64_t sata_uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high. Resets UAHC DMA and register shims and the UCTL
3591 registers 0x10_0030-0x10_00F8.
3592
3593 It does not reset UCTL registers 0x10_0000-0x10_0028. These can be accessed when
3594 [SATA_UCTL_RST] is asserted.
3595
3596 The UCTL registers starting from 0x10_0030 can be accessed only after the host-controller
3597 clock is active and [SATA_UCTL_RST] is deasserted.
3598
3599 Internal:
3600 Note that soft-resetting the UCTL while it is active may cause violations of
3601 RSL, NCB, and GIB protocols. */
3602 uint64_t sata_uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
3603 Internal:
3604 Note that soft-resetting the UAHC while it is active may cause violations of RSL
3605 or NCB protocols. */
3606 uint64_t reserved_2_3 : 2;
3607 uint64_t csclk_force : 1; /**< [ 4: 4](R/W) Force conditional clock to be running. For diagnostic use only.
3608 0 = No override.
3609 1 = Override the enable of conditional clock to force it running. */
3610 uint64_t dma_psn_ign : 1; /**< [ 5: 5](R/W) Handling of poison indication on DMA read responses.
3611 0 = Treat poison data the same way as fault, sending an AXI error to the SATA
3612 controller.
3613 1 = Ignore poison and proceed with the transaction as if no problems. */
3614 uint64_t reserved_6_23 : 18;
3615 uint64_t a_clkdiv_sel : 3; /**< [ 26: 24](R/W) The host-controller clock frequency is the coprocessor-clock frequency divided by
3616 [A_CLKDIV_SEL]. The host-controller clock frequency must be at or below 333MHz.
3617 This field can be changed only when [A_CLKDIV_RST] = 1. The divider values are the
3618 following:
3619 0x0 = divide by 1.
3620 0x1 = divide by 2.
3621 0x2 = divide by 3.
3622 0x3 = divide by 4.
3623 0x4 = divide by 6.
3624 0x5 = divide by 8.
3625 0x6 = divide by 16.
3626 0x7 = divide by 24. */
3627 uint64_t cmd_flr_done : 1; /**< [ 27: 27](RO/H) This bit tells you if commands set before SATA()_UCTL_CTL[CMD_FLR_EN] are finished or not.
3628 This bit is only valid after SATA()_UCTL_CTL[CMD_FLR_EN] is set. */
3629 uint64_t a_clkdiv_rst : 1; /**< [ 28: 28](R/W) Host-controller-clock divider reset. Divided clocks are not generated while the divider is
3630 being reset.
3631 This also resets the suspend-clock divider. */
3632 uint64_t a_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the host-controller clock divider.
3633 0 = Use the divided coprocessor clock from the [A_CLKDIV_SEL] divider.
3634 1 = use the bypass clock from the GPIO pins (generally bypass is only used for scan
3635 purposes).
3636
3637 This signal is a multiplexer-select signal; it does not enable the host-controller clock.
3638 You must set [A_CLK_EN] separately. [A_CLK_BYP_SEL] select should not be changed unless
3639 [A_CLK_EN] is disabled. The bypass clock can be selected and running even if the host-
3640 controller clock dividers are not running. */
3641 uint64_t a_clk_en : 1; /**< [ 30: 30](R/W) Host-controller clock enable. When set to one, the host-controller clock is generated. This
3642 also enables access to UCTL registers 0x30-0xF8. */
3643 uint64_t cmd_flr_en : 1; /**< [ 31: 31](R/W) Select an option for doing SATA FLR based on finishing existing commands or DMA transactions.
3644 0 = DMA-base FLR.
3645 1 = Command-base FLR.
3646
3647 Command-base option will require AHCI software to read SATA()_UAHC_P0_CI to make sure there is
3648 no more command to process, then proceed FLR by negating PCC master enable signal.
3649
3650 This option has to be set before PCC master enable negates. Futher commands write to
3651 SATA()_UAHC_P0_CI after this bit is set will not be executed.
3652
3653 To check if commands have finished, read SATA()_UCTL_CTL[CMD_FLR_DONE]. */
3654 uint64_t reserved_32_63 : 32;
3655 #endif /* Word 0 - End */
3656 } cn9;
3657 };
3658 typedef union bdk_satax_uctl_ctl bdk_satax_uctl_ctl_t;
3659
3660 static inline uint64_t BDK_SATAX_UCTL_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_CTL(unsigned long a)3661 static inline uint64_t BDK_SATAX_UCTL_CTL(unsigned long a)
3662 {
3663 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3664 return 0x810000100000ll + 0x1000000000ll * ((a) & 0x1);
3665 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
3666 return 0x810000100000ll + 0x1000000000ll * ((a) & 0x7);
3667 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
3668 return 0x810000100000ll + 0x1000000000ll * ((a) & 0xf);
3669 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
3670 return 0x810000100000ll + 0x1000000000ll * ((a) & 0x3);
3671 __bdk_csr_fatal("SATAX_UCTL_CTL", 1, a, 0, 0, 0);
3672 }
3673
3674 #define typedef_BDK_SATAX_UCTL_CTL(a) bdk_satax_uctl_ctl_t
3675 #define bustype_BDK_SATAX_UCTL_CTL(a) BDK_CSR_TYPE_NCB
3676 #define basename_BDK_SATAX_UCTL_CTL(a) "SATAX_UCTL_CTL"
3677 #define device_bar_BDK_SATAX_UCTL_CTL(a) 0x4 /* PF_BAR4 */
3678 #define busnum_BDK_SATAX_UCTL_CTL(a) (a)
3679 #define arguments_BDK_SATAX_UCTL_CTL(a) (a),-1,-1,-1
3680
3681 /**
3682 * Register (NCB) sata#_uctl_ecc
3683 *
3684 * SATA UCTL ECC Control/Debug Register
3685 * This register can be used to disable ECC correction, insert ECC errors, and debug ECC
3686 * failures.
3687 *
3688 * Fields ECC_ERR* are captured when there are no outstanding ECC errors indicated in INTSTAT
3689 * and a new ECC error arrives. Prioritization for multiple events occurring on the same cycle is
3690 * indicated by the ECC_ERR_SOURCE enumeration: highest encoded value has highest priority.
3691 *
3692 * Fields *ECC_DIS: Disables ECC correction, SBE and DBE errors are still reported.
3693 * If ECC_DIS is 0x1, then no data-correction occurs.
3694 *
3695 * Fields *ECC_FLIP_SYND: Flip the syndrom[1:0] bits to generate 1-bit/2-bits error for testing.
3696 *
3697 * Accessible only when SATA()_UCTL_CTL[A_CLK_EN].
3698 *
3699 * Reset by NCB reset or SATA()_UCTL_CTL[SATA_UCTL_RST].
3700 */
3701 union bdk_satax_uctl_ecc
3702 {
3703 uint64_t u;
3704 struct bdk_satax_uctl_ecc_s
3705 {
3706 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3707 uint64_t reserved_62_63 : 2;
3708 uint64_t ecc_err_source : 4; /**< [ 61: 58](RO/H) Source of ECC error, see SATA_UCTL_ECC_ERR_SOURCE_E. */
3709 uint64_t ecc_err_syndrome : 18; /**< [ 57: 40](RO/H) Syndrome bits of the ECC error. */
3710 uint64_t ecc_err_address : 8; /**< [ 39: 32](RO/H) RAM address of the ECC error. */
3711 uint64_t reserved_21_31 : 11;
3712 uint64_t uctl_xm_r_ecc_flip_synd : 2;/**< [ 20: 19](R/W) Insert ECC error for testing purposes. */
3713 uint64_t uctl_xm_r_ecc_cor_dis : 1; /**< [ 18: 18](R/W) Enables ECC correction on UCTL AxiMaster read-data FIFO. */
3714 uint64_t uctl_xm_w_ecc_flip_synd : 2;/**< [ 17: 16](R/W) Insert ECC error for testing purposes. */
3715 uint64_t uctl_xm_w_ecc_cor_dis : 1; /**< [ 15: 15](R/W) Enables ECC correction on UCTL AxiMaster write-data FIFO. */
3716 uint64_t reserved_9_14 : 6;
3717 uint64_t uahc_rx_ecc_flip_synd : 2; /**< [ 8: 7](R/W) Insert ECC error for testing purposes. */
3718 uint64_t uahc_rx_ecc_cor_dis : 1; /**< [ 6: 6](R/W) Enables ECC correction on UAHC RxFIFO RAMs. */
3719 uint64_t uahc_tx_ecc_flip_synd : 2; /**< [ 5: 4](R/W) Insert ECC error for testing purposes. */
3720 uint64_t uahc_tx_ecc_cor_dis : 1; /**< [ 3: 3](R/W) Enables ECC correction on UAHC TxFIFO RAMs. */
3721 uint64_t uahc_fb_ecc_flip_synd : 2; /**< [ 2: 1](R/W) Insert ECC error for testing purposes. */
3722 uint64_t uahc_fb_ecc_cor_dis : 1; /**< [ 0: 0](R/W) Enables ECC correction on UAHC FBS RAM. */
3723 #else /* Word 0 - Little Endian */
3724 uint64_t uahc_fb_ecc_cor_dis : 1; /**< [ 0: 0](R/W) Enables ECC correction on UAHC FBS RAM. */
3725 uint64_t uahc_fb_ecc_flip_synd : 2; /**< [ 2: 1](R/W) Insert ECC error for testing purposes. */
3726 uint64_t uahc_tx_ecc_cor_dis : 1; /**< [ 3: 3](R/W) Enables ECC correction on UAHC TxFIFO RAMs. */
3727 uint64_t uahc_tx_ecc_flip_synd : 2; /**< [ 5: 4](R/W) Insert ECC error for testing purposes. */
3728 uint64_t uahc_rx_ecc_cor_dis : 1; /**< [ 6: 6](R/W) Enables ECC correction on UAHC RxFIFO RAMs. */
3729 uint64_t uahc_rx_ecc_flip_synd : 2; /**< [ 8: 7](R/W) Insert ECC error for testing purposes. */
3730 uint64_t reserved_9_14 : 6;
3731 uint64_t uctl_xm_w_ecc_cor_dis : 1; /**< [ 15: 15](R/W) Enables ECC correction on UCTL AxiMaster write-data FIFO. */
3732 uint64_t uctl_xm_w_ecc_flip_synd : 2;/**< [ 17: 16](R/W) Insert ECC error for testing purposes. */
3733 uint64_t uctl_xm_r_ecc_cor_dis : 1; /**< [ 18: 18](R/W) Enables ECC correction on UCTL AxiMaster read-data FIFO. */
3734 uint64_t uctl_xm_r_ecc_flip_synd : 2;/**< [ 20: 19](R/W) Insert ECC error for testing purposes. */
3735 uint64_t reserved_21_31 : 11;
3736 uint64_t ecc_err_address : 8; /**< [ 39: 32](RO/H) RAM address of the ECC error. */
3737 uint64_t ecc_err_syndrome : 18; /**< [ 57: 40](RO/H) Syndrome bits of the ECC error. */
3738 uint64_t ecc_err_source : 4; /**< [ 61: 58](RO/H) Source of ECC error, see SATA_UCTL_ECC_ERR_SOURCE_E. */
3739 uint64_t reserved_62_63 : 2;
3740 #endif /* Word 0 - End */
3741 } s;
3742 /* struct bdk_satax_uctl_ecc_s cn; */
3743 };
3744 typedef union bdk_satax_uctl_ecc bdk_satax_uctl_ecc_t;
3745
3746 static inline uint64_t BDK_SATAX_UCTL_ECC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_ECC(unsigned long a)3747 static inline uint64_t BDK_SATAX_UCTL_ECC(unsigned long a)
3748 {
3749 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3750 return 0x8100001000f0ll + 0x1000000000ll * ((a) & 0x1);
3751 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
3752 return 0x8100001000f0ll + 0x1000000000ll * ((a) & 0x7);
3753 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
3754 return 0x8100001000f0ll + 0x1000000000ll * ((a) & 0xf);
3755 __bdk_csr_fatal("SATAX_UCTL_ECC", 1, a, 0, 0, 0);
3756 }
3757
3758 #define typedef_BDK_SATAX_UCTL_ECC(a) bdk_satax_uctl_ecc_t
3759 #define bustype_BDK_SATAX_UCTL_ECC(a) BDK_CSR_TYPE_NCB
3760 #define basename_BDK_SATAX_UCTL_ECC(a) "SATAX_UCTL_ECC"
3761 #define device_bar_BDK_SATAX_UCTL_ECC(a) 0x0 /* PF_BAR0 */
3762 #define busnum_BDK_SATAX_UCTL_ECC(a) (a)
3763 #define arguments_BDK_SATAX_UCTL_ECC(a) (a),-1,-1,-1
3764
3765 /**
3766 * Register (NCB) sata#_uctl_intena_w1c
3767 *
3768 * SATA UCTL Interrupt Enable Clear Register
3769 * This register clears interrupt enable bits.
3770 */
3771 union bdk_satax_uctl_intena_w1c
3772 {
3773 uint64_t u;
3774 struct bdk_satax_uctl_intena_w1c_s
3775 {
3776 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3777 uint64_t reserved_14_63 : 50;
3778 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3779 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3780 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3781 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3782 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3783 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3784 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
3785 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
3786 uint64_t reserved_5 : 1;
3787 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
3788 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
3789 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
3790 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
3791 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
3792 #else /* Word 0 - Little Endian */
3793 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
3794 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
3795 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
3796 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
3797 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
3798 uint64_t reserved_5 : 1;
3799 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
3800 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
3801 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3802 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3803 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3804 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3805 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3806 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3807 uint64_t reserved_14_63 : 50;
3808 #endif /* Word 0 - End */
3809 } s;
3810 struct bdk_satax_uctl_intena_w1c_cn9
3811 {
3812 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3813 uint64_t reserved_8_63 : 56;
3814 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[DMA_RD_ERR]. */
3815 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[DMA_WR_ERR]. */
3816 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[DMA_PSN]. */
3817 uint64_t reserved_2_4 : 3;
3818 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[XM_BAD_DMA]. */
3819 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[XS_NCB_OOB]. */
3820 #else /* Word 0 - Little Endian */
3821 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[XS_NCB_OOB]. */
3822 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[XM_BAD_DMA]. */
3823 uint64_t reserved_2_4 : 3;
3824 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[DMA_PSN]. */
3825 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[DMA_WR_ERR]. */
3826 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_INTSTAT[DMA_RD_ERR]. */
3827 uint64_t reserved_8_63 : 56;
3828 #endif /* Word 0 - End */
3829 } cn9;
3830 struct bdk_satax_uctl_intena_w1c_cn81xx
3831 {
3832 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3833 uint64_t reserved_14_63 : 50;
3834 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3835 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3836 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3837 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3838 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3839 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3840 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
3841 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
3842 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
3843 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
3844 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
3845 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
3846 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
3847 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
3848 #else /* Word 0 - Little Endian */
3849 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
3850 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
3851 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
3852 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
3853 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
3854 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
3855 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
3856 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
3857 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3858 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3859 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3860 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3861 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3862 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for SATA(0..1)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3863 uint64_t reserved_14_63 : 50;
3864 #endif /* Word 0 - End */
3865 } cn81xx;
3866 struct bdk_satax_uctl_intena_w1c_cn88xx
3867 {
3868 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3869 uint64_t reserved_14_63 : 50;
3870 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3871 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3872 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3873 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3874 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3875 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3876 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
3877 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
3878 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_R_DBE]. */
3879 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
3880 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
3881 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
3882 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
3883 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
3884 #else /* Word 0 - Little Endian */
3885 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
3886 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
3887 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
3888 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
3889 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
3890 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[XM_R_DBE]. */
3891 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
3892 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
3893 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3894 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3895 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3896 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3897 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3898 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3899 uint64_t reserved_14_63 : 50;
3900 #endif /* Word 0 - End */
3901 } cn88xx;
3902 struct bdk_satax_uctl_intena_w1c_cn83xx
3903 {
3904 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3905 uint64_t reserved_14_63 : 50;
3906 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3907 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3908 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3909 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3910 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3911 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3912 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[DMA_RD_ERR]. */
3913 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[DMA_WR_ERR]. */
3914 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_R_DBE]. */
3915 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_R_SBE]. */
3916 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_W_DBE]. */
3917 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_W_SBE]. */
3918 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_BAD_DMA]. */
3919 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XS_NCB_OOB]. */
3920 #else /* Word 0 - Little Endian */
3921 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XS_NCB_OOB]. */
3922 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_BAD_DMA]. */
3923 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_W_SBE]. */
3924 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_W_DBE]. */
3925 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_R_SBE]. */
3926 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[XM_R_DBE]. */
3927 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[DMA_WR_ERR]. */
3928 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[DMA_RD_ERR]. */
3929 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3930 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3931 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3932 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3933 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3934 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for SATA(0..5)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3935 uint64_t reserved_14_63 : 50;
3936 #endif /* Word 0 - End */
3937 } cn83xx;
3938 };
3939 typedef union bdk_satax_uctl_intena_w1c bdk_satax_uctl_intena_w1c_t;
3940
3941 static inline uint64_t BDK_SATAX_UCTL_INTENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_INTENA_W1C(unsigned long a)3942 static inline uint64_t BDK_SATAX_UCTL_INTENA_W1C(unsigned long a)
3943 {
3944 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3945 return 0x810000100040ll + 0x1000000000ll * ((a) & 0x1);
3946 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
3947 return 0x810000100040ll + 0x1000000000ll * ((a) & 0x7);
3948 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
3949 return 0x810000100040ll + 0x1000000000ll * ((a) & 0xf);
3950 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
3951 return 0x810000100040ll + 0x1000000000ll * ((a) & 0x3);
3952 __bdk_csr_fatal("SATAX_UCTL_INTENA_W1C", 1, a, 0, 0, 0);
3953 }
3954
3955 #define typedef_BDK_SATAX_UCTL_INTENA_W1C(a) bdk_satax_uctl_intena_w1c_t
3956 #define bustype_BDK_SATAX_UCTL_INTENA_W1C(a) BDK_CSR_TYPE_NCB
3957 #define basename_BDK_SATAX_UCTL_INTENA_W1C(a) "SATAX_UCTL_INTENA_W1C"
3958 #define device_bar_BDK_SATAX_UCTL_INTENA_W1C(a) 0x4 /* PF_BAR4 */
3959 #define busnum_BDK_SATAX_UCTL_INTENA_W1C(a) (a)
3960 #define arguments_BDK_SATAX_UCTL_INTENA_W1C(a) (a),-1,-1,-1
3961
3962 /**
3963 * Register (NCB) sata#_uctl_intena_w1s
3964 *
3965 * SATA UCTL Interrupt Enable Set Register
3966 * This register sets interrupt enable bits.
3967 */
3968 union bdk_satax_uctl_intena_w1s
3969 {
3970 uint64_t u;
3971 struct bdk_satax_uctl_intena_w1s_s
3972 {
3973 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3974 uint64_t reserved_14_63 : 50;
3975 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
3976 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
3977 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
3978 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
3979 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
3980 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3981 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
3982 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
3983 uint64_t reserved_5 : 1;
3984 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
3985 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
3986 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
3987 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
3988 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
3989 #else /* Word 0 - Little Endian */
3990 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
3991 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
3992 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
3993 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
3994 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
3995 uint64_t reserved_5 : 1;
3996 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
3997 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
3998 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
3999 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4000 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4001 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4002 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4003 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4004 uint64_t reserved_14_63 : 50;
4005 #endif /* Word 0 - End */
4006 } s;
4007 struct bdk_satax_uctl_intena_w1s_cn9
4008 {
4009 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4010 uint64_t reserved_8_63 : 56;
4011 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[DMA_RD_ERR]. */
4012 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[DMA_WR_ERR]. */
4013 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[DMA_PSN]. */
4014 uint64_t reserved_2_4 : 3;
4015 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[XM_BAD_DMA]. */
4016 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[XS_NCB_OOB]. */
4017 #else /* Word 0 - Little Endian */
4018 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[XS_NCB_OOB]. */
4019 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[XM_BAD_DMA]. */
4020 uint64_t reserved_2_4 : 3;
4021 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[DMA_PSN]. */
4022 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[DMA_WR_ERR]. */
4023 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_INTSTAT[DMA_RD_ERR]. */
4024 uint64_t reserved_8_63 : 56;
4025 #endif /* Word 0 - End */
4026 } cn9;
4027 struct bdk_satax_uctl_intena_w1s_cn81xx
4028 {
4029 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4030 uint64_t reserved_14_63 : 50;
4031 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4032 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4033 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4034 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4035 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4036 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4037 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
4038 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
4039 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
4040 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
4041 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
4042 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
4043 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
4044 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
4045 #else /* Word 0 - Little Endian */
4046 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
4047 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
4048 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
4049 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
4050 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
4051 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
4052 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
4053 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
4054 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4055 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4056 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4057 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4058 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4059 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for SATA(0..1)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4060 uint64_t reserved_14_63 : 50;
4061 #endif /* Word 0 - End */
4062 } cn81xx;
4063 struct bdk_satax_uctl_intena_w1s_cn88xx
4064 {
4065 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4066 uint64_t reserved_14_63 : 50;
4067 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4068 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4069 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4070 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4071 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4072 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4073 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
4074 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
4075 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_R_DBE]. */
4076 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
4077 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
4078 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
4079 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
4080 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
4081 #else /* Word 0 - Little Endian */
4082 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
4083 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
4084 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
4085 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
4086 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
4087 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[XM_R_DBE]. */
4088 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
4089 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
4090 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4091 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4092 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4093 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4094 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4095 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4096 uint64_t reserved_14_63 : 50;
4097 #endif /* Word 0 - End */
4098 } cn88xx;
4099 struct bdk_satax_uctl_intena_w1s_cn83xx
4100 {
4101 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4102 uint64_t reserved_14_63 : 50;
4103 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4104 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4105 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4106 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4107 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4108 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4109 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[DMA_RD_ERR]. */
4110 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[DMA_WR_ERR]. */
4111 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_R_DBE]. */
4112 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_R_SBE]. */
4113 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_W_DBE]. */
4114 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_W_SBE]. */
4115 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_BAD_DMA]. */
4116 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XS_NCB_OOB]. */
4117 #else /* Word 0 - Little Endian */
4118 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XS_NCB_OOB]. */
4119 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_BAD_DMA]. */
4120 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_W_SBE]. */
4121 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_W_DBE]. */
4122 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_R_SBE]. */
4123 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[XM_R_DBE]. */
4124 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[DMA_WR_ERR]. */
4125 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[DMA_RD_ERR]. */
4126 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4127 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4128 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4129 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4130 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4131 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for SATA(0..5)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4132 uint64_t reserved_14_63 : 50;
4133 #endif /* Word 0 - End */
4134 } cn83xx;
4135 };
4136 typedef union bdk_satax_uctl_intena_w1s bdk_satax_uctl_intena_w1s_t;
4137
4138 static inline uint64_t BDK_SATAX_UCTL_INTENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_INTENA_W1S(unsigned long a)4139 static inline uint64_t BDK_SATAX_UCTL_INTENA_W1S(unsigned long a)
4140 {
4141 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4142 return 0x810000100048ll + 0x1000000000ll * ((a) & 0x1);
4143 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
4144 return 0x810000100048ll + 0x1000000000ll * ((a) & 0x7);
4145 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
4146 return 0x810000100048ll + 0x1000000000ll * ((a) & 0xf);
4147 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4148 return 0x810000100048ll + 0x1000000000ll * ((a) & 0x3);
4149 __bdk_csr_fatal("SATAX_UCTL_INTENA_W1S", 1, a, 0, 0, 0);
4150 }
4151
4152 #define typedef_BDK_SATAX_UCTL_INTENA_W1S(a) bdk_satax_uctl_intena_w1s_t
4153 #define bustype_BDK_SATAX_UCTL_INTENA_W1S(a) BDK_CSR_TYPE_NCB
4154 #define basename_BDK_SATAX_UCTL_INTENA_W1S(a) "SATAX_UCTL_INTENA_W1S"
4155 #define device_bar_BDK_SATAX_UCTL_INTENA_W1S(a) 0x4 /* PF_BAR4 */
4156 #define busnum_BDK_SATAX_UCTL_INTENA_W1S(a) (a)
4157 #define arguments_BDK_SATAX_UCTL_INTENA_W1S(a) (a),-1,-1,-1
4158
4159 /**
4160 * Register (NCB) sata#_uctl_intstat
4161 *
4162 * SATA UCTL Interrupt Status Register
4163 * Summary of different bits of interrupts.
4164 *
4165 * Accessible always.
4166 *
4167 * Reset NCB reset.
4168 */
4169 union bdk_satax_uctl_intstat
4170 {
4171 uint64_t u;
4172 struct bdk_satax_uctl_intstat_s
4173 {
4174 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4175 uint64_t reserved_14_63 : 50;
4176 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Detected double-bit error on the UAHC Rx FIFO. */
4177 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Detected single-bit error on the UAHC Rx FIFO. */
4178 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Detected double-bit error on the UAHC Tx FIFO. */
4179 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Detected single-bit error on the UAHC Tx FIFO. */
4180 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Detected double-bit error on the UAHC FBS memory. */
4181 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Detected single-bit error on the UAHC FBS memory. */
4182 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
4183 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
4184 uint64_t reserved_5 : 1;
4185 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Detected single-bit error on the UCTL AxiMaster read-data FIFO. */
4186 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Detected double-bit error on the UCTL AxiMaster write-data FIFO. */
4187 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Detected single-bit error on the UCTL AxiMaster write-data FIFO. */
4188 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Detected bad DMA access from UAHC to NCB. The error information is logged in
4189 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates
4190 the assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
4191 combinations and address out-of-bounds.
4192
4193 For more information on exact failures, see description in
4194 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE].
4195
4196 The hardware does not translate the request correctly and results may violate NCB
4197 protocols. */
4198 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1MB of register
4199 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
4200 to be set to 1. The error information is logged in
4201 SATA()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
4202 #else /* Word 0 - Little Endian */
4203 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1MB of register
4204 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
4205 to be set to 1. The error information is logged in
4206 SATA()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
4207 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Detected bad DMA access from UAHC to NCB. The error information is logged in
4208 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates
4209 the assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
4210 combinations and address out-of-bounds.
4211
4212 For more information on exact failures, see description in
4213 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE].
4214
4215 The hardware does not translate the request correctly and results may violate NCB
4216 protocols. */
4217 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Detected single-bit error on the UCTL AxiMaster write-data FIFO. */
4218 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Detected double-bit error on the UCTL AxiMaster write-data FIFO. */
4219 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Detected single-bit error on the UCTL AxiMaster read-data FIFO. */
4220 uint64_t reserved_5 : 1;
4221 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
4222 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
4223 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Detected single-bit error on the UAHC FBS memory. */
4224 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Detected double-bit error on the UAHC FBS memory. */
4225 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Detected single-bit error on the UAHC Tx FIFO. */
4226 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Detected double-bit error on the UAHC Tx FIFO. */
4227 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Detected single-bit error on the UAHC Rx FIFO. */
4228 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Detected double-bit error on the UAHC Rx FIFO. */
4229 uint64_t reserved_14_63 : 50;
4230 #endif /* Word 0 - End */
4231 } s;
4232 struct bdk_satax_uctl_intstat_cn8
4233 {
4234 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4235 uint64_t reserved_14_63 : 50;
4236 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Detected double-bit error on the UAHC Rx FIFO. */
4237 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Detected single-bit error on the UAHC Rx FIFO. */
4238 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Detected double-bit error on the UAHC Tx FIFO. */
4239 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Detected single-bit error on the UAHC Tx FIFO. */
4240 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Detected double-bit error on the UAHC FBS memory. */
4241 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Detected single-bit error on the UAHC FBS memory. */
4242 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
4243 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
4244 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1C/H) Detected double-bit error on the UCTL AxiMaster read-data FIFO. */
4245 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Detected single-bit error on the UCTL AxiMaster read-data FIFO. */
4246 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Detected double-bit error on the UCTL AxiMaster write-data FIFO. */
4247 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Detected single-bit error on the UCTL AxiMaster write-data FIFO. */
4248 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Detected bad DMA access from UAHC to NCB. The error information is logged in
4249 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates
4250 the assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
4251 combinations and address out-of-bounds.
4252
4253 For more information on exact failures, see description in
4254 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE].
4255
4256 The hardware does not translate the request correctly and results may violate NCB
4257 protocols. */
4258 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1MB of register
4259 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
4260 to be set to 1. The error information is logged in
4261 SATA()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
4262 #else /* Word 0 - Little Endian */
4263 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1MB of register
4264 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
4265 to be set to 1. The error information is logged in
4266 SATA()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
4267 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Detected bad DMA access from UAHC to NCB. The error information is logged in
4268 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates
4269 the assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
4270 combinations and address out-of-bounds.
4271
4272 For more information on exact failures, see description in
4273 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE].
4274
4275 The hardware does not translate the request correctly and results may violate NCB
4276 protocols. */
4277 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1C/H) Detected single-bit error on the UCTL AxiMaster write-data FIFO. */
4278 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1C/H) Detected double-bit error on the UCTL AxiMaster write-data FIFO. */
4279 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1C/H) Detected single-bit error on the UCTL AxiMaster read-data FIFO. */
4280 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1C/H) Detected double-bit error on the UCTL AxiMaster read-data FIFO. */
4281 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
4282 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
4283 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1C/H) Detected single-bit error on the UAHC FBS memory. */
4284 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1C/H) Detected double-bit error on the UAHC FBS memory. */
4285 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1C/H) Detected single-bit error on the UAHC Tx FIFO. */
4286 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1C/H) Detected double-bit error on the UAHC Tx FIFO. */
4287 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1C/H) Detected single-bit error on the UAHC Rx FIFO. */
4288 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1C/H) Detected double-bit error on the UAHC Rx FIFO. */
4289 uint64_t reserved_14_63 : 50;
4290 #endif /* Word 0 - End */
4291 } cn8;
4292 struct bdk_satax_uctl_intstat_cn9
4293 {
4294 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4295 uint64_t reserved_8_63 : 56;
4296 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
4297 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
4298 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Received DMA read response with poisoned data from NCBO.
4299 Hardware also sets SATA()_UCTL_RAS[DMA_PSN]. */
4300 uint64_t reserved_2_4 : 3;
4301 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Detected bad DMA access from UAHC to NCB. The error information is logged in
4302 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates
4303 the assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
4304 combinations and address out-of-bounds.
4305
4306 For more information on exact failures, see description in
4307 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE].
4308
4309 The hardware does not translate the request correctly and results may violate NCB
4310 protocols. */
4311 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1MB of register
4312 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
4313 to be set to 1. The error information is logged in
4314 SATA()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
4315 #else /* Word 0 - Little Endian */
4316 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1MB of register
4317 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
4318 to be set to 1. The error information is logged in
4319 SATA()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
4320 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1C/H) Detected bad DMA access from UAHC to NCB. The error information is logged in
4321 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates
4322 the assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
4323 combinations and address out-of-bounds.
4324
4325 For more information on exact failures, see description in
4326 SATA()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE].
4327
4328 The hardware does not translate the request correctly and results may violate NCB
4329 protocols. */
4330 uint64_t reserved_2_4 : 3;
4331 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Received DMA read response with poisoned data from NCBO.
4332 Hardware also sets SATA()_UCTL_RAS[DMA_PSN]. */
4333 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
4334 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
4335 uint64_t reserved_8_63 : 56;
4336 #endif /* Word 0 - End */
4337 } cn9;
4338 };
4339 typedef union bdk_satax_uctl_intstat bdk_satax_uctl_intstat_t;
4340
4341 static inline uint64_t BDK_SATAX_UCTL_INTSTAT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_INTSTAT(unsigned long a)4342 static inline uint64_t BDK_SATAX_UCTL_INTSTAT(unsigned long a)
4343 {
4344 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4345 return 0x810000100030ll + 0x1000000000ll * ((a) & 0x1);
4346 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
4347 return 0x810000100030ll + 0x1000000000ll * ((a) & 0x7);
4348 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
4349 return 0x810000100030ll + 0x1000000000ll * ((a) & 0xf);
4350 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4351 return 0x810000100030ll + 0x1000000000ll * ((a) & 0x3);
4352 __bdk_csr_fatal("SATAX_UCTL_INTSTAT", 1, a, 0, 0, 0);
4353 }
4354
4355 #define typedef_BDK_SATAX_UCTL_INTSTAT(a) bdk_satax_uctl_intstat_t
4356 #define bustype_BDK_SATAX_UCTL_INTSTAT(a) BDK_CSR_TYPE_NCB
4357 #define basename_BDK_SATAX_UCTL_INTSTAT(a) "SATAX_UCTL_INTSTAT"
4358 #define device_bar_BDK_SATAX_UCTL_INTSTAT(a) 0x4 /* PF_BAR4 */
4359 #define busnum_BDK_SATAX_UCTL_INTSTAT(a) (a)
4360 #define arguments_BDK_SATAX_UCTL_INTSTAT(a) (a),-1,-1,-1
4361
4362 /**
4363 * Register (NCB) sata#_uctl_intstat_w1s
4364 *
4365 * SATA UCTL Interrupt Set Register
4366 * This register sets interrupt bits.
4367 */
4368 union bdk_satax_uctl_intstat_w1s
4369 {
4370 uint64_t u;
4371 struct bdk_satax_uctl_intstat_w1s_s
4372 {
4373 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4374 uint64_t reserved_14_63 : 50;
4375 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4376 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4377 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4378 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4379 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4380 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4381 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
4382 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
4383 uint64_t reserved_5 : 1;
4384 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
4385 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
4386 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
4387 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
4388 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
4389 #else /* Word 0 - Little Endian */
4390 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
4391 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
4392 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
4393 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
4394 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
4395 uint64_t reserved_5 : 1;
4396 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
4397 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
4398 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4399 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4400 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4401 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4402 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4403 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4404 uint64_t reserved_14_63 : 50;
4405 #endif /* Word 0 - End */
4406 } s;
4407 struct bdk_satax_uctl_intstat_w1s_cn9
4408 {
4409 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4410 uint64_t reserved_8_63 : 56;
4411 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[DMA_RD_ERR]. */
4412 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[DMA_WR_ERR]. */
4413 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[DMA_PSN]. */
4414 uint64_t reserved_2_4 : 3;
4415 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[XM_BAD_DMA]. */
4416 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[XS_NCB_OOB]. */
4417 #else /* Word 0 - Little Endian */
4418 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[XS_NCB_OOB]. */
4419 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[XM_BAD_DMA]. */
4420 uint64_t reserved_2_4 : 3;
4421 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[DMA_PSN]. */
4422 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[DMA_WR_ERR]. */
4423 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..3)_UCTL_INTSTAT[DMA_RD_ERR]. */
4424 uint64_t reserved_8_63 : 56;
4425 #endif /* Word 0 - End */
4426 } cn9;
4427 struct bdk_satax_uctl_intstat_w1s_cn81xx
4428 {
4429 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4430 uint64_t reserved_14_63 : 50;
4431 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4432 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4433 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4434 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4435 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4436 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4437 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
4438 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
4439 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
4440 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
4441 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
4442 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
4443 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
4444 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
4445 #else /* Word 0 - Little Endian */
4446 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
4447 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
4448 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
4449 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
4450 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
4451 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
4452 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
4453 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
4454 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4455 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4456 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4457 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4458 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4459 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets SATA(0..1)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4460 uint64_t reserved_14_63 : 50;
4461 #endif /* Word 0 - End */
4462 } cn81xx;
4463 struct bdk_satax_uctl_intstat_w1s_cn88xx
4464 {
4465 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4466 uint64_t reserved_14_63 : 50;
4467 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4468 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4469 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4470 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4471 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4472 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4473 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
4474 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
4475 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_R_DBE]. */
4476 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
4477 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
4478 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
4479 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
4480 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
4481 #else /* Word 0 - Little Endian */
4482 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XS_NCB_OOB]. */
4483 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_BAD_DMA]. */
4484 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_W_SBE]. */
4485 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_W_DBE]. */
4486 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_R_SBE]. */
4487 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[XM_R_DBE]. */
4488 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[DMA_WR_ERR]. */
4489 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[DMA_RD_ERR]. */
4490 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4491 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4492 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4493 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4494 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4495 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets SATA(0..15)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4496 uint64_t reserved_14_63 : 50;
4497 #endif /* Word 0 - End */
4498 } cn88xx;
4499 struct bdk_satax_uctl_intstat_w1s_cn83xx
4500 {
4501 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4502 uint64_t reserved_14_63 : 50;
4503 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4504 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4505 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4506 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4507 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4508 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4509 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[DMA_RD_ERR]. */
4510 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[DMA_WR_ERR]. */
4511 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_R_DBE]. */
4512 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_R_SBE]. */
4513 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_W_DBE]. */
4514 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_W_SBE]. */
4515 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_BAD_DMA]. */
4516 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XS_NCB_OOB]. */
4517 #else /* Word 0 - Little Endian */
4518 uint64_t xs_ncb_oob : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XS_NCB_OOB]. */
4519 uint64_t xm_bad_dma : 1; /**< [ 1: 1](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_BAD_DMA]. */
4520 uint64_t xm_w_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_W_SBE]. */
4521 uint64_t xm_w_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_W_DBE]. */
4522 uint64_t xm_r_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_R_SBE]. */
4523 uint64_t xm_r_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[XM_R_DBE]. */
4524 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[DMA_WR_ERR]. */
4525 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[DMA_RD_ERR]. */
4526 uint64_t uahc_fb_sbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_FB_SBE]. */
4527 uint64_t uahc_fb_dbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_FB_DBE]. */
4528 uint64_t uahc_tx_sbe : 1; /**< [ 10: 10](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_TX_SBE]. */
4529 uint64_t uahc_tx_dbe : 1; /**< [ 11: 11](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_TX_DBE]. */
4530 uint64_t uahc_rx_sbe : 1; /**< [ 12: 12](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_RX_SBE]. */
4531 uint64_t uahc_rx_dbe : 1; /**< [ 13: 13](R/W1S/H) Reads or sets SATA(0..5)_UCTL_INTSTAT[UAHC_RX_DBE]. */
4532 uint64_t reserved_14_63 : 50;
4533 #endif /* Word 0 - End */
4534 } cn83xx;
4535 };
4536 typedef union bdk_satax_uctl_intstat_w1s bdk_satax_uctl_intstat_w1s_t;
4537
4538 static inline uint64_t BDK_SATAX_UCTL_INTSTAT_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_INTSTAT_W1S(unsigned long a)4539 static inline uint64_t BDK_SATAX_UCTL_INTSTAT_W1S(unsigned long a)
4540 {
4541 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4542 return 0x810000100038ll + 0x1000000000ll * ((a) & 0x1);
4543 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
4544 return 0x810000100038ll + 0x1000000000ll * ((a) & 0x7);
4545 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
4546 return 0x810000100038ll + 0x1000000000ll * ((a) & 0xf);
4547 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4548 return 0x810000100038ll + 0x1000000000ll * ((a) & 0x3);
4549 __bdk_csr_fatal("SATAX_UCTL_INTSTAT_W1S", 1, a, 0, 0, 0);
4550 }
4551
4552 #define typedef_BDK_SATAX_UCTL_INTSTAT_W1S(a) bdk_satax_uctl_intstat_w1s_t
4553 #define bustype_BDK_SATAX_UCTL_INTSTAT_W1S(a) BDK_CSR_TYPE_NCB
4554 #define basename_BDK_SATAX_UCTL_INTSTAT_W1S(a) "SATAX_UCTL_INTSTAT_W1S"
4555 #define device_bar_BDK_SATAX_UCTL_INTSTAT_W1S(a) 0x4 /* PF_BAR4 */
4556 #define busnum_BDK_SATAX_UCTL_INTSTAT_W1S(a) (a)
4557 #define arguments_BDK_SATAX_UCTL_INTSTAT_W1S(a) (a),-1,-1,-1
4558
4559 /**
4560 * Register (NCB) sata#_uctl_ras
4561 *
4562 * SATA UCTL RAS Register
4563 * This register is intended for delivery of RAS events to the SCP, so should be
4564 * ignored by OS drivers.
4565 */
4566 union bdk_satax_uctl_ras
4567 {
4568 uint64_t u;
4569 struct bdk_satax_uctl_ras_s
4570 {
4571 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4572 uint64_t reserved_1_63 : 63;
4573 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1C/H) Received DMA read response with poisoned data from NCBO.
4574 Hardware also sets SATA()_UCTL_INTSTAT[DMA_PSN]. */
4575 #else /* Word 0 - Little Endian */
4576 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1C/H) Received DMA read response with poisoned data from NCBO.
4577 Hardware also sets SATA()_UCTL_INTSTAT[DMA_PSN]. */
4578 uint64_t reserved_1_63 : 63;
4579 #endif /* Word 0 - End */
4580 } s;
4581 /* struct bdk_satax_uctl_ras_s cn; */
4582 };
4583 typedef union bdk_satax_uctl_ras bdk_satax_uctl_ras_t;
4584
4585 static inline uint64_t BDK_SATAX_UCTL_RAS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_RAS(unsigned long a)4586 static inline uint64_t BDK_SATAX_UCTL_RAS(unsigned long a)
4587 {
4588 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4589 return 0x810000100050ll + 0x1000000000ll * ((a) & 0x3);
4590 __bdk_csr_fatal("SATAX_UCTL_RAS", 1, a, 0, 0, 0);
4591 }
4592
4593 #define typedef_BDK_SATAX_UCTL_RAS(a) bdk_satax_uctl_ras_t
4594 #define bustype_BDK_SATAX_UCTL_RAS(a) BDK_CSR_TYPE_NCB
4595 #define basename_BDK_SATAX_UCTL_RAS(a) "SATAX_UCTL_RAS"
4596 #define device_bar_BDK_SATAX_UCTL_RAS(a) 0x4 /* PF_BAR4 */
4597 #define busnum_BDK_SATAX_UCTL_RAS(a) (a)
4598 #define arguments_BDK_SATAX_UCTL_RAS(a) (a),-1,-1,-1
4599
4600 /**
4601 * Register (NCB) sata#_uctl_ras_ena_w1c
4602 *
4603 * SATA UCTL RAS Enable Clear Register
4604 * This register clears interrupt enable bits.
4605 */
4606 union bdk_satax_uctl_ras_ena_w1c
4607 {
4608 uint64_t u;
4609 struct bdk_satax_uctl_ras_ena_w1c_s
4610 {
4611 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4612 uint64_t reserved_1_63 : 63;
4613 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_RAS[DMA_PSN]. */
4614 #else /* Word 0 - Little Endian */
4615 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for SATA(0..3)_UCTL_RAS[DMA_PSN]. */
4616 uint64_t reserved_1_63 : 63;
4617 #endif /* Word 0 - End */
4618 } s;
4619 /* struct bdk_satax_uctl_ras_ena_w1c_s cn; */
4620 };
4621 typedef union bdk_satax_uctl_ras_ena_w1c bdk_satax_uctl_ras_ena_w1c_t;
4622
4623 static inline uint64_t BDK_SATAX_UCTL_RAS_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_RAS_ENA_W1C(unsigned long a)4624 static inline uint64_t BDK_SATAX_UCTL_RAS_ENA_W1C(unsigned long a)
4625 {
4626 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4627 return 0x810000100060ll + 0x1000000000ll * ((a) & 0x3);
4628 __bdk_csr_fatal("SATAX_UCTL_RAS_ENA_W1C", 1, a, 0, 0, 0);
4629 }
4630
4631 #define typedef_BDK_SATAX_UCTL_RAS_ENA_W1C(a) bdk_satax_uctl_ras_ena_w1c_t
4632 #define bustype_BDK_SATAX_UCTL_RAS_ENA_W1C(a) BDK_CSR_TYPE_NCB
4633 #define basename_BDK_SATAX_UCTL_RAS_ENA_W1C(a) "SATAX_UCTL_RAS_ENA_W1C"
4634 #define device_bar_BDK_SATAX_UCTL_RAS_ENA_W1C(a) 0x4 /* PF_BAR4 */
4635 #define busnum_BDK_SATAX_UCTL_RAS_ENA_W1C(a) (a)
4636 #define arguments_BDK_SATAX_UCTL_RAS_ENA_W1C(a) (a),-1,-1,-1
4637
4638 /**
4639 * Register (NCB) sata#_uctl_ras_ena_w1s
4640 *
4641 * SATA UCTL RAS Enable Set Register
4642 * This register sets interrupt enable bits.
4643 */
4644 union bdk_satax_uctl_ras_ena_w1s
4645 {
4646 uint64_t u;
4647 struct bdk_satax_uctl_ras_ena_w1s_s
4648 {
4649 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4650 uint64_t reserved_1_63 : 63;
4651 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_RAS[DMA_PSN]. */
4652 #else /* Word 0 - Little Endian */
4653 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for SATA(0..3)_UCTL_RAS[DMA_PSN]. */
4654 uint64_t reserved_1_63 : 63;
4655 #endif /* Word 0 - End */
4656 } s;
4657 /* struct bdk_satax_uctl_ras_ena_w1s_s cn; */
4658 };
4659 typedef union bdk_satax_uctl_ras_ena_w1s bdk_satax_uctl_ras_ena_w1s_t;
4660
4661 static inline uint64_t BDK_SATAX_UCTL_RAS_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_RAS_ENA_W1S(unsigned long a)4662 static inline uint64_t BDK_SATAX_UCTL_RAS_ENA_W1S(unsigned long a)
4663 {
4664 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4665 return 0x810000100068ll + 0x1000000000ll * ((a) & 0x3);
4666 __bdk_csr_fatal("SATAX_UCTL_RAS_ENA_W1S", 1, a, 0, 0, 0);
4667 }
4668
4669 #define typedef_BDK_SATAX_UCTL_RAS_ENA_W1S(a) bdk_satax_uctl_ras_ena_w1s_t
4670 #define bustype_BDK_SATAX_UCTL_RAS_ENA_W1S(a) BDK_CSR_TYPE_NCB
4671 #define basename_BDK_SATAX_UCTL_RAS_ENA_W1S(a) "SATAX_UCTL_RAS_ENA_W1S"
4672 #define device_bar_BDK_SATAX_UCTL_RAS_ENA_W1S(a) 0x4 /* PF_BAR4 */
4673 #define busnum_BDK_SATAX_UCTL_RAS_ENA_W1S(a) (a)
4674 #define arguments_BDK_SATAX_UCTL_RAS_ENA_W1S(a) (a),-1,-1,-1
4675
4676 /**
4677 * Register (NCB) sata#_uctl_ras_w1s
4678 *
4679 * SATA UCTL RAS Set Register
4680 * This register sets interrupt bits.
4681 */
4682 union bdk_satax_uctl_ras_w1s
4683 {
4684 uint64_t u;
4685 struct bdk_satax_uctl_ras_w1s_s
4686 {
4687 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4688 uint64_t reserved_1_63 : 63;
4689 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..3)_UCTL_RAS[DMA_PSN]. */
4690 #else /* Word 0 - Little Endian */
4691 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1S/H) Reads or sets SATA(0..3)_UCTL_RAS[DMA_PSN]. */
4692 uint64_t reserved_1_63 : 63;
4693 #endif /* Word 0 - End */
4694 } s;
4695 /* struct bdk_satax_uctl_ras_w1s_s cn; */
4696 };
4697 typedef union bdk_satax_uctl_ras_w1s bdk_satax_uctl_ras_w1s_t;
4698
4699 static inline uint64_t BDK_SATAX_UCTL_RAS_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_RAS_W1S(unsigned long a)4700 static inline uint64_t BDK_SATAX_UCTL_RAS_W1S(unsigned long a)
4701 {
4702 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4703 return 0x810000100058ll + 0x1000000000ll * ((a) & 0x3);
4704 __bdk_csr_fatal("SATAX_UCTL_RAS_W1S", 1, a, 0, 0, 0);
4705 }
4706
4707 #define typedef_BDK_SATAX_UCTL_RAS_W1S(a) bdk_satax_uctl_ras_w1s_t
4708 #define bustype_BDK_SATAX_UCTL_RAS_W1S(a) BDK_CSR_TYPE_NCB
4709 #define basename_BDK_SATAX_UCTL_RAS_W1S(a) "SATAX_UCTL_RAS_W1S"
4710 #define device_bar_BDK_SATAX_UCTL_RAS_W1S(a) 0x4 /* PF_BAR4 */
4711 #define busnum_BDK_SATAX_UCTL_RAS_W1S(a) (a)
4712 #define arguments_BDK_SATAX_UCTL_RAS_W1S(a) (a),-1,-1,-1
4713
4714 /**
4715 * Register (NCB) sata#_uctl_shim_cfg
4716 *
4717 * SATA UCTL Shim Configuration Register
4718 * This register allows configuration of various shim (UCTL) features.
4719 *
4720 * Fields XS_NCB_OOB_* are captured when there are no outstanding OOB errors indicated in INTSTAT
4721 * and a new OOB error arrives.
4722 *
4723 * Fields XS_BAD_DMA_* are captured when there are no outstanding DMA errors indicated in INTSTAT
4724 * and a new DMA error arrives.
4725 *
4726 * Accessible only when SATA()_UCTL_CTL[A_CLK_EN].
4727 *
4728 * Reset by NCB reset or SATA()_UCTL_CTL[SATA_UCTL_RST].
4729 */
4730 union bdk_satax_uctl_shim_cfg
4731 {
4732 uint64_t u;
4733 struct bdk_satax_uctl_shim_cfg_s
4734 {
4735 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4736 uint64_t xs_ncb_oob_wrn : 1; /**< [ 63: 63](RO/H) Read/write error log for out-of-bound UAHC register access.
4737 0 = read, 1 = write. */
4738 uint64_t reserved_60_62 : 3;
4739 uint64_t xs_ncb_oob_osrc : 12; /**< [ 59: 48](RO/H) SRCID error log for out-of-bound UAHC register access. The NCB outbound SRCID for the OOB
4740 error.
4741 \<59:58\> = chipID.
4742 \<57\> = Request source: 0 = core, 1 = NCB-device.
4743 \<56:51\> = core/NCB-device number. Note that for NCB devices, \<56\> is always 0.
4744 \<50:48\> = SubID. */
4745 uint64_t xm_bad_dma_wrn : 1; /**< [ 47: 47](RO/H) Read/write error log for bad DMA access from UAHC.
4746 0 = read error log, 1 = write error log. */
4747 uint64_t reserved_44_46 : 3;
4748 uint64_t xm_bad_dma_type : 4; /**< [ 43: 40](RO/H) ErrType error log for bad DMA access from UAHC. Encodes the type of error encountered
4749 (error largest encoded value has priority). See SATA_UCTL_XM_BAD_DMA_TYPE_E. */
4750 uint64_t reserved_14_39 : 26;
4751 uint64_t dma_read_cmd : 2; /**< [ 13: 12](R/W) Selects the NCB read command used by DMA accesses. See SATA_UCTL_DMA_READ_CMD_E. */
4752 uint64_t reserved_11 : 1;
4753 uint64_t dma_write_cmd : 1; /**< [ 10: 10](R/W) Selects the NCB write command used by DMA accesses. See enum SATA_UCTL_DMA_WRITE_CMD_E. */
4754 uint64_t reserved_0_9 : 10;
4755 #else /* Word 0 - Little Endian */
4756 uint64_t reserved_0_9 : 10;
4757 uint64_t dma_write_cmd : 1; /**< [ 10: 10](R/W) Selects the NCB write command used by DMA accesses. See enum SATA_UCTL_DMA_WRITE_CMD_E. */
4758 uint64_t reserved_11 : 1;
4759 uint64_t dma_read_cmd : 2; /**< [ 13: 12](R/W) Selects the NCB read command used by DMA accesses. See SATA_UCTL_DMA_READ_CMD_E. */
4760 uint64_t reserved_14_39 : 26;
4761 uint64_t xm_bad_dma_type : 4; /**< [ 43: 40](RO/H) ErrType error log for bad DMA access from UAHC. Encodes the type of error encountered
4762 (error largest encoded value has priority). See SATA_UCTL_XM_BAD_DMA_TYPE_E. */
4763 uint64_t reserved_44_46 : 3;
4764 uint64_t xm_bad_dma_wrn : 1; /**< [ 47: 47](RO/H) Read/write error log for bad DMA access from UAHC.
4765 0 = read error log, 1 = write error log. */
4766 uint64_t xs_ncb_oob_osrc : 12; /**< [ 59: 48](RO/H) SRCID error log for out-of-bound UAHC register access. The NCB outbound SRCID for the OOB
4767 error.
4768 \<59:58\> = chipID.
4769 \<57\> = Request source: 0 = core, 1 = NCB-device.
4770 \<56:51\> = core/NCB-device number. Note that for NCB devices, \<56\> is always 0.
4771 \<50:48\> = SubID. */
4772 uint64_t reserved_60_62 : 3;
4773 uint64_t xs_ncb_oob_wrn : 1; /**< [ 63: 63](RO/H) Read/write error log for out-of-bound UAHC register access.
4774 0 = read, 1 = write. */
4775 #endif /* Word 0 - End */
4776 } s;
4777 /* struct bdk_satax_uctl_shim_cfg_s cn; */
4778 };
4779 typedef union bdk_satax_uctl_shim_cfg bdk_satax_uctl_shim_cfg_t;
4780
4781 static inline uint64_t BDK_SATAX_UCTL_SHIM_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_SHIM_CFG(unsigned long a)4782 static inline uint64_t BDK_SATAX_UCTL_SHIM_CFG(unsigned long a)
4783 {
4784 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4785 return 0x8100001000e8ll + 0x1000000000ll * ((a) & 0x1);
4786 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
4787 return 0x8100001000e8ll + 0x1000000000ll * ((a) & 0x7);
4788 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
4789 return 0x8100001000e8ll + 0x1000000000ll * ((a) & 0xf);
4790 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4791 return 0x8100001000e8ll + 0x1000000000ll * ((a) & 0x3);
4792 __bdk_csr_fatal("SATAX_UCTL_SHIM_CFG", 1, a, 0, 0, 0);
4793 }
4794
4795 #define typedef_BDK_SATAX_UCTL_SHIM_CFG(a) bdk_satax_uctl_shim_cfg_t
4796 #define bustype_BDK_SATAX_UCTL_SHIM_CFG(a) BDK_CSR_TYPE_NCB
4797 #define basename_BDK_SATAX_UCTL_SHIM_CFG(a) "SATAX_UCTL_SHIM_CFG"
4798 #define device_bar_BDK_SATAX_UCTL_SHIM_CFG(a) 0x4 /* PF_BAR4 */
4799 #define busnum_BDK_SATAX_UCTL_SHIM_CFG(a) (a)
4800 #define arguments_BDK_SATAX_UCTL_SHIM_CFG(a) (a),-1,-1,-1
4801
4802 /**
4803 * Register (NCB) sata#_uctl_spare0
4804 *
4805 * INTERNAL: SATA UCTL Spare Register 0
4806 *
4807 * This register is spare.
4808 *
4809 * Accessible always.
4810 *
4811 * Reset NCB reset.
4812 */
4813 union bdk_satax_uctl_spare0
4814 {
4815 uint64_t u;
4816 struct bdk_satax_uctl_spare0_s
4817 {
4818 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4819 uint64_t spare : 64; /**< [ 63: 0](R/W) Spare. */
4820 #else /* Word 0 - Little Endian */
4821 uint64_t spare : 64; /**< [ 63: 0](R/W) Spare. */
4822 #endif /* Word 0 - End */
4823 } s;
4824 /* struct bdk_satax_uctl_spare0_s cn; */
4825 };
4826 typedef union bdk_satax_uctl_spare0 bdk_satax_uctl_spare0_t;
4827
4828 static inline uint64_t BDK_SATAX_UCTL_SPARE0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_SPARE0(unsigned long a)4829 static inline uint64_t BDK_SATAX_UCTL_SPARE0(unsigned long a)
4830 {
4831 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4832 return 0x810000100010ll + 0x1000000000ll * ((a) & 0x1);
4833 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
4834 return 0x810000100010ll + 0x1000000000ll * ((a) & 0x7);
4835 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
4836 return 0x810000100010ll + 0x1000000000ll * ((a) & 0xf);
4837 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4838 return 0x810000100010ll + 0x1000000000ll * ((a) & 0x3);
4839 __bdk_csr_fatal("SATAX_UCTL_SPARE0", 1, a, 0, 0, 0);
4840 }
4841
4842 #define typedef_BDK_SATAX_UCTL_SPARE0(a) bdk_satax_uctl_spare0_t
4843 #define bustype_BDK_SATAX_UCTL_SPARE0(a) BDK_CSR_TYPE_NCB
4844 #define basename_BDK_SATAX_UCTL_SPARE0(a) "SATAX_UCTL_SPARE0"
4845 #define device_bar_BDK_SATAX_UCTL_SPARE0(a) 0x4 /* PF_BAR4 */
4846 #define busnum_BDK_SATAX_UCTL_SPARE0(a) (a)
4847 #define arguments_BDK_SATAX_UCTL_SPARE0(a) (a),-1,-1,-1
4848
4849 /**
4850 * Register (NCB) sata#_uctl_spare1
4851 *
4852 * INTERNAL: SATA UCTL Spare Register 1
4853 *
4854 * This register is spare.
4855 *
4856 * Accessible only when SATA()_UCTL_CTL[A_CLK_EN].
4857 *
4858 * Reset by NCB reset or SATA()_UCTL_CTL[SATA_UCTL_RST].
4859 */
4860 union bdk_satax_uctl_spare1
4861 {
4862 uint64_t u;
4863 struct bdk_satax_uctl_spare1_s
4864 {
4865 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4866 uint64_t spare : 64; /**< [ 63: 0](R/W) Spare. */
4867 #else /* Word 0 - Little Endian */
4868 uint64_t spare : 64; /**< [ 63: 0](R/W) Spare. */
4869 #endif /* Word 0 - End */
4870 } s;
4871 /* struct bdk_satax_uctl_spare1_s cn; */
4872 };
4873 typedef union bdk_satax_uctl_spare1 bdk_satax_uctl_spare1_t;
4874
4875 static inline uint64_t BDK_SATAX_UCTL_SPARE1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SATAX_UCTL_SPARE1(unsigned long a)4876 static inline uint64_t BDK_SATAX_UCTL_SPARE1(unsigned long a)
4877 {
4878 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4879 return 0x8100001000f8ll + 0x1000000000ll * ((a) & 0x1);
4880 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=5))
4881 return 0x8100001000f8ll + 0x1000000000ll * ((a) & 0x7);
4882 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=15))
4883 return 0x8100001000f8ll + 0x1000000000ll * ((a) & 0xf);
4884 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
4885 return 0x8100001000f8ll + 0x1000000000ll * ((a) & 0x3);
4886 __bdk_csr_fatal("SATAX_UCTL_SPARE1", 1, a, 0, 0, 0);
4887 }
4888
4889 #define typedef_BDK_SATAX_UCTL_SPARE1(a) bdk_satax_uctl_spare1_t
4890 #define bustype_BDK_SATAX_UCTL_SPARE1(a) BDK_CSR_TYPE_NCB
4891 #define basename_BDK_SATAX_UCTL_SPARE1(a) "SATAX_UCTL_SPARE1"
4892 #define device_bar_BDK_SATAX_UCTL_SPARE1(a) 0x4 /* PF_BAR4 */
4893 #define busnum_BDK_SATAX_UCTL_SPARE1(a) (a)
4894 #define arguments_BDK_SATAX_UCTL_SPARE1(a) (a),-1,-1,-1
4895
4896 #endif /* __BDK_CSRS_SATA_H__ */
4897