1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "efuse.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "phy.h"
10 #include "reg.h"
11 #include "rtw8851b.h"
12 #include "rtw8851b_rfk.h"
13 #include "rtw8851b_rfk_table.h"
14 #include "rtw8851b_table.h"
15 #include "txrx.h"
16 #include "util.h"
17
18 #define RTW8851B_FW_FORMAT_MAX 0
19 #define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw"
20 #define RTW8851B_MODULE_FIRMWARE \
21 RTW8851B_FW_BASENAME ".bin"
22
23 static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = {
24 {5, 343, grp_0}, /* ACH 0 */
25 {5, 343, grp_0}, /* ACH 1 */
26 {5, 343, grp_0}, /* ACH 2 */
27 {5, 343, grp_0}, /* ACH 3 */
28 {0, 0, grp_0}, /* ACH 4 */
29 {0, 0, grp_0}, /* ACH 5 */
30 {0, 0, grp_0}, /* ACH 6 */
31 {0, 0, grp_0}, /* ACH 7 */
32 {4, 344, grp_0}, /* B0MGQ */
33 {4, 344, grp_0}, /* B0HIQ */
34 {0, 0, grp_0}, /* B1MGQ */
35 {0, 0, grp_0}, /* B1HIQ */
36 {40, 0, 0} /* FWCMDQ */
37 };
38
39 static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = {
40 448, /* Group 0 */
41 0, /* Group 1 */
42 448, /* Public Max */
43 0 /* WP threshold */
44 };
45
46 static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = {
47 [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie,
48 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
49 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
50 RTW89_HCIFC_POH},
51 [RTW89_QTA_INVALID] = {NULL},
52 };
53
54 static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
55 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
56 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
57 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
58 &rtw89_mac_size.ple_qt58},
59 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6,
60 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
61 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
62 &rtw89_mac_size.ple_qt_51b_wow},
63 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
64 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
65 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
66 &rtw89_mac_size.ple_qt13},
67 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
68 NULL},
69 };
70
71 static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = {
72 {0x46D0, GENMASK(1, 0), 0x3},
73 {0x4AD4, GENMASK(31, 0), 0xf},
74 {0x4688, GENMASK(23, 16), 0x80},
75 {0x4688, GENMASK(31, 24), 0x80},
76 {0x4694, GENMASK(7, 0), 0x80},
77 {0x4694, GENMASK(15, 8), 0x80},
78 {0x4AE4, GENMASK(11, 6), 0x34},
79 {0x4AE4, GENMASK(17, 12), 0x0},
80 {0x469C, GENMASK(31, 26), 0x34},
81 };
82
83 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_en_defs);
84
85 static const struct rtw89_reg3_def rtw8851b_btc_preagc_dis_defs[] = {
86 {0x46D0, GENMASK(1, 0), 0x0},
87 {0x4AD4, GENMASK(31, 0), 0x60},
88 {0x4688, GENMASK(23, 16), 0x10},
89 {0x4690, GENMASK(31, 24), 0x2a},
90 {0x4694, GENMASK(15, 8), 0x2a},
91 {0x4AE4, GENMASK(11, 6), 0x26},
92 {0x4AE4, GENMASK(17, 12), 0x1e},
93 {0x469C, GENMASK(31, 26), 0x26},
94 };
95
96 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_dis_defs);
97
98 static const u32 rtw8851b_h2c_regs[RTW89_H2CREG_MAX] = {
99 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
100 R_AX_H2CREG_DATA3
101 };
102
103 static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = {
104 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
105 R_AX_C2HREG_DATA3
106 };
107
108 static const u32 rtw8851b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
109 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
110 };
111
112 static const struct rtw89_page_regs rtw8851b_page_regs = {
113 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
114 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
115 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
116 .ach_page_info = R_AX_ACH0_PAGE_INFO,
117 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
118 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
119 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
120 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
121 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
122 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
123 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
124 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
125 };
126
127 static const struct rtw89_reg_def rtw8851b_dcfo_comp = {
128 R_DCFO_COMP_S0_V2, B_DCFO_COMP_S0_MSK_V2
129 };
130
131 static const struct rtw89_imr_info rtw8851b_imr_info = {
132 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
133 .wsec_imr_reg = R_AX_SEC_DEBUG,
134 .wsec_imr_set = B_AX_IMR_ERROR,
135 .mpdu_tx_imr_set = 0,
136 .mpdu_rx_imr_set = 0,
137 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
138 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
139 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
140 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
141 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
142 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
143 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
144 .wde_imr_clr = B_AX_WDE_IMR_CLR,
145 .wde_imr_set = B_AX_WDE_IMR_SET,
146 .ple_imr_clr = B_AX_PLE_IMR_CLR,
147 .ple_imr_set = B_AX_PLE_IMR_SET,
148 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
149 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
150 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
151 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
152 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
153 .other_disp_imr_set = 0,
154 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
155 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
156 .bbrpt_err_imr_set = 0,
157 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
158 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
159 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
160 .cdma_imr_0_reg = R_AX_DLE_CTRL,
161 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
162 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
163 .cdma_imr_1_reg = 0,
164 .cdma_imr_1_clr = 0,
165 .cdma_imr_1_set = 0,
166 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
167 .phy_intf_imr_clr = 0,
168 .phy_intf_imr_set = 0,
169 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
170 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
171 .rmac_imr_set = B_AX_RMAC_IMR_SET,
172 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
173 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
174 .tmac_imr_set = B_AX_TMAC_IMR_SET,
175 };
176
177 static const struct rtw89_xtal_info rtw8851b_xtal_info = {
178 .xcap_reg = R_AX_XTAL_ON_CTRL3,
179 .sc_xo_mask = B_AX_XTAL_SC_XO_A_BLOCK_MASK,
180 .sc_xi_mask = B_AX_XTAL_SC_XI_A_BLOCK_MASK,
181 };
182
183 static const struct rtw89_rrsr_cfgs rtw8851b_rrsr_cfgs = {
184 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
185 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
186 };
187
188 static const struct rtw89_rfkill_regs rtw8851b_rfkill_regs = {
189 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
190 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
191 0xf},
192 .mode = {R_AX_GPIO_EXT_CTRL + 2,
193 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
194 0x0},
195 };
196
197 static const struct rtw89_dig_regs rtw8851b_dig_regs = {
198 .seg0_pd_reg = R_SEG0R_PD_V1,
199 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
200 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
201 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
202 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
203 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
204 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
205 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
206 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
207 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
208 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
209 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
210 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
211 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
212 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
213 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
214 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
215 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
216 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
217 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
218 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
219 };
220
221 static const struct rtw89_edcca_regs rtw8851b_edcca_regs = {
222 .edcca_level = R_SEG0R_EDCCA_LVL_V1,
223 .edcca_mask = B_EDCCA_LVL_MSK0,
224 .edcca_p_mask = B_EDCCA_LVL_MSK1,
225 .ppdu_level = R_SEG0R_EDCCA_LVL_V1,
226 .ppdu_mask = B_EDCCA_LVL_MSK3,
227 .rpt_a = R_EDCCA_RPT_A,
228 .rpt_b = R_EDCCA_RPT_B,
229 .rpt_sel = R_EDCCA_RPT_SEL,
230 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
231 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
232 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
233 };
234
235 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = {
236 {255, 0, 0, 7}, /* 0 -> original */
237 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
238 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
239 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
240 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
241 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
242 {6, 1, 0, 7},
243 {13, 1, 0, 7},
244 {13, 1, 0, 7}
245 };
246
247 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_dl[] = {
248 {255, 0, 0, 7}, /* 0 -> original */
249 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
250 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
251 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
252 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
253 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
254 {255, 1, 0, 7},
255 {255, 1, 0, 7},
256 {255, 1, 0, 7}
257 };
258
259 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = {
260 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
261 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
262 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
263 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
264 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
265 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
266 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
267 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
268 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
269 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
270 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
271 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
272 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
273 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
274 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
275 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
276 };
277
278 static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
279 static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
280
rtw8851b_pwr_on_func(struct rtw89_dev * rtwdev)281 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
282 {
283 u32 val32;
284 u8 val8;
285 int ret;
286
287 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
288 B_AX_AFSM_PCIE_SUS_EN);
289 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
290 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
291 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
292 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
293
294 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
295 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
296 if (ret)
297 return ret;
298
299 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
300 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
301
302 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
303 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
304 if (ret)
305 return ret;
306
307 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
308 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
309 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
310 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
311
312 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
313 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
314
315 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
316 XTAL_SI_OFF_WEI);
317 if (ret)
318 return ret;
319 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
320 XTAL_SI_OFF_EI);
321 if (ret)
322 return ret;
323 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
324 if (ret)
325 return ret;
326 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
327 XTAL_SI_PON_WEI);
328 if (ret)
329 return ret;
330 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
331 XTAL_SI_PON_EI);
332 if (ret)
333 return ret;
334 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
335 if (ret)
336 return ret;
337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
338 if (ret)
339 return ret;
340 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
341 if (ret)
342 return ret;
343 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
344 if (ret)
345 return ret;
346 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
347 if (ret)
348 return ret;
349
350 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
351 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
352 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
353
354 fsleep(1000);
355
356 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
357 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
358 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
359 B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1);
360
361 if (rtwdev->hal.cv == CHIP_CAV) {
362 ret = rtw89_read_efuse_ver(rtwdev, &val8);
363 if (!ret)
364 rtwdev->hal.cv = val8;
365 }
366
367 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
368 B_AX_XTAL_SI_ADDR_NOT_CHK);
369 if (rtwdev->hal.cv != CHIP_CAV) {
370 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
371 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
372 }
373
374 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
375 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
376 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
377 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
378 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
379 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
380 B_AX_DMACREG_GCKEN);
381 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
382 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
383 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
384 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
385 B_AX_RMAC_EN);
386
387 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
388 PINMUX_EESK_FUNC_SEL_BT_LOG);
389
390 return 0;
391 }
392
rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev * rtwdev)393 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
394 {
395 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
396 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
397 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
398 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
399 }
400
rtw8851b_pwr_off_func(struct rtw89_dev * rtwdev)401 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
402 {
403 u32 val32;
404 int ret;
405
406 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
407 XTAL_SI_RFC2RF);
408 if (ret)
409 return ret;
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
411 if (ret)
412 return ret;
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
414 if (ret)
415 return ret;
416 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
417 if (ret)
418 return ret;
419 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
420 XTAL_SI_SRAM2RFC);
421 if (ret)
422 return ret;
423 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
424 if (ret)
425 return ret;
426 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
427 if (ret)
428 return ret;
429
430 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
431 B_AX_XTAL_SI_ADDR_NOT_CHK);
432 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
433 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
434 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
435
436 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
437
438 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
439 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
440 if (ret)
441 return ret;
442
443 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
444
445 if (rtwdev->hal.cv == CHIP_CAV) {
446 rtw8851b_patch_swr_pfm2pwm(rtwdev);
447 } else {
448 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
449 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
450 }
451
452 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
453
454 return 0;
455 }
456
rtw8851b_efuse_parsing(struct rtw89_efuse * efuse,struct rtw8851b_efuse * map)457 static void rtw8851b_efuse_parsing(struct rtw89_efuse *efuse,
458 struct rtw8851b_efuse *map)
459 {
460 ether_addr_copy(efuse->addr, map->e.mac_addr);
461 efuse->rfe_type = map->rfe_type;
462 efuse->xtal_cap = map->xtal_k;
463 }
464
rtw8851b_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8851b_efuse * map)465 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
466 struct rtw8851b_efuse *map)
467 {
468 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
469 struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi};
470 u8 i, j;
471
472 tssi->thermal[RF_PATH_A] = map->path_a_therm;
473
474 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
475 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
476 sizeof(ofst[i]->cck_tssi));
477
478 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
479 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
480 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
481 i, j, tssi->tssi_cck[i][j]);
482
483 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
484 sizeof(ofst[i]->bw40_tssi));
485 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
486 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
487
488 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
489 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
490 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
491 i, j, tssi->tssi_mcs[i][j]);
492 }
493 }
494
_decode_efuse_gain(u8 data,s8 * high,s8 * low)495 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
496 {
497 if (high)
498 *high = sign_extend32(u8_get_bits(data, GENMASK(7, 4)), 3);
499 if (low)
500 *low = sign_extend32(u8_get_bits(data, GENMASK(3, 0)), 3);
501
502 return data != 0xff;
503 }
504
rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8851b_efuse * map)505 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
506 struct rtw8851b_efuse *map)
507 {
508 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
509 bool valid = false;
510
511 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
512 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
513 NULL);
514 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
515 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
516 NULL);
517 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
518 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
519 NULL);
520 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
521 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
522 NULL);
523 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
524 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
525 NULL);
526
527 gain->offset_valid = valid;
528 }
529
rtw8851b_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)530 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
531 enum rtw89_efuse_block block)
532 {
533 struct rtw89_efuse *efuse = &rtwdev->efuse;
534 struct rtw8851b_efuse *map;
535
536 map = (struct rtw8851b_efuse *)log_map;
537
538 efuse->country_code[0] = map->country_code[0];
539 efuse->country_code[1] = map->country_code[1];
540 rtw8851b_efuse_parsing_tssi(rtwdev, map);
541 rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
542
543 switch (rtwdev->hci.type) {
544 case RTW89_HCI_TYPE_PCIE:
545 rtw8851b_efuse_parsing(efuse, map);
546 break;
547 default:
548 return -EOPNOTSUPP;
549 }
550
551 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
552
553 return 0;
554 }
555
rtw8851b_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)556 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
557 {
558 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
559 static const u32 tssi_trim_addr[RF_PATH_NUM_8851B] = {0x5D6};
560 u32 addr = rtwdev->chip->phycap_addr;
561 bool pg = false;
562 u32 ofst;
563 u8 i, j;
564
565 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
566 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
567 /* addrs are in decreasing order */
568 ofst = tssi_trim_addr[i] - addr - j;
569 tssi->tssi_trim[i][j] = phycap_map[ofst];
570
571 if (phycap_map[ofst] != 0xff)
572 pg = true;
573 }
574 }
575
576 if (!pg) {
577 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
578 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
579 "[TSSI][TRIM] no PG, set all trim info to 0\n");
580 }
581
582 for (i = 0; i < RF_PATH_NUM_8851B; i++)
583 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
584 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
585 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
586 i, j, tssi->tssi_trim[i][j],
587 tssi_trim_addr[i] - j);
588 }
589
rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)590 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
591 u8 *phycap_map)
592 {
593 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
594 static const u32 thm_trim_addr[RF_PATH_NUM_8851B] = {0x5DF};
595 u32 addr = rtwdev->chip->phycap_addr;
596 u8 i;
597
598 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
599 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
600
601 rtw89_debug(rtwdev, RTW89_DBG_RFK,
602 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
603 i, info->thermal_trim[i]);
604
605 if (info->thermal_trim[i] != 0xff)
606 info->pg_thermal_trim = true;
607 }
608 }
609
rtw8851b_thermal_trim(struct rtw89_dev * rtwdev)610 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
611 {
612 #define __thm_setting(raw) \
613 ({ \
614 u8 __v = (raw); \
615 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
616 })
617 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
618 u8 i, val;
619
620 if (!info->pg_thermal_trim) {
621 rtw89_debug(rtwdev, RTW89_DBG_RFK,
622 "[THERMAL][TRIM] no PG, do nothing\n");
623
624 return;
625 }
626
627 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
628 val = __thm_setting(info->thermal_trim[i]);
629 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
630
631 rtw89_debug(rtwdev, RTW89_DBG_RFK,
632 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
633 i, val);
634 }
635 #undef __thm_setting
636 }
637
rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)638 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
639 u8 *phycap_map)
640 {
641 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
642 static const u32 pabias_trim_addr[] = {0x5DE};
643 u32 addr = rtwdev->chip->phycap_addr;
644 u8 i;
645
646 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
647 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
648
649 rtw89_debug(rtwdev, RTW89_DBG_RFK,
650 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
651 i, info->pa_bias_trim[i]);
652
653 if (info->pa_bias_trim[i] != 0xff)
654 info->pg_pa_bias_trim = true;
655 }
656 }
657
rtw8851b_pa_bias_trim(struct rtw89_dev * rtwdev)658 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
659 {
660 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
661 u8 pabias_2g, pabias_5g;
662 u8 i;
663
664 if (!info->pg_pa_bias_trim) {
665 rtw89_debug(rtwdev, RTW89_DBG_RFK,
666 "[PA_BIAS][TRIM] no PG, do nothing\n");
667
668 return;
669 }
670
671 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
672 pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));
673 pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));
674
675 rtw89_debug(rtwdev, RTW89_DBG_RFK,
676 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
677 i, pabias_2g, pabias_5g);
678
679 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
680 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
681 }
682 }
683
rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev * rtwdev,u8 * phycap_map)684 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
685 {
686 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
687 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
688 };
689 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
690 u32 phycap_addr = rtwdev->chip->phycap_addr;
691 bool valid = false;
692 int path, i;
693 u8 data;
694
695 for (path = 0; path < BB_PATH_NUM_8851B; path++)
696 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
697 if (comp_addrs[path][i] == 0)
698 continue;
699
700 data = phycap_map[comp_addrs[path][i] - phycap_addr];
701 valid |= _decode_efuse_gain(data, NULL,
702 &gain->comp[path][i]);
703 }
704
705 gain->comp_valid = valid;
706 }
707
rtw8851b_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)708 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
709 {
710 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
711 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
712 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
713 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
714
715 return 0;
716 }
717
rtw8851b_set_bb_gpio(struct rtw89_dev * rtwdev,u8 gpio_idx,bool inv,u8 src_sel)718 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
719 u8 src_sel)
720 {
721 u32 addr, mask;
722
723 if (gpio_idx >= 32)
724 return;
725
726 /* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */
727 addr = R_RFE_SEL0_A2 + (gpio_idx / 16) * sizeof(u32);
728 mask = B_RFE_SEL0_MASK << (gpio_idx % 16) * 2;
729
730 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
731 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
732
733 /* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */
734 addr = R_RFE_SEL0_BASE + (gpio_idx / 8) * sizeof(u32);
735 mask = B_RFE_SEL0_SRC_MASK << (gpio_idx % 8) * 4;
736
737 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
738 }
739
rtw8851b_set_mac_gpio(struct rtw89_dev * rtwdev,u8 func)740 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
741 {
742 static const struct rtw89_reg3_def func16 = {
743 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO16_FUNC_SEL_MASK, BIT(3)
744 };
745 static const struct rtw89_reg3_def func17 = {
746 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO17_FUNC_SEL_MASK, BIT(7) >> 4,
747 };
748 const struct rtw89_reg3_def *def;
749
750 switch (func) {
751 case 16:
752 def = &func16;
753 break;
754 case 17:
755 def = &func17;
756 break;
757 default:
758 rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
759 return;
760 }
761
762 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
763 }
764
rtw8851b_rfe_gpio(struct rtw89_dev * rtwdev)765 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
766 {
767 u8 rfe_type = rtwdev->efuse.rfe_type;
768
769 if (rfe_type > 50)
770 return;
771
772 if (rfe_type % 3 == 2) {
773 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
774 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
775
776 rtw8851b_set_mac_gpio(rtwdev, 16);
777 rtw8851b_set_mac_gpio(rtwdev, 17);
778 }
779 }
780
rtw8851b_power_trim(struct rtw89_dev * rtwdev)781 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
782 {
783 rtw8851b_thermal_trim(rtwdev);
784 rtw8851b_pa_bias_trim(rtwdev);
785 }
786
rtw8851b_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)787 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
788 const struct rtw89_chan *chan,
789 u8 mac_idx)
790 {
791 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
792 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
793 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
794 u8 txsc20 = 0, txsc40 = 0;
795
796 switch (chan->band_width) {
797 case RTW89_CHANNEL_WIDTH_80:
798 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
799 fallthrough;
800 case RTW89_CHANNEL_WIDTH_40:
801 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
802 break;
803 default:
804 break;
805 }
806
807 switch (chan->band_width) {
808 case RTW89_CHANNEL_WIDTH_80:
809 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
810 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
811 break;
812 case RTW89_CHANNEL_WIDTH_40:
813 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
814 rtw89_write32(rtwdev, sub_carr, txsc20);
815 break;
816 case RTW89_CHANNEL_WIDTH_20:
817 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
818 rtw89_write32(rtwdev, sub_carr, 0);
819 break;
820 default:
821 break;
822 }
823
824 if (chan->channel > 14) {
825 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
826 rtw89_write8_set(rtwdev, chk_rate,
827 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
828 } else {
829 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
830 rtw89_write8_clr(rtwdev, chk_rate,
831 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
832 }
833 }
834
835 static const u32 rtw8851b_sco_barker_threshold[14] = {
836 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
837 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
838 };
839
840 static const u32 rtw8851b_sco_cck_threshold[14] = {
841 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
842 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
843 };
844
rtw8851b_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch)845 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
846 {
847 u8 ch_element = primary_ch - 1;
848
849 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
850 rtw8851b_sco_barker_threshold[ch_element]);
851 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
852 rtw8851b_sco_cck_threshold[ch_element]);
853 }
854
rtw8851b_sco_mapping(u8 central_ch)855 static u8 rtw8851b_sco_mapping(u8 central_ch)
856 {
857 if (central_ch == 1)
858 return 109;
859 else if (central_ch >= 2 && central_ch <= 6)
860 return 108;
861 else if (central_ch >= 7 && central_ch <= 10)
862 return 107;
863 else if (central_ch >= 11 && central_ch <= 14)
864 return 106;
865 else if (central_ch == 36 || central_ch == 38)
866 return 51;
867 else if (central_ch >= 40 && central_ch <= 58)
868 return 50;
869 else if (central_ch >= 60 && central_ch <= 64)
870 return 49;
871 else if (central_ch == 100 || central_ch == 102)
872 return 48;
873 else if (central_ch >= 104 && central_ch <= 126)
874 return 47;
875 else if (central_ch >= 128 && central_ch <= 151)
876 return 46;
877 else if (central_ch >= 153 && central_ch <= 177)
878 return 45;
879 else
880 return 0;
881 }
882
883 struct rtw8851b_bb_gain {
884 u32 gain_g[BB_PATH_NUM_8851B];
885 u32 gain_a[BB_PATH_NUM_8851B];
886 u32 gain_mask;
887 };
888
889 static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
890 { .gain_g = {0x4678}, .gain_a = {0x45DC},
891 .gain_mask = 0x00ff0000 },
892 { .gain_g = {0x4678}, .gain_a = {0x45DC},
893 .gain_mask = 0xff000000 },
894 { .gain_g = {0x467C}, .gain_a = {0x4660},
895 .gain_mask = 0x000000ff },
896 { .gain_g = {0x467C}, .gain_a = {0x4660},
897 .gain_mask = 0x0000ff00 },
898 { .gain_g = {0x467C}, .gain_a = {0x4660},
899 .gain_mask = 0x00ff0000 },
900 { .gain_g = {0x467C}, .gain_a = {0x4660},
901 .gain_mask = 0xff000000 },
902 { .gain_g = {0x4680}, .gain_a = {0x4664},
903 .gain_mask = 0x000000ff },
904 };
905
906 static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
907 { .gain_g = {0x4680}, .gain_a = {0x4664},
908 .gain_mask = 0x00ff0000 },
909 { .gain_g = {0x4680}, .gain_a = {0x4664},
910 .gain_mask = 0xff000000 },
911 };
912
rtw8851b_set_gain_error(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_rf_path path)913 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
914 enum rtw89_subband subband,
915 enum rtw89_rf_path path)
916 {
917 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
918 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
919 s32 val;
920 u32 reg;
921 u32 mask;
922 int i;
923
924 for (i = 0; i < LNA_GAIN_NUM; i++) {
925 if (subband == RTW89_CH_2G)
926 reg = bb_gain_lna[i].gain_g[path];
927 else
928 reg = bb_gain_lna[i].gain_a[path];
929
930 mask = bb_gain_lna[i].gain_mask;
931 val = gain->lna_gain[gain_band][path][i];
932 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
933 }
934
935 for (i = 0; i < TIA_GAIN_NUM; i++) {
936 if (subband == RTW89_CH_2G)
937 reg = bb_gain_tia[i].gain_g[path];
938 else
939 reg = bb_gain_tia[i].gain_a[path];
940
941 mask = bb_gain_tia[i].gain_mask;
942 val = gain->tia_gain[gain_band][path][i];
943 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
944 }
945 }
946
rtw8851b_set_gain_offset(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_phy_idx phy_idx)947 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
948 enum rtw89_subband subband,
949 enum rtw89_phy_idx phy_idx)
950 {
951 static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1};
952 static const u32 gain_err_addr[] = {R_P0_AGC_RSVD};
953 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
954 enum rtw89_gain_offset gain_ofdm_band;
955 s32 offset_ofdm, offset_cck;
956 s32 offset_a;
957 s32 tmp;
958 u8 path;
959
960 if (!efuse_gain->comp_valid)
961 goto next;
962
963 for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) {
964 tmp = efuse_gain->comp[path][subband];
965 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
966 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
967 }
968
969 next:
970 if (!efuse_gain->offset_valid)
971 return;
972
973 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
974
975 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
976
977 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
978 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
979 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
980
981 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
982 offset_cck = -efuse_gain->offset[RF_PATH_A][0];
983
984 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
985 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
986 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
987
988 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
989 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
990 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
991
992 if (subband == RTW89_CH_2G) {
993 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
994 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
995 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
996 B_RX_RPL_OFST_CCK_MASK, tmp);
997 }
998 }
999
1000 static
rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev * rtwdev,enum rtw89_subband subband)1001 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
1002 {
1003 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1004 u8 band = rtw89_subband_to_bb_gain_band(subband);
1005 u32 val;
1006
1007 val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
1008 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
1009 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
1010 val >>= B_P0_RPL1_SHIFT;
1011 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
1012 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
1013
1014 val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
1015 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
1016 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
1017 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
1018 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
1019 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
1020
1021 val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
1022 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
1023 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
1024 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
1025 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
1026 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
1027 }
1028
rtw8851b_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1029 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
1030 const struct rtw89_chan *chan,
1031 enum rtw89_phy_idx phy_idx)
1032 {
1033 u8 subband = chan->subband_type;
1034 u8 central_ch = chan->channel;
1035 bool is_2g = central_ch <= 14;
1036 u8 sco_comp;
1037
1038 if (is_2g)
1039 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1040 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
1041 else
1042 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1043 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
1044 /* SCO compensate FC setting */
1045 sco_comp = rtw8851b_sco_mapping(central_ch);
1046 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1047
1048 if (chan->band_type == RTW89_BAND_6G)
1049 return;
1050
1051 /* CCK parameters */
1052 if (central_ch == 14) {
1053 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1054 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1055 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1056 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1057 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1058 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1059 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1060 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1061 } else {
1062 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1063 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1064 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1065 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1066 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1067 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1068 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1069 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1070 }
1071
1072 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
1073 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1074 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
1075 }
1076
rtw8851b_bw_setting(struct rtw89_dev * rtwdev,u8 bw)1077 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
1078 {
1079 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
1080 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
1081 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
1082 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
1083 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
1084 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
1085 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
1086
1087 switch (bw) {
1088 case RTW89_CHANNEL_WIDTH_5:
1089 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1090 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
1091 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
1092 break;
1093 case RTW89_CHANNEL_WIDTH_10:
1094 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1095 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
1096 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1097 break;
1098 case RTW89_CHANNEL_WIDTH_20:
1099 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1100 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1101 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1102 break;
1103 case RTW89_CHANNEL_WIDTH_40:
1104 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1105 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1106 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1107 break;
1108 case RTW89_CHANNEL_WIDTH_80:
1109 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1110 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1111 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1112 break;
1113 default:
1114 rtw89_warn(rtwdev, "Fail to set ADC\n");
1115 }
1116 }
1117
rtw8851b_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)1118 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1119 enum rtw89_phy_idx phy_idx)
1120 {
1121 switch (bw) {
1122 case RTW89_CHANNEL_WIDTH_5:
1123 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1124 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1125 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1126 break;
1127 case RTW89_CHANNEL_WIDTH_10:
1128 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1129 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1130 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1131 break;
1132 case RTW89_CHANNEL_WIDTH_20:
1133 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1134 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1135 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1136 break;
1137 case RTW89_CHANNEL_WIDTH_40:
1138 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1139 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1140 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1141 pri_ch, phy_idx);
1142 /* CCK primary channel */
1143 if (pri_ch == RTW89_SC_20_UPPER)
1144 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1145 else
1146 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1147
1148 break;
1149 case RTW89_CHANNEL_WIDTH_80:
1150 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1151 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1152 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1153 pri_ch, phy_idx);
1154 break;
1155 default:
1156 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1157 pri_ch);
1158 }
1159
1160 rtw8851b_bw_setting(rtwdev, bw);
1161 }
1162
rtw8851b_ctrl_cck_en(struct rtw89_dev * rtwdev,bool cck_en)1163 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1164 {
1165 if (cck_en) {
1166 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1167 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1168 B_PD_ARBITER_OFF, 0);
1169 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1170 } else {
1171 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1172 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1173 B_PD_ARBITER_OFF, 1);
1174 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1175 }
1176 }
1177
rtw8851b_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1178 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
1179 const struct rtw89_chan *chan)
1180 {
1181 u8 center_chan = chan->channel;
1182
1183 switch (chan->band_type) {
1184 case RTW89_BAND_5G:
1185 if (center_chan == 151 || center_chan == 153 ||
1186 center_chan == 155 || center_chan == 163)
1187 return 5760;
1188 else if (center_chan == 54 || center_chan == 58)
1189 return 5280;
1190 break;
1191 default:
1192 break;
1193 }
1194
1195 return 0;
1196 }
1197
1198 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1199 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1200 #define MAX_TONE_NUM 2048
1201
rtw8851b_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1202 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1203 const struct rtw89_chan *chan,
1204 enum rtw89_phy_idx phy_idx)
1205 {
1206 u32 spur_freq;
1207 s32 freq_diff, csi_idx, csi_tone_idx;
1208
1209 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1210 if (spur_freq == 0) {
1211 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1212 0, phy_idx);
1213 return;
1214 }
1215
1216 freq_diff = (spur_freq - chan->freq) * 1000000;
1217 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1218 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1219
1220 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1221 csi_tone_idx, phy_idx);
1222 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1223 }
1224
1225 static const struct rtw89_nbi_reg_def rtw8851b_nbi_reg_def = {
1226 .notch1_idx = {0x46E4, 0xFF},
1227 .notch1_frac_idx = {0x46E4, 0xC00},
1228 .notch1_en = {0x46E4, 0x1000},
1229 .notch2_idx = {0x47A4, 0xFF},
1230 .notch2_frac_idx = {0x47A4, 0xC00},
1231 .notch2_en = {0x47A4, 0x1000},
1232 };
1233
rtw8851b_set_nbi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1234 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1235 const struct rtw89_chan *chan)
1236 {
1237 const struct rtw89_nbi_reg_def *nbi = &rtw8851b_nbi_reg_def;
1238 s32 nbi_frac_idx, nbi_frac_tone_idx;
1239 s32 nbi_idx, nbi_tone_idx;
1240 bool notch2_chk = false;
1241 u32 spur_freq, fc;
1242 s32 freq_diff;
1243
1244 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1245 if (spur_freq == 0) {
1246 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1247 nbi->notch1_en.mask, 0);
1248 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1249 nbi->notch2_en.mask, 0);
1250 return;
1251 }
1252
1253 fc = chan->freq;
1254 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1255 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1256 if ((fc > spur_freq &&
1257 chan->channel < chan->primary_channel) ||
1258 (fc < spur_freq &&
1259 chan->channel > chan->primary_channel))
1260 notch2_chk = true;
1261 }
1262
1263 freq_diff = (spur_freq - fc) * 1000000;
1264 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
1265 &nbi_frac_idx);
1266
1267 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1268 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1269 } else {
1270 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1271 128 : 256;
1272
1273 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1274 }
1275 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx,
1276 CARRIER_SPACING_78_125);
1277
1278 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1279 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1280 nbi->notch2_idx.mask, nbi_tone_idx);
1281 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1282 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1283 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1284 nbi->notch2_en.mask, 0);
1285 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1286 nbi->notch2_en.mask, 1);
1287 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1288 nbi->notch1_en.mask, 0);
1289 } else {
1290 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1291 nbi->notch1_idx.mask, nbi_tone_idx);
1292 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1293 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1294 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1295 nbi->notch1_en.mask, 0);
1296 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1297 nbi->notch1_en.mask, 1);
1298 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1299 nbi->notch2_en.mask, 0);
1300 }
1301 }
1302
rtw8851b_set_cfr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1303 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
1304 {
1305 if (chan->band_type == RTW89_BAND_2G &&
1306 chan->band_width == RTW89_CHANNEL_WIDTH_20 &&
1307 (chan->channel == 1 || chan->channel == 13)) {
1308 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1309 B_PATH0_TX_CFR_LGC0, 0xf8);
1310 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1311 B_PATH0_TX_CFR_LGC1, 0x120);
1312 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1313 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x0);
1314 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1315 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x3);
1316 } else {
1317 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1318 B_PATH0_TX_CFR_LGC0, 0x120);
1319 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1320 B_PATH0_TX_CFR_LGC1, 0x3ff);
1321 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1322 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x3);
1323 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1324 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x7);
1325 }
1326 }
1327
rtw8851b_5m_mask(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1328 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1329 enum rtw89_phy_idx phy_idx)
1330 {
1331 u8 pri_ch = chan->pri_ch_idx;
1332 bool mask_5m_low;
1333 bool mask_5m_en;
1334
1335 switch (chan->band_width) {
1336 case RTW89_CHANNEL_WIDTH_40:
1337 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
1338 mask_5m_en = true;
1339 mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1340 break;
1341 case RTW89_CHANNEL_WIDTH_80:
1342 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
1343 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1344 pri_ch == RTW89_SC_20_LOWEST;
1345 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1346 break;
1347 default:
1348 mask_5m_en = false;
1349 break;
1350 }
1351
1352 if (!mask_5m_en) {
1353 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1354 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1355 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1356 return;
1357 }
1358
1359 if (mask_5m_low) {
1360 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1361 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1362 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1363 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1364 } else {
1365 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1366 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1367 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1368 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1369 }
1370 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1371 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1372 }
1373
rtw8851b_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1374 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1375 {
1376 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1377 fsleep(1);
1378 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1379 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1380 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1381 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1382 }
1383
rtw8851b_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,enum rtw89_phy_idx phy_idx,bool en)1384 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1385 enum rtw89_phy_idx phy_idx, bool en)
1386 {
1387 if (en) {
1388 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1389 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1390 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1391 if (band == RTW89_BAND_2G)
1392 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1393 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1394 } else {
1395 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1396 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1397 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1398 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1399 fsleep(1);
1400 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1401 }
1402 }
1403
rtw8851b_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1404 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
1405 enum rtw89_phy_idx phy_idx)
1406 {
1407 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1408 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1);
1409 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1410 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1411 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1412 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3);
1413 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1414 }
1415
1416 static
rtw8851b_bb_gpio_trsw(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 tx_path_en,u8 trsw_tx,u8 trsw_rx,u8 trsw_a,u8 trsw_b)1417 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1418 u8 tx_path_en, u8 trsw_tx,
1419 u8 trsw_rx, u8 trsw_a, u8 trsw_b)
1420 {
1421 u32 mask_ofst = 16;
1422 u32 val;
1423
1424 if (path != RF_PATH_A)
1425 return;
1426
1427 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1428 val = u32_encode_bits(trsw_a, B_P0_TRSW_A) |
1429 u32_encode_bits(trsw_b, B_P0_TRSW_B);
1430
1431 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
1432 (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1433 }
1434
rtw8851b_bb_gpio_init(struct rtw89_dev * rtwdev)1435 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
1436 {
1437 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
1438 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
1439 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
1440 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
1441 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
1442
1443 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1444 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1445 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1446 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1447
1448 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1449 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1450 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1451 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1452 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1453 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1454 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1455 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1456 }
1457
rtw8851b_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1458 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1459 enum rtw89_phy_idx phy_idx)
1460 {
1461 u32 addr;
1462
1463 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1464 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1465 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1466 }
1467
rtw8851b_bb_sethw(struct rtw89_dev * rtwdev)1468 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
1469 {
1470 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1471
1472 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1473
1474 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1475 rtw8851b_bb_gpio_init(rtwdev);
1476
1477 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
1478 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
1479
1480 /* read these registers after loading BB parameters */
1481 gain->offset_base[RTW89_PHY_0] =
1482 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1483 gain->rssi_base[RTW89_PHY_0] =
1484 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1485 }
1486
rtw8851b_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1487 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1488 enum rtw89_phy_idx phy_idx)
1489 {
1490 u8 band = chan->band_type, chan_idx;
1491 bool cck_en = chan->channel <= 14;
1492 u8 pri_ch_idx = chan->pri_ch_idx;
1493
1494 if (cck_en)
1495 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1496
1497 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1498 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1499 rtw8851b_ctrl_cck_en(rtwdev, cck_en);
1500 rtw8851b_set_nbi_tone_idx(rtwdev, chan);
1501 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1502
1503 if (chan->band_type == RTW89_BAND_5G) {
1504 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1505 B_PATH0_BT_SHARE_V1, 0x0);
1506 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1507 B_PATH0_BTG_PATH_V1, 0x0);
1508 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1509 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1510 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1511 B_BT_DYN_DC_EST_EN_MSK, 0x0);
1512 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1513 }
1514
1515 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1516 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1517 rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1518 rtw8851b_set_cfr(rtwdev, chan);
1519 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1520 }
1521
rtw8851b_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1522 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
1523 const struct rtw89_chan *chan,
1524 enum rtw89_mac_idx mac_idx,
1525 enum rtw89_phy_idx phy_idx)
1526 {
1527 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
1528 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1529 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1530 }
1531
rtw8851b_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)1532 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1533 enum rtw89_rf_path path)
1534 {
1535 if (en) {
1536 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
1537 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
1538 } else {
1539 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
1540 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
1541 }
1542 }
1543
rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)1544 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1545 u8 phy_idx)
1546 {
1547 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1548 }
1549
rtw8851b_adc_en(struct rtw89_dev * rtwdev,bool en)1550 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
1551 {
1552 if (en)
1553 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1554 else
1555 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1556 }
1557
rtw8851b_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1558 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1559 struct rtw89_channel_help_params *p,
1560 const struct rtw89_chan *chan,
1561 enum rtw89_mac_idx mac_idx,
1562 enum rtw89_phy_idx phy_idx)
1563 {
1564 if (enter) {
1565 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1566 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1567 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1568 rtw8851b_adc_en(rtwdev, false);
1569 fsleep(40);
1570 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1571 } else {
1572 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1573 rtw8851b_adc_en(rtwdev, true);
1574 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1575 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1576 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1577 }
1578 }
1579
rtw8851b_rfk_init(struct rtw89_dev * rtwdev)1580 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
1581 {
1582 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1583 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1584 rtw8851b_lck_init(rtwdev);
1585
1586 rtw8851b_dpk_init(rtwdev);
1587 rtw8851b_aack(rtwdev);
1588 rtw8851b_rck(rtwdev);
1589 rtw8851b_dack(rtwdev);
1590 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0);
1591 }
1592
rtw8851b_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)1593 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev,
1594 struct rtw89_vif_link *rtwvif_link)
1595 {
1596 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
1597 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
1598
1599 rtw8851b_rx_dck(rtwdev, phy_idx, chanctx_idx);
1600 rtw8851b_iqk(rtwdev, phy_idx, chanctx_idx);
1601 rtw8851b_tssi(rtwdev, phy_idx, true, chanctx_idx);
1602 rtw8851b_dpk(rtwdev, phy_idx, chanctx_idx);
1603 }
1604
rtw8851b_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)1605 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
1606 enum rtw89_phy_idx phy_idx,
1607 const struct rtw89_chan *chan)
1608 {
1609 rtw8851b_tssi_scan(rtwdev, phy_idx, chan);
1610 }
1611
rtw8851b_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)1612 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev,
1613 struct rtw89_vif_link *rtwvif_link,
1614 bool start)
1615 {
1616 rtw8851b_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx,
1617 rtwvif_link->chanctx_idx);
1618 }
1619
rtw8851b_rfk_track(struct rtw89_dev * rtwdev)1620 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
1621 {
1622 rtw8851b_dpk_track(rtwdev);
1623 rtw8851b_lck_track(rtwdev);
1624 }
1625
rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1626 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1627 enum rtw89_phy_idx phy_idx, s16 ref)
1628 {
1629 const u16 tssi_16dbm_cw = 0x12c;
1630 const u8 base_cw_0db = 0x27;
1631 const s8 ofst_int = 0;
1632 s16 pwr_s10_3;
1633 s16 rf_pwr_cw;
1634 u16 bb_pwr_cw;
1635 u32 pwr_cw;
1636 u32 tssi_ofst_cw;
1637
1638 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1639 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
1640 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
1641 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1642 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1643
1644 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1645 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1646 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1647 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1648
1649 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
1650 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
1651 u32_encode_bits(ref, B_DPD_REF);
1652 }
1653
rtw8851b_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1654 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1655 enum rtw89_phy_idx phy_idx)
1656 {
1657 static const u32 addr[RF_PATH_NUM_8851B] = {0x5800};
1658 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
1659 const u8 ofst_ofdm = 0x4;
1660 const u8 ofst_cck = 0x8;
1661 const s16 ref_ofdm = 0;
1662 const s16 ref_cck = 0;
1663 u32 val;
1664 u8 i;
1665
1666 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1667
1668 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1669 B_AX_PWR_REF, 0x0);
1670
1671 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1672 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1673
1674 for (i = 0; i < RF_PATH_NUM_8851B; i++)
1675 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1676 phy_idx);
1677
1678 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1679 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1680
1681 for (i = 0; i < RF_PATH_NUM_8851B; i++)
1682 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1683 phy_idx);
1684 }
1685
rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 tx_shape_idx,enum rtw89_phy_idx phy_idx)1686 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1687 const struct rtw89_chan *chan,
1688 u8 tx_shape_idx,
1689 enum rtw89_phy_idx phy_idx)
1690 {
1691 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
1692 #define __DFIR_CFG_MASK 0xffffffff
1693 #define __DFIR_CFG_NR 8
1694 #define __DECL_DFIR_PARAM(_name, _val...) \
1695 static const u32 param_ ## _name[] = {_val}; \
1696 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
1697
1698 __DECL_DFIR_PARAM(flat,
1699 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1700 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1701 __DECL_DFIR_PARAM(sharp,
1702 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1703 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
1704 __DECL_DFIR_PARAM(sharp_14,
1705 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1706 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
1707 u8 ch = chan->channel;
1708 const u32 *param;
1709 u32 addr;
1710 int i;
1711
1712 if (ch > 14) {
1713 rtw89_warn(rtwdev,
1714 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
1715 return;
1716 }
1717
1718 if (ch == 14)
1719 param = param_sharp_14;
1720 else
1721 param = tx_shape_idx == 0 ? param_flat : param_sharp;
1722
1723 for (i = 0; i < __DFIR_CFG_NR; i++) {
1724 addr = __DFIR_CFG_ADDR(i);
1725 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1726 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
1727 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1728 phy_idx);
1729 }
1730
1731 #undef __DECL_DFIR_PARAM
1732 #undef __DFIR_CFG_NR
1733 #undef __DFIR_CFG_MASK
1734 #undef __DECL_CFG_ADDR
1735 }
1736
rtw8851b_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1737 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
1738 const struct rtw89_chan *chan,
1739 enum rtw89_phy_idx phy_idx)
1740 {
1741 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1742 u8 band = chan->band_type;
1743 u8 regd = rtw89_regd_get(rtwdev, band);
1744 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd];
1745 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd];
1746
1747 if (band == RTW89_BAND_2G)
1748 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1749
1750 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1751 tx_shape_ofdm);
1752 }
1753
rtw8851b_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1754 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
1755 const struct rtw89_chan *chan,
1756 enum rtw89_phy_idx phy_idx)
1757 {
1758 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1759 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1760 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1761 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1762 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1763 }
1764
rtw8851b_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1765 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1766 enum rtw89_phy_idx phy_idx)
1767 {
1768 rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1769 }
1770
1771 static
rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1772 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1773 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1774 {
1775 u32 reg;
1776
1777 if (pw_ofst < -16 || pw_ofst > 15) {
1778 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1779 return;
1780 }
1781
1782 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1783 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1784
1785 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1786 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1787
1788 pw_ofst = max_t(s8, pw_ofst - 3, -16);
1789 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1790 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1791 }
1792
1793 static int
rtw8851b_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1794 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1795 {
1796 int ret;
1797
1798 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1799 if (ret)
1800 return ret;
1801
1802 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1803 if (ret)
1804 return ret;
1805
1806 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1807 if (ret)
1808 return ret;
1809
1810 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1811 RTW89_MAC_1 : RTW89_MAC_0);
1812
1813 return 0;
1814 }
1815
rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1816 static void rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1817 enum rtw89_phy_idx phy_idx)
1818 {
1819 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1820
1821 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8851b_btc_preagc_en_defs_tbl :
1822 &rtw8851b_btc_preagc_dis_defs_tbl);
1823
1824 if (!en) {
1825 if (chan->band_type == RTW89_BAND_2G) {
1826 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1827 B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1828 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1829 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1830 } else {
1831 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1832 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1833 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1834 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1835 }
1836 }
1837 }
1838
rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1839 static void rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1840 enum rtw89_phy_idx phy_idx)
1841 {
1842 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1843
1844 if (en) {
1845 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1846 B_PATH0_BT_SHARE_V1, 0x1);
1847 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1848 B_PATH0_BTG_PATH_V1, 0x1);
1849 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1850 B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1851 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1852 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1853 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1854 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1855 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
1856 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1857 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1858 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1859 } else {
1860 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1861 B_PATH0_BT_SHARE_V1, 0x0);
1862 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1863 B_PATH0_BTG_PATH_V1, 0x0);
1864 if (chan->band_type == RTW89_BAND_2G) {
1865 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1866 B_PATH0_G_LNA6_OP1DB_V1, 0x80);
1867 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1868 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
1869 } else {
1870 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1871 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1872 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1873 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1874 }
1875 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1876 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1877 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1878 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1879 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1880 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1881 }
1882 }
1883
rtw8851b_bb_ctrl_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path)1884 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1885 enum rtw89_rf_path_bit rx_path)
1886 {
1887 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1888 u32 rst_mask0;
1889
1890 if (rx_path == RF_A) {
1891 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1892 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1893 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1894 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1895 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1896 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1897 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1898 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1899 }
1900
1901 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1902
1903 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1904 if (rx_path == RF_A) {
1905 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1906 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1907 }
1908 }
1909
rtw8851b_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)1910 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1911 {
1912 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
1913
1914 if (rtwdev->hal.rx_nss == 1) {
1915 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1916 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1917 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1918 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1919 }
1920
1921 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1922 }
1923
rtw8851b_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1924 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1925 {
1926 if (rtwdev->is_tssi_mode[rf_path]) {
1927 u32 addr = R_TSSI_THER + (rf_path << 13);
1928
1929 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
1930 }
1931
1932 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1933 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1934 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1935
1936 fsleep(200);
1937
1938 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1939 }
1940
rtw8851b_btc_set_rfe(struct rtw89_dev * rtwdev)1941 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
1942 {
1943 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
1944 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
1945
1946 if (ver->fcxinit == 7) {
1947 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
1948 md->md_v7.kt_ver = rtwdev->hal.cv;
1949 md->md_v7.bt_solo = 0;
1950 md->md_v7.switch_type = BTC_SWITCH_INTERNAL;
1951 md->md_v7.ant.isolation = 10;
1952 md->md_v7.kt_ver_adie = rtwdev->hal.acv;
1953
1954 if (md->md_v7.rfe_type == 0)
1955 return;
1956
1957 /* rfe_type 3*n+1: 1-Ant(shared),
1958 * 3*n+2: 2-Ant+Div(non-shared),
1959 * 3*n+3: 2-Ant+no-Div(non-shared)
1960 */
1961 md->md_v7.ant.num = (md->md_v7.rfe_type % 3 == 1) ? 1 : 2;
1962 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
1963 md->md_v7.ant.single_pos = RF_PATH_A;
1964 md->md_v7.ant.btg_pos = RF_PATH_A;
1965 md->md_v7.ant.stream_cnt = 1;
1966
1967 if (md->md_v7.ant.num == 1) {
1968 md->md_v7.ant.type = BTC_ANT_SHARED;
1969 md->md_v7.bt_pos = BTC_BT_BTG;
1970 md->md_v7.wa_type = 1;
1971 md->md_v7.ant.diversity = 0;
1972 } else { /* ant.num == 2 */
1973 md->md_v7.ant.type = BTC_ANT_DEDICATED;
1974 md->md_v7.bt_pos = BTC_BT_ALONE;
1975 md->md_v7.switch_type = BTC_SWITCH_EXTERNAL;
1976 md->md_v7.wa_type = 0;
1977 if (md->md_v7.rfe_type % 3 == 2)
1978 md->md_v7.ant.diversity = 1;
1979 }
1980 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
1981 rtwdev->btc.ant_type = md->md_v7.ant.type;
1982 } else {
1983 md->md.rfe_type = rtwdev->efuse.rfe_type;
1984 md->md.cv = rtwdev->hal.cv;
1985 md->md.bt_solo = 0;
1986 md->md.switch_type = BTC_SWITCH_INTERNAL;
1987 md->md.ant.isolation = 10;
1988 md->md.kt_ver_adie = rtwdev->hal.acv;
1989
1990 if (md->md.rfe_type == 0)
1991 return;
1992
1993 /* rfe_type 3*n+1: 1-Ant(shared),
1994 * 3*n+2: 2-Ant+Div(non-shared),
1995 * 3*n+3: 2-Ant+no-Div(non-shared)
1996 */
1997 md->md.ant.num = (md->md.rfe_type % 3 == 1) ? 1 : 2;
1998 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
1999 md->md.ant.single_pos = RF_PATH_A;
2000 md->md.ant.btg_pos = RF_PATH_A;
2001 md->md.ant.stream_cnt = 1;
2002
2003 if (md->md.ant.num == 1) {
2004 md->md.ant.type = BTC_ANT_SHARED;
2005 md->md.bt_pos = BTC_BT_BTG;
2006 md->md.wa_type = 1;
2007 md->md.ant.diversity = 0;
2008 } else { /* ant.num == 2 */
2009 md->md.ant.type = BTC_ANT_DEDICATED;
2010 md->md.bt_pos = BTC_BT_ALONE;
2011 md->md.switch_type = BTC_SWITCH_EXTERNAL;
2012 md->md.wa_type = 0;
2013 if (md->md.rfe_type % 3 == 2)
2014 md->md.ant.diversity = 1;
2015 }
2016 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
2017 rtwdev->btc.ant_type = md->md.ant.type;
2018 }
2019 }
2020
2021 static
rtw8851b_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)2022 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2023 {
2024 if (group > BTC_BT_SS_GROUP)
2025 group--; /* Tx-group=1, Rx-group=2 */
2026
2027 if (rtwdev->btc.ant_type == BTC_ANT_SHARED) /* 1-Ant */
2028 group += 3;
2029
2030 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2031 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2032 }
2033
rtw8851b_btc_init_cfg(struct rtw89_dev * rtwdev)2034 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
2035 {
2036 static const struct rtw89_mac_ax_coex coex_params = {
2037 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
2038 .direction = RTW89_MAC_AX_COEX_INNER,
2039 };
2040 const struct rtw89_chip_info *chip = rtwdev->chip;
2041 struct rtw89_btc *btc = &rtwdev->btc;
2042 union rtw89_btc_module_info *md = &btc->mdinfo;
2043 const struct rtw89_btc_ver *ver = btc->ver;
2044 u8 path, path_min, path_max, str_cnt, ant_sing_pos;
2045
2046 /* PTA init */
2047 rtw89_mac_coex_init(rtwdev, &coex_params);
2048
2049 /* set WL Tx response = Hi-Pri */
2050 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2051 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2052
2053 if (ver->fcxinit == 7) {
2054 str_cnt = md->md_v7.ant.stream_cnt;
2055 ant_sing_pos = md->md_v7.ant.single_pos;
2056 } else {
2057 str_cnt = md->md.ant.stream_cnt;
2058 ant_sing_pos = md->md.ant.single_pos;
2059 }
2060
2061 /* for 1-Ant && 1-ss case: only 1-path */
2062 if (str_cnt == 1) {
2063 path_min = ant_sing_pos;
2064 path_max = path_min;
2065 } else {
2066 path_min = RF_PATH_A;
2067 path_max = RF_PATH_B;
2068 }
2069
2070 for (path = path_min; path <= path_max; path++) {
2071 /* set rf gnt-debug off */
2072 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
2073
2074 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
2075 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
2076
2077 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */
2078 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
2079
2080 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
2081 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
2082
2083 /* if GNT_WL = 0 && BT = Tx_group -->
2084 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
2085 */
2086 if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path)
2087 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2088 else
2089 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2090
2091 /* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */
2092 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2093 }
2094
2095 /* set PTA break table */
2096 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2097
2098 /* enable BT counter 0xda40[16,2] = 2b'11 */
2099 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2100
2101 btc->cx.wl.status.map.init_ok = true;
2102 }
2103
2104 static
rtw8851b_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)2105 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2106 {
2107 u32 bitmap;
2108 u32 reg;
2109
2110 switch (map) {
2111 case BTC_PRI_MASK_TX_RESP:
2112 reg = R_BTC_BT_COEX_MSK_TABLE;
2113 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
2114 break;
2115 case BTC_PRI_MASK_BEACON:
2116 reg = R_AX_WL_PRI_MSK;
2117 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
2118 break;
2119 case BTC_PRI_MASK_RX_CCK:
2120 reg = R_BTC_BT_COEX_MSK_TABLE;
2121 bitmap = B_BTC_PRI_MASK_RXCCK_V1;
2122 break;
2123 default:
2124 return;
2125 }
2126
2127 if (state)
2128 rtw89_write32_set(rtwdev, reg, bitmap);
2129 else
2130 rtw89_write32_clr(rtwdev, reg, bitmap);
2131 }
2132
2133 union rtw8851b_btc_wl_txpwr_ctrl {
2134 u32 txpwr_val;
2135 struct {
2136 union {
2137 u16 ctrl_all_time;
2138 struct {
2139 s16 data:9;
2140 u16 rsvd:6;
2141 u16 flag:1;
2142 } all_time;
2143 };
2144 union {
2145 u16 ctrl_gnt_bt;
2146 struct {
2147 s16 data:9;
2148 u16 rsvd:7;
2149 } gnt_bt;
2150 };
2151 };
2152 } __packed;
2153
2154 static void
rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)2155 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2156 {
2157 union rtw8851b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2158 s32 val;
2159
2160 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2161 do { \
2162 u32 _wrt = FIELD_PREP(_msk, _val); \
2163 BUILD_BUG_ON(!!(_msk & _en)); \
2164 if (_cond) \
2165 _wrt |= _en; \
2166 else \
2167 _wrt &= ~_en; \
2168 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2169 _msk | _en, _wrt); \
2170 } while (0)
2171
2172 switch (arg.ctrl_all_time) {
2173 case 0xffff:
2174 val = 0;
2175 break;
2176 default:
2177 val = arg.all_time.data;
2178 break;
2179 }
2180
2181 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2182 val, B_AX_FORCE_PWR_BY_RATE_EN,
2183 arg.ctrl_all_time != 0xffff);
2184
2185 switch (arg.ctrl_gnt_bt) {
2186 case 0xffff:
2187 val = 0;
2188 break;
2189 default:
2190 val = arg.gnt_bt.data;
2191 break;
2192 }
2193
2194 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2195 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2196
2197 #undef __write_ctrl
2198 }
2199
2200 static
rtw8851b_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)2201 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2202 {
2203 val = clamp_t(s8, val, -100, 0) + 100;
2204 val = min(val + 6, 100); /* compensate offset */
2205
2206 return val;
2207 }
2208
2209 static
rtw8851b_btc_update_bt_cnt(struct rtw89_dev * rtwdev)2210 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2211 {
2212 /* Feature move to firmware */
2213 }
2214
rtw8851b_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)2215 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2216 {
2217 struct rtw89_btc *btc = &rtwdev->btc;
2218
2219 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2220 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2221 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2222
2223 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2224 if (state)
2225 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2226 else
2227 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2228
2229 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2230 }
2231
2232 #define LNA2_51B_MA 0x700
2233
2234 static const struct rtw89_reg2_def btc_8851b_rf_0[] = {{0x2, 0x0}};
2235 static const struct rtw89_reg2_def btc_8851b_rf_1[] = {{0x2, 0x1}};
2236
rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)2237 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2238 {
2239 /* To improve BT ACI in co-rx
2240 * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2241 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2242 */
2243 struct rtw89_btc *btc = &rtwdev->btc;
2244 const struct rtw89_reg2_def *rf;
2245 u32 n, i, val;
2246
2247 switch (level) {
2248 case 0: /* original */
2249 default:
2250 btc->dm.wl_lna2 = 0;
2251 break;
2252 case 1: /* for FDD free-run */
2253 btc->dm.wl_lna2 = 0;
2254 break;
2255 case 2: /* for BTG Co-Rx*/
2256 btc->dm.wl_lna2 = 1;
2257 break;
2258 }
2259
2260 if (btc->dm.wl_lna2 == 0) {
2261 rf = btc_8851b_rf_0;
2262 n = ARRAY_SIZE(btc_8851b_rf_0);
2263 } else {
2264 rf = btc_8851b_rf_1;
2265 n = ARRAY_SIZE(btc_8851b_rf_1);
2266 }
2267
2268 for (i = 0; i < n; i++, rf++) {
2269 val = rf->data;
2270 /* bit[10] = 1 if non-shared-ant for 8851b */
2271 if (btc->ant_type == BTC_ANT_DEDICATED)
2272 val |= 0x4;
2273
2274 rtw89_write_rf(rtwdev, btc->btg_pos, rf->addr, LNA2_51B_MA, val);
2275 }
2276 }
2277
rtw8851b_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2278 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2279 struct rtw89_rx_phy_ppdu *phy_ppdu,
2280 struct ieee80211_rx_status *status)
2281 {
2282 u16 chan = phy_ppdu->chan_idx;
2283 enum nl80211_band band;
2284 u8 ch;
2285
2286 if (chan == 0)
2287 return;
2288
2289 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
2290 status->freq = ieee80211_channel_to_frequency(ch, band);
2291 status->band = band;
2292 }
2293
rtw8851b_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2294 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
2295 struct rtw89_rx_phy_ppdu *phy_ppdu,
2296 struct ieee80211_rx_status *status)
2297 {
2298 u8 path;
2299 u8 *rx_power = phy_ppdu->rssi;
2300
2301 if (!status->signal)
2302 status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]);
2303
2304 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2305 status->chains |= BIT(path);
2306 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2307 }
2308 if (phy_ppdu->valid)
2309 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2310 }
2311
rtw8851b_mac_enable_bb_rf(struct rtw89_dev * rtwdev)2312 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2313 {
2314 int ret;
2315
2316 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2317 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2318 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2319 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2320 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2321
2322 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2323 FULL_BIT_MASK);
2324 if (ret)
2325 return ret;
2326
2327 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2328 FULL_BIT_MASK);
2329 if (ret)
2330 return ret;
2331
2332 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2333
2334 return 0;
2335 }
2336
rtw8851b_mac_disable_bb_rf(struct rtw89_dev * rtwdev)2337 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2338 {
2339 u8 wl_rfc_s0;
2340 u8 wl_rfc_s1;
2341 int ret;
2342
2343 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2344 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2345 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2346
2347 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2348 if (ret)
2349 return ret;
2350 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
2351 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2352 FULL_BIT_MASK);
2353 if (ret)
2354 return ret;
2355
2356 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2357 if (ret)
2358 return ret;
2359 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
2360 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
2361 FULL_BIT_MASK);
2362 return ret;
2363 }
2364
2365 static const struct rtw89_chip_ops rtw8851b_chip_ops = {
2366 .enable_bb_rf = rtw8851b_mac_enable_bb_rf,
2367 .disable_bb_rf = rtw8851b_mac_disable_bb_rf,
2368 .bb_preinit = NULL,
2369 .bb_postinit = NULL,
2370 .bb_reset = rtw8851b_bb_reset,
2371 .bb_sethw = rtw8851b_bb_sethw,
2372 .read_rf = rtw89_phy_read_rf_v1,
2373 .write_rf = rtw89_phy_write_rf_v1,
2374 .set_channel = rtw8851b_set_channel,
2375 .set_channel_help = rtw8851b_set_channel_help,
2376 .read_efuse = rtw8851b_read_efuse,
2377 .read_phycap = rtw8851b_read_phycap,
2378 .fem_setup = NULL,
2379 .rfe_gpio = rtw8851b_rfe_gpio,
2380 .rfk_hw_init = NULL,
2381 .rfk_init = rtw8851b_rfk_init,
2382 .rfk_init_late = NULL,
2383 .rfk_channel = rtw8851b_rfk_channel,
2384 .rfk_band_changed = rtw8851b_rfk_band_changed,
2385 .rfk_scan = rtw8851b_rfk_scan,
2386 .rfk_track = rtw8851b_rfk_track,
2387 .power_trim = rtw8851b_power_trim,
2388 .set_txpwr = rtw8851b_set_txpwr,
2389 .set_txpwr_ctrl = rtw8851b_set_txpwr_ctrl,
2390 .init_txpwr_unit = rtw8851b_init_txpwr_unit,
2391 .get_thermal = rtw8851b_get_thermal,
2392 .ctrl_btg_bt_rx = rtw8851b_ctrl_btg_bt_rx,
2393 .query_ppdu = rtw8851b_query_ppdu,
2394 .convert_rpl_to_rssi = NULL,
2395 .phy_rpt_to_rssi = NULL,
2396 .ctrl_nbtg_bt_tx = rtw8851b_ctrl_nbtg_bt_tx,
2397 .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path,
2398 .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset,
2399 .digital_pwr_comp = NULL,
2400 .pwr_on_func = rtw8851b_pwr_on_func,
2401 .pwr_off_func = rtw8851b_pwr_off_func,
2402 .query_rxdesc = rtw89_core_query_rxdesc,
2403 .fill_txdesc = rtw89_core_fill_txdesc,
2404 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2405 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2406 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2407 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2408 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2409 .h2c_dctl_sec_cam = NULL,
2410 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
2411 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
2412 .h2c_ampdu_cmac_tbl = NULL,
2413 .h2c_default_dmac_tbl = NULL,
2414 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
2415 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
2416
2417 .btc_set_rfe = rtw8851b_btc_set_rfe,
2418 .btc_init_cfg = rtw8851b_btc_init_cfg,
2419 .btc_set_wl_pri = rtw8851b_btc_set_wl_pri,
2420 .btc_set_wl_txpwr_ctrl = rtw8851b_btc_set_wl_txpwr_ctrl,
2421 .btc_get_bt_rssi = rtw8851b_btc_get_bt_rssi,
2422 .btc_update_bt_cnt = rtw8851b_btc_update_bt_cnt,
2423 .btc_wl_s1_standby = rtw8851b_btc_wl_s1_standby,
2424 .btc_set_wl_rx_gain = rtw8851b_btc_set_wl_rx_gain,
2425 .btc_set_policy = rtw89_btc_set_policy_v1,
2426 };
2427
2428 #ifdef CONFIG_PM
2429 static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = {
2430 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2431 .n_patterns = RTW89_MAX_PATTERN_NUM,
2432 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2433 .pattern_min_len = 1,
2434 };
2435 #endif
2436
2437 const struct rtw89_chip_info rtw8851b_chip_info = {
2438 .chip_id = RTL8851B,
2439 .chip_gen = RTW89_CHIP_AX,
2440 .ops = &rtw8851b_chip_ops,
2441 .mac_def = &rtw89_mac_gen_ax,
2442 .phy_def = &rtw89_phy_gen_ax,
2443 .fw_basename = RTW8851B_FW_BASENAME,
2444 .fw_format_max = RTW8851B_FW_FORMAT_MAX,
2445 .try_ce_fw = true,
2446 .bbmcu_nr = 0,
2447 .needed_fw_elms = 0,
2448 .fifo_size = 196608,
2449 .small_fifo_size = true,
2450 .dle_scc_rsvd_size = 98304,
2451 .max_amsdu_limit = 3500,
2452 .dis_2g_40m_ul_ofdma = true,
2453 .rsvd_ple_ofst = 0x2f800,
2454 .hfc_param_ini = rtw8851b_hfc_param_ini_pcie,
2455 .dle_mem = rtw8851b_dle_mem_pcie,
2456 .wde_qempty_acq_grpnum = 4,
2457 .wde_qempty_mgq_grpsel = 4,
2458 .rf_base_addr = {0xe000},
2459 .thermal_th = {0x32, 0x35},
2460 .pwr_on_seq = NULL,
2461 .pwr_off_seq = NULL,
2462 .bb_table = &rtw89_8851b_phy_bb_table,
2463 .bb_gain_table = &rtw89_8851b_phy_bb_gain_table,
2464 .rf_table = {&rtw89_8851b_phy_radioa_table,},
2465 .nctl_table = &rtw89_8851b_phy_nctl_table,
2466 .nctl_post_table = &rtw8851b_nctl_post_defs_tbl,
2467 .dflt_parms = &rtw89_8851b_dflt_parms,
2468 .rfe_parms_conf = rtw89_8851b_rfe_parms_conf,
2469 .txpwr_factor_bb = 3,
2470 .txpwr_factor_rf = 2,
2471 .txpwr_factor_mac = 1,
2472 .dig_table = NULL,
2473 .dig_regs = &rtw8851b_dig_regs,
2474 .tssi_dbw_table = NULL,
2475 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
2476 .support_link_num = 0,
2477 .support_chanctx_num = 0,
2478 .support_rnr = false,
2479 .support_bands = BIT(NL80211_BAND_2GHZ) |
2480 BIT(NL80211_BAND_5GHZ),
2481 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
2482 BIT(NL80211_CHAN_WIDTH_40) |
2483 BIT(NL80211_CHAN_WIDTH_80),
2484 .support_unii4 = true,
2485 .support_ant_gain = false,
2486 .ul_tb_waveform_ctrl = true,
2487 .ul_tb_pwr_diff = false,
2488 .hw_sec_hdr = false,
2489 .hw_mgmt_tx_encrypt = false,
2490 .rf_path_num = 1,
2491 .tx_nss = 1,
2492 .rx_nss = 1,
2493 .acam_num = 32,
2494 .bcam_num = 20,
2495 .scam_num = 128,
2496 .bacam_num = 2,
2497 .bacam_dynamic_num = 4,
2498 .bacam_ver = RTW89_BACAM_V0,
2499 .ppdu_max_usr = 4,
2500 .sec_ctrl_efuse_size = 4,
2501 .physical_efuse_size = 1216,
2502 .logical_efuse_size = 2048,
2503 .limit_efuse_size = 1280,
2504 .dav_phy_efuse_size = 0,
2505 .dav_log_efuse_size = 0,
2506 .efuse_blocks = NULL,
2507 .phycap_addr = 0x580,
2508 .phycap_size = 128,
2509 .para_ver = 0,
2510 .wlcx_desired = 0x06000000,
2511 .btcx_desired = 0x7,
2512 .scbd = 0x1,
2513 .mailbox = 0x1,
2514
2515 .afh_guard_ch = 6,
2516 .wl_rssi_thres = rtw89_btc_8851b_wl_rssi_thres,
2517 .bt_rssi_thres = rtw89_btc_8851b_bt_rssi_thres,
2518 .rssi_tol = 2,
2519 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8851b_mon_reg),
2520 .mon_reg = rtw89_btc_8851b_mon_reg,
2521 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_ul),
2522 .rf_para_ulink = rtw89_btc_8851b_rf_ul,
2523 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
2524 .rf_para_dlink = rtw89_btc_8851b_rf_dl,
2525 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2526 BIT(RTW89_PS_MODE_CLK_GATED),
2527 .low_power_hci_modes = 0,
2528 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2529 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2530 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2531 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2532 .txwd_info_size = sizeof(struct rtw89_txwd_info),
2533 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2534 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2535 .h2c_regs = rtw8851b_h2c_regs,
2536 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2537 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2538 .c2h_regs = rtw8851b_c2h_regs,
2539 .page_regs = &rtw8851b_page_regs,
2540 .wow_reason_reg = rtw8851b_wow_wakeup_regs,
2541 .cfo_src_fd = true,
2542 .cfo_hw_comp = true,
2543 .dcfo_comp = &rtw8851b_dcfo_comp,
2544 .dcfo_comp_sft = 12,
2545 .imr_info = &rtw8851b_imr_info,
2546 .imr_dmac_table = NULL,
2547 .imr_cmac_table = NULL,
2548 .rrsr_cfgs = &rtw8851b_rrsr_cfgs,
2549 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},
2550 .bss_clr_map_reg = R_BSS_CLR_MAP_V1,
2551 .rfkill_init = &rtw8851b_rfkill_regs,
2552 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
2553 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
2554 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
2555 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
2556 .edcca_regs = &rtw8851b_edcca_regs,
2557 #ifdef CONFIG_PM
2558 .wowlan_stub = &rtw_wowlan_stub_8851b,
2559 #endif
2560 .xtal_info = &rtw8851b_xtal_info,
2561 };
2562 EXPORT_SYMBOL(rtw8851b_chip_info);
2563
2564 MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE);
2565 MODULE_AUTHOR("Realtek Corporation");
2566 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver");
2567 MODULE_LICENSE("Dual BSD/GPL");
2568