1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <console/console.h> 4 #include <soc/qclib_common.h> 5 #include <device/mmio.h> 6 7 #define LONG_SYS_DCB_REG 0x7801C0 8 #define FUSE_BIT 15 9 dcb_fuse_longsys1p8(void)10static int dcb_fuse_longsys1p8(void) 11 { 12 unsigned int fuse_value, bit_value; 13 fuse_value = read32((unsigned int *)LONG_SYS_DCB_REG); 14 bit_value = (fuse_value >> FUSE_BIT) & 0x1; 15 return bit_value; 16 } 17 qclib_file(enum qclib_cbfs_file file)18const char *qclib_file(enum qclib_cbfs_file file) 19 { 20 if ((file == QCLIB_CBFS_DCB) && dcb_fuse_longsys1p8()) { 21 printk(BIOS_INFO, "Using DCB for Longsys 1.8V memory based on fuse setting\n"); 22 return CONFIG_CBFS_PREFIX "/dcb_longsys1p8"; 23 } else { 24 return qclib_file_default(file); 25 } 26 } 27 qclib_soc_override(struct qclib_cb_if_table * table)28int qclib_soc_override(struct qclib_cb_if_table *table) 29 { 30 /* Lazor boards need a hack to limit DDR frequency on certain memory parts to work 31 around a stability issue. */ 32 if (CONFIG(BOARD_GOOGLE_LAZOR)) 33 table->global_attributes |= QCLIB_GA_DDR_FMAX_LIMIT_HYNIX8GB; 34 35 return 0; 36 } 37