1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ 4 #define __SOC_ROCKCHIP_RK3399_GRF_H__ 5 6 #include <soc/addressmap.h> 7 #include <soc/soc.h> 8 #include <types.h> 9 10 struct rk3399_grf_regs { 11 u32 reserved[0x800]; 12 u32 usb3_perf_con0; 13 u32 usb3_perf_con1; 14 u32 usb3_perf_con2; 15 u32 usb3_perf_rd_max_latency_num; 16 u32 usb3_perf_rd_latency_samp_num; 17 u32 usb3_perf_rd_latency_acc_num; 18 u32 usb3_perf_rd_axi_total_byte; 19 u32 usb3_perf_wr_axi_total_byte; 20 u32 usb3_perf_working_cnt; 21 u32 reserved1[0x103]; 22 u32 usb3otg0_con0; 23 u32 usb3otg0_con1; 24 u32 reserved2[2]; 25 u32 usb3otg1_con0; 26 u32 usb3otg1_con1; 27 u32 reserved3[2]; 28 u32 usb3otg0_status_lat0; 29 u32 usb3otg0_status_lat1; 30 u32 usb3otg0_status_cb; 31 u32 reserved4; 32 u32 usb3otg1_status_lat0; 33 u32 usb3otg1_status_lat1; 34 u32 usb3ogt1_status_cb; 35 u32 reserved5[0x6e5]; 36 u32 pcie_perf_con0; 37 u32 pcie_perf_con1; 38 u32 pcie_perf_con2; 39 u32 pcie_perf_rd_max_latency_num; 40 u32 pcie_perf_rd_latency_samp_num; 41 u32 pcie_perf_rd_laterncy_acc_num; 42 u32 pcie_perf_rd_axi_total_byte; 43 u32 pcie_perf_wr_axi_total_byte; 44 u32 pcie_perf_working_cnt; 45 u32 reserved6[0x37]; 46 u32 usb20_host0_con0; 47 u32 usb20_host0_con1; 48 u32 reserved7[2]; 49 u32 usb20_host1_con0; 50 u32 usb20_host1_con1; 51 u32 reserved8[2]; 52 u32 hsic_con0; 53 u32 hsic_con1; 54 u32 reserved9[6]; 55 u32 grf_usbhost0_status; 56 u32 grf_usbhost1_Status; 57 u32 grf_hsic_status; 58 u32 reserved10[0xc9]; 59 u32 hsicphy_con0; 60 u32 reserved11[3]; 61 u32 usbphy_ctrl[2][26 + 6]; /* 26 PHY regs, 6 reserved padding regs */ 62 u32 reserved13[0x729]; 63 u32 soc_con9; 64 u32 reserved14[0x0a]; 65 u32 soc_con20; 66 u32 soc_con21; 67 u32 soc_con22; 68 u32 soc_con23; 69 u32 soc_con24; 70 u32 soc_con25; 71 u32 soc_con26; 72 u32 reserved15[0xf65]; 73 u32 cpu_con[4]; 74 u32 reserved16[0x1c]; 75 u32 cpu_status[6]; 76 u32 reserved17[0x1a]; 77 u32 a53_perf_con[4]; 78 u32 a53_perf_rd_mon_st; 79 u32 a53_perf_rd_mon_end; 80 u32 a53_perf_wr_mon_st; 81 u32 a53_perf_wr_mon_end; 82 u32 a53_perf_rd_max_latency_num; 83 u32 a53_perf_rd_latency_samp_num; 84 u32 a53_perf_rd_laterncy_acc_num; 85 u32 a53_perf_rd_axi_total_byte; 86 u32 a53_perf_wr_axi_total_byte; 87 u32 a53_perf_working_cnt; 88 u32 a53_perf_int_status; 89 u32 reserved18[0x31]; 90 u32 a72_perf_con[4]; 91 u32 a72_perf_rd_mon_st; 92 u32 a72_perf_rd_mon_end; 93 u32 a72_perf_wr_mon_st; 94 u32 a72_perf_wr_mon_end; 95 u32 a72_perf_rd_max_latency_num; 96 u32 a72_perf_rd_latency_samp_num; 97 u32 a72_perf_rd_laterncy_acc_num; 98 u32 a72_perf_rd_axi_total_byte; 99 u32 a72_perf_wr_axi_total_byte; 100 u32 a72_perf_working_cnt; 101 u32 a72_perf_int_status; 102 u32 reserved19[0x7f6]; 103 u32 soc_con5; 104 u32 soc_con6; 105 u32 reserved20[0x779]; 106 u32 gpio2a_iomux; 107 union { 108 u32 iomux_spi2; 109 u32 gpio2b_iomux; 110 }; 111 union { 112 u32 gpio2c_iomux; 113 u32 iomux_spi5; 114 }; 115 u32 gpio2d_iomux; 116 union { 117 u32 gpio3a_iomux; 118 u32 iomux_spi0; 119 }; 120 u32 gpio3b_iomux; 121 u32 gpio3c_iomux; 122 union { 123 u32 iomux_i2s0; 124 u32 gpio3d_iomux; 125 }; 126 union { 127 u32 iomux_i2sclk; 128 u32 gpio4a_iomux; 129 }; 130 union { 131 u32 iomux_sdmmc; 132 u32 iomux_uart2a; 133 u32 gpio4b_iomux; 134 }; 135 union { 136 u32 iomux_pwm_0; 137 u32 iomux_pwm_1; 138 u32 iomux_uart2b; 139 u32 iomux_uart2c; 140 u32 iomux_edp_hotplug; 141 u32 gpio4c_iomux; 142 }; 143 u32 gpio4d_iomux; 144 u32 reserved21[4]; 145 u32 gpio2_p[3][4]; 146 u32 reserved22[4]; 147 u32 gpio2_sr[3][4]; 148 u32 reserved23[4]; 149 u32 gpio2_smt[3][4]; 150 u32 reserved24[(0xe130 - 0xe0ec)/4 - 1]; 151 u32 gpio4b_e01; 152 u32 gpio4b_e2; 153 u32 reserved24a[(0xe200 - 0xe134)/4 - 1]; 154 u32 soc_con0; 155 u32 soc_con1; 156 u32 soc_con2; 157 u32 soc_con3; 158 u32 soc_con4; 159 u32 soc_con5_pcie; 160 u32 reserved25; 161 u32 soc_con7; 162 u32 soc_con8; 163 u32 soc_con9_pcie; 164 u32 reserved26[0x1e]; 165 u32 soc_status[6]; 166 u32 reserved27[0x32]; 167 u32 ddrc0_con0; 168 u32 ddrc0_con1; 169 u32 ddrc1_con0; 170 u32 ddrc1_con1; 171 u32 reserved28[0xac]; 172 u32 io_vsel; 173 u32 saradc_testbit; 174 u32 tsadc_testbit_l; 175 u32 tsadc_testbit_h; 176 u32 reserved29[0x6c]; 177 u32 chip_id_addr; 178 u32 reserved30[0x1f]; 179 u32 fast_boot_addr; 180 u32 reserved31[0x1df]; 181 u32 emmccore_con[12]; 182 u32 reserved32[4]; 183 u32 emmccore_status[4]; 184 u32 reserved33[0x1cc]; 185 u32 emmcphy_con[7]; 186 u32 reserved34; 187 u32 emmcphy_status; 188 }; 189 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0); 190 191 struct rk3399_pmugrf_regs { 192 union { 193 u32 iomux_pwm_3a; 194 u32 gpio0a_iomux; 195 }; 196 u32 gpio0b_iomux; 197 u32 reserved0[2]; 198 union { 199 u32 spi1_rxd; 200 u32 tsadc_int; 201 u32 gpio1a_iomux; 202 }; 203 union { 204 u32 spi1_csclktx; 205 u32 iomux_pwm_3b; 206 u32 iomux_i2c0_sda; 207 u32 gpio1b_iomux; 208 }; 209 union { 210 u32 iomux_pwm_2; 211 u32 iomux_i2c0_scl; 212 u32 gpio1c_iomux; 213 }; 214 u32 gpio1d_iomux; 215 u32 reserved1[8]; 216 u32 gpio0_p[2][4]; 217 u32 reserved3[8]; 218 u32 gpio0a_e; 219 u32 reserved4; 220 u32 gpio0b_e; 221 u32 reserved5[5]; 222 u32 gpio1a_e; 223 u32 reserved6; 224 u32 gpio1b_e; 225 u32 reserved7; 226 u32 gpio1c_e; 227 u32 reserved8; 228 u32 gpio1d_e; 229 u32 reserved9[0x11]; 230 u32 gpio0l_sr; 231 u32 reserved10; 232 u32 gpio1l_sr; 233 u32 gpio1h_sr; 234 u32 reserved11[4]; 235 u32 gpio0a_smt; 236 u32 gpio0b_smt; 237 u32 reserved12[2]; 238 u32 gpio1a_smt; 239 u32 gpio1b_smt; 240 u32 gpio1c_smt; 241 u32 gpio1d_smt; 242 u32 reserved13[8]; 243 u32 gpio0l_he; 244 u32 reserved14; 245 u32 gpio1l_he; 246 u32 gpio1h_he; 247 u32 reserved15[4]; 248 u32 soc_con0; 249 u32 reserved16[9]; 250 u32 soc_con10; 251 u32 soc_con11; 252 u32 reserved17[0x24]; 253 u32 pmupvtm_con0; 254 u32 pmupvtm_con1; 255 u32 pmupvtm_status0; 256 u32 pmupvtm_status1; 257 u32 grf_osc_e; 258 u32 reserved18[0x2b]; 259 u32 os_reg0; 260 u32 os_reg1; 261 u32 os_reg2; 262 u32 os_reg3; 263 }; 264 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c); 265 266 struct rk3399_pmusgrf_regs { 267 u32 ddr_rgn_con[35]; 268 u32 reserved[0x1fe5]; 269 u32 soc_con8; 270 u32 soc_con9; 271 u32 soc_con10; 272 u32 soc_con11; 273 u32 soc_con12; 274 u32 soc_con13; 275 u32 soc_con14; 276 u32 soc_con15; 277 u32 reserved1[3]; 278 u32 soc_con19; 279 u32 soc_con20; 280 u32 soc_con21; 281 u32 soc_con22; 282 u32 reserved2[0x29]; 283 u32 perilp_con[9]; 284 u32 reserved4[7]; 285 u32 perilp_status; 286 u32 reserved5[0xfaf]; 287 u32 soc_con0; 288 u32 soc_con1; 289 u32 reserved6[0x3e]; 290 u32 pmu_con[9]; 291 u32 reserved7[0x17]; 292 u32 fast_boot_addr; 293 u32 reserved8[0x1f]; 294 u32 efuse_prg_mask; 295 u32 efuse_read_mask; 296 u32 reserved9[0x0e]; 297 u32 pmu_slv_con0; 298 u32 pmu_slv_con1; 299 u32 reserved10[0x771]; 300 u32 soc_con3; 301 u32 soc_con4; 302 u32 soc_con5; 303 u32 soc_con6; 304 u32 soc_con7; 305 u32 reserved11[8]; 306 u32 soc_con16; 307 u32 soc_con17; 308 u32 soc_con18; 309 u32 reserved12[0xdd]; 310 u32 slv_secure_con0; 311 u32 slv_secure_con1; 312 u32 reserved13; 313 u32 slv_secure_con2; 314 u32 slv_secure_con3; 315 u32 slv_secure_con4; 316 }; 317 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); 318 319 static struct rk3399_grf_regs * const rk3399_grf = (void *)GRF_BASE; 320 static struct rk3399_pmugrf_regs * const rk3399_pmugrf = (void *)PMUGRF_BASE; 321 static struct rk3399_pmusgrf_regs * const rk3399_pmusgrf = (void *)PMUSGRF_BASE; 322 323 #define UART2A_SEL RK_CLRSETBITS(3 << 10, 0 << 10) 324 #define UART2B_SEL RK_CLRSETBITS(3 << 10, 1 << 10) 325 #define UART2C_SEL RK_CLRSETBITS(3 << 10, 2 << 10) 326 #define PWM3_SEL_A RK_CLRBITS(1 << 5) 327 #define PWM3_SEL_B RK_SETBITS(1 << 5) 328 329 #define IOMUX_UART2A RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0) 330 #define IOMUX_UART2B RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0) 331 #define IOMUX_UART2C RK_CLRSETBITS(3 << 8 | 3 << 6, 1 << 8 | 1 << 6) 332 #define IOMUX_SPI0 RK_CLRSETBITS(0xff << 8, \ 333 2 << 14 | 2 << 12 | 2 << 10 | 2 << 8) 334 #define IOMUX_SPI1_RX RK_CLRSETBITS(3 << 14, 2 << 14) 335 #define IOMUX_SPI1_CSCLKTX RK_CLRSETBITS(0x3f << 0, 2 << 4 |\ 336 2 << 2 | 2 << 0) 337 #define IOMUX_SPI2 RK_CLRSETBITS(0xff << 2, 1 << 8 | 1 << 6 |\ 338 1 << 4 | 1 << 2) 339 #define IOMUX_SPI5 RK_CLRSETBITS(0xff << 8, \ 340 2 << 14 | 2 << 12 | 2 << 10 | 2 << 8) 341 #define IOMUX_SDMMC RK_CLRSETBITS(0xfff, 1 << 10 | 1 << 8 | 1 << 6 |\ 342 1 << 4 | 1 << 2 | 1 << 0) 343 #define IOMUX_I2C0_SCL RK_CLRSETBITS(3 << 0, 2 << 0) 344 #define IOMUX_I2C0_SDA RK_CLRSETBITS(3 << 14, 2 << 14) 345 346 #define IOMUX_I2S0_SD0 RK_SETBITS(1 << 14 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) 347 #define IOMUX_I2SCLK RK_SETBITS(1 << 0) 348 349 #define IOMUX_PWM_0 RK_SETBITS(1 << 4) 350 #define IOMUX_PWM_1 RK_SETBITS(1 << 12) 351 #define IOMUX_PWM_2 RK_SETBITS(1 << 6) 352 #define IOMUX_PWM_3_A RK_SETBITS(1 << 12) 353 #define IOMUX_PWM_3_B RK_SETBITS(1 << 12) 354 #define IOMUX_TSADC_INT RK_CLRSETBITS(3 << 12, 1 << 12) 355 #define IOMUX_EDP_HOTPLUG RK_CLRSETBITS(3 << 14, 2 << 14) 356 #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ 357