1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <stdint.h>
4 #include <amdblocks/acpimmio.h>
5 #include <amdblocks/gpio.h>
6 #include <amdblocks/gpio_defs.h>
7 #include <device/pci_def.h>
8 #include <device/pci_ops.h>
9 #include <gpio.h>
10 #include <northbridge/amd/agesa/state_machine.h>
11
12 #include "gpio_ftns.h"
13
14 static void early_lpc_init(void);
15
board_BeforeAgesa(struct sysinfo * cb)16 void board_BeforeAgesa(struct sysinfo *cb)
17 {
18 u32 val;
19
20 early_lpc_init();
21
22 /* Disable SVI2 controller to wait for command completion */
23 val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C);
24 if (!(val & (1 << 30))) {
25 val |= (1 << 30);
26 pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val);
27 }
28
29 /* Release GPIO32/33 for other uses. */
30 pm_write8(0xea, 1);
31 }
32
33 const struct soc_amd_gpio gpio_common[] = {
34 PAD_GPI(GPIO_49, PULL_NONE),
35 PAD_GPI(GPIO_50, PULL_NONE),
36 PAD_GPI(GPIO_71, PULL_NONE),
37 PAD_GPO(GPIO_57, LOW),
38 PAD_GPO(GPIO_58, LOW),
39 PAD_GPO(GPIO_59, LOW),
40 PAD_GPO(GPIO_51, HIGH),
41 PAD_GPO(GPIO_55, HIGH),
42 PAD_GPO(GPIO_64, HIGH),
43 PAD_GPO(GPIO_68, HIGH),
44 };
45
46 const struct soc_amd_gpio gpio_apu2[] = {
47 PAD_GPI(GPIO_32, PULL_NONE),
48 };
49
50 const struct soc_amd_gpio gpio_apu34[] = {
51 PAD_GPI(GPIO_32, PULL_NONE),
52 PAD_GPO(GPIO_33, LOW),
53 };
54
55 const struct soc_amd_gpio gpio_apu5[] = {
56 PAD_GPI(GPIO_22, PULL_NONE),
57 PAD_GPO(GPIO_32, HIGH),
58 PAD_GPO(GPIO_33, HIGH),
59 };
60
early_lpc_init(void)61 static void early_lpc_init(void)
62 {
63 gpio_configure_pads(gpio_common, ARRAY_SIZE(gpio_common));
64
65 if (CONFIG(BOARD_PCENGINES_APU2))
66 gpio_configure_pads(gpio_apu2, ARRAY_SIZE(gpio_apu2));
67
68 if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4))
69 gpio_configure_pads(gpio_apu34, ARRAY_SIZE(gpio_apu34));
70
71 if (CONFIG(BOARD_PCENGINES_APU5))
72 gpio_configure_pads(gpio_apu5, ARRAY_SIZE(gpio_apu5));
73 }
74