1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef __SOC_TI_AM335X_CLOCK_H__ 4 #define __SOC_TI_AM335X_CLOCK_H__ 5 6 #include <stdint.h> 7 8 enum { 9 CM_ST_NO_SLEEP = 0x0, 10 CM_ST_SW_SLEEP = 0x1, 11 CM_ST_SW_WKUP = 0x2 12 }; 13 14 enum { 15 CM_MODULEMODE_DISABLED = 0x0, 16 CM_MODULEMODE_ENABLED = 0x2 17 }; 18 19 enum { 20 CM_FCLK_DIS = 0x0 << 18, 21 CM_FCLK_EN = 0x1 << 18 22 }; 23 24 /* Clock module peripheral registers */ 25 struct am335x_cm_per_regs { 26 uint32_t l4ls_st; // 0x0 27 uint32_t l3s_st; // 0x4 28 uint8_t _rsv0[4]; // 0x8-0xb 29 uint32_t l3_st; // 0xc 30 uint8_t _rsv1[4]; // 0x10-0x13 31 uint32_t cpgmac0; // 0x14 32 uint32_t lcdc; // 0x18 33 uint32_t usb0; // 0x1c 34 uint8_t _rsv2[4]; // 0x20-0x23 35 uint32_t tptc0; // 0x24 36 uint32_t emif; // 0x28 37 uint32_t ocmcram; // 0x2c 38 uint32_t gpmc; // 0x30 39 uint32_t mcasp0; // 0x34 40 uint32_t uart5; // 0x38 41 uint32_t mmc0; // 0x3c 42 uint32_t elm; // 0x40 43 uint32_t i2c2; // 0x44 44 uint32_t i2c1; // 0x48 45 uint32_t spi0; // 0x4c 46 uint32_t spi1; // 0x50 47 uint8_t _rsv3[0xc]; // 0x54-0x5f 48 uint32_t l4ls; // 0x60 49 uint8_t _rsv4[4]; // 0x64-0x67 50 uint32_t mcasp1; // 0x68 51 uint32_t uart1; // 0x6c 52 uint32_t uart2; // 0x70 53 uint32_t uart3; // 0x74 54 uint32_t uart4; // 0x78 55 uint32_t timer7; // 0x7c 56 uint32_t timer2; // 0x80 57 uint32_t timer3; // 0x84 58 uint32_t timer4; // 0x88 59 uint8_t _rsv5[0x20]; // 0x90-0xab 60 uint32_t gpio1; // 0xac 61 uint32_t gpio2; // 0xb0 62 uint32_t gpio3; // 0xb4 63 uint8_t _rsv6[4]; // 0xb8-0xbb 64 uint32_t tpcc; // 0xbc 65 uint32_t dcan0; // 0xc0 66 uint32_t dcan1; // 0xc4 67 uint8_t _rsv7[4]; // 0xc8-0xcb 68 uint32_t epwmss1; // 0xcc 69 uint8_t _rsv8[4]; // 0xd0-0xd3 70 uint32_t epwmss0; // 0xd4 71 uint32_t epwmss2; // 0xd8 72 uint32_t l3_instr; // 0xdc 73 uint32_t l3; // 0xe0 74 uint32_t ieee5000; // 0xe4 75 uint32_t pru_icss; // 0xe8 76 uint32_t timer5; // 0xec 77 uint32_t timer6; // 0xf0 78 uint32_t mmc1; // 0xf4 79 uint32_t mmc2; // 0xf8 80 uint32_t tptc1; // 0xfc 81 uint32_t tptc2; // 0x100 82 uint8_t _rsv9[8]; // 0x104-0x10b 83 uint32_t spinlock; // 0x10c 84 uint32_t mailbox0; // 0x110 85 uint8_t _rsv10[8]; // 0x114-0x11b 86 uint32_t l4hs_st; // 0x11c 87 uint32_t l4hs; // 0x120 88 uint8_t _rsv11[8]; // 0x124-0x12b 89 uint32_t ocpwp_l3_st; // 0x12c 90 uint32_t ocpwp; // 0x130 91 uint8_t _rsv12[0xb]; // 0x134-0x13f 92 uint32_t pru_icss_st; // 0x140 93 uint32_t cpsw_st; // 0x144 94 uint32_t lcdc_st; // 0x148 95 uint32_t clkdiv32k; // 0x14c 96 uint32_t clk_24mhz_st; // 0x150 97 } __packed; 98 static struct am335x_cm_per_regs * const am335x_cm_per = (void *)0x44e00000; 99 100 /* Clock module wakeup registers */ 101 struct am335x_cm_wkup_regs { 102 uint32_t wkup_st; // 0x0 103 uint32_t wkup_control; // 0x4 104 uint32_t wkup_gpio0; // 0x8 105 uint32_t wkup_l4wkup; // 0xc 106 uint32_t wkup_timer0; // 0x10 107 uint32_t wkup_debugss; // 0x14 108 uint32_t l3_aon_st; // 0x18 109 uint32_t autoidle_dpll_mpu; // 0x1c 110 uint32_t idlest_dpll_mpu; // 0x20 111 uint32_t ssc_deltamstep_dpll_mpu; // 0x24 112 uint32_t ssc_modfreqdiv_dpll_mpu; // 0x28 113 uint32_t clksel_dpll_mpu; // 0x2c 114 uint32_t autoidle_dpll_ddr; // 0x30 115 uint32_t idlest_dpll_ddr; // 0x34 116 uint32_t ssc_deltamstep_dpll_ddr; // 0x38 117 uint32_t ssc_modfreqdiv_dpll_ddr; // 0x3c 118 uint32_t clksel_dpll_ddr; // 0x40 119 uint32_t autoidle_dpll_disp; // 0x44 120 uint32_t idlest_dpll_disp; // 0x48 121 uint32_t ssc_deltamstep_dpll_disp; // 0x4c 122 uint32_t ssc_modfreqdiv_dpll_disp; // 0x50 123 uint32_t clksel_dpll_disp; // 0x54 124 uint32_t autoidle_dpll_core; // 0x58 125 uint32_t idlest_dpll_core; // 0x5c 126 uint32_t ssc_deltamstep_dpll_core; // 0x60 127 uint32_t ssc_modfreqdiv_dpll_core; // 0x64 128 uint32_t clksel_dpll_core; // 0x68 129 uint32_t autoidle_dpll_per; // 0x6c 130 uint32_t idlest_dpll_per; // 0x70 131 uint32_t ssc_deltamstep_dpll_per; // 0x74 132 uint32_t ssc_modfreqdiv_dpll_per; // 0x78 133 uint32_t clkdcoldo_dpll_per; // 0x7c 134 uint32_t div_m4_dpll_core; // 0x80 135 uint32_t div_m5_dpll_core; // 0x84 136 uint32_t clkmode_dpll_mpu; // 0x88 137 uint32_t clkmode_dpll_per; // 0x8c 138 uint32_t clkmode_dpll_core; // 0x90 139 uint32_t clkmode_dpll_ddr; // 0x94 140 uint32_t clkmode_dpll_disp; // 0x98 141 uint32_t clksel_dpll_periph; // 0x9c 142 uint32_t div_m2_dpll_ddr; // 0xa0 143 uint32_t div_m2_dpll_disp; // 0xa4 144 uint32_t div_m2_dpll_mpu; // 0xa8 145 uint32_t div_m2_dpll_per; // 0xac 146 uint32_t wkup_wkup_m3; // 0xb0 147 uint32_t wkup_uart0; // 0xb4 148 uint32_t wkup_i2c0; // 0xb8 149 uint32_t wkup_adc_tsc; // 0xbc 150 uint32_t wkup_smartreflex0; // 0xc0 151 uint32_t wkup_timer1; // 0xc4 152 uint32_t wkup_smartreflex1; // 0xc8 153 uint32_t l4_wkup_aon_st; // 0xcc 154 uint8_t _rsv0[4]; // 0xd0-0xd3 155 uint32_t wkup_wdt1; // 0xd4 156 uint32_t div_m6_dpll_core; // 0xd8 157 } __packed; 158 static struct am335x_cm_wkup_regs * const am335x_cm_wkup = (void *)0x44e00400; 159 160 /* Clock module pll registers */ 161 struct am335x_cm_dpll_regs { 162 uint8_t _rsv0[4]; // 0x0-0x3 163 uint32_t clksel_timer7_clk; // 0x4 164 uint32_t clksel_timer2_clk; // 0x8 165 uint32_t clksel_timer3_clk; // 0xc 166 uint32_t clksel_timer4_clk; // 0x10 167 uint32_t cm_mac_clksel; // 0x14 168 uint32_t clksel_timer5_clk; // 0x18 169 uint32_t clksel_timer6_clk; // 0x1c 170 uint32_t cm_cpts_rft_clksel; // 0x20 171 uint8_t _rsv1[4]; // 0x24-0x27 172 uint32_t clksel_timer1ms_clk; // 0x28 173 uint32_t clksel_gfx_fclk; // 0x2c 174 uint32_t clksel_pru_icss_ocp_clk; // 0x30 175 uint32_t clksel_lcdc_pixel_clk; // 0x34 176 uint32_t clksel_wdt1_clk; // 0x38 177 uint32_t clksel_gpio0_dbclk; // 0x3c 178 } __packed; 179 static struct am335x_cm_dpll_regs * const am335x_cm_dpll = (void *)0x44e00500; 180 181 /* Clock module mpu registers */ 182 struct am335x_cm_mpu_regs { 183 uint32_t st; // 0x0 184 uint32_t mpu; // 0x4 185 } __packed; 186 static struct am335x_cm_mpu_regs * const am335x_cm_mpu = (void *)0x44e00600; 187 188 /* Clock module device registers */ 189 struct am335x_cm_device_regs { 190 uint32_t cm_clkout_ctrl; // 0x0 191 } __packed; 192 static struct am335x_cm_device_regs * const am335x_cm_device = 193 (void *)0x44e00700; 194 195 /* Clock module RTC registers */ 196 struct am335x_cm_rtc_regs { 197 uint32_t rtc; // 0x0 198 uint32_t st; // 0x4 199 } __packed; 200 static struct am335x_cm_rtc_regs * const am335x_cm_rtc = (void *)0x44e00800; 201 202 /* Clock module graphics controller registers */ 203 struct am335x_cm_gfx_regs { 204 uint32_t l3_st; // 0x0 205 uint32_t gfx; // 0x4 206 uint8_t _rsv0[4]; // 0x8-0xb 207 uint32_t l4ls_gfx_st; // 0xc 208 uint32_t mmucfg; // 0x10 209 uint32_t mmudata; // 0x14 210 } __packed; 211 static struct am335x_cm_gfx_regs * const am335x_cm_gfx = (void *)0x44e00900; 212 213 /* Clock module efuse registers */ 214 struct am335x_cm_cefuse_regs { 215 uint32_t st; // 0x0 216 uint8_t _rsv0[0x1c]; // 0x4-0x1f 217 uint32_t cefuse; // 0x20 218 } __packed; 219 static struct am335x_cm_cefuse_regs * const am335x_cm_cefuse = 220 (void *)0x44e00a00; 221 222 #endif /* __SOC_TI_AM335X_CLOCK_H__ */ 223