1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __RK_MIPI_H 4 #define __RK_MIPI_H 5 6 #include <mipi/dsi.h> 7 #include <types.h> 8 9 struct rk_mipi_regs { 10 u32 dsi_version; 11 u32 dsi_pwr_up; 12 u32 dsi_clk_cfg; 13 u32 dsi_dpi_vcid; 14 u32 dsi_dpi_color_coding; 15 u32 dsi_dpi_cfg_pol; 16 u32 dsi_dpi_lp_cmd_tim; 17 u8 reserved0[0x28 - 0x18]; 18 u32 dsi_pckhdl_cfg; 19 u8 reserved1[0x30 - 0x2c]; 20 u32 dsi_mode_cfg; 21 u32 dsi_vid_mode_cfg; 22 u32 dsi_vid_pkt_size; 23 u32 dsi_vid_num_chumks; 24 u32 dsi_vid_null_pkt_size; 25 u32 dsi_vid_hsa_time; 26 u32 dsi_vid_hbp_time; 27 u32 dsi_vid_hline_time; 28 u32 dsi_vid_vsa_lines; 29 u32 dsi_vid_vbp_lines; 30 u32 dsi_vid_vfp_lines; 31 u32 dsi_vid_vactive_lines; 32 u32 dsi_edpi_cmd_size; 33 u32 dsi_cmd_mode_cfg; 34 u32 dsi_gen_hdr; 35 u32 dsi_gen_pld_data; 36 u32 dsi_cmd_pkt_status; 37 u32 dsi_to_cnt_cfg; 38 u8 reserved2[0x88 - 0x78]; 39 u32 dsi_bta_to_cnt; 40 u32 reserved3; 41 u32 dsi_lpclk_ctrl; 42 u32 dsi_phy_tmr_lpclk_cfg; 43 u32 dsi_phy_tmr_cfg; 44 u32 dsi_phy_rstz; 45 u32 dsi_phy_if_cfg; 46 u8 reserved4[0xac - 0xa4]; 47 u32 dsi_phy_status; 48 u32 dsi_phy_tst_ctrl0; 49 u32 dsi_phy_tst_ctrl1; 50 u32 dsi_int_st0; 51 u32 dsi_int_st1; 52 u32 dsi_int_msk0; 53 u32 dsi_int_msk1; 54 }; 55 check_member(rk_mipi_regs, dsi_int_msk1, 0xc8); 56 57 #define RESET 0 58 #define POWERUP BIT(0) 59 60 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 61 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 62 63 #define EN18_LOOSELY BIT(8) 64 #define DPI_COLOR_CODING_16BIT_1 0x0 65 #define DPI_COLOR_CODING_16BIT_2 0x1 66 #define DPI_COLOR_CODING_16BIT_3 0x2 67 #define DPI_COLOR_CODING_18BIT_1 0x3 68 #define DPI_COLOR_CODING_18BIT_2 0x4 69 #define DPI_COLOR_CODING_24BIT 0x5 70 71 #define COLORM_ACTIVE_LOW BIT(4) 72 #define SHUTD_ACTIVE_LOW BIT(3) 73 #define HSYNC_ACTIVE_LOW BIT(2) 74 #define VSYNC_ACTIVE_LOW BIT(1) 75 #define DATAEN_ACTIVE_LOW BIT(0) 76 77 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 78 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 79 80 #define EN_CRC_RX BIT(4) 81 #define EN_ECC_RX BIT(3) 82 #define EN_BTA BIT(2) 83 #define EN_EOTP_RX BIT(1) 84 #define EN_EOTP_TX BIT(0) 85 86 #define ENABLE_VIDEO_MODE 0 87 #define ENABLE_CMD_MODE BIT(0) 88 89 #define FRAME_BTA_ACK BIT(14) 90 #define ENABLE_LOW_POWER (0x3f << 8) 91 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 92 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 93 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 94 #define VID_MODE_TYPE_BURST 0x2 95 96 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 97 #define VID_PKT_MAX_SIZE 0x3fff 98 99 #define MAX_RD_PKT_SIZE_LP BIT(24) 100 #define DCS_LW_TX_LP BIT(19) 101 #define DCS_SR_0P_TX_LP BIT(18) 102 #define DCS_SW_1P_TX_LP BIT(17) 103 #define DCS_SW_0P_TX_LP BIT(16) 104 #define GEN_LW_TX_LP BIT(14) 105 #define GEN_SR_2P_TX_LP BIT(13) 106 #define GEN_SR_1P_TX_LP BIT(12) 107 #define GEN_SR_0P_TX_LP BIT(11) 108 #define GEN_SW_2P_TX_LP BIT(10) 109 #define GEN_SW_1P_TX_LP BIT(9) 110 #define GEN_SW_0P_TX_LP BIT(8) 111 #define EN_ACK_RQST BIT(1) 112 #define EN_TEAR_FX BIT(0) 113 114 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 115 DCS_LW_TX_LP | \ 116 DCS_SR_0P_TX_LP | \ 117 DCS_SW_1P_TX_LP | \ 118 DCS_SW_0P_TX_LP | \ 119 GEN_LW_TX_LP | \ 120 GEN_SR_2P_TX_LP | \ 121 GEN_SR_1P_TX_LP | \ 122 GEN_SR_0P_TX_LP | \ 123 GEN_SW_2P_TX_LP | \ 124 GEN_SW_1P_TX_LP | \ 125 GEN_SW_0P_TX_LP) 126 127 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 128 #define GEN_HDATA_MASK (0xffff << 8) 129 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 130 #define GEN_HTYPE_MASK 0xff 131 132 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 133 #define LPRX_TO_CNT(p) ((p) & 0xffff) 134 135 #define AUTO_CLKLANE_CTRL BIT(1) 136 #define PHY_TXREQUESTCLKHS BIT(0) 137 138 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 139 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 140 141 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 142 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 143 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 144 145 #define PHY_DISFORCEPLL 0 146 #define PHY_ENFORCEPLL BIT(3) 147 #define PHY_DISABLECLK 0 148 #define PHY_ENABLECLK BIT(2) 149 #define PHY_RSTZ 0 150 #define PHY_UNRSTZ BIT(1) 151 #define PHY_SHUTDOWNZ 0 152 #define PHY_UNSHUTDOWNZ BIT(0) 153 154 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 155 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 156 157 #define LOCK BIT(0) 158 #define STOP_STATE_CLK_LANE BIT(2) 159 160 #define PHY_TESTCLK BIT(1) 161 #define PHY_UNTESTCLK 0 162 #define PHY_TESTCLR BIT(0) 163 #define PHY_UNTESTCLR 0 164 165 #define PHY_TESTEN BIT(16) 166 #define PHY_UNTESTEN 0 167 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 168 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 169 170 #define BYPASS_VCO_RANGE BIT(7) 171 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 172 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 173 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 174 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 175 #define REF_BIAS_CUR_SEL BIT(0) 176 177 #define CP_CURRENT_1_5UA 0x0 178 #define CP_CURRENT_3UA 0x1 179 #define CP_CURRENT_4_5UA 0x2 180 #define CP_CURRENT_7_5UA 0x6 181 #define CP_CURRENT_6UA 0x9 182 #define CP_CURRENT_12UA 0xb 183 #define CP_CURRENT_SEL(val) ((val) & 0xf) 184 185 #define CP_PROGRAM_EN BIT(7) 186 187 #define LPF_PROGRAM_EN BIT(6) 188 #define LPF_RESISTORS_15_5KOHM 0x1 189 #define LPF_RESISTORS_13KOHM 0x2 190 #define LPF_RESISTORS_11_5KOHM 0x4 191 #define LPF_RESISTORS_10_5KOHM 0x8 192 #define LPF_RESISTORS_8KOHM 0x10 193 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 194 195 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 196 197 #define INPUT_DIVIDER(val) ((val - 1) & 0x7f) 198 #define LOW_PROGRAM_EN 0 199 #define HIGH_PROGRAM_EN BIT(7) 200 #define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f) 201 #define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0xf) 202 #define PLL_LOOP_DIV_EN BIT(5) 203 #define PLL_INPUT_DIV_EN BIT(4) 204 205 #define POWER_CONTROL BIT(6) 206 #define INTERNAL_REG_CURRENT BIT(3) 207 #define BIAS_BLOCK_ON BIT(2) 208 #define BANDGAP_ON BIT(0) 209 210 #define TER_RESISTOR_HIGH BIT(7) 211 #define TER_RESISTOR_LOW 0 212 #define LEVEL_SHIFTERS_ON BIT(6) 213 #define TER_CAL_DONE BIT(5) 214 #define SETRD_MAX (0x7 << 2) 215 #define POWER_MANAGE BIT(1) 216 #define TER_RESISTORS_ON BIT(0) 217 218 #define BIASEXTR_SEL(val) ((val) & 0x7) 219 #define BANDGAP_SEL(val) ((val) & 0x7) 220 #define TLP_PROGRAM_EN BIT(7) 221 #define THS_PRE_PROGRAM_EN BIT(7) 222 #define THS_ZERO_PROGRAM_EN BIT(6) 223 224 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 225 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 226 #define PLL_LPF_AND_CP_CONTROL 0x12 227 #define PLL_INPUT_DIVIDER_RATIO 0x17 228 #define PLL_LOOP_DIVIDER_RATIO 0x18 229 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 230 #define BANDGAP_AND_BIAS_CONTROL 0x20 231 #define TERMINATION_RESISTER_CONTROL 0x21 232 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 233 #define HS_RX_CONTROL_OF_LANE_0 0x44 234 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 235 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 236 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 237 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 238 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 239 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 240 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 241 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 242 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 243 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 244 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 245 246 #define GEN_CMD_EMPTY BIT(0) 247 #define GEN_CMD_FULL BIT(1) 248 #define GEN_PLD_W_EMPTY BIT(2) 249 #define GEN_PLD_W_FULL BIT(3) 250 #define GEN_PLD_R_EMPTY BIT(4) 251 #define GEN_PLD_R_FULL BIT(5) 252 #define GEN_RD_CMD_BUSY BIT(6) 253 254 #define MIPI_INIT_CMD(...) { \ 255 .len = sizeof((char[]){__VA_ARGS__}), \ 256 .data = (char[]){__VA_ARGS__} } 257 258 enum mipi_dsi_pixel_format { 259 MIPI_DSI_FMT_RGB888, 260 MIPI_DSI_FMT_RGB666, 261 MIPI_DSI_FMT_RGB666_PACKED, 262 MIPI_DSI_FMT_RGB565, 263 }; 264 265 enum { 266 BANDGAP_97_07, 267 BANDGAP_98_05, 268 BANDGAP_99_02, 269 BANDGAP_100_00, 270 BANDGAP_93_17, 271 BANDGAP_94_15, 272 BANDGAP_95_12, 273 BANDGAP_96_10, 274 }; 275 276 enum { 277 BIASEXTR_87_1, 278 BIASEXTR_91_5, 279 BIASEXTR_95_9, 280 BIASEXTR_100, 281 BIASEXTR_105_94, 282 BIASEXTR_111_88, 283 BIASEXTR_118_8, 284 BIASEXTR_127_7, 285 }; 286 287 enum rk_mipi_dsi_mode { 288 MIPI_DSI_CMD_MODE, 289 MIPI_DSI_VID_MODE, 290 }; 291 292 struct dphy_pll_parameter_map { 293 unsigned int max_mbps; 294 u8 hsfreqrange; 295 u8 icpctrl; 296 u8 lpfctrl; 297 }; 298 299 struct rk_mipi_dsi { 300 struct rk_mipi_regs *mipi_regs; 301 u64 lane_bps; /* per lane */ 302 u32 lanes; 303 u32 format; 304 u16 input_div; 305 u16 feedback_div; 306 }; 307 308 struct panel_init_command { 309 int len; 310 char *data; 311 }; 312 313 struct mipi_panel_data { 314 u8 mipi_num; 315 enum mipi_dsi_pixel_format format; 316 u8 lanes; 317 u32 display_on_udelay; 318 u32 video_mode_udelay; 319 struct panel_init_command *init_cmd; 320 }; 321 322 void rk_mipi_prepare(const struct edid *edid, 323 const struct mipi_panel_data *panel_data); 324 #endif 325