1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* Register map for Exynos5 FIMD */ 4 5 #ifndef CPU_SAMSUNG_EXYNOS5420_FIMD_H 6 #define CPU_SAMSUNG_EXYNOS5420_FIMD_H 7 8 #include <soc/cpu.h> 9 10 /* FIMD register map */ 11 struct exynos5_fimd { 12 /* This is an incomplete list. Add registers as and when required */ 13 u32 vidcon0; 14 u8 res1[0x1c]; 15 u32 wincon0; 16 u32 wincon1; 17 u32 wincon2; 18 u32 wincon3; 19 u32 wincon4; 20 u32 shadowcon; 21 u8 res2[0x8]; 22 u32 vidosd0a; 23 u32 vidosd0b; 24 u32 vidosd0c; 25 u8 res3[0x54]; 26 u32 vidw00add0b0; 27 u8 res4[0x2c]; 28 u32 vidw00add1b0; 29 u8 res5[0x2c]; 30 u32 vidw00add2; 31 u8 res6[0x3c]; 32 u32 w1keycon0; 33 u32 w1keycon1; 34 u32 w2keycon0; 35 u32 w2keycon1; 36 u32 w3keycon0; 37 u32 w3keycon1; 38 u32 w4keycon0; 39 u32 w4keycon1; 40 u8 res7[0x20]; 41 u32 win0map; 42 u8 res8[0xdc]; 43 u32 blendcon; 44 u8 res9[0x18]; 45 u32 dpclkcon; 46 }; 47 check_member(exynos5_fimd, dpclkcon, 0x27c); 48 49 #define W0_SHADOW_PROTECT (0x1 << 10) 50 #define COMPKEY_F 0xffffff 51 #define ENVID_F_ON (0x1 << 0) 52 #define ENVID_ON (0x1 << 1) 53 #define CLKVAL_F 0xb 54 #define CLKVAL_F_OFFSET 6 55 56 /* 57 * Structure containing display panel specific data for FIMD 58 */ 59 struct exynos5_fimd_panel { 60 unsigned int is_dp:1; /* Display Panel interface is eDP */ 61 unsigned int is_mipi:1; /* Display Panel interface is MIPI */ 62 unsigned int fixvclk:2; /* VCLK hold scheme at data underflow */ 63 64 /* 65 * Polarity of the VCLK active edge 66 * 0-falling 67 * 1-rising 68 */ 69 unsigned int ivclk:1; 70 unsigned int clkval_f; /* Divider to create pixel clock */ 71 72 unsigned int upper_margin; /* Vertical Backporch */ 73 unsigned int lower_margin; /* Vertical frontporch */ 74 unsigned int vsync; /* Vertical Sync Pulse Width */ 75 unsigned int left_margin; /* Horizontal Backporch */ 76 unsigned int right_margin; /* Horizontal Frontporch */ 77 unsigned int hsync; /* Horizontal Sync Pulse Width */ 78 unsigned int xres; /* X Resolution */ 79 unsigned int yres; /* Y Resolution */ 80 }; 81 82 /* LCDIF Register Map */ 83 struct exynos5_disp_ctrl { 84 u32 vidout_con; 85 u32 vidcon1; 86 u8 res1[0x8]; 87 u32 vidtcon0; 88 u32 vidtcon1; 89 u32 vidtcon2; 90 u32 vidtcon3; 91 u8 res2[0x184]; 92 u32 trigcon; 93 }; 94 check_member(exynos5_disp_ctrl, trigcon, 0x1a4); 95 96 #define VCLK_RISING_EDGE (1 << 7) 97 #define VCLK_RUNNING (1 << 9) 98 99 #define CHANNEL0_EN (1 << 0) 100 101 #define VSYNC_PULSE_WIDTH_VAL 0x3 102 #define VSYNC_PULSE_WIDTH_OFFSET 0 103 #define V_FRONT_PORCH_VAL 0x3 104 #define V_FRONT_PORCH_OFFSET 8 105 #define V_BACK_PORCH_VAL 0x3 106 #define V_BACK_PORCH_OFFSET 16 107 108 #define HSYNC_PULSE_WIDTH_VAL 0x3 109 #define HSYNC_PULSE_WIDTH_OFFSET 0 110 #define H_FRONT_PORCH_VAL 0x3 111 #define H_FRONT_PORCH_OFFSET 8 112 #define H_BACK_PORCH_VAL 0x3 113 #define H_BACK_PORCH_OFFSET 16 114 115 #define HOZVAL_OFFSET 0 116 #define LINEVAL_OFFSET 11 117 118 #define BPPMODE_F_RGB_16BIT_565 0x5 119 #define BPPMODE_F_OFFSET 2 120 #define ENWIN_F_ENABLE (1 << 0) 121 #define HALF_WORD_SWAP_EN (1 << 16) 122 123 #define OSD_RIGHTBOTX_F_OFFSET 11 124 #define OSD_RIGHTBOTY_F_OFFSET 0 125 126 #define FIMD_CTRL_ADDR 0x14400000 127 #define FIMD_CTRL ((struct exynos_fb *)FIMD_CTRL_ADDR) 128 129 /* from u-boot fb.h. It needs to be merged with these dp structs maybe. */ 130 enum { 131 FIMD_RGB_INTERFACE = 1, 132 FIMD_CPU_INTERFACE = 2, 133 }; 134 135 enum exynos_fb_rgb_mode_t { 136 MODE_RGB_P = 0, 137 MODE_BGR_P = 1, 138 MODE_RGB_S = 2, 139 MODE_BGR_S = 3, 140 }; 141 142 typedef struct vidinfo { 143 u16 vl_col; /* Number of columns (i.e. 640) */ 144 u16 vl_row; /* Number of rows (i.e. 480) */ 145 u16 vl_width; /* Width of display area in millimeters */ 146 u16 vl_height; /* Height of display area in millimeters */ 147 148 /* LCD configuration register */ 149 u8 vl_freq; /* Frequency */ 150 u8 vl_clkp; /* Clock polarity */ 151 u8 vl_oep; /* Output Enable polarity */ 152 u8 vl_hsp; /* Horizontal Sync polarity */ 153 u8 vl_vsp; /* Vertical Sync polarity */ 154 u8 vl_dp; /* Data polarity */ 155 u8 vl_bpix; /* Bits per pixel */ 156 157 /* Horizontal control register. Timing from data sheet */ 158 u8 vl_hspw; /* Horz sync pulse width */ 159 u8 vl_hfpd; /* Wait before of line */ 160 u8 vl_hbpd; /* Wait end of line */ 161 162 /* Vertical control register. */ 163 u8 vl_vspw; /* Vertical sync pulse width */ 164 u8 vl_vfpd; /* Wait before of frame */ 165 u8 vl_vbpd; /* Wait end of frame */ 166 u8 vl_cmd_allow_len; /* Wait end of frame */ 167 168 unsigned int win_id; 169 unsigned int init_delay; 170 unsigned int power_on_delay; 171 unsigned int reset_delay; 172 unsigned int interface_mode; 173 unsigned int mipi_enabled; 174 unsigned int dp_enabled; 175 unsigned int cs_setup; 176 unsigned int wr_setup; 177 unsigned int wr_act; 178 unsigned int wr_hold; 179 unsigned int rgb_mode; 180 unsigned int resolution; 181 182 /* parent clock name(MPLL, EPLL or VPLL) */ 183 unsigned int pclk_name; 184 /* ratio value for source clock from parent clock. */ 185 unsigned int sclk_div; 186 187 unsigned int dual_lcd_enabled; 188 void *screen_base; 189 void *cmap; /* Points at 8 to 16 bit conversion map. */ 190 } vidinfo_t; 191 192 /* fimd.c */ 193 void exynos_set_trigger(void); 194 int exynos_is_i80_frame_done(void); 195 void exynos_fimd_lcd_off(void); 196 void exynos_fimd_window_off(unsigned int win_id); 197 unsigned long exynos_fimd_calc_fbsize(vidinfo_t *vid); 198 void exynos_fimd_lcd_disable(void); 199 void exynos_fimd_lcd_init(vidinfo_t *vid); 200 201 #endif 202