1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <stdint.h>
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <device/pci_ops.h>
8 #include <device/pci_ids.h>
9 #include <pc80/isa-dma.h>
10 #include <pc80/mc146818rtc.h>
11 #include <arch/ioapic.h>
12 #if CONFIG(HAVE_ACPI_TABLES)
13 #include <acpi/acpi.h>
14 #include <acpi/acpigen.h>
15 #endif
16 #include "i82371eb.h"
17 #include "chip.h"
18
isa_init(struct device * dev)19 static void isa_init(struct device *dev)
20 {
21 u32 reg32;
22 struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
23
24 /* Initialize the real time clock (RTC). */
25 cmos_init(0);
26
27 /*
28 * Enable special cycles, needed for soft poweroff.
29 */
30 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL);
31
32 /*
33 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
34 * bus, which is a subset of ISA. We select the full ISA bus here.
35 */
36 reg32 = pci_read_config32(dev, GENCFG);
37 reg32 |= ISA; /* Select ISA, not EIO. */
38
39 /* Some boards use GPO22/23. Select it if configured. */
40 reg32 = ONOFF(sb->gpo22_enable, reg32, GPO2223);
41 pci_write_config32(dev, GENCFG, reg32);
42
43 /* Initialize ISA DMA. */
44 isa_dma_init();
45
46 /*
47 * Unlike most other southbridges the 82371EB doesn't have a built-in
48 * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
49 * have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
50 *
51 * Thus, we can/must only enable the IOAPIC if it actually exists,
52 * i.e. the respective mainboard does "select IOAPIC".
53 */
54 if (CONFIG(IOAPIC)) {
55 u16 reg16;
56 const u8 ioapic_id = 2;
57
58 /* Enable IOAPIC. */
59 reg16 = pci_read_config16(dev, XBCS);
60 reg16 |= (1 << 8); /* APIC Chip Select */
61 pci_write_config16(dev, XBCS, reg16);
62
63 /* Set and verify the IOAPIC ID. */
64 setup_ioapic(IO_APIC_ADDR, ioapic_id);
65 if (ioapic_id != get_ioapic_id(IO_APIC_ADDR))
66 die("IOAPIC error!\n");
67 }
68 }
69
70 #define ACPI_SCI_IRQ 9
71
ioapic_get_sci_pin(u8 * gsi,u8 * irq,u8 * flags)72 void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
73 {
74 *gsi = ACPI_SCI_IRQ;
75 *irq = ACPI_SCI_IRQ;
76 *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
77 }
78
sb_read_resources(struct device * dev)79 static void sb_read_resources(struct device *dev)
80 {
81 struct resource *res;
82
83 pci_dev_read_resources(dev);
84
85 res = new_resource(dev, 1);
86 res->base = 0x0UL;
87 res->size = 0x1000UL;
88 res->limit = 0xffffUL;
89 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
90
91 res = new_resource(dev, 2);
92 res->base = 0xff800000UL;
93 res->size = 0x00800000UL; /* 8 MB for flash */
94 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
95 IORESOURCE_RESERVE;
96
97 res = new_resource(dev, 3); /* IOAPIC */
98 res->base = IO_APIC_ADDR;
99 res->size = 0x00001000;
100 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
101 IORESOURCE_RESERVE;
102 }
103
104 static const struct device_operations isa_ops = {
105 .read_resources = sb_read_resources,
106 .set_resources = pci_dev_set_resources,
107 .enable_resources = pci_dev_enable_resources,
108 #if CONFIG(HAVE_ACPI_TABLES)
109 .write_acpi_tables = acpi_write_hpet,
110 .acpi_fill_ssdt = generate_cpu_entries,
111 #endif
112 .init = isa_init,
113 .scan_bus = scan_static_bus,
114 .ops_pci = 0, /* No subsystem IDs on 82371EB! */
115 };
116
117 static const struct pci_driver isa_driver __pci_driver = {
118 .ops = &isa_ops,
119 .vendor = PCI_VID_INTEL,
120 .device = PCI_DID_INTEL_82371AB_ISA,
121 };
122
123 static const struct pci_driver isa_SB_driver __pci_driver = {
124 .ops = &isa_ops,
125 .vendor = PCI_VID_INTEL,
126 .device = PCI_DID_INTEL_82371SB_ISA,
127 };
128