1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <arch/null_breakpoint.h>
4 #include <bootsplash.h>
5 #include <bootstate.h>
6 #include <cbfs.h>
7 #include <cbmem.h>
8 #include <commonlib/fsp.h>
9 #include <stdlib.h>
10 #include <console/console.h>
11 #include <fsp/api.h>
12 #include <fsp/util.h>
13 #include <mrc_cache.h>
14 #include <program_loading.h>
15 #include <soc/intel/common/reset.h>
16 #include <soc/intel/common/vbt.h>
17 #include <stage_cache.h>
18 #include <string.h>
19 #include <timestamp.h>
20 #include <types.h>
21 #include <mode_switch.h>
22
23 struct fsp_header fsps_hdr;
24
25 /* Callbacks for SoC/Mainboard specific overrides */
platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)26 void __weak platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
27 {
28 /* Leave for the SoC/Mainboard to implement if necessary. */
29 }
30
31 /* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2
32 * has multiple stages as below.
33 */
34 enum fsp_silicon_init_phases {
35 FSP_SILICON_INIT_API,
36 FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API,
37 FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API
38 };
39
fsps_return_value_handler(enum fsp_silicon_init_phases phases,efi_return_status_t status)40 static void fsps_return_value_handler(enum fsp_silicon_init_phases phases,
41 efi_return_status_t status)
42 {
43 uint8_t postcode;
44
45 /* Handle any reset request returned by FSP-S APIs */
46 fsp_handle_reset(status);
47
48 if (status == FSP_SUCCESS)
49 return;
50 /* Handle all other errors returned by FSP-S APIs */
51 /* Assume video failure if attempted to initialize graphics */
52 if (CONFIG(RUN_FSP_GOP) && vbt_get())
53 postcode = POSTCODE_VIDEO_FAILURE;
54 else
55 postcode = POSTCODE_HW_INIT_FAILURE; /* else generic */
56
57 switch (phases) {
58 case FSP_SILICON_INIT_API:
59 fsp_die_with_post_code(status, postcode, "FspSiliconInit error");
60 break;
61 case FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API:
62 fsp_printk(status, BIOS_SPEW, "FspMultiPhaseSiInit NumberOfPhases");
63 break;
64 case FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API:
65 fsp_printk(status, BIOS_SPEW, "FspMultiPhaseSiInit ExecutePhase");
66 break;
67 default:
68 break;
69 }
70 }
71
fsp_is_multi_phase_init_enabled(void)72 bool fsp_is_multi_phase_init_enabled(void)
73 {
74 return CONFIG(FSPS_USE_MULTI_PHASE_INIT) &&
75 (fsps_hdr.fsp_multi_phase_si_init_entry_offset != 0);
76 }
77
fsp_fill_common_arch_params(FSPS_UPD * supd)78 static void fsp_fill_common_arch_params(FSPS_UPD *supd)
79 {
80 #if (CONFIG(FSPS_HAS_ARCH_UPD) && !CONFIG(PLATFORM_USES_FSP2_4))
81 FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd;
82 s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled();
83 #endif
84 }
85
do_silicon_init(struct fsp_header * hdr)86 static void do_silicon_init(struct fsp_header *hdr)
87 {
88 FSPS_UPD *upd, *supd;
89 fsp_silicon_init_fn silicon_init;
90 efi_return_status_t status;
91 fsp_multi_phase_init_fn multi_phase_si_init;
92 struct fsp_multi_phase_params multi_phase_params;
93 struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
94
95 supd = (FSPS_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
96
97 fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE);
98
99 /* FSPS UPD and coreboot structure sizes should match. However, enforcing the exact
100 * match mandates simultaneous updates to coreboot and FSP repos. Allow coreboot
101 * to proceed if its UPD structure is smaller than FSP one to enable staggered UPD
102 * update process on both sides. The mismatch indicates a temporary build problem,
103 * don't leave it like this as FSP default settings can be bad choices for coreboot.
104 */
105 if (!hdr->cfg_region_size || hdr->cfg_region_size < sizeof(FSPS_UPD))
106 die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
107 "Invalid FSPS UPD region\n");
108 else if (hdr->cfg_region_size > sizeof(FSPS_UPD))
109 printk(BIOS_ERR, "FSP and coreboot are out of sync! FSPS UPD size > coreboot\n");
110
111 upd = xmalloc(hdr->cfg_region_size);
112
113 memcpy(upd, supd, hdr->cfg_region_size);
114
115 /* Fill common settings on behalf of chipset. */
116 if (CONFIG(FSPS_HAS_ARCH_UPD))
117 fsp_fill_common_arch_params(upd);
118 /* Give SoC/mainboard a chance to populate entries */
119 platform_fsp_silicon_init_params_cb(upd);
120
121 /* Populate logo related entries */
122 if (CONFIG(BMP_LOGO))
123 soc_load_logo(upd);
124
125 /* Call SiliconInit */
126 silicon_init = (void *)(uintptr_t)(hdr->image_base +
127 hdr->fsp_silicon_init_entry_offset);
128 fsp_debug_before_silicon_init(silicon_init, supd, upd);
129
130 timestamp_add_now(TS_FSP_SILICON_INIT_START);
131 post_code(POSTCODE_FSP_SILICON_INIT);
132
133 /* FSP disables the interrupt handler so remove debug exceptions temporarily */
134 null_breakpoint_disable();
135 if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
136 status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd);
137 else
138 status = silicon_init(upd);
139 null_breakpoint_init();
140
141 fsp_printk(status, BIOS_INFO, "FSPS");
142
143 timestamp_add_now(TS_FSP_SILICON_INIT_END);
144 post_code(POSTCODE_FSP_SILICON_EXIT);
145
146 fsp_debug_after_silicon_init(status);
147 fsps_return_value_handler(FSP_SILICON_INIT_API, status);
148
149 /* Reinitialize CPUs if FSP-S has done MP Init */
150 if (CONFIG(USE_INTEL_FSP_MP_INIT) && !fsp_is_multi_phase_init_enabled())
151 do_mpinit_after_fsp();
152
153 if (!CONFIG(PLATFORM_USES_FSP2_2))
154 return;
155
156 /* Check if SoC user would like to call Multi Phase Init */
157 if (!fsp_is_multi_phase_init_enabled())
158 return;
159
160 /* Call MultiPhaseSiInit */
161 multi_phase_si_init = (void *)(uintptr_t)(hdr->image_base +
162 hdr->fsp_multi_phase_si_init_entry_offset);
163
164 /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */
165 if (multi_phase_si_init == NULL)
166 return;
167
168 post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY);
169 timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_START);
170 /* Get NumberOfPhases Value */
171 multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES;
172 multi_phase_params.phase_index = 0;
173 multi_phase_params.multi_phase_param_ptr = &multi_phase_get_number;
174 status = multi_phase_si_init(&multi_phase_params);
175 fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, status);
176
177 /* Execute Multi Phase Execution */
178 for (uint32_t i = 1; i <= multi_phase_get_number.number_of_phases; i++) {
179 printk(BIOS_SPEW, "Executing Phase %u of FspMultiPhaseSiInit\n", i);
180 /*
181 * Give SoC/mainboard a chance to perform any operation before
182 * Multi Phase Execution
183 */
184 platform_fsp_silicon_multi_phase_init_cb(i);
185
186 multi_phase_params.multi_phase_action = EXECUTE_PHASE;
187 multi_phase_params.phase_index = i;
188 multi_phase_params.multi_phase_param_ptr = NULL;
189 status = multi_phase_si_init(&multi_phase_params);
190 if (CONFIG(FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN))
191 status = fsp_get_pch_reset_status();
192 fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API, status);
193 }
194 timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
195 post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT);
196
197 /* Reinitialize CPUs if FSP-S has done MP Init */
198 if (CONFIG(USE_INTEL_FSP_MP_INIT))
199 do_mpinit_after_fsp();
200 }
201
fsps_allocator(void * arg_unused,size_t size,const union cbfs_mdata * mdata_unused)202 static void *fsps_allocator(void *arg_unused, size_t size, const union cbfs_mdata *mdata_unused)
203 {
204 return cbmem_add(CBMEM_ID_REFCODE, size);
205 }
206
fsps_load(void)207 void fsps_load(void)
208 {
209 const char *fsps_cbfs = soc_select_fsp_s_cbfs();
210 struct fsp_load_descriptor fspld = {
211 .fsp_prog = PROG_INIT(PROG_REFCODE, fsps_cbfs),
212 .alloc = fsps_allocator,
213 };
214 struct prog *fsps = &fspld.fsp_prog;
215 static int load_done;
216
217 if (load_done)
218 return;
219
220 timestamp_add_now(TS_FSP_SILICON_INIT_LOAD);
221
222 if (resume_from_stage_cache()) {
223 printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n");
224 stage_cache_load_stage(STAGE_REFCODE, fsps);
225 if (fsp_validate_component(&fsps_hdr, prog_start(fsps), prog_size(fsps)))
226 die("On resume fsps header is invalid\n");
227 load_done = 1;
228 return;
229 }
230
231 if (fsp_load_component(&fspld, &fsps_hdr) != CB_SUCCESS)
232 die("FSP-S failed to load\n");
233
234 stage_cache_add(STAGE_REFCODE, fsps);
235
236 load_done = 1;
237 }
238
preload_fsps(void)239 void preload_fsps(void)
240 {
241 if (!CONFIG(CBFS_PRELOAD))
242 return;
243
244 const char *fsps_cbfs = soc_select_fsp_s_cbfs();
245 printk(BIOS_DEBUG, "Preloading %s\n", fsps_cbfs);
246 cbfs_preload(fsps_cbfs);
247 }
248
fsp_silicon_init(void)249 void fsp_silicon_init(void)
250 {
251 fsps_load();
252 do_silicon_init(&fsps_hdr);
253
254 if (CONFIG(CACHE_MRC_SETTINGS) && CONFIG(FSP_NVS_DATA_POST_SILICON_INIT))
255 save_memory_training_data();
256
257 if (CONFIG(DISPLAY_FSP_TIMESTAMPS))
258 fsp_display_timestamp();
259 }
260
soc_load_logo(FSPS_UPD * supd)261 __weak void soc_load_logo(FSPS_UPD *supd) { }
262
release_logo(void * arg_unused)263 static void release_logo(void *arg_unused)
264 {
265 if (CONFIG(BMP_LOGO))
266 bmp_release_logo();
267 }
268
269 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, release_logo, NULL);
270