1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <arch/io.h>
4 #include <device/pnp_ops.h>
5 #include <stdint.h>
6 #include <commonlib/helpers.h>
7 #include "aspeed.h"
8
lpc_read(uint8_t port,uint32_t addr,uint32_t * value)9 void lpc_read(uint8_t port, uint32_t addr, uint32_t *value)
10 {
11 uint32_t data = 0;
12 uint8_t tmp;
13 pnp_devfn_t dev = PNP_DEV(port, LDN_ILPC2AHB);
14
15 pnp_enter_conf_state(dev);
16 pnp_set_logical_device(dev);
17 pnp_set_enable(dev, 1);
18
19 /* Write Address */
20 pnp_write_config(dev, LPC2AHB_ADD0_REG, ((addr & 0xff000000) >> 24));
21 pnp_write_config(dev, LPC2AHB_ADD1_REG, ((addr & 0x00ff0000) >> 16));
22 pnp_write_config(dev, LPC2AHB_ADD2_REG, ((addr & 0x0000ff00) >> 8));
23 pnp_write_config(dev, LPC2AHB_ADD3_REG, (addr & 0x000000ff));
24
25 /* Write Mode */
26 tmp = pnp_read_config(dev, LPC2AHB_LEN_REG);
27 pnp_write_config(dev, LPC2AHB_LEN_REG, (tmp & 0xfc) | LPC2AHB_4_BYTE);
28
29 /* Fire the command */
30 outb(LPC2AHB_RW_REG, port);
31 tmp = inb(port + 1);
32
33 /* Get Data */
34 data |= (pnp_read_config(dev, LPC2AHB_DAT0_REG) << 24) |
35 (pnp_read_config(dev, LPC2AHB_DAT1_REG) << 16) |
36 (pnp_read_config(dev, LPC2AHB_DAT2_REG) << 8) |
37 pnp_read_config(dev, LPC2AHB_DAT3_REG);
38 *value = data;
39
40 pnp_set_enable(dev, 0);
41 pnp_exit_conf_state(dev);
42 }
43
lpc_write(uint8_t port,uint32_t addr,uint32_t data)44 void lpc_write(uint8_t port, uint32_t addr, uint32_t data)
45 {
46 uint8_t tmp;
47 pnp_devfn_t dev = PNP_DEV(port, LDN_ILPC2AHB);
48
49 pnp_enter_conf_state(dev);
50 pnp_set_logical_device(dev);
51 pnp_set_enable(dev, 1);
52
53 /* Write Address */
54 pnp_write_config(dev, LPC2AHB_ADD0_REG, ((addr & 0xFF000000) >> 24));
55 pnp_write_config(dev, LPC2AHB_ADD1_REG, ((addr & 0x00FF0000) >> 16));
56 pnp_write_config(dev, LPC2AHB_ADD2_REG, ((addr & 0x0000FF00) >> 8));
57 pnp_write_config(dev, LPC2AHB_ADD3_REG, (addr & 0x000000FF));
58
59 /* Write Data */
60 pnp_write_config(dev, LPC2AHB_DAT0_REG, ((data & 0xFF000000) >> 24));
61 pnp_write_config(dev, LPC2AHB_DAT1_REG, ((data & 0x00FF0000) >> 16));
62 pnp_write_config(dev, LPC2AHB_DAT2_REG, ((data & 0x0000FF00) >> 8));
63 pnp_write_config(dev, LPC2AHB_DAT3_REG, (data & 0x000000FF));
64
65 /* Write Mode */
66 tmp = pnp_read_config(dev, LPC2AHB_LEN_REG);
67 pnp_write_config(dev, LPC2AHB_LEN_REG, (tmp & 0xfc) | LPC2AHB_4_BYTE);
68
69 /* Fire */
70 pnp_write_config(dev, LPC2AHB_RW_REG, 0xcf);
71
72 pnp_set_enable(dev, 0);
73 pnp_exit_conf_state(dev);
74 }
75
aspeed_early_config(pnp_devfn_t dev,config_data * table,uint8_t count)76 void aspeed_early_config(pnp_devfn_t dev, config_data *table, uint8_t count)
77 {
78 uint8_t i, t, port;
79 uint32_t v, addr;
80 port = dev >> 8;
81 for (i = 0; i < count; i++) {
82 if (table[i].type == MEM) {
83 addr = (u32)(table[i].base | table[i].reg);
84 lpc_read(port, addr, &v);
85 v &= table[i].and;
86 v |= table[i].or;
87 lpc_write(port, addr, v);
88 } else if (table[i].type == SIO) {
89 pnp_enter_conf_state(dev);
90 pnp_set_logical_device(dev);
91 t = pnp_read_config(dev, ACT_REG) | ACTIVATE_VALUE;
92 pnp_write_config(dev, ACT_REG, t);
93 t = pnp_read_config(dev, (uint8_t)(table[i].reg));
94 t &= (uint8_t)(table[i].and);
95 t |= (uint8_t)(table[i].or);
96 pnp_write_config(dev, (uint8_t)(table[i].reg), t);
97 pnp_set_logical_device(dev);
98 t = pnp_read_config(dev, ACT_REG) & ~ACTIVATE_VALUE;
99 pnp_write_config(dev, ACT_REG, t);
100 pnp_exit_conf_state(dev);
101 }
102 }
103 }
104
aspeed_enable_port80_direct_gpio(pnp_devfn_t dev,gpio_group_sel g)105 void aspeed_enable_port80_direct_gpio(pnp_devfn_t dev, gpio_group_sel g)
106 {
107 struct config_data port80[] = {
108 /* Set command source 0 */
109 [Step1] = {
110 .type = MEM,
111 .base = ASPEED_GPIO_BASE,
112 .reg = TO_BE_UPDATE,
113 .and = AndMask32((g % 4) * 8, (g % 4) * 8),
114 .or = (LPC & 0x01) << ((g % 4) * 8)
115 },
116 /* Set command source 1 */
117 [Step2] = {
118 .type = MEM,
119 .base = ASPEED_GPIO_BASE,
120 .reg = TO_BE_UPDATE,
121 .and = AndMask32((g % 4) * 8, (g % 4) * 8),
122 .or = (LPC & 0x02) << ((g % 4) * 8)
123 },
124 /* Unlock SCU registers */
125 [Step3] = {
126 .type = MEM,
127 .base = ASPEED_SCU_BASE,
128 .reg = PRO_KEY_REG,
129 .and = 0,
130 .or = PRO_KEY_PASSWORD
131 },
132 /* Program multi-function to GPIO */
133 [Step4] = {
134 .type = MEM,
135 .base = ASPEED_SCU_BASE,
136 .reg = TO_BE_UPDATE,
137 .and = TO_BE_UPDATE,
138 .or = TO_BE_UPDATE
139 },
140 [Step5] = {
141 .type = MEM,
142 .base = ASPEED_SCU_BASE,
143 .reg = TO_BE_UPDATE,
144 .and = TO_BE_UPDATE,
145 .or = TO_BE_UPDATE
146 },
147 [Step6] = {
148 .type = MEM,
149 .base = ASPEED_SCU_BASE,
150 .reg = TO_BE_UPDATE,
151 .and = TO_BE_UPDATE,
152 .or = TO_BE_UPDATE
153 },
154 [Step7] = {
155 .type = MEM,
156 .base = ASPEED_SCU_BASE,
157 .reg = TO_BE_UPDATE,
158 .and = TO_BE_UPDATE,
159 .or = TO_BE_UPDATE
160 },
161 /* Program GPIO as output */
162 [Step8] = {
163 .type = MEM,
164 .base = ASPEED_GPIO_BASE,
165 .reg = TO_BE_UPDATE,
166 .and = AndMask32((((g % 4) + 1) * 8) - 1, (g % 4) * 8),
167 .or = 0xFF << ((g % 4) * 8)
168 },
169 /* Set snooping address#0 as 80h */
170 [Step9] = {
171 .type = MEM,
172 .base = ASPEED_LPC_BASE,
173 .reg = SNPWADR_REG,
174 .and = AndMask32(15, 0),
175 .or = SNOOP_ADDR_PORT80
176 },
177 /* Enable snooping address#0 */
178 [Step10] = {
179 .type = MEM,
180 .base = ASPEED_LPC_BASE,
181 .reg = HICR5_REG,
182 .and = AndMask32(0, 0),
183 .or = 1 << SNOOP_ADDR_EN
184 },
185 /* Lock SCU registers */
186 [Step11] = {
187 .type = MEM,
188 .base = ASPEED_SCU_BASE,
189 .reg = PRO_KEY_REG,
190 .and = 0,
191 .or = 0
192 },
193 /* Select group for port80 GPIO */
194 [Step12] = {
195 .type = SIO,
196 .base = 0,
197 .reg = PORT80_GPIO_SEL_REG,
198 .and = AndMask32(4, 0),
199 .or = g
200 },
201 /* Enable port80 GPIO */
202 [Step13] = {
203 .type = SIO,
204 .base = 0,
205 .reg = ACT_REG,
206 .and = AndMask32(8, 8),
207 .or = PORT80_GPIO_EN
208 },
209 };
210
211 switch (g) {
212 case GPIOA:
213 case GPIOB:
214 case GPIOC:
215 case GPIOD:
216 port80[Step1].reg = A_B_C_D_CMD_SOURCE0_REG;
217 port80[Step2].reg = A_B_C_D_CMD_SOURCE1_REG;
218 port80[Step8].reg = A_B_C_D_DIRECTION_REG;
219 break;
220 case GPIOE:
221 case GPIOF:
222 case GPIOG:
223 case GPIOH:
224 port80[Step1].reg = E_F_G_H_CMD_SOURCE0_REG;
225 port80[Step2].reg = E_F_G_H_CMD_SOURCE1_REG;
226 port80[Step8].reg = E_F_G_H_DIRECTION_REG;
227 break;
228 case GPIOI:
229 case GPIOJ:
230 case GPIOK:
231 case GPIOL:
232 port80[Step1].reg = I_J_K_L_CMD_SOURCE0_REG;
233 port80[Step2].reg = I_J_K_L_CMD_SOURCE1_REG;
234 port80[Step8].reg = I_J_K_L_DIRECTION_REG;
235 break;
236 case GPIOM:
237 case GPION:
238 case GPIOO:
239 case GPIOP:
240 port80[Step1].reg = M_N_O_P_CMD_SOURCE0_REG;
241 port80[Step2].reg = M_N_O_P_CMD_SOURCE1_REG;
242 port80[Step8].reg = M_N_O_P_DIRECTION_REG;
243 break;
244 case GPIOQ:
245 case GPIOR:
246 case GPIOS:
247 case GPIOT:
248 port80[Step1].reg = Q_R_S_T_CMD_SOURCE0_REG;
249 port80[Step2].reg = Q_R_S_T_CMD_SOURCE1_REG;
250 port80[Step8].reg = Q_R_S_T_DIRECTION_REG;
251 break;
252 case GPIOU:
253 case GPIOV:
254 case GPIOW:
255 case GPIOX:
256 port80[Step1].reg = U_V_W_X_CMD_SOURCE0_REG;
257 port80[Step2].reg = U_V_W_X_CMD_SOURCE1_REG;
258 port80[Step8].reg = U_V_W_X_DIRECTION_REG;
259 break;
260 case GPIOY:
261 case GPIOZ:
262 case GPIOAA:
263 case GPIOAB:
264 port80[Step1].reg = Y_Z_AA_AB_CMD_SOURCE0_REG;
265 port80[Step2].reg = Y_Z_AA_AB_CMD_SOURCE1_REG;
266 port80[Step8].reg = Y_Z_AA_AB_DIRECTION_REG;
267 break;
268 }
269
270 switch (g) {
271 case GPIOA:
272 port80[Step4].reg = MUL_FUNC_PIN_CTL1_REG;
273 port80[Step4].and = AndMask32(7, 0) & AndMask32(15, 15);
274 port80[Step5].reg = MUL_FUNC_PIN_CTL4_REG;
275 port80[Step5].and = AndMask32(6, 6) & AndMask32(2, 2) & AndMask32(22, 22);
276 port80[Step6].type = NOP;
277 port80[Step7].type = NOP;
278 break;
279 case GPIOB:
280 port80[Step4].reg = HW_STRAP_REG;
281 port80[Step4].and = AndMask32(23, 23);
282 port80[Step5].reg = MUL_FUNC_PIN_CTL1_REG;
283 port80[Step5].and = AndMask32(14, 13);
284 port80[Step6].type = NOP;
285 port80[Step7].type = NOP;
286 break;
287 case GPIOC:
288 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
289 port80[Step4].and = AndMask32(0, 0);
290 port80[Step5].reg = MUL_FUNC_PIN_CTL5_REG;
291 port80[Step5].and = AndMask32(26, 23);
292 port80[Step6].type = NOP;
293 port80[Step7].type = NOP;
294 break;
295 case GPIOD:
296 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
297 port80[Step4].and = AndMask32(1, 1);
298 port80[Step5].reg = MUL_FUNC_PIN_CTL4_REG;
299 port80[Step5].and = AndMask32(11, 8);
300 port80[Step6].reg = HW_STRAP_REG;
301 port80[Step6].and = AndMask32(21, 21);
302 port80[Step7].type = NOP;
303 break;
304 case GPIOE:
305 port80[Step4].reg = MUL_FUNC_PIN_CTL1_REG;
306 port80[Step4].and = AndMask32(23, 16);
307 port80[Step5].reg = MUL_FUNC_PIN_CTL4_REG;
308 port80[Step5].and = AndMask32(15, 12);
309 port80[Step6].reg = HW_STRAP_REG;
310 port80[Step6].and = AndMask32(22, 22);
311 port80[Step7].type = NOP;
312 break;
313 case GPIOF:
314 port80[Step4].base = ASPEED_LPC_BASE;
315 port80[Step4].reg = LHCR0_REG;
316 port80[Step4].and = AndMask32(0, 0);
317 port80[Step5].reg = MUL_FUNC_PIN_CTL1_REG;
318 port80[Step5].and = AndMask32(31, 24);
319 port80[Step6].reg = MUL_FUNC_PIN_CTL5_REG;
320 port80[Step6].and = AndMask32(30, 30);
321 port80[Step7].type = NOP;
322 break;
323 case GPIOG:
324 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
325 port80[Step4].and = AndMask32(6, 6);
326 port80[Step5].reg = MUL_FUNC_PIN_CTL2_REG;
327 port80[Step5].and = AndMask32(7, 0);
328 port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG;
329 port80[Step6].and = AndMask32(12, 12);
330 port80[Step7].type = NOP;
331 break;
332 case GPIOH:
333 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
334 port80[Step4].and = AndMask32(7, 6);
335 port80[Step5].reg = FRQ_CNT_CTL_REG;
336 port80[Step5].and = AndMask32(8, 8);
337 port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG;
338 port80[Step6].and = AndMask32(7, 5);
339 port80[Step7].type = NOP;
340 break;
341 case GPIOI:
342 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
343 port80[Step4].and = AndMask32(6, 6);
344 port80[Step5].reg = HW_STRAP_REG;
345 port80[Step5].and = AndMask32(13, 12) & AndMask32(5, 5);
346 port80[Step6].type = NOP;
347 port80[Step7].type = NOP;
348 break;
349 case GPIOJ:
350 port80[Step4].reg = FRQ_CNT_CTL_REG;
351 port80[Step4].and = AndMask32(8, 8);
352 port80[Step5].reg = MUL_FUNC_PIN_CTL2_REG;
353 port80[Step5].and = AndMask32(15, 8);
354 port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG;
355 port80[Step6].and = AndMask32(8, 8);
356 port80[Step7].type = NOP;
357 break;
358 case GPIOK:
359 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
360 port80[Step4].and = AndMask32(21, 18);
361 port80[Step5].type = NOP;
362 port80[Step6].type = NOP;
363 port80[Step7].type = NOP;
364 break;
365 case GPIOL:
366 port80[Step4].reg = MUL_FUNC_PIN_CTL2_REG;
367 port80[Step4].and = AndMask32(23, 16);
368 port80[Step5].type = NOP;
369 port80[Step6].type = NOP;
370 port80[Step7].type = NOP;
371 break;
372 case GPIOM:
373 port80[Step4].reg = MUL_FUNC_PIN_CTL2_REG;
374 port80[Step4].and = AndMask32(31, 24);
375 port80[Step5].type = NOP;
376 port80[Step6].type = NOP;
377 port80[Step7].type = NOP;
378 break;
379 case GPION:
380 port80[Step4].reg = MUL_FUNC_PIN_CTL3_REG;
381 port80[Step4].and = AndMask32(7, 0);
382 port80[Step5].type = NOP;
383 port80[Step6].type = NOP;
384 port80[Step7].type = NOP;
385 break;
386 case GPIOO:
387 port80[Step4].reg = MUL_FUNC_PIN_CTL3_REG;
388 port80[Step4].and = AndMask32(15, 8);
389 port80[Step5].reg = MUL_FUNC_PIN_CTL5_REG;
390 port80[Step5].and = AndMask32(5, 5) & AndMask32(5, 4);
391 port80[Step6].type = NOP;
392 port80[Step7].type = NOP;
393 break;
394 case GPIOP:
395 port80[Step4].reg = MUL_FUNC_PIN_CTL3_REG;
396 port80[Step4].and = AndMask32(23, 16);
397 port80[Step5].reg = MUL_FUNC_PIN_CTL5_REG;
398 port80[Step5].and = AndMask32(5, 5) & AndMask32(5, 4) & AndMask32(28, 28);
399 port80[Step6].type = NOP;
400 port80[Step7].type = NOP;
401 break;
402 case GPIOQ:
403 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
404 port80[Step4].and = AndMask32(17, 16) & AndMask32(27, 27);
405 port80[Step5].reg = MISC_CTL_REG;
406 port80[Step5].and = AndMask32(1, 1) & AndMask32(29, 29);
407 port80[Step6].type = NOP;
408 port80[Step7].type = NOP;
409 break;
410 case GPIOR:
411 port80[Step4].reg = MUL_FUNC_PIN_CTL3_REG;
412 port80[Step4].and = AndMask32(31, 24);
413 port80[Step5].type = NOP;
414 port80[Step6].type = NOP;
415 port80[Step7].type = NOP;
416 break;
417 case GPIOS:
418 port80[Step4].reg = MUL_FUNC_PIN_CTL4_REG;
419 port80[Step4].and = AndMask32(7, 0);
420 port80[Step5].reg = MUL_FUNC_PIN_CTL6_REG;
421 port80[Step5].and = AndMask32(1, 0);
422 port80[Step6].type = NOP;
423 port80[Step7].type = NOP;
424 break;
425 case GPIOT:
426 port80[Step4].reg = MUL_FUNC_PIN_CTL7_REG;
427 port80[Step4].and = AndMask32(7, 0);
428 port80[Step4].or = ~AndMask32(7, 0);
429 port80[Step5].type = NOP;
430 port80[Step6].type = NOP;
431 port80[Step7].type = NOP;
432 break;
433 case GPIOU:
434 port80[Step4].reg = MUL_FUNC_PIN_CTL7_REG;
435 port80[Step4].and = AndMask32(15, 8);
436 port80[Step4].or = ~AndMask32(15, 8);
437 port80[Step5].type = NOP;
438 port80[Step6].type = NOP;
439 port80[Step7].type = NOP;
440 break;
441 case GPIOV:
442 port80[Step4].reg = MUL_FUNC_PIN_CTL7_REG;
443 port80[Step4].and = AndMask32(23, 16);
444 port80[Step4].or = ~AndMask32(23, 16);
445 port80[Step5].type = NOP;
446 port80[Step6].type = NOP;
447 port80[Step7].type = NOP;
448 break;
449 case GPIOW:
450 port80[Step4].reg = MUL_FUNC_PIN_CTL7_REG;
451 port80[Step4].and = AndMask32(31, 24);
452 port80[Step4].or = ~AndMask32(31, 24);
453 port80[Step5].type = NOP;
454 port80[Step6].type = NOP;
455 port80[Step7].type = NOP;
456 break;
457 case GPIOX:
458 port80[Step4].reg = MUL_FUNC_PIN_CTL8_REG;
459 port80[Step4].and = AndMask32(7, 0);
460 port80[Step4].or = ~AndMask32(7, 0);
461 port80[Step5].type = NOP;
462 port80[Step6].type = NOP;
463 port80[Step7].type = NOP;
464 break;
465 case GPIOY:
466 port80[Step4].reg = HW_STRAP_REG;
467 port80[Step4].and = AndMask32(19, 19);
468 port80[Step5].reg = MUL_FUNC_PIN_CTL8_REG;
469 port80[Step5].and = AndMask32(15, 8);
470 port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG;
471 port80[Step6].and = AndMask32(11, 10);
472 port80[Step7].type = NOP;
473 break;
474 case GPIOZ:
475 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
476 port80[Step4].and = AndMask32(31, 31);
477 port80[Step5].reg = MUL_FUNC_PIN_CTL8_REG;
478 port80[Step5].and = AndMask32(23, 16);
479 port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG;
480 port80[Step6].and = AndMask32(1, 0);
481 port80[Step6].reg = HW_STRAP_REG;
482 port80[Step6].and = AndMask32(19, 19);
483 break;
484 case GPIOAA:
485 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
486 port80[Step4].and = AndMask32(31, 31);
487 port80[Step5].reg = MUL_FUNC_PIN_CTL8_REG;
488 port80[Step5].and = AndMask32(31, 24);
489 port80[Step6].type = NOP;
490 port80[Step7].type = NOP;
491 break;
492 case GPIOAB:
493 port80[Step4].reg = MUL_FUNC_PIN_CTL5_REG;
494 port80[Step4].and = AndMask32(31, 31);
495 port80[Step5].reg = MUL_FUNC_PIN_CTL9_REG;
496 port80[Step5].and = AndMask32(3, 0);
497 port80[Step6].reg = MUL_FUNC_PIN_CTL6_REG;
498 port80[Step6].and = AndMask32(1, 0);
499 port80[Step7].type = NOP;
500 break;
501 default:
502 return;
503 }
504
505 aspeed_early_config(dev, port80, ARRAY_SIZE(port80));
506 }
507
aspeed_enable_uart_pin(pnp_devfn_t dev)508 void aspeed_enable_uart_pin(pnp_devfn_t dev)
509 {
510 struct config_data uart[] = {
511 /* Unlock SCU registers */
512 [Step1] = {
513 .type = MEM,
514 .base = ASPEED_SCU_BASE,
515 .reg = PRO_KEY_REG,
516 .and = 0,
517 .or = PRO_KEY_PASSWORD
518 },
519 /* Enable UART function pin */
520 [Step2] = {
521 .type = MEM,
522 .base = ASPEED_SCU_BASE,
523 .reg = TO_BE_UPDATE,
524 .and = TO_BE_UPDATE,
525 .or = TO_BE_UPDATE
526 },
527 [Step3] = {
528 .type = MEM,
529 .base = ASPEED_SCU_BASE,
530 .reg = MUL_FUNC_PIN_CTL6_REG,
531 .and = AndMask32(1, 0),
532 .or = DIGI_VIDEO_OUT_PINS_DIS
533 },
534 /* Lock SCU registers */
535 [Step4] = {
536 .type = MEM,
537 .base = ASPEED_SCU_BASE,
538 .reg = PRO_KEY_REG,
539 .and = 0,
540 .or = 0
541 },
542 };
543
544 switch (dev & 0xff) {
545 case LDN_SUART1:
546 uart[Step2].reg = MUL_FUNC_PIN_CTL2_REG;
547 uart[Step2].and = AndMask32(23, 22);
548 uart[Step2].or = (1 << UART1_TXD1_EN_BIT) | (1 << UART1_RXD1_EN_BIT);
549 break;
550 case LDN_SUART2:
551 uart[Step2].reg = MUL_FUNC_PIN_CTL2_REG;
552 uart[Step2].and = AndMask32(31, 30);
553 uart[Step2].or = (1 << UART2_TXD2_EN_BIT) | (1 << UART2_RXD2_EN_BIT);
554 break;
555 case LDN_SUART3:
556 uart[Step2].reg = MUL_FUNC_PIN_CTL1_REG;
557 uart[Step2].and = AndMask32(23, 22);
558 uart[Step2].or = (1 << UART3_TXD3_EN_BIT) | (1 << UART3_RXD3_EN_BIT);
559 uart[Step3].type = NOP;
560 break;
561 case LDN_SUART4:
562 uart[Step2].reg = MUL_FUNC_PIN_CTL1_REG;
563 uart[Step2].and = AndMask32(31, 30);
564 uart[Step2].or = (1 << UART4_TXD4_EN_BIT) | (1 << UART4_RXD4_EN_BIT);
565 uart[Step3].type = NOP;
566 break;
567 default:
568 return;
569 }
570
571 aspeed_early_config(dev, uart, ARRAY_SIZE(uart));
572 }
573