1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef CPU_X86_MSR_H
4 #define CPU_X86_MSR_H
5
6 #include <cpu/x86/msr_access.h> /* IWYU pragma: export */
7
8 /* Intel SDM: Table 2-1
9 * IA-32 architectural MSR: Extended Feature Enable Register
10 *
11 * AMD64 Programmers Manual vol2 Revision 3.30 and/or the device's BKDG
12 */
13
14 #define IA32_EFER 0xC0000080
15 #define EFER_NXE (1 << 11)
16 #define EFER_LMA (1 << 10)
17 #define EFER_LME (1 << 8)
18 #define EFER_SCE (1 << 0)
19
20 /* Page attribute type MSR */
21 #define TSC_MSR 0x10
22 #define IA32_PLATFORM_ID 0x17
23 #define IA32_APIC_BASE_MSR_INDEX 0x1B
24 #define IA32_FEATURE_CONTROL 0x3a
25 #define FEATURE_CONTROL_LOCK_BIT (1 << 0)
26 #define FEATURE_ENABLE_VMX (1 << 2)
27 #define SMRR_ENABLE (1 << 3)
28 #define CPUID_VMX (1 << 5)
29 #define CPUID_SMX (1 << 6)
30 #define CPUID_DCA (1 << 18)
31 #define CPUID_X2APIC (1 << 21)
32 #define CPUID_AES (1 << 25)
33 #define SGX_GLOBAL_ENABLE (1 << 18)
34 #define PLATFORM_INFO_SET_TDP (1 << 29)
35 #define IA32_BIOS_UPDT_TRIG 0x79
36 #define IA32_BIOS_SIGN_ID 0x8b
37 #define IA32_MPERF 0xe7
38 #define IA32_APERF 0xe8
39 /* STM */
40 #define IA32_SMM_MONITOR_CTL_MSR 0x9B
41 #define SMBASE_RO_MSR 0x98
42 #define IA32_SMM_MONITOR_VALID (1 << 0)
43 #define IA32_MCG_CAP 0x179
44 #define MCG_CTL_P (1 << 8)
45 #define MCA_BANKS_MASK 0xff
46 #define IA32_PERF_STATUS 0x198
47 #define IA32_PERF_CTL 0x199
48 #define IA32_THERM_INTERRUPT 0x19b
49 #define IA32_MISC_ENABLE 0x1a0
50 #define FAST_STRINGS_ENABLE_BIT (1 << 0)
51 #define SPEED_STEP_ENABLE_BIT (1 << 16)
52 #define IA32_ENERGY_PERF_BIAS 0x1b0
53 #define ENERGY_POLICY_PERFORMANCE 0
54 #define ENERGY_POLICY_NORMAL 6
55 #define ENERGY_POLICY_POWERSAVE 15
56 #define ENERGY_POLICY_MASK 0xf
57 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
58 #define SMRR_PHYSBASE_MSR 0x1F2
59 #define SMRR_PHYSMASK_MSR 0x1F3
60 #define IA32_PLATFORM_DCA_CAP 0x1f8
61 #define DCA_TYPE0_EN (1 << 0)
62 #define IA32_PAT 0x277
63 #define IA32_MC0_CTL 0x400
64 #define IA32_MC_CTL(bank) (IA32_MC0_CTL + 4 * (bank))
65 #define IA32_MC0_STATUS 0x401
66 #define IA32_MC_STATUS(bank) (IA32_MC0_STATUS + 4 * (bank))
67 #define MCA_STATUS_HI_VAL (1UL << (63 - 32))
68 #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
69 #define MCA_STATUS_HI_UC (1UL << (61 - 32))
70 #define MCA_STATUS_HI_EN (1UL << (60 - 32))
71 #define MCA_STATUS_HI_MISCV (1UL << (59 - 32))
72 #define MCA_STATUS_HI_ADDRV (1UL << (58 - 32))
73 #define MCA_STATUS_HI_PCC (1UL << (57 - 32))
74 #define MCA_STATUS_HI_COREID_VAL (1UL << (56 - 32))
75 #define MCA_STATUS_HI_CECC (1UL << (46 - 32))
76 #define MCA_STATUS_HI_UECC (1UL << (45 - 32))
77 #define MCA_STATUS_HI_DEFERRED (1UL << (44 - 32))
78 #define MCA_STATUS_HI_POISON (1UL << (43 - 32))
79 #define MCA_STATUS_HI_SUBLINK (1UL << (41 - 32))
80 #define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)
81 #define MCA_STATUS_LO_ERRCODE_EXT_SH 16
82 #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
83 #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
84 #define IA32_LT_UNLOCK_MEMORY 0x2e6
85 #define IA32_MC0_ADDR 0x402
86 #define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank))
87 #define IA32_MC0_MISC 0x403
88 #define IA32_MC_MISC(bank) (IA32_MC0_MISC + 4 * (bank))
89 #define IA32_VMX_BASIC_MSR 0x480
90 #define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32))
91 #define IA32_VMX_MISC_MSR 0x485
92
93 #define IA32_PM_ENABLE 0x770
94 #define HWP_ENABLE 0x1
95 #define IA32_HWP_CAPABILITIES 0x771
96 #define IA32_HWP_REQUEST 0x774
97 #define IA32_HWP_REQUEST_EPP_MASK 0xff000000
98 #define IA32_HWP_REQUEST_EPP_SHIFT 24
99 #define IA32_HWP_STATUS 0x777
100 #define IA32_L3_PROTECTED_WAYS 0xc85
101 #define IA32_SF_QOS_INFO 0xc87
102 #define IA32_SF_WAY_COUNT_MASK 0x3f
103 #define IA32_PQR_ASSOC 0xc8f
104 /* MSR bits 33:32 encode slot number 0-3 */
105 #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
106 #define IA32_L3_MASK_1 0xc91
107 #define IA32_L3_MASK_2 0xc92
108
109 #define IA32_CR_SF_QOS_MASK_1 0x1891
110 #define IA32_CR_SF_QOS_MASK_2 0x1892
111
112 #ifndef __ASSEMBLER__
113
114 typedef struct msrinit_struct {
115 unsigned int index;
116 msr_t msr;
117 } msrinit_t;
118
119 /* Get MCA bank count from MSR */
mca_get_bank_count(void)120 static inline unsigned int mca_get_bank_count(void)
121 {
122 msr_t msr = rdmsr(IA32_MCG_CAP);
123 return msr.lo & MCA_BANKS_MASK;
124 }
125
126 /* Clear all MCA status registers */
mca_clear_status(void)127 static inline void mca_clear_status(void)
128 {
129 const unsigned int num_banks = mca_get_bank_count();
130 const msr_t msr = {.lo = 0, .hi = 0};
131
132 for (unsigned int i = 0 ; i < num_banks ; i++)
133 wrmsr(IA32_MC_STATUS(i), msr);
134 }
135
136 /* Helpers for interpreting MC[i]_STATUS */
137
mca_valid(msr_t msr)138 static inline int mca_valid(msr_t msr)
139 {
140 return !!(msr.hi & MCA_STATUS_HI_VAL);
141 }
142
mca_over(msr_t msr)143 static inline int mca_over(msr_t msr)
144 {
145 return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);
146 }
147
mca_uc(msr_t msr)148 static inline int mca_uc(msr_t msr)
149 {
150 return !!(msr.hi & MCA_STATUS_HI_UC);
151 }
152
mca_en(msr_t msr)153 static inline int mca_en(msr_t msr)
154 {
155 return !!(msr.hi & MCA_STATUS_HI_EN);
156 }
157
mca_miscv(msr_t msr)158 static inline int mca_miscv(msr_t msr)
159 {
160 return !!(msr.hi & MCA_STATUS_HI_MISCV);
161 }
162
mca_addrv(msr_t msr)163 static inline int mca_addrv(msr_t msr)
164 {
165 return !!(msr.hi & MCA_STATUS_HI_ADDRV);
166 }
167
mca_pcc(msr_t msr)168 static inline int mca_pcc(msr_t msr)
169 {
170 return !!(msr.hi & MCA_STATUS_HI_PCC);
171 }
172
mca_idv(msr_t msr)173 static inline int mca_idv(msr_t msr)
174 {
175 return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);
176 }
177
mca_cecc(msr_t msr)178 static inline int mca_cecc(msr_t msr)
179 {
180 return !!(msr.hi & MCA_STATUS_HI_CECC);
181 }
182
mca_uecc(msr_t msr)183 static inline int mca_uecc(msr_t msr)
184 {
185 return !!(msr.hi & MCA_STATUS_HI_UECC);
186 }
187
mca_defd(msr_t msr)188 static inline int mca_defd(msr_t msr)
189 {
190 return !!(msr.hi & MCA_STATUS_HI_DEFERRED);
191 }
192
mca_poison(msr_t msr)193 static inline int mca_poison(msr_t msr)
194 {
195 return !!(msr.hi & MCA_STATUS_HI_POISON);
196 }
197
mca_sublink(msr_t msr)198 static inline int mca_sublink(msr_t msr)
199 {
200 return !!(msr.hi & MCA_STATUS_HI_SUBLINK);
201 }
202
mca_err_code(msr_t reg)203 static inline uint16_t mca_err_code(msr_t reg)
204 {
205 return reg.lo & MCA_STATUS_LO_ERRCODE_MASK;
206 }
207
mca_err_extcode(msr_t reg)208 static inline uint16_t mca_err_extcode(msr_t reg)
209 {
210 return reg.lo & MCA_STATUS_LO_ERRCODE_EXT_MASK;
211 }
212
213 /* Machine Check errors may be categorized by type, as determined by the
214 * Error Code field of MC[i]_STATUS. The definitions below can typically
215 * be found by searching the BKDG for a table called "Error Code Types".
216 */
217 /* TLB Errors 0000 0000 0001 TTLL */
218 #define MCA_ERRCODE_TLB_DETECT 0xfff0
219 #define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */
220 #define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)
221 #define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */
222 #define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)
223
224 /* Memory Errors 0000 0001 RRRR TTLL */
225 #define MCA_ERRCODE_MEM_DETECT 0xff00
226 #define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */
227 #define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)
228 #define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */
229 #define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)
230 #define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */
231 #define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)
232
233 /* Bus Errors 0000 1PPT RRRR IILL */
234 #define MCA_ERRCODE_BUS_DETECT 0xf800
235 #define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */
236 #define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)
237 #define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */
238 #define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)
239 #define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */
240 #define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)
241 #define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */
242 #define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)
243 #define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */
244 #define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)
245
246 /* Int. Unclassified Errors 0000 01UU 0000 0000 */
247 #define MCA_ERRCODE_INT_DETECT 0xfc00
248 #define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */
249 #define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)
250
251 #define MCA_BANK_LS 0 /* Load-store, including DC */
252 #define MCA_BANK_IF 1 /* Instruction Fetch, including IC */
253 #define MCA_BANK_CU 2 /* Combined Unit, including L2 */
254 /* bank 3 reserved */
255 #define MCA_BANK_NB 4 /* Northbridge, including IO link */
256 #define MCA_BANK_EX 5 /* Execution Unit */
257 #define MCA_BANK_FP 6 /* Floating Point */
258
259 enum mca_err_code_types {
260 MCA_ERRTYPE_UNKNOWN,
261 MCA_ERRTYPE_TLB,
262 MCA_ERRTYPE_MEM,
263 MCA_ERRTYPE_BUS,
264 MCA_ERRTYPE_INT
265 };
266
mca_err_type(msr_t reg)267 static inline enum mca_err_code_types mca_err_type(msr_t reg)
268 {
269 uint16_t error = mca_err_code(reg);
270 if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */
271 return MCA_ERRTYPE_BUS;
272 if (error & MCA_ERRCODE_INT_DETECT)
273 return MCA_ERRTYPE_INT;
274 if (error & MCA_ERRCODE_MEM_DETECT)
275 return MCA_ERRTYPE_MEM;
276 if (error & MCA_ERRCODE_TLB_DETECT)
277 return MCA_ERRTYPE_TLB;
278 return MCA_ERRTYPE_UNKNOWN;
279 }
280
281 /**
282 * Helper for reading a MSR
283 *
284 * @param[in] reg The MSR.
285 */
msr_read(unsigned int reg)286 static inline uint64_t msr_read(unsigned int reg)
287 {
288 msr_t msr = rdmsr(reg);
289 return msr.raw;
290 }
291
292 /**
293 * Helper for writing a MSR
294 *
295 * @param[in] reg The MSR.
296 * @param[in] value The value to be written to the MSR.
297 */
msr_write(unsigned int reg,uint64_t value)298 static inline void msr_write(unsigned int reg, uint64_t value)
299 {
300 msr_t msr = { .raw = value };
301 wrmsr(reg, msr);
302 }
303
304 /**
305 * Helper for (un)setting MSR bitmasks
306 *
307 * @param[in] reg The MSR.
308 * @param[in] unset Bitmask with ones to the bits to unset from the MSR.
309 * @param[in] set Bitmask with ones to the bits to set from the MSR.
310 */
msr_unset_and_set(unsigned int reg,uint64_t unset,uint64_t set)311 static inline void msr_unset_and_set(unsigned int reg, uint64_t unset, uint64_t set)
312 {
313 msr_t msr;
314
315 msr = rdmsr(reg);
316 msr.raw &= ~unset;
317 msr.raw |= set;
318 wrmsr(reg, msr);
319 }
320
321 /**
322 * Helper for setting MSR bitmasks
323 *
324 * @param[in] reg The MSR.
325 * @param[in] set Bitmask with ones to the bits to set from the MSR.
326 */
msr_set(unsigned int reg,uint64_t set)327 static inline void msr_set(unsigned int reg, uint64_t set)
328 {
329 msr_unset_and_set(reg, 0, set);
330 }
331
332 /**
333 * Helper for unsetting MSR bitmasks
334 *
335 * @param[in] reg The MSR.
336 * @param[in] unset Bitmask with ones to the bits to unset from the MSR.
337 */
msr_unset(unsigned int reg,uint64_t unset)338 static inline void msr_unset(unsigned int reg, uint64_t unset)
339 {
340 msr_unset_and_set(reg, unset, 0);
341 }
342
343 #endif /* __ASSEMBLER__ */
344 #endif /* CPU_X86_MSR_H */
345