1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef PEI_DATA_H 4 #define PEI_DATA_H 5 6 #include <stdint.h> 7 8 typedef void (*tx_byte_func)(unsigned char byte); 9 #define PEI_VERSION 15 10 11 #define PEI_USB_OC_PIN_SKIP 8 12 13 enum pei_usb2_port_location { 14 PEI_USB_PORT_BACK_PANEL = 0, 15 PEI_USB_PORT_FRONT_PANEL, 16 PEI_USB_PORT_DOCK, 17 PEI_USB_PORT_MINI_PCIE, 18 PEI_USB_PORT_FLEX, 19 PEI_USB_PORT_INTERNAL, 20 PEI_USB_PORT_SKIP 21 }; 22 23 /* Usb Port Length: 24 * [16:4] = length in inches in octal format 25 * [3:0] = decimal point 26 */ 27 struct pei_usb2_port_setting { 28 uint16_t length; 29 uint8_t enable; 30 uint8_t over_current_pin; 31 uint8_t location; 32 } __packed; 33 34 struct pei_usb3_port_setting { 35 uint8_t enable; 36 uint8_t over_current_pin; 37 } __packed; 38 39 struct pei_data 40 { 41 uint32_t pei_version; 42 uint32_t mchbar; 43 uint32_t dmibar; 44 uint32_t epbar; 45 uint32_t pciexbar; 46 uint16_t smbusbar; 47 /* Unused by HSW MRC, but changes to the memory layout of this struct break the ABI */ 48 uint32_t _unused_wdbbar; 49 uint32_t _unused_wdbsize; 50 uint32_t hpet_address; 51 uint32_t rcba; 52 uint32_t pmbase; 53 uint32_t gpiobase; 54 uint32_t temp_mmio_base; 55 /* System type: 0 => Mobile, 1 => Desktop/Server, 5 => ULT, Others => Reserved */ 56 uint32_t system_type; 57 uint32_t tseg_size; 58 uint8_t spd_addresses[4]; 59 int boot_mode; 60 int ec_present; 61 int gbe_enable; 62 // 0 = leave channel enabled 63 // 1 = disable dimm 0 on channel 64 // 2 = disable dimm 1 on channel 65 // 3 = disable dimm 0+1 on channel 66 int dimm_channel0_disabled; 67 int dimm_channel1_disabled; 68 /* Enable 2x Refresh Mode */ 69 int ddr_refresh_2x; 70 int dq_pins_interleaved; 71 /* Data read from flash and passed into MRC */ 72 unsigned char *mrc_input; 73 unsigned int mrc_input_len; 74 /* Data from MRC that should be saved to flash */ 75 unsigned char *mrc_output; 76 unsigned int mrc_output_len; 77 /* Max frequency to run DDR3 at. Can be one of four values: 800, 1067, 1333, 1600 */ 78 uint32_t max_ddr3_freq; 79 /* Route all USB ports to XHCI controller in resume path */ 80 int usb_xhci_on_resume; 81 struct pei_usb2_port_setting usb2_ports[16]; 82 struct pei_usb3_port_setting usb3_ports[16]; 83 uint8_t spd_data[4][SPD_SIZE_MAX_DDR3]; 84 tx_byte_func tx_byte; 85 } __packed; 86 87 #endif 88