1 /* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988-2013 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 Under Section 7 of GPL version 3, you are granted additional 17 permissions described in the GCC Runtime Library Exception, version 18 3.1, as published by the Free Software Foundation. 19 20 You should have received a copy of the GNU General Public License and 21 a copy of the GCC Runtime Library Exception along with this program; 22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23 <http://www.gnu.org/licenses/>. */ 24 25 /* The purpose of this file is to define the characteristics of the i386, 26 independent of assembler syntax or operating system. 27 28 Three other files build on this one to describe a specific assembler syntax: 29 bsd386.h, att386.h, and sun386.h. 30 31 The actual tm.h file for a particular system should include 32 this file, and then the file for the appropriate assembler syntax. 33 34 Many macros that specify assembler syntax are omitted entirely from 35 this file because they really belong in the files for particular 36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 38 that start with ASM_ or end in ASM_OP. */ 39 40 /* Redefines for option macros. */ 41 42 #define TARGET_64BIT TARGET_ISA_64BIT 43 #define TARGET_MMX TARGET_ISA_MMX 44 #define TARGET_3DNOW TARGET_ISA_3DNOW 45 #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A 46 #define TARGET_SSE TARGET_ISA_SSE 47 #define TARGET_SSE2 TARGET_ISA_SSE2 48 #define TARGET_SSE3 TARGET_ISA_SSE3 49 #define TARGET_SSSE3 TARGET_ISA_SSSE3 50 #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 51 #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 52 #define TARGET_AVX TARGET_ISA_AVX 53 #define TARGET_AVX2 TARGET_ISA_AVX2 54 #define TARGET_FMA TARGET_ISA_FMA 55 #define TARGET_SSE4A TARGET_ISA_SSE4A 56 #define TARGET_FMA4 TARGET_ISA_FMA4 57 #define TARGET_XOP TARGET_ISA_XOP 58 #define TARGET_LWP TARGET_ISA_LWP 59 #define TARGET_ROUND TARGET_ISA_ROUND 60 #define TARGET_ABM TARGET_ISA_ABM 61 #define TARGET_BMI TARGET_ISA_BMI 62 #define TARGET_BMI2 TARGET_ISA_BMI2 63 #define TARGET_LZCNT TARGET_ISA_LZCNT 64 #define TARGET_TBM TARGET_ISA_TBM 65 #define TARGET_POPCNT TARGET_ISA_POPCNT 66 #define TARGET_SAHF TARGET_ISA_SAHF 67 #define TARGET_MOVBE TARGET_ISA_MOVBE 68 #define TARGET_CRC32 TARGET_ISA_CRC32 69 #define TARGET_AES TARGET_ISA_AES 70 #define TARGET_PCLMUL TARGET_ISA_PCLMUL 71 #define TARGET_CMPXCHG16B TARGET_ISA_CX16 72 #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE 73 #define TARGET_RDRND TARGET_ISA_RDRND 74 #define TARGET_F16C TARGET_ISA_F16C 75 #define TARGET_RTM TARGET_ISA_RTM 76 #define TARGET_HLE TARGET_ISA_HLE 77 #define TARGET_RDSEED TARGET_ISA_RDSEED 78 #define TARGET_PRFCHW TARGET_ISA_PRFCHW 79 #define TARGET_ADX TARGET_ISA_ADX 80 #define TARGET_FXSR TARGET_ISA_FXSR 81 #define TARGET_XSAVE TARGET_ISA_XSAVE 82 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT 83 84 #define TARGET_LP64 TARGET_ABI_64 85 #define TARGET_X32 TARGET_ABI_X32 86 87 /* SSE4.1 defines round instructions */ 88 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 89 #define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) 90 91 #include "config/vxworks-dummy.h" 92 93 #include "config/i386/i386-opts.h" 94 95 #define MAX_STRINGOP_ALGS 4 96 97 /* Specify what algorithm to use for stringops on known size. 98 When size is unknown, the UNKNOWN_SIZE alg is used. When size is 99 known at compile time or estimated via feedback, the SIZE array 100 is walked in order until MAX is greater then the estimate (or -1 101 means infinity). Corresponding ALG is used then. 102 When NOALIGN is true the code guaranting the alignment of the memory 103 block is skipped. 104 105 For example initializer: 106 {{256, loop}, {-1, rep_prefix_4_byte}} 107 will use loop for blocks smaller or equal to 256 bytes, rep prefix will 108 be used otherwise. */ 109 struct stringop_algs 110 { 111 const enum stringop_alg unknown_size; 112 const struct stringop_strategy { 113 const int max; 114 const enum stringop_alg alg; 115 int noalign; 116 } size [MAX_STRINGOP_ALGS]; 117 }; 118 119 /* Define the specific costs for a given cpu */ 120 121 struct processor_costs { 122 const int add; /* cost of an add instruction */ 123 const int lea; /* cost of a lea instruction */ 124 const int shift_var; /* variable shift costs */ 125 const int shift_const; /* constant shift costs */ 126 const int mult_init[5]; /* cost of starting a multiply 127 in QImode, HImode, SImode, DImode, TImode*/ 128 const int mult_bit; /* cost of multiply per each bit set */ 129 const int divide[5]; /* cost of a divide/mod 130 in QImode, HImode, SImode, DImode, TImode*/ 131 int movsx; /* The cost of movsx operation. */ 132 int movzx; /* The cost of movzx operation. */ 133 const int large_insn; /* insns larger than this cost more */ 134 const int move_ratio; /* The threshold of number of scalar 135 memory-to-memory move insns. */ 136 const int movzbl_load; /* cost of loading using movzbl */ 137 const int int_load[3]; /* cost of loading integer registers 138 in QImode, HImode and SImode relative 139 to reg-reg move (2). */ 140 const int int_store[3]; /* cost of storing integer register 141 in QImode, HImode and SImode */ 142 const int fp_move; /* cost of reg,reg fld/fst */ 143 const int fp_load[3]; /* cost of loading FP register 144 in SFmode, DFmode and XFmode */ 145 const int fp_store[3]; /* cost of storing FP register 146 in SFmode, DFmode and XFmode */ 147 const int mmx_move; /* cost of moving MMX register. */ 148 const int mmx_load[2]; /* cost of loading MMX register 149 in SImode and DImode */ 150 const int mmx_store[2]; /* cost of storing MMX register 151 in SImode and DImode */ 152 const int sse_move; /* cost of moving SSE register. */ 153 const int sse_load[3]; /* cost of loading SSE register 154 in SImode, DImode and TImode*/ 155 const int sse_store[3]; /* cost of storing SSE register 156 in SImode, DImode and TImode*/ 157 const int mmxsse_to_integer; /* cost of moving mmxsse register to 158 integer and vice versa. */ 159 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 160 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 161 const int prefetch_block; /* bytes moved to cache for prefetch. */ 162 const int simultaneous_prefetches; /* number of parallel prefetch 163 operations. */ 164 const int branch_cost; /* Default value for BRANCH_COST. */ 165 const int fadd; /* cost of FADD and FSUB instructions. */ 166 const int fmul; /* cost of FMUL instruction. */ 167 const int fdiv; /* cost of FDIV instruction. */ 168 const int fabs; /* cost of FABS instruction. */ 169 const int fchs; /* cost of FCHS instruction. */ 170 const int fsqrt; /* cost of FSQRT instruction. */ 171 /* Specify what algorithm 172 to use for stringops on unknown size. */ 173 struct stringop_algs memcpy[2], memset[2]; 174 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding 175 load and store. */ 176 const int scalar_load_cost; /* Cost of scalar load. */ 177 const int scalar_store_cost; /* Cost of scalar store. */ 178 const int vec_stmt_cost; /* Cost of any vector operation, excluding 179 load, store, vector-to-scalar and 180 scalar-to-vector operation. */ 181 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ 182 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ 183 const int vec_align_load_cost; /* Cost of aligned vector load. */ 184 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 185 const int vec_store_cost; /* Cost of vector store. */ 186 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 187 cost model. */ 188 const int cond_not_taken_branch_cost;/* Cost of not taken branch for 189 vectorizer cost model. */ 190 }; 191 192 extern const struct processor_costs *ix86_cost; 193 extern const struct processor_costs ix86_size_cost; 194 195 #define ix86_cur_cost() \ 196 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 197 198 /* Macros used in the machine description to test the flags. */ 199 200 /* configure can arrange to change it. */ 201 202 #ifndef TARGET_CPU_DEFAULT 203 #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC32 204 #endif 205 206 #ifndef TARGET_FPMATH_DEFAULT 207 #define TARGET_FPMATH_DEFAULT \ 208 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 209 #endif 210 211 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 212 213 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 214 compile-time constant. */ 215 #ifdef IN_LIBGCC2 216 #undef TARGET_64BIT 217 #ifdef __x86_64__ 218 #define TARGET_64BIT 1 219 #else 220 #define TARGET_64BIT 0 221 #endif 222 #else 223 #ifndef TARGET_BI_ARCH 224 #undef TARGET_64BIT 225 #if TARGET_64BIT_DEFAULT 226 #define TARGET_64BIT 1 227 #else 228 #define TARGET_64BIT 0 229 #endif 230 #endif 231 #endif 232 233 #define HAS_LONG_COND_BRANCH 1 234 #define HAS_LONG_UNCOND_BRANCH 1 235 236 #define TARGET_386 (ix86_tune == PROCESSOR_I386) 237 #define TARGET_486 (ix86_tune == PROCESSOR_I486) 238 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 239 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 240 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 241 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 242 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 243 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 244 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 245 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 246 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 247 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 248 #define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7) 249 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) 250 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 251 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 252 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 253 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 254 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 255 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 256 #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) 257 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) 258 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) 259 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) 260 261 /* Feature tests against the various tunings. */ 262 enum ix86_tune_indices { 263 X86_TUNE_USE_LEAVE, 264 X86_TUNE_PUSH_MEMORY, 265 X86_TUNE_ZERO_EXTEND_WITH_AND, 266 X86_TUNE_UNROLL_STRLEN, 267 X86_TUNE_BRANCH_PREDICTION_HINTS, 268 X86_TUNE_DOUBLE_WITH_ADD, 269 X86_TUNE_USE_SAHF, 270 X86_TUNE_MOVX, 271 X86_TUNE_PARTIAL_REG_STALL, 272 X86_TUNE_PARTIAL_FLAG_REG_STALL, 273 X86_TUNE_LCP_STALL, 274 X86_TUNE_USE_HIMODE_FIOP, 275 X86_TUNE_USE_SIMODE_FIOP, 276 X86_TUNE_USE_MOV0, 277 X86_TUNE_USE_CLTD, 278 X86_TUNE_USE_XCHGB, 279 X86_TUNE_SPLIT_LONG_MOVES, 280 X86_TUNE_READ_MODIFY_WRITE, 281 X86_TUNE_READ_MODIFY, 282 X86_TUNE_PROMOTE_QIMODE, 283 X86_TUNE_FAST_PREFIX, 284 X86_TUNE_SINGLE_STRINGOP, 285 X86_TUNE_QIMODE_MATH, 286 X86_TUNE_HIMODE_MATH, 287 X86_TUNE_PROMOTE_QI_REGS, 288 X86_TUNE_PROMOTE_HI_REGS, 289 X86_TUNE_SINGLE_POP, 290 X86_TUNE_DOUBLE_POP, 291 X86_TUNE_SINGLE_PUSH, 292 X86_TUNE_DOUBLE_PUSH, 293 X86_TUNE_INTEGER_DFMODE_MOVES, 294 X86_TUNE_PARTIAL_REG_DEPENDENCY, 295 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, 296 X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, 297 X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, 298 X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, 299 X86_TUNE_SSE_SPLIT_REGS, 300 X86_TUNE_SSE_TYPELESS_STORES, 301 X86_TUNE_SSE_LOAD0_BY_PXOR, 302 X86_TUNE_MEMORY_MISMATCH_STALL, 303 X86_TUNE_PROLOGUE_USING_MOVE, 304 X86_TUNE_EPILOGUE_USING_MOVE, 305 X86_TUNE_SHIFT1, 306 X86_TUNE_USE_FFREEP, 307 X86_TUNE_INTER_UNIT_MOVES, 308 X86_TUNE_INTER_UNIT_CONVERSIONS, 309 X86_TUNE_FOUR_JUMP_LIMIT, 310 X86_TUNE_SCHEDULE, 311 X86_TUNE_USE_BT, 312 X86_TUNE_USE_INCDEC, 313 X86_TUNE_PAD_RETURNS, 314 X86_TUNE_PAD_SHORT_FUNCTION, 315 X86_TUNE_EXT_80387_CONSTANTS, 316 X86_TUNE_AVOID_VECTOR_DECODE, 317 X86_TUNE_PROMOTE_HIMODE_IMUL, 318 X86_TUNE_SLOW_IMUL_IMM32_MEM, 319 X86_TUNE_SLOW_IMUL_IMM8, 320 X86_TUNE_MOVE_M1_VIA_OR, 321 X86_TUNE_NOT_UNPAIRABLE, 322 X86_TUNE_NOT_VECTORMODE, 323 X86_TUNE_USE_VECTOR_FP_CONVERTS, 324 X86_TUNE_USE_VECTOR_CONVERTS, 325 X86_TUNE_FUSE_CMP_AND_BRANCH, 326 X86_TUNE_OPT_AGU, 327 X86_TUNE_VECTORIZE_DOUBLE, 328 X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, 329 X86_TUNE_AVX128_OPTIMAL, 330 X86_TUNE_REASSOC_INT_TO_PARALLEL, 331 X86_TUNE_REASSOC_FP_TO_PARALLEL, 332 X86_TUNE_GENERAL_REGS_SSE_SPILL, 333 X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, 334 335 X86_TUNE_LAST 336 }; 337 338 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 339 340 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 341 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 342 #define TARGET_ZERO_EXTEND_WITH_AND \ 343 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 344 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 345 #define TARGET_BRANCH_PREDICTION_HINTS \ 346 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 347 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 348 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 349 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 350 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 351 #define TARGET_PARTIAL_FLAG_REG_STALL \ 352 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 353 #define TARGET_LCP_STALL \ 354 ix86_tune_features[X86_TUNE_LCP_STALL] 355 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 356 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 357 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 358 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 359 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 360 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 361 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 362 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 363 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 364 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 365 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 366 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 367 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 368 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 369 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 370 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] 371 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] 372 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] 373 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] 374 #define TARGET_INTEGER_DFMODE_MOVES \ 375 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 376 #define TARGET_PARTIAL_REG_DEPENDENCY \ 377 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 378 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 379 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 380 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 381 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] 382 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ 383 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] 384 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ 385 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] 386 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 387 #define TARGET_SSE_TYPELESS_STORES \ 388 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 389 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 390 #define TARGET_MEMORY_MISMATCH_STALL \ 391 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 392 #define TARGET_PROLOGUE_USING_MOVE \ 393 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 394 #define TARGET_EPILOGUE_USING_MOVE \ 395 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 396 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 397 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 398 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] 399 #define TARGET_INTER_UNIT_CONVERSIONS\ 400 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 401 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 402 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 403 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 404 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 405 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 406 #define TARGET_PAD_SHORT_FUNCTION \ 407 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] 408 #define TARGET_EXT_80387_CONSTANTS \ 409 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 410 #define TARGET_AVOID_VECTOR_DECODE \ 411 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 412 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 413 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 414 #define TARGET_SLOW_IMUL_IMM32_MEM \ 415 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 416 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 417 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 418 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 419 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 420 #define TARGET_USE_VECTOR_FP_CONVERTS \ 421 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 422 #define TARGET_USE_VECTOR_CONVERTS \ 423 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 424 #define TARGET_FUSE_CMP_AND_BRANCH \ 425 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] 426 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 427 #define TARGET_VECTORIZE_DOUBLE \ 428 ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE] 429 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ 430 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] 431 #define TARGET_AVX128_OPTIMAL \ 432 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] 433 #define TARGET_REASSOC_INT_TO_PARALLEL \ 434 ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL] 435 #define TARGET_REASSOC_FP_TO_PARALLEL \ 436 ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL] 437 #define TARGET_GENERAL_REGS_SSE_SPILL \ 438 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] 439 #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ 440 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] 441 442 /* Feature tests against the various architecture variations. */ 443 enum ix86_arch_indices { 444 X86_ARCH_CMOV, 445 X86_ARCH_CMPXCHG, 446 X86_ARCH_CMPXCHG8B, 447 X86_ARCH_XADD, 448 X86_ARCH_BSWAP, 449 450 X86_ARCH_LAST 451 }; 452 453 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 454 455 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 456 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 457 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 458 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 459 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 460 461 /* For sane SSE instruction set generation we need fcomi instruction. 462 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic 463 expands to a sequence that includes conditional move. */ 464 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) 465 466 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 467 468 extern unsigned char x86_prefetch_sse; 469 #define TARGET_PREFETCH_SSE x86_prefetch_sse 470 471 #define ASSEMBLER_DIALECT (ix86_asm_dialect) 472 473 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 474 #define TARGET_MIX_SSE_I387 \ 475 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 476 477 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 478 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 479 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 480 #define TARGET_SUN_TLS 0 481 482 #ifndef TARGET_64BIT_DEFAULT 483 #define TARGET_64BIT_DEFAULT 0 484 #endif 485 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 486 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 487 #endif 488 489 /* Fence to use after loop using storent. */ 490 491 extern tree x86_mfence; 492 #define FENCE_FOLLOWING_MOVNT x86_mfence 493 494 /* Once GDB has been enhanced to deal with functions without frame 495 pointers, we can change this to allow for elimination of 496 the frame pointer in leaf functions. */ 497 #define TARGET_DEFAULT 0 498 499 /* Extra bits to force. */ 500 #define TARGET_SUBTARGET_DEFAULT 0 501 #define TARGET_SUBTARGET_ISA_DEFAULT 0 502 503 /* Extra bits to force on w/ 32-bit mode. */ 504 #define TARGET_SUBTARGET32_DEFAULT 0 505 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 506 507 /* Extra bits to force on w/ 64-bit mode. */ 508 #define TARGET_SUBTARGET64_DEFAULT 0 509 #define TARGET_SUBTARGET64_ISA_DEFAULT 0 510 511 /* Replace MACH-O, ifdefs by in-line tests, where possible. 512 (a) Macros defined in config/i386/darwin.h */ 513 #define TARGET_MACHO 0 514 #define TARGET_MACHO_BRANCH_ISLANDS 0 515 #define MACHOPIC_ATT_STUB 0 516 /* (b) Macros defined in config/darwin.h */ 517 #define MACHO_DYNAMIC_NO_PIC_P 0 518 #define MACHOPIC_INDIRECT 0 519 #define MACHOPIC_PURE 0 520 521 /* For the RDOS */ 522 #define TARGET_RDOS 0 523 524 /* For the Windows 64-bit ABI. */ 525 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 526 527 /* For the Windows 32-bit ABI. */ 528 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 529 530 /* This is re-defined by cygming.h. */ 531 #define TARGET_SEH 0 532 533 /* The default abi used by target. */ 534 #define DEFAULT_ABI SYSV_ABI 535 536 /* Subtargets may reset this to 1 in order to enable 96-bit long double 537 with the rounding mode forced to 53 bits. */ 538 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 539 540 /* -march=native handling only makes sense with compiler running on 541 an x86 or x86_64 chip. If changing this condition, also change 542 the condition in driver-i386.c. */ 543 #if defined(__i386__) || defined(__x86_64__) 544 /* In driver-i386.c. */ 545 extern const char *host_detect_local_cpu (int argc, const char **argv); 546 #define EXTRA_SPEC_FUNCTIONS \ 547 { "local_cpu_detect", host_detect_local_cpu }, 548 #define HAVE_LOCAL_CPU_DETECT 549 #endif 550 551 #if TARGET_64BIT_DEFAULT 552 #define OPT_ARCH64 "!m32" 553 #define OPT_ARCH32 "m32" 554 #else 555 #define OPT_ARCH64 "m64|mx32" 556 #define OPT_ARCH32 "m64|mx32:;" 557 #endif 558 559 /* Support for configure-time defaults of some command line options. 560 The order here is important so that -march doesn't squash the 561 tune or cpu values. */ 562 #define OPTION_DEFAULT_SPECS \ 563 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 564 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 565 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 566 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 567 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 568 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 569 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 570 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 571 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 572 573 /* Specs for the compiler proper */ 574 575 #ifndef CC1_CPU_SPEC 576 #define CC1_CPU_SPEC_1 "" 577 578 #ifndef HAVE_LOCAL_CPU_DETECT 579 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 580 #else 581 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 582 "%{march=native:%>march=native %:local_cpu_detect(arch) \ 583 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ 584 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" 585 #endif 586 #endif 587 588 /* Target CPU builtins. */ 589 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 590 591 /* Target Pragmas. */ 592 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 593 594 #ifndef CC1_SPEC 595 #define CC1_SPEC "%(cc1_cpu) " 596 #endif 597 598 /* This macro defines names of additional specifications to put in the 599 specs that can be used in various specifications like CC1_SPEC. Its 600 definition is an initializer with a subgrouping for each command option. 601 602 Each subgrouping contains a string constant, that defines the 603 specification name, and a string constant that used by the GCC driver 604 program. 605 606 Do not define this macro if it does not need to do anything. */ 607 608 #ifndef SUBTARGET_EXTRA_SPECS 609 #define SUBTARGET_EXTRA_SPECS 610 #endif 611 612 #define EXTRA_SPECS \ 613 { "cc1_cpu", CC1_CPU_SPEC }, \ 614 SUBTARGET_EXTRA_SPECS 615 616 617 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the 618 FPU, assume that the fpcw is set to extended precision; when using 619 only SSE, rounding is correct; when using both SSE and the FPU, 620 the rounding precision is indeterminate, since either may be chosen 621 apparently at random. */ 622 #define TARGET_FLT_EVAL_METHOD \ 623 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 624 625 /* Whether to allow x87 floating-point arithmetic on MODE (one of 626 SFmode, DFmode and XFmode) in the current excess precision 627 configuration. */ 628 #define X87_ENABLE_ARITH(MODE) \ 629 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) 630 631 /* Likewise, whether to allow direct conversions from integer mode 632 IMODE (HImode, SImode or DImode) to MODE. */ 633 #define X87_ENABLE_FLOAT(MODE, IMODE) \ 634 (flag_excess_precision == EXCESS_PRECISION_FAST \ 635 || (MODE) == XFmode \ 636 || ((MODE) == DFmode && (IMODE) == SImode) \ 637 || (IMODE) == HImode) 638 639 /* target machine storage layout */ 640 641 #define SHORT_TYPE_SIZE 16 642 #define INT_TYPE_SIZE 32 643 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 644 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 645 #define LONG_LONG_TYPE_SIZE 64 646 #define FLOAT_TYPE_SIZE 32 647 #define DOUBLE_TYPE_SIZE 64 648 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 80) 649 650 /* Define this to set long double type size to use in libgcc2.c, which can 651 not depend on target_flags. */ 652 #ifdef __LONG_DOUBLE_64__ 653 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 654 #else 655 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 656 #endif 657 658 #define WIDEST_HARDWARE_FP_SIZE 80 659 660 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 661 #define MAX_BITS_PER_WORD 64 662 #else 663 #define MAX_BITS_PER_WORD 32 664 #endif 665 666 /* Define this if most significant byte of a word is the lowest numbered. */ 667 /* That is true on the 80386. */ 668 669 #define BITS_BIG_ENDIAN 0 670 671 /* Define this if most significant byte of a word is the lowest numbered. */ 672 /* That is not true on the 80386. */ 673 #define BYTES_BIG_ENDIAN 0 674 675 /* Define this if most significant word of a multiword number is the lowest 676 numbered. */ 677 /* Not true for 80386 */ 678 #define WORDS_BIG_ENDIAN 0 679 680 /* Width of a word, in units (bytes). */ 681 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 682 683 #ifndef IN_LIBGCC2 684 #define MIN_UNITS_PER_WORD 4 685 #endif 686 687 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 688 #define PARM_BOUNDARY BITS_PER_WORD 689 690 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 691 #define STACK_BOUNDARY \ 692 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) 693 694 /* Stack boundary of the main function guaranteed by OS. */ 695 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 696 697 /* Minimum stack boundary. */ 698 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32) 699 700 /* Boundary (in *bits*) on which the stack pointer prefers to be 701 aligned; the compiler cannot rely on having this alignment. */ 702 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 703 704 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 705 both 32bit and 64bit, to support codes that need 128 bit stack 706 alignment for SSE instructions, but can't realign the stack. */ 707 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 708 709 /* 1 if -mstackrealign should be turned on by default. It will 710 generate an alternate prologue and epilogue that realigns the 711 runtime stack if nessary. This supports mixing codes that keep a 712 4-byte aligned stack, as specified by i386 psABI, with codes that 713 need a 16-byte aligned stack, as required by SSE instructions. */ 714 #define STACK_REALIGN_DEFAULT 0 715 716 /* Boundary (in *bits*) on which the incoming stack is aligned. */ 717 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 718 719 /* According to Windows x64 software convention, the maximum stack allocatable 720 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of 721 instructions allowed to adjust the stack pointer in the epilog, forcing the 722 use of frame pointer for frames larger than 2 GB. This theorical limit 723 is reduced by 256, an over-estimated upper bound for the stack use by the 724 prologue. 725 We define only one threshold for both the prolog and the epilog. When the 726 frame size is larger than this threshold, we allocate the area to save SSE 727 regs, then save them, and then allocate the remaining. There is no SEH 728 unwind info for this later allocation. */ 729 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) 730 731 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 732 mandatory for the 64-bit ABI, and may or may not be true for other 733 operating systems. */ 734 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 735 736 /* Minimum allocation boundary for the code of a function. */ 737 #define FUNCTION_BOUNDARY 8 738 739 /* C++ stores the virtual bit in the lowest bit of function pointers. */ 740 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 741 742 /* Minimum size in bits of the largest boundary to which any 743 and all fundamental data types supported by the hardware 744 might need to be aligned. No data type wants to be aligned 745 rounder than this. 746 747 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 748 and Pentium Pro XFmode values at 128 bit boundaries. */ 749 750 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256 : 128) 751 752 /* Maximum stack alignment. */ 753 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 754 755 /* Alignment value for attribute ((aligned)). It is a constant since 756 it is the part of the ABI. We shouldn't change it with -mavx. */ 757 #define ATTRIBUTE_ALIGNED_VALUE 128 758 759 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 760 #define ALIGN_MODE_128(MODE) \ 761 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 762 763 /* The published ABIs say that doubles should be aligned on word 764 boundaries, so lower the alignment for structure fields unless 765 -malign-double is set. */ 766 767 /* ??? Blah -- this macro is used directly by libobjc. Since it 768 supports no vector modes, cut out the complexity and fall back 769 on BIGGEST_FIELD_ALIGNMENT. */ 770 #ifdef IN_TARGET_LIBS 771 #ifdef __x86_64__ 772 #define BIGGEST_FIELD_ALIGNMENT 128 773 #else 774 #define BIGGEST_FIELD_ALIGNMENT 32 775 #endif 776 #else 777 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 778 x86_field_alignment (FIELD, COMPUTED) 779 #endif 780 781 /* If defined, a C expression to compute the alignment given to a 782 constant that is being placed in memory. EXP is the constant 783 and ALIGN is the alignment that the object would ordinarily have. 784 The value of this macro is used instead of that alignment to align 785 the object. 786 787 If this macro is not defined, then ALIGN is used. 788 789 The typical use of this macro is to increase alignment for string 790 constants to be word aligned so that `strcpy' calls that copy 791 constants can be done inline. */ 792 793 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 794 795 /* If defined, a C expression to compute the alignment for a static 796 variable. TYPE is the data type, and ALIGN is the alignment that 797 the object would ordinarily have. The value of this macro is used 798 instead of that alignment to align the object. 799 800 If this macro is not defined, then ALIGN is used. 801 802 One use of this macro is to increase alignment of medium-size 803 data to make it all fit in fewer cache lines. Another is to 804 cause character arrays to be word-aligned so that `strcpy' calls 805 that copy constants to character arrays can be done inline. */ 806 807 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 808 809 /* If defined, a C expression to compute the alignment for a local 810 variable. TYPE is the data type, and ALIGN is the alignment that 811 the object would ordinarily have. The value of this macro is used 812 instead of that alignment to align the object. 813 814 If this macro is not defined, then ALIGN is used. 815 816 One use of this macro is to increase alignment of medium-size 817 data to make it all fit in fewer cache lines. */ 818 819 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 820 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 821 822 /* If defined, a C expression to compute the alignment for stack slot. 823 TYPE is the data type, MODE is the widest mode available, and ALIGN 824 is the alignment that the slot would ordinarily have. The value of 825 this macro is used instead of that alignment to align the slot. 826 827 If this macro is not defined, then ALIGN is used when TYPE is NULL, 828 Otherwise, LOCAL_ALIGNMENT will be used. 829 830 One use of this macro is to set alignment of stack slot to the 831 maximum alignment of all possible modes which the slot may have. */ 832 833 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 834 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 835 836 /* If defined, a C expression to compute the alignment for a local 837 variable DECL. 838 839 If this macro is not defined, then 840 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 841 842 One use of this macro is to increase alignment of medium-size 843 data to make it all fit in fewer cache lines. */ 844 845 #define LOCAL_DECL_ALIGNMENT(DECL) \ 846 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 847 848 /* If defined, a C expression to compute the minimum required alignment 849 for dynamic stack realignment purposes for EXP (a TYPE or DECL), 850 MODE, assuming normal alignment ALIGN. 851 852 If this macro is not defined, then (ALIGN) will be used. */ 853 854 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 855 ix86_minimum_alignment (EXP, MODE, ALIGN) 856 857 858 /* Set this nonzero if move instructions will actually fail to work 859 when given unaligned data. */ 860 #define STRICT_ALIGNMENT 0 861 862 /* If bit field type is int, don't let it cross an int, 863 and give entire struct the alignment of an int. */ 864 /* Required on the 386 since it doesn't have bit-field insns. */ 865 #define PCC_BITFIELD_TYPE_MATTERS 1 866 867 /* Standard register usage. */ 868 869 /* This processor has special stack-like registers. See reg-stack.c 870 for details. */ 871 872 #define STACK_REGS 873 874 #define IS_STACK_MODE(MODE) \ 875 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \ 876 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ 877 || (MODE) == XFmode) 878 879 /* Number of actual hardware registers. 880 The hardware registers are assigned numbers for the compiler 881 from 0 to just below FIRST_PSEUDO_REGISTER. 882 All registers that the compiler knows about must be given numbers, 883 even those that are not normally considered general registers. 884 885 In the 80386 we give the 8 general purpose registers the numbers 0-7. 886 We number the floating point registers 8-15. 887 Note that registers 0-7 can be accessed as a short or int, 888 while only 0-3 may be used with byte `mov' instructions. 889 890 Reg 16 does not correspond to any hardware register, but instead 891 appears in the RTL as an argument pointer prior to reload, and is 892 eliminated during reloading in favor of either the stack or frame 893 pointer. */ 894 895 #define FIRST_PSEUDO_REGISTER 53 896 897 /* Number of hardware registers that go into the DWARF-2 unwind info. 898 If not defined, equals FIRST_PSEUDO_REGISTER. */ 899 900 #define DWARF_FRAME_REGISTERS 17 901 902 /* 1 for registers that have pervasive standard uses 903 and are not available for the register allocator. 904 On the 80386, the stack pointer is such, as is the arg pointer. 905 906 REX registers are disabled for 32bit targets in 907 TARGET_CONDITIONAL_REGISTER_USAGE. */ 908 909 #define FIXED_REGISTERS \ 910 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 911 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 912 /*arg,flags,fpsr,fpcr,frame*/ \ 913 1, 1, 1, 1, 1, \ 914 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 915 0, 0, 0, 0, 0, 0, 0, 0, \ 916 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 917 0, 0, 0, 0, 0, 0, 0, 0, \ 918 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 919 0, 0, 0, 0, 0, 0, 0, 0, \ 920 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 921 0, 0, 0, 0, 0, 0, 0, 0 } 922 923 /* 1 for registers not available across function calls. 924 These must include the FIXED_REGISTERS and also any 925 registers that can be used without being saved. 926 The latter must include the registers where values are returned 927 and the register where structure-value addresses are passed. 928 Aside from that, you can include as many other registers as you like. 929 930 Value is set to 1 if the register is call used unconditionally. 931 Bit one is set if the register is call used on TARGET_32BIT ABI. 932 Bit two is set if the register is call used on TARGET_64BIT ABI. 933 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. 934 935 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 936 937 #define CALL_USED_REGISTERS \ 938 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 939 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 940 /*arg,flags,fpsr,fpcr,frame*/ \ 941 1, 1, 1, 1, 1, \ 942 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 943 1, 1, 1, 1, 1, 1, 6, 6, \ 944 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 945 1, 1, 1, 1, 1, 1, 1, 1, \ 946 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 947 1, 1, 1, 1, 2, 2, 2, 2, \ 948 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 949 6, 6, 6, 6, 6, 6, 6, 6 } 950 951 /* Order in which to allocate registers. Each register must be 952 listed once, even those in FIXED_REGISTERS. List frame pointer 953 late and fixed registers last. Note that, in general, we prefer 954 registers listed in CALL_USED_REGISTERS, keeping the others 955 available for storage of persistent values. 956 957 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 958 so this is just empty initializer for array. */ 959 960 #define REG_ALLOC_ORDER \ 961 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 962 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 963 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 964 48, 49, 50, 51, 52 } 965 966 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 967 to be rearranged based on a particular function. When using sse math, 968 we want to allocate SSE before x87 registers and vice versa. */ 969 970 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () 971 972 973 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 974 975 /* Return number of consecutive hard regs needed starting at reg REGNO 976 to hold something of mode MODE. 977 This is ordinarily the length in words of a value of mode MODE 978 but can be less for certain modes in special long registers. 979 980 Actually there are no two word move instructions for consecutive 981 registers. And only registers 0-3 may have mov byte instructions 982 applied to them. */ 983 984 #define HARD_REGNO_NREGS(REGNO, MODE) \ 985 (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 986 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 987 : ((MODE) == XFmode \ 988 ? (TARGET_64BIT ? 2 : 3) \ 989 : (MODE) == XCmode \ 990 ? (TARGET_64BIT ? 4 : 6) \ 991 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 992 993 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 994 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 995 ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 996 ? 0 \ 997 : ((MODE) == XFmode || (MODE) == XCmode)) \ 998 : 0) 999 1000 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1001 1002 #define VALID_AVX256_REG_MODE(MODE) \ 1003 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1004 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ 1005 || (MODE) == V4DFmode) 1006 1007 #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ 1008 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) 1009 1010 #define VALID_SSE2_REG_MODE(MODE) \ 1011 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1012 || (MODE) == V2DImode || (MODE) == DFmode) 1013 1014 #define VALID_SSE_REG_MODE(MODE) \ 1015 ((MODE) == V1TImode || (MODE) == TImode \ 1016 || (MODE) == V4SFmode || (MODE) == V4SImode \ 1017 || (MODE) == SFmode || (MODE) == TFmode) 1018 1019 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1020 ((MODE) == V2SFmode || (MODE) == SFmode) 1021 1022 #define VALID_MMX_REG_MODE(MODE) \ 1023 ((MODE == V1DImode) || (MODE) == DImode \ 1024 || (MODE) == V2SImode || (MODE) == SImode \ 1025 || (MODE) == V4HImode || (MODE) == V8QImode) 1026 1027 #define VALID_DFP_MODE_P(MODE) \ 1028 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1029 1030 #define VALID_FP_MODE_P(MODE) \ 1031 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1032 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1033 1034 #define VALID_INT_MODE_P(MODE) \ 1035 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1036 || (MODE) == DImode \ 1037 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1038 || (MODE) == CDImode \ 1039 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1040 || (MODE) == TFmode || (MODE) == TCmode))) 1041 1042 /* Return true for modes passed in SSE registers. */ 1043 #define SSE_REG_MODE_P(MODE) \ 1044 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1045 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1046 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1047 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1048 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ 1049 || (MODE) == V2TImode) 1050 1051 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1052 1053 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1054 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1055 1056 /* Value is 1 if it is a good idea to tie two pseudo registers 1057 when one has mode MODE1 and one has mode MODE2. 1058 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1059 for any hard reg, then this must be 0 for correct output. */ 1060 1061 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 1062 1063 /* It is possible to write patterns to move flags; but until someone 1064 does it, */ 1065 #define AVOID_CCMODE_COPIES 1066 1067 /* Specify the modes required to caller save a given hard regno. 1068 We do this on i386 to prevent flags from being saved at all. 1069 1070 Kill any attempts to combine saving of modes. */ 1071 1072 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1073 (CC_REGNO_P (REGNO) ? VOIDmode \ 1074 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1075 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 1076 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1077 : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO)) ? SImode \ 1078 : (MODE)) 1079 1080 /* The only ABI that saves SSE registers across calls is Win64 (thus no 1081 need to check the current ABI here), and with AVX enabled Win64 only 1082 guarantees that the low 16 bytes are saved. */ 1083 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1084 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16) 1085 1086 /* Specify the registers used for certain standard purposes. 1087 The values of these macros are register numbers. */ 1088 1089 /* on the 386 the pc register is %eip, and is not usable as a general 1090 register. The ordinary mov instructions won't work */ 1091 /* #define PC_REGNUM */ 1092 1093 /* Register to use for pushing function arguments. */ 1094 #define STACK_POINTER_REGNUM 7 1095 1096 /* Base register for access to local variables of the function. */ 1097 #define HARD_FRAME_POINTER_REGNUM 6 1098 1099 /* Base register for access to local variables of the function. */ 1100 #define FRAME_POINTER_REGNUM 20 1101 1102 /* First floating point reg */ 1103 #define FIRST_FLOAT_REG 8 1104 1105 /* First & last stack-like regs */ 1106 #define FIRST_STACK_REG FIRST_FLOAT_REG 1107 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1108 1109 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1110 #define LAST_SSE_REG (FIRST_SSE_REG + 7) 1111 1112 #define FIRST_MMX_REG (LAST_SSE_REG + 1) 1113 #define LAST_MMX_REG (FIRST_MMX_REG + 7) 1114 1115 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1116 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1117 1118 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1119 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1120 1121 /* Override this in other tm.h files to cope with various OS lossage 1122 requiring a frame pointer. */ 1123 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1124 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1125 #endif 1126 1127 /* Make sure we can access arbitrary call frames. */ 1128 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1129 1130 /* Base register for access to arguments of the function. */ 1131 #define ARG_POINTER_REGNUM 16 1132 1133 /* Register to hold the addressing base for position independent 1134 code access to data items. We don't use PIC pointer for 64bit 1135 mode. Define the regnum to dummy value to prevent gcc from 1136 pessimizing code dealing with EBX. 1137 1138 To avoid clobbering a call-saved register unnecessarily, we renumber 1139 the pic register when possible. The change is visible after the 1140 prologue has been emitted. */ 1141 1142 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG 1143 1144 #define PIC_OFFSET_TABLE_REGNUM \ 1145 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1146 || !flag_pic ? INVALID_REGNUM \ 1147 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1148 : REAL_PIC_OFFSET_TABLE_REGNUM) 1149 1150 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1151 1152 /* This is overridden by <cygwin.h>. */ 1153 #define MS_AGGREGATE_RETURN 0 1154 1155 #define KEEP_AGGREGATE_RETURN_POINTER 0 1156 1157 /* Define the classes of registers for register constraints in the 1158 machine description. Also define ranges of constants. 1159 1160 One of the classes must always be named ALL_REGS and include all hard regs. 1161 If there is more than one class, another class must be named NO_REGS 1162 and contain no registers. 1163 1164 The name GENERAL_REGS must be the name of a class (or an alias for 1165 another name such as ALL_REGS). This is the class of registers 1166 that is allowed by "g" or "r" in a register constraint. 1167 Also, registers outside this class are allocated only when 1168 instructions express preferences for them. 1169 1170 The classes must be numbered in nondecreasing order; that is, 1171 a larger-numbered class must never be contained completely 1172 in a smaller-numbered class. 1173 1174 For any two classes, it is very desirable that there be another 1175 class that represents their union. 1176 1177 It might seem that class BREG is unnecessary, since no useful 386 1178 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1179 and the "b" register constraint is useful in asms for syscalls. 1180 1181 The flags, fpsr and fpcr registers are in no class. */ 1182 1183 enum reg_class 1184 { 1185 NO_REGS, 1186 AREG, DREG, CREG, BREG, SIREG, DIREG, 1187 AD_REGS, /* %eax/%edx for DImode */ 1188 Q_REGS, /* %eax %ebx %ecx %edx */ 1189 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1190 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1191 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1192 CLOBBERED_REGS, /* call-clobbered integer registers */ 1193 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp 1194 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ 1195 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1196 FLOAT_REGS, 1197 SSE_FIRST_REG, 1198 SSE_REGS, 1199 MMX_REGS, 1200 FP_TOP_SSE_REGS, 1201 FP_SECOND_SSE_REGS, 1202 FLOAT_SSE_REGS, 1203 FLOAT_INT_REGS, 1204 INT_SSE_REGS, 1205 FLOAT_INT_SSE_REGS, 1206 ALL_REGS, LIM_REG_CLASSES 1207 }; 1208 1209 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1210 1211 #define INTEGER_CLASS_P(CLASS) \ 1212 reg_class_subset_p ((CLASS), GENERAL_REGS) 1213 #define FLOAT_CLASS_P(CLASS) \ 1214 reg_class_subset_p ((CLASS), FLOAT_REGS) 1215 #define SSE_CLASS_P(CLASS) \ 1216 reg_class_subset_p ((CLASS), SSE_REGS) 1217 #define MMX_CLASS_P(CLASS) \ 1218 ((CLASS) == MMX_REGS) 1219 #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1220 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1221 #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1222 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1223 #define MAYBE_SSE_CLASS_P(CLASS) \ 1224 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1225 #define MAYBE_MMX_CLASS_P(CLASS) \ 1226 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1227 1228 #define Q_CLASS_P(CLASS) \ 1229 reg_class_subset_p ((CLASS), Q_REGS) 1230 1231 /* Give names of register classes as strings for dump file. */ 1232 1233 #define REG_CLASS_NAMES \ 1234 { "NO_REGS", \ 1235 "AREG", "DREG", "CREG", "BREG", \ 1236 "SIREG", "DIREG", \ 1237 "AD_REGS", \ 1238 "Q_REGS", "NON_Q_REGS", \ 1239 "INDEX_REGS", \ 1240 "LEGACY_REGS", \ 1241 "CLOBBERED_REGS", \ 1242 "GENERAL_REGS", \ 1243 "FP_TOP_REG", "FP_SECOND_REG", \ 1244 "FLOAT_REGS", \ 1245 "SSE_FIRST_REG", \ 1246 "SSE_REGS", \ 1247 "MMX_REGS", \ 1248 "FP_TOP_SSE_REGS", \ 1249 "FP_SECOND_SSE_REGS", \ 1250 "FLOAT_SSE_REGS", \ 1251 "FLOAT_INT_REGS", \ 1252 "INT_SSE_REGS", \ 1253 "FLOAT_INT_SSE_REGS", \ 1254 "ALL_REGS" } 1255 1256 /* Define which registers fit in which classes. This is an initializer 1257 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1258 1259 Note that CLOBBERED_REGS are calculated by 1260 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1261 1262 #define REG_CLASS_CONTENTS \ 1263 { { 0x00, 0x0 }, \ 1264 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1265 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1266 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1267 { 0x03, 0x0 }, /* AD_REGS */ \ 1268 { 0x0f, 0x0 }, /* Q_REGS */ \ 1269 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1270 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1271 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1272 { 0x00, 0x0 }, /* CLOBBERED_REGS */ \ 1273 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1274 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1275 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1276 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ 1277 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1278 { 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1279 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1280 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1281 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1282 { 0x11ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1283 { 0x1ff100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1284 { 0x1ff1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1285 { 0xffffffff,0x1fffff } \ 1286 } 1287 1288 /* The same information, inverted: 1289 Return the class number of the smallest class containing 1290 reg number REGNO. This could be a conditional expression 1291 or could index an array. */ 1292 1293 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1294 1295 /* When this hook returns true for MODE, the compiler allows 1296 registers explicitly used in the rtl to be used as spill registers 1297 but prevents the compiler from extending the lifetime of these 1298 registers. */ 1299 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 1300 1301 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) 1302 #define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG) 1303 1304 #define GENERAL_REG_P(X) \ 1305 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1306 #define GENERAL_REGNO_P(N) \ 1307 (IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N)) 1308 1309 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) 1310 #define ANY_QI_REGNO_P(N) \ 1311 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) 1312 1313 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1314 #define REX_INT_REGNO_P(N) \ 1315 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1316 1317 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) 1318 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1319 1320 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1321 #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) 1322 1323 #define X87_FLOAT_MODE_P(MODE) \ 1324 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1325 1326 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) 1327 #define SSE_REGNO_P(N) \ 1328 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1329 || REX_SSE_REGNO_P (N)) 1330 1331 #define REX_SSE_REGNO_P(N) \ 1332 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1333 1334 #define SSE_REGNO(N) \ 1335 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1336 1337 #define SSE_FLOAT_MODE_P(MODE) \ 1338 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1339 1340 #define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1341 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1342 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1343 1344 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) 1345 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1346 1347 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG) 1348 1349 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1350 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1351 1352 /* The class value for index registers, and the one for base regs. */ 1353 1354 #define INDEX_REG_CLASS INDEX_REGS 1355 #define BASE_REG_CLASS GENERAL_REGS 1356 1357 /* Place additional restrictions on the register class to use when it 1358 is necessary to be able to hold a value of mode MODE in a reload 1359 register for which class CLASS would ordinarily be used. 1360 1361 We avoid classes containing registers from multiple units due to 1362 the limitation in ix86_secondary_memory_needed. We limit these 1363 classes to their "natural mode" single unit register class, depending 1364 on the unit availability. 1365 1366 Please note that reg_class_subset_p is not commutative, so these 1367 conditions mean "... if (CLASS) includes ALL registers from the 1368 register set." */ 1369 1370 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1371 (((MODE) == QImode && !TARGET_64BIT \ 1372 && reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \ 1373 : (((MODE) == SImode || (MODE) == DImode) \ 1374 && reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \ 1375 : (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \ 1376 && reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \ 1377 : (X87_FLOAT_MODE_P (MODE) \ 1378 && reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \ 1379 : (CLASS)) 1380 1381 /* If we are copying between general and FP registers, we need a memory 1382 location. The same is true for SSE and MMX registers. */ 1383 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1384 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1385 1386 /* Get_secondary_mem widens integral modes to BITS_PER_WORD. 1387 There is no need to emit full 64 bit move on 64 bit targets 1388 for integral modes that can be moved using 32 bit move. */ 1389 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1390 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ 1391 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1392 : MODE) 1393 1394 /* Return a class of registers that cannot change FROM mode to TO mode. */ 1395 1396 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1397 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1398 1399 /* Stack layout; function entry, exit and calling. */ 1400 1401 /* Define this if pushing a word on the stack 1402 makes the stack pointer a smaller address. */ 1403 #define STACK_GROWS_DOWNWARD 1404 1405 /* Define this to nonzero if the nominal address of the stack frame 1406 is at the high-address end of the local variables; 1407 that is, each additional local variable allocated 1408 goes at a more negative offset in the frame. */ 1409 #define FRAME_GROWS_DOWNWARD 1 1410 1411 /* Offset within stack frame to start allocating local variables at. 1412 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1413 first local allocated. Otherwise, it is the offset to the BEGINNING 1414 of the first local allocated. */ 1415 #define STARTING_FRAME_OFFSET 0 1416 1417 /* If we generate an insn to push BYTES bytes, this says how many the stack 1418 pointer really advances by. On 386, we have pushw instruction that 1419 decrements by exactly 2 no matter what the position was, there is no pushb. 1420 1421 But as CIE data alignment factor on this arch is -4 for 32bit targets 1422 and -8 for 64bit targets, we need to make sure all stack pointer adjustments 1423 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */ 1424 1425 #define PUSH_ROUNDING(BYTES) \ 1426 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD) 1427 1428 /* If defined, the maximum amount of space required for outgoing arguments 1429 will be computed and placed into the variable `crtl->outgoing_args_size'. 1430 No space will be pushed onto the stack for each call; instead, the 1431 function prologue should increase the stack frame size by this amount. 1432 1433 64-bit MS ABI seem to require 16 byte alignment everywhere except for 1434 function prologue and apilogue. This is not possible without 1435 ACCUMULATE_OUTGOING_ARGS. */ 1436 1437 #define ACCUMULATE_OUTGOING_ARGS \ 1438 (TARGET_ACCUMULATE_OUTGOING_ARGS || TARGET_64BIT_MS_ABI) 1439 1440 /* If defined, a C expression whose value is nonzero when we want to use PUSH 1441 instructions to pass outgoing arguments. */ 1442 1443 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1444 1445 /* We want the stack and args grow in opposite directions, even if 1446 PUSH_ARGS is 0. */ 1447 #define PUSH_ARGS_REVERSED 1 1448 1449 /* Offset of first parameter from the argument pointer register value. */ 1450 #define FIRST_PARM_OFFSET(FNDECL) 0 1451 1452 /* Define this macro if functions should assume that stack space has been 1453 allocated for arguments even when their values are passed in registers. 1454 1455 The value of this macro is the size, in bytes, of the area reserved for 1456 arguments passed in registers for the function represented by FNDECL. 1457 1458 This space can be allocated by the caller, or be a part of the 1459 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1460 which. */ 1461 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1462 1463 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1464 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) 1465 1466 /* Define how to find the value returned by a library function 1467 assuming the value has mode MODE. */ 1468 1469 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1470 1471 /* Define the size of the result block used for communication between 1472 untyped_call and untyped_return. The block contains a DImode value 1473 followed by the block used by fnsave and frstor. */ 1474 1475 #define APPLY_RESULT_SIZE (8+108) 1476 1477 /* 1 if N is a possible register number for function argument passing. */ 1478 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1479 1480 /* Define a data type for recording info about an argument list 1481 during the scan of that argument list. This data type should 1482 hold all necessary information about the function itself 1483 and about the args processed so far, enough to enable macros 1484 such as FUNCTION_ARG to determine where the next arg should go. */ 1485 1486 typedef struct ix86_args { 1487 int words; /* # words passed so far */ 1488 int nregs; /* # registers available for passing */ 1489 int regno; /* next available register number */ 1490 int fastcall; /* fastcall or thiscall calling convention 1491 is used */ 1492 int sse_words; /* # sse words passed so far */ 1493 int sse_nregs; /* # sse registers available for passing */ 1494 int warn_avx; /* True when we want to warn about AVX ABI. */ 1495 int warn_sse; /* True when we want to warn about SSE ABI. */ 1496 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1497 int sse_regno; /* next available sse register number */ 1498 int mmx_words; /* # mmx words passed so far */ 1499 int mmx_nregs; /* # mmx registers available for passing */ 1500 int mmx_regno; /* next available mmx register number */ 1501 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1502 int caller; /* true if it is caller. */ 1503 int float_in_sse; /* Set to 1 or 2 for 32bit targets if 1504 SFmode/DFmode arguments should be passed 1505 in SSE registers. Otherwise 0. */ 1506 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1507 MS_ABI for ms abi. */ 1508 } CUMULATIVE_ARGS; 1509 1510 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1511 for a call to a function whose data type is FNTYPE. 1512 For a library call, FNTYPE is 0. */ 1513 1514 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1515 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 1516 (N_NAMED_ARGS) != -1) 1517 1518 /* Output assembler code to FILE to increment profiler label # LABELNO 1519 for profiling a function entry. */ 1520 1521 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1522 1523 #define MCOUNT_NAME "_mcount" 1524 1525 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" 1526 1527 #define PROFILE_COUNT_REGISTER "edx" 1528 1529 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1530 the stack pointer does not matter. The value is tested only in 1531 functions that have frame pointers. 1532 No definition is equivalent to always zero. */ 1533 /* Note on the 386 it might be more efficient not to define this since 1534 we have to restore it ourselves from the frame pointer, in order to 1535 use pop */ 1536 1537 #define EXIT_IGNORE_STACK 1 1538 1539 /* Output assembler code for a block containing the constant parts 1540 of a trampoline, leaving space for the variable parts. */ 1541 1542 /* On the 386, the trampoline contains two instructions: 1543 mov #STATIC,ecx 1544 jmp FUNCTION 1545 The trampoline is generated entirely at runtime. The operand of JMP 1546 is the address of FUNCTION relative to the instruction following the 1547 JMP (which is 5 bytes long). */ 1548 1549 /* Length in units of the trampoline for entering a nested function. */ 1550 1551 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) 1552 1553 /* Definitions for register eliminations. 1554 1555 This is an array of structures. Each structure initializes one pair 1556 of eliminable registers. The "from" register number is given first, 1557 followed by "to". Eliminations of the same "from" register are listed 1558 in order of preference. 1559 1560 There are two registers that can always be eliminated on the i386. 1561 The frame pointer and the arg pointer can be replaced by either the 1562 hard frame pointer or to the stack pointer, depending upon the 1563 circumstances. The hard frame pointer is not used before reload and 1564 so it is not eligible for elimination. */ 1565 1566 #define ELIMINABLE_REGS \ 1567 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1568 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1569 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1570 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1571 1572 /* Define the offset between two registers, one to be eliminated, and the other 1573 its replacement, at the start of a routine. */ 1574 1575 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1576 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1577 1578 /* Addressing modes, and classification of registers for them. */ 1579 1580 /* Macros to check register numbers against specific register classes. */ 1581 1582 /* These assume that REGNO is a hard or pseudo reg number. 1583 They give nonzero only if REGNO is a hard reg of the suitable class 1584 or a pseudo reg currently allocated to a suitable hard reg. 1585 Since they use reg_renumber, they are safe only once reg_renumber 1586 has been allocated, which happens in reginfo.c during register 1587 allocation. */ 1588 1589 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1590 ((REGNO) < STACK_POINTER_REGNUM \ 1591 || REX_INT_REGNO_P (REGNO) \ 1592 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1593 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1594 1595 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1596 (GENERAL_REGNO_P (REGNO) \ 1597 || (REGNO) == ARG_POINTER_REGNUM \ 1598 || (REGNO) == FRAME_POINTER_REGNUM \ 1599 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1600 1601 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1602 and check its validity for a certain class. 1603 We have two alternate definitions for each of them. 1604 The usual definition accepts all pseudo regs; the other rejects 1605 them unless they have been allocated suitable hard regs. 1606 The symbol REG_OK_STRICT causes the latter definition to be used. 1607 1608 Most source files want to accept pseudo regs in the hope that 1609 they will get allocated to the class that the insn wants them to be in. 1610 Source files for reload pass need to be strict. 1611 After reload, it makes no difference, since pseudo regs have 1612 been eliminated by then. */ 1613 1614 1615 /* Non strict versions, pseudos are ok. */ 1616 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1617 (REGNO (X) < STACK_POINTER_REGNUM \ 1618 || REX_INT_REGNO_P (REGNO (X)) \ 1619 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1620 1621 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1622 (GENERAL_REGNO_P (REGNO (X)) \ 1623 || REGNO (X) == ARG_POINTER_REGNUM \ 1624 || REGNO (X) == FRAME_POINTER_REGNUM \ 1625 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1626 1627 /* Strict versions, hard registers only */ 1628 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1629 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1630 1631 #ifndef REG_OK_STRICT 1632 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1633 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1634 1635 #else 1636 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1637 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1638 #endif 1639 1640 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1641 that is a valid memory address for an instruction. 1642 The MODE argument is the machine mode for the MEM expression 1643 that wants to use this address. 1644 1645 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1646 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1647 1648 See legitimize_pic_address in i386.c for details as to what 1649 constitutes a legitimate address when -fpic is used. */ 1650 1651 #define MAX_REGS_PER_ADDRESS 2 1652 1653 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1654 1655 /* Try a machine-dependent way of reloading an illegitimate address 1656 operand. If we find one, push the reload and jump to WIN. This 1657 macro is used in only one place: `find_reloads_address' in reload.c. */ 1658 1659 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \ 1660 do { \ 1661 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1662 (int)(TYPE), (INDL))) \ 1663 goto WIN; \ 1664 } while (0) 1665 1666 /* If defined, a C expression to determine the base term of address X. 1667 This macro is used in only one place: `find_base_term' in alias.c. 1668 1669 It is always safe for this macro to not be defined. It exists so 1670 that alias analysis can understand machine-dependent addresses. 1671 1672 The typical use of this macro is to handle addresses containing 1673 a label_ref or symbol_ref within an UNSPEC. */ 1674 1675 #define FIND_BASE_TERM(X) ix86_find_base_term (X) 1676 1677 /* Nonzero if the constant value X is a legitimate general operand 1678 when generating PIC code. It is given that flag_pic is on and 1679 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1680 1681 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1682 1683 #define SYMBOLIC_CONST(X) \ 1684 (GET_CODE (X) == SYMBOL_REF \ 1685 || GET_CODE (X) == LABEL_REF \ 1686 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1687 1688 /* Max number of args passed in registers. If this is more than 3, we will 1689 have problems with ebx (register #4), since it is a caller save register and 1690 is also used as the pic register in ELF. So for now, don't allow more than 1691 3 registers to be passed in registers. */ 1692 1693 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1694 #define X86_64_REGPARM_MAX 6 1695 #define X86_64_MS_REGPARM_MAX 4 1696 1697 #define X86_32_REGPARM_MAX 3 1698 1699 #define REGPARM_MAX \ 1700 (TARGET_64BIT \ 1701 ? (TARGET_64BIT_MS_ABI \ 1702 ? X86_64_MS_REGPARM_MAX \ 1703 : X86_64_REGPARM_MAX) \ 1704 : X86_32_REGPARM_MAX) 1705 1706 #define X86_64_SSE_REGPARM_MAX 8 1707 #define X86_64_MS_SSE_REGPARM_MAX 4 1708 1709 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1710 1711 #define SSE_REGPARM_MAX \ 1712 (TARGET_64BIT \ 1713 ? (TARGET_64BIT_MS_ABI \ 1714 ? X86_64_MS_SSE_REGPARM_MAX \ 1715 : X86_64_SSE_REGPARM_MAX) \ 1716 : X86_32_SSE_REGPARM_MAX) 1717 1718 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1719 1720 /* Specify the machine mode that this machine uses 1721 for the index in the tablejump instruction. */ 1722 #define CASE_VECTOR_MODE \ 1723 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1724 1725 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1726 #define DEFAULT_SIGNED_CHAR 1 1727 1728 /* Max number of bytes we can move from memory to memory 1729 in one reasonably fast instruction. */ 1730 #define MOVE_MAX 16 1731 1732 /* MOVE_MAX_PIECES is the number of bytes at a time which we can 1733 move efficiently, as opposed to MOVE_MAX which is the maximum 1734 number of bytes we can move with a single instruction. */ 1735 #define MOVE_MAX_PIECES UNITS_PER_WORD 1736 1737 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1738 move-instruction pairs, we will do a movmem or libcall instead. 1739 Increasing the value will always make code faster, but eventually 1740 incurs high cost in increased code size. 1741 1742 If you don't define this, a reasonable default is used. */ 1743 1744 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1745 1746 /* If a clear memory operation would take CLEAR_RATIO or more simple 1747 move-instruction sequences, we will do a clrmem or libcall instead. */ 1748 1749 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 1750 1751 /* Define if shifts truncate the shift count which implies one can 1752 omit a sign-extension or zero-extension of a shift count. 1753 1754 On i386, shifts do truncate the count. But bit test instructions 1755 take the modulo of the bit offset operand. */ 1756 1757 /* #define SHIFT_COUNT_TRUNCATED */ 1758 1759 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1760 is done just by pretending it is already truncated. */ 1761 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1762 1763 /* A macro to update M and UNSIGNEDP when an object whose type is 1764 TYPE and which has the specified mode and signedness is to be 1765 stored in a register. This macro is only called when TYPE is a 1766 scalar type. 1767 1768 On i386 it is sometimes useful to promote HImode and QImode 1769 quantities to SImode. The choice depends on target type. */ 1770 1771 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1772 do { \ 1773 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1774 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1775 (MODE) = SImode; \ 1776 } while (0) 1777 1778 /* Specify the machine mode that pointers have. 1779 After generation of rtl, the compiler makes no further distinction 1780 between pointers and any other objects of this machine mode. */ 1781 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) 1782 1783 /* A C expression whose value is zero if pointers that need to be extended 1784 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1785 greater then zero if they are zero-extended and less then zero if the 1786 ptr_extend instruction should be used. */ 1787 1788 #define POINTERS_EXTEND_UNSIGNED 1 1789 1790 /* A function address in a call instruction 1791 is a byte address (for indexing purposes) 1792 so give the MEM rtx a byte's mode. */ 1793 #define FUNCTION_MODE QImode 1794 1795 1796 /* A C expression for the cost of a branch instruction. A value of 1 1797 is the default; other values are interpreted relative to that. */ 1798 1799 #define BRANCH_COST(speed_p, predictable_p) \ 1800 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 1801 1802 /* An integer expression for the size in bits of the largest integer machine 1803 mode that should actually be used. We allow pairs of registers. */ 1804 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 1805 1806 /* Define this macro as a C expression which is nonzero if accessing 1807 less than a word of memory (i.e. a `char' or a `short') is no 1808 faster than accessing a word of memory, i.e., if such access 1809 require more than one instruction or if there is no difference in 1810 cost between byte and (aligned) word loads. 1811 1812 When this macro is not defined, the compiler will access a field by 1813 finding the smallest containing object; when it is defined, a 1814 fullword load will be used if alignment permits. Unless bytes 1815 accesses are faster than word accesses, using word accesses is 1816 preferable since it may eliminate subsequent memory access if 1817 subsequent accesses occur to other fields in the same word of the 1818 structure, but to different bytes. */ 1819 1820 #define SLOW_BYTE_ACCESS 0 1821 1822 /* Nonzero if access to memory by shorts is slow and undesirable. */ 1823 #define SLOW_SHORT_ACCESS 0 1824 1825 /* Define this macro to be the value 1 if unaligned accesses have a 1826 cost many times greater than aligned accesses, for example if they 1827 are emulated in a trap handler. 1828 1829 When this macro is nonzero, the compiler will act as if 1830 `STRICT_ALIGNMENT' were nonzero when generating code for block 1831 moves. This can cause significantly more instructions to be 1832 produced. Therefore, do not set this macro nonzero if unaligned 1833 accesses only add a cycle or two to the time for a memory access. 1834 1835 If the value of this macro is always zero, it need not be defined. */ 1836 1837 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1838 1839 /* Define this macro if it is as good or better to call a constant 1840 function address than to call an address kept in a register. 1841 1842 Desirable on the 386 because a CALL with a constant address is 1843 faster than one with a register address. */ 1844 1845 #define NO_FUNCTION_CSE 1846 1847 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1848 return the mode to be used for the comparison. 1849 1850 For floating-point equality comparisons, CCFPEQmode should be used. 1851 VOIDmode should be used in all other cases. 1852 1853 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1854 possible, to allow for more combinations. */ 1855 1856 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1857 1858 /* Return nonzero if MODE implies a floating point inequality can be 1859 reversed. */ 1860 1861 #define REVERSIBLE_CC_MODE(MODE) 1 1862 1863 /* A C expression whose value is reversed condition code of the CODE for 1864 comparison done in CC_MODE mode. */ 1865 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1866 1867 1868 /* Control the assembler format that we output, to the extent 1869 this does not vary between assemblers. */ 1870 1871 /* How to refer to registers in assembler output. 1872 This sequence is indexed by compiler's hard-register-number (see above). */ 1873 1874 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 1875 For non floating point regs, the following are the HImode names. 1876 1877 For float regs, the stack top is sometimes referred to as "%st(0)" 1878 instead of just "%st". TARGET_PRINT_OPERAND handles this with the 1879 "y" code. */ 1880 1881 #define HI_REGISTER_NAMES \ 1882 {"ax","dx","cx","bx","si","di","bp","sp", \ 1883 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 1884 "argp", "flags", "fpsr", "fpcr", "frame", \ 1885 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 1886 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 1887 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1888 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 1889 1890 #define REGISTER_NAMES HI_REGISTER_NAMES 1891 1892 /* Table of additional register names to use in user input. */ 1893 1894 #define ADDITIONAL_REGISTER_NAMES \ 1895 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 1896 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 1897 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 1898 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 1899 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 1900 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 1901 1902 /* Note we are omitting these since currently I don't know how 1903 to get gcc to use these, since they want the same but different 1904 number as al, and ax. 1905 */ 1906 1907 #define QI_REGISTER_NAMES \ 1908 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 1909 1910 /* These parallel the array above, and can be used to access bits 8:15 1911 of regs 0 through 3. */ 1912 1913 #define QI_HIGH_REGISTER_NAMES \ 1914 {"ah", "dh", "ch", "bh", } 1915 1916 /* How to renumber registers for dbx and gdb. */ 1917 1918 #define DBX_REGISTER_NUMBER(N) \ 1919 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 1920 1921 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 1922 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 1923 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 1924 1925 /* Before the prologue, RA is at 0(%esp). */ 1926 #define INCOMING_RETURN_ADDR_RTX \ 1927 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 1928 1929 /* After the prologue, RA is at -4(AP) in the current frame. */ 1930 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1931 ((COUNT) == 0 \ 1932 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 1933 -UNITS_PER_WORD)) \ 1934 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD))) 1935 1936 /* PC is dbx register 8; let's use that column for RA. */ 1937 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 1938 1939 /* Before the prologue, the top of the frame is at 4(%esp). */ 1940 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 1941 1942 /* Describe how we implement __builtin_eh_return. */ 1943 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 1944 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 1945 1946 1947 /* Select a format to encode pointers in exception handling data. CODE 1948 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1949 true if the symbol may be affected by dynamic relocations. 1950 1951 ??? All x86 object file formats are capable of representing this. 1952 After all, the relocation needed is the same as for the call insn. 1953 Whether or not a particular assembler allows us to enter such, I 1954 guess we'll have to see. */ 1955 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1956 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 1957 1958 /* This is how to output an insn to push a register on the stack. 1959 It need not be very fast code. */ 1960 1961 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 1962 do { \ 1963 if (TARGET_64BIT) \ 1964 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 1965 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 1966 else \ 1967 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 1968 } while (0) 1969 1970 /* This is how to output an insn to pop a register from the stack. 1971 It need not be very fast code. */ 1972 1973 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 1974 do { \ 1975 if (TARGET_64BIT) \ 1976 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 1977 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 1978 else \ 1979 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 1980 } while (0) 1981 1982 /* This is how to output an element of a case-vector that is absolute. */ 1983 1984 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1985 ix86_output_addr_vec_elt ((FILE), (VALUE)) 1986 1987 /* This is how to output an element of a case-vector that is relative. */ 1988 1989 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1990 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 1991 1992 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ 1993 1994 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 1995 { \ 1996 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 1997 (PTR) += TARGET_AVX ? 1 : 2; \ 1998 } 1999 2000 /* A C statement or statements which output an assembler instruction 2001 opcode to the stdio stream STREAM. The macro-operand PTR is a 2002 variable of type `char *' which points to the opcode name in 2003 its "internal" form--the form that is written in the machine 2004 description. */ 2005 2006 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2007 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2008 2009 /* A C statement to output to the stdio stream FILE an assembler 2010 command to pad the location counter to a multiple of 1<<LOG 2011 bytes if it is within MAX_SKIP bytes. */ 2012 2013 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2014 #undef ASM_OUTPUT_MAX_SKIP_PAD 2015 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2016 if ((LOG) != 0) \ 2017 { \ 2018 if ((MAX_SKIP) == 0) \ 2019 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2020 else \ 2021 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2022 } 2023 #endif 2024 2025 /* Write the extra assembler code needed to declare a function 2026 properly. */ 2027 2028 #undef ASM_OUTPUT_FUNCTION_LABEL 2029 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 2030 ix86_asm_output_function_label (FILE, NAME, DECL) 2031 2032 /* Under some conditions we need jump tables in the text section, 2033 because the assembler cannot handle label differences between 2034 sections. This is the case for x86_64 on Mach-O for example. */ 2035 2036 #define JUMP_TABLES_IN_TEXT_SECTION \ 2037 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2038 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2039 2040 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2041 and switch back. For x86 we do this only to save a few bytes that 2042 would otherwise be unused in the text section. */ 2043 #define CRT_MKSTR2(VAL) #VAL 2044 #define CRT_MKSTR(x) CRT_MKSTR2(x) 2045 2046 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2047 asm (SECTION_OP "\n\t" \ 2048 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2049 TEXT_SECTION_ASM_OP); 2050 2051 /* Default threshold for putting data in large sections 2052 with x86-64 medium memory model */ 2053 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 2054 2055 /* Which processor to tune code generation for. These must be in sync 2056 with processor_target_table in i386.c. */ 2057 2058 enum processor_type 2059 { 2060 PROCESSOR_GENERIC32 = 0, 2061 PROCESSOR_GENERIC64, 2062 PROCESSOR_I386, /* 80386 */ 2063 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2064 PROCESSOR_PENTIUM, 2065 PROCESSOR_PENTIUMPRO, 2066 PROCESSOR_PENTIUM4, 2067 PROCESSOR_NOCONA, 2068 PROCESSOR_CORE2, 2069 PROCESSOR_COREI7, 2070 PROCESSOR_HASWELL, 2071 PROCESSOR_ATOM, 2072 PROCESSOR_GEODE, 2073 PROCESSOR_K6, 2074 PROCESSOR_ATHLON, 2075 PROCESSOR_K8, 2076 PROCESSOR_AMDFAM10, 2077 PROCESSOR_BDVER1, 2078 PROCESSOR_BDVER2, 2079 PROCESSOR_BDVER3, 2080 PROCESSOR_BTVER1, 2081 PROCESSOR_BTVER2, 2082 PROCESSOR_max 2083 }; 2084 2085 extern enum processor_type ix86_tune; 2086 extern enum processor_type ix86_arch; 2087 2088 /* Size of the RED_ZONE area. */ 2089 #define RED_ZONE_SIZE 128 2090 /* Reserved area of the red zone for temporaries. */ 2091 #define RED_ZONE_RESERVE 8 2092 2093 extern unsigned int ix86_preferred_stack_boundary; 2094 extern unsigned int ix86_incoming_stack_boundary; 2095 2096 /* Smallest class containing REGNO. */ 2097 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2098 2099 enum ix86_fpcmp_strategy { 2100 IX86_FPCMP_SAHF, 2101 IX86_FPCMP_COMI, 2102 IX86_FPCMP_ARITH 2103 }; 2104 2105 /* To properly truncate FP values into integers, we need to set i387 control 2106 word. We can't emit proper mode switching code before reload, as spills 2107 generated by reload may truncate values incorrectly, but we still can avoid 2108 redundant computation of new control word by the mode switching pass. 2109 The fldcw instructions are still emitted redundantly, but this is probably 2110 not going to be noticeable problem, as most CPUs do have fast path for 2111 the sequence. 2112 2113 The machinery is to emit simple truncation instructions and split them 2114 before reload to instructions having USEs of two memory locations that 2115 are filled by this code to old and new control word. 2116 2117 Post-reload pass may be later used to eliminate the redundant fildcw if 2118 needed. */ 2119 2120 enum ix86_entity 2121 { 2122 AVX_U128 = 0, 2123 I387_TRUNC, 2124 I387_FLOOR, 2125 I387_CEIL, 2126 I387_MASK_PM, 2127 MAX_386_ENTITIES 2128 }; 2129 2130 enum ix86_stack_slot 2131 { 2132 SLOT_TEMP = 0, 2133 SLOT_CW_STORED, 2134 SLOT_CW_TRUNC, 2135 SLOT_CW_FLOOR, 2136 SLOT_CW_CEIL, 2137 SLOT_CW_MASK_PM, 2138 MAX_386_STACK_LOCALS 2139 }; 2140 2141 enum avx_u128_state 2142 { 2143 AVX_U128_CLEAN, 2144 AVX_U128_DIRTY, 2145 AVX_U128_ANY 2146 }; 2147 2148 /* Define this macro if the port needs extra instructions inserted 2149 for mode switching in an optimizing compilation. */ 2150 2151 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2152 ix86_optimize_mode_switching[(ENTITY)] 2153 2154 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2155 initializer for an array of integers. Each initializer element N 2156 refers to an entity that needs mode switching, and specifies the 2157 number of different modes that might need to be set for this 2158 entity. The position of the initializer in the initializer - 2159 starting counting at zero - determines the integer that is used to 2160 refer to the mode-switched entity in question. */ 2161 2162 #define NUM_MODES_FOR_MODE_SWITCHING \ 2163 { AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2164 2165 /* ENTITY is an integer specifying a mode-switched entity. If 2166 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2167 return an integer value not larger than the corresponding element 2168 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2169 must be switched into prior to the execution of INSN. */ 2170 2171 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2172 2173 /* If this macro is defined, it is evaluated for every INSN during 2174 mode switching. It determines the mode that an insn results in (if 2175 different from the incoming mode). */ 2176 2177 #define MODE_AFTER(ENTITY, MODE, I) ix86_mode_after ((ENTITY), (MODE), (I)) 2178 2179 /* If this macro is defined, it is evaluated for every ENTITY that 2180 needs mode switching. It should evaluate to an integer, which is 2181 a mode that ENTITY is assumed to be switched to at function entry. */ 2182 2183 #define MODE_ENTRY(ENTITY) ix86_mode_entry (ENTITY) 2184 2185 /* If this macro is defined, it is evaluated for every ENTITY that 2186 needs mode switching. It should evaluate to an integer, which is 2187 a mode that ENTITY is assumed to be switched to at function exit. */ 2188 2189 #define MODE_EXIT(ENTITY) ix86_mode_exit (ENTITY) 2190 2191 /* This macro specifies the order in which modes for ENTITY are 2192 processed. 0 is the highest priority. */ 2193 2194 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2195 2196 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2197 is the set of hard registers live at the point where the insn(s) 2198 are to be inserted. */ 2199 2200 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2201 ix86_emit_mode_set ((ENTITY), (MODE), (HARD_REGS_LIVE)) 2202 2203 /* Avoid renaming of stack registers, as doing so in combination with 2204 scheduling just increases amount of live registers at time and in 2205 the turn amount of fxch instructions needed. 2206 2207 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2208 2209 #define HARD_REGNO_RENAME_OK(SRC, TARGET) !STACK_REGNO_P (SRC) 2210 2211 2212 #define FASTCALL_PREFIX '@' 2213 2214 /* Machine specific frame tracking during prologue/epilogue generation. */ 2215 2216 #ifndef USED_FOR_TARGET 2217 struct GTY(()) machine_frame_state 2218 { 2219 /* This pair tracks the currently active CFA as reg+offset. When reg 2220 is drap_reg, we don't bother trying to record here the real CFA when 2221 it might really be a DW_CFA_def_cfa_expression. */ 2222 rtx cfa_reg; 2223 HOST_WIDE_INT cfa_offset; 2224 2225 /* The current offset (canonically from the CFA) of ESP and EBP. 2226 When stack frame re-alignment is active, these may not be relative 2227 to the CFA. However, in all cases they are relative to the offsets 2228 of the saved registers stored in ix86_frame. */ 2229 HOST_WIDE_INT sp_offset; 2230 HOST_WIDE_INT fp_offset; 2231 2232 /* The size of the red-zone that may be assumed for the purposes of 2233 eliding register restore notes in the epilogue. This may be zero 2234 if no red-zone is in effect, or may be reduced from the real 2235 red-zone value by a maximum runtime stack re-alignment value. */ 2236 int red_zone_offset; 2237 2238 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid 2239 value within the frame. If false then the offset above should be 2240 ignored. Note that DRAP, if valid, *always* points to the CFA and 2241 thus has an offset of zero. */ 2242 BOOL_BITFIELD sp_valid : 1; 2243 BOOL_BITFIELD fp_valid : 1; 2244 BOOL_BITFIELD drap_valid : 1; 2245 2246 /* Indicate whether the local stack frame has been re-aligned. When 2247 set, the SP/FP offsets above are relative to the aligned frame 2248 and not the CFA. */ 2249 BOOL_BITFIELD realigned : 1; 2250 }; 2251 2252 /* Private to winnt.c. */ 2253 struct seh_frame_state; 2254 2255 struct GTY(()) machine_function { 2256 struct stack_local_entry *stack_locals; 2257 const char *some_ld_name; 2258 int varargs_gpr_size; 2259 int varargs_fpr_size; 2260 int optimize_mode_switching[MAX_386_ENTITIES]; 2261 2262 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE 2263 has been computed for. */ 2264 int use_fast_prologue_epilogue_nregs; 2265 2266 /* For -fsplit-stack support: A stack local which holds a pointer to 2267 the stack arguments for a function with a variable number of 2268 arguments. This is set at the start of the function and is used 2269 to initialize the overflow_arg_area field of the va_list 2270 structure. */ 2271 rtx split_stack_varargs_pointer; 2272 2273 /* This value is used for amd64 targets and specifies the current abi 2274 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2275 ENUM_BITFIELD(calling_abi) call_abi : 8; 2276 2277 /* Nonzero if the function accesses a previous frame. */ 2278 BOOL_BITFIELD accesses_prev_frame : 1; 2279 2280 /* Nonzero if the function requires a CLD in the prologue. */ 2281 BOOL_BITFIELD needs_cld : 1; 2282 2283 /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2284 expander to determine the style used. */ 2285 BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2286 2287 /* If true, the current function needs the default PIC register, not 2288 an alternate register (on x86) and must not use the red zone (on 2289 x86_64), even if it's a leaf function. We don't want the 2290 function to be regarded as non-leaf because TLS calls need not 2291 affect register allocation. This flag is set when a TLS call 2292 instruction is expanded within a function, and never reset, even 2293 if all such instructions are optimized away. Use the 2294 ix86_current_function_calls_tls_descriptor macro for a better 2295 approximation. */ 2296 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2297 2298 /* If true, the current function has a STATIC_CHAIN is placed on the 2299 stack below the return address. */ 2300 BOOL_BITFIELD static_chain_on_stack : 1; 2301 2302 /* During prologue/epilogue generation, the current frame state. 2303 Otherwise, the frame state at the end of the prologue. */ 2304 struct machine_frame_state fs; 2305 2306 /* During SEH output, this is non-null. */ 2307 struct seh_frame_state * GTY((skip(""))) seh; 2308 }; 2309 #endif 2310 2311 #define ix86_stack_locals (cfun->machine->stack_locals) 2312 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2313 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2314 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2315 #define ix86_current_function_needs_cld (cfun->machine->needs_cld) 2316 #define ix86_tls_descriptor_calls_expanded_in_cfun \ 2317 (cfun->machine->tls_descriptor_call_expanded_p) 2318 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2319 calls are optimized away, we try to detect cases in which it was 2320 optimized away. Since such instructions (use (reg REG_SP)), we can 2321 verify whether there's any such instruction live by testing that 2322 REG_SP is live. */ 2323 #define ix86_current_function_calls_tls_descriptor \ 2324 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2325 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2326 2327 /* Control behavior of x86_file_start. */ 2328 #define X86_FILE_START_VERSION_DIRECTIVE false 2329 #define X86_FILE_START_FLTUSED false 2330 2331 /* Flag to mark data that is in the large address area. */ 2332 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2333 #define SYMBOL_REF_FAR_ADDR_P(X) \ 2334 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2335 2336 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2337 have defined always, to avoid ifdefing. */ 2338 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2339 #define SYMBOL_REF_DLLIMPORT_P(X) \ 2340 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2341 2342 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2343 #define SYMBOL_REF_DLLEXPORT_P(X) \ 2344 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2345 2346 extern void debug_ready_dispatch (void); 2347 extern void debug_dispatch_window (int); 2348 2349 /* The value at zero is only defined for the BMI instructions 2350 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ 2351 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2352 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI) 2353 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2354 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT) 2355 2356 2357 /* Flags returned by ix86_get_callcvt (). */ 2358 #define IX86_CALLCVT_CDECL 0x1 2359 #define IX86_CALLCVT_STDCALL 0x2 2360 #define IX86_CALLCVT_FASTCALL 0x4 2361 #define IX86_CALLCVT_THISCALL 0x8 2362 #define IX86_CALLCVT_REGPARM 0x10 2363 #define IX86_CALLCVT_SSEREGPARM 0x20 2364 2365 #define IX86_BASE_CALLCVT(FLAGS) \ 2366 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ 2367 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) 2368 2369 #define RECIP_MASK_NONE 0x00 2370 #define RECIP_MASK_DIV 0x01 2371 #define RECIP_MASK_SQRT 0x02 2372 #define RECIP_MASK_VEC_DIV 0x04 2373 #define RECIP_MASK_VEC_SQRT 0x08 2374 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ 2375 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2376 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2377 2378 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 2379 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 2380 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 2381 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 2382 2383 #define IX86_HLE_ACQUIRE (1 << 16) 2384 #define IX86_HLE_RELEASE (1 << 17) 2385 2386 /* 2387 Local variables: 2388 version-control: t 2389 End: 2390 */ 2391