1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <soc/usb/snps_usb_phy.h>
5 #include <soc/addressmap.h>
6 #include <commonlib/helpers.h>
7 #include <soc/usb/usb_common.h>
8
9 #define SLEEPM BIT(0)
10
11 #define TERMSEL BIT(5)
12
13 #define POR BIT(1)
14
15 #define FSEL_MASK GENMASK(7, 5)
16 #define FSEL_DEFAULT (0x3 << 4)
17
18 #define VBUSVLDEXTSEL0 BIT(4)
19 #define PLLBTUNE BIT(5)
20
21 #define VREGBYPASS BIT(0)
22
23 #define VBUSVLDEXT0 BIT(0)
24
25 #define USB2_SUSPEND_N BIT(2)
26 #define USB2_SUSPEND_N_SEL BIT(3)
27
28 #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
29
30 #define REFCLK_SEL_MASK GENMASK(1, 0)
31 #define REFCLK_SEL_DEFAULT (0x2 << 0)
32
33 #define PARAM_OVRD_MASK 0xFF
34
35 struct hs_usb_phy_reg *hs_phy_reg = (void *)HS_USB_PRIM_PHY_BASE;
36
hs_usb_phy_init(void * board_data)37 void hs_usb_phy_init(void *board_data)
38 {
39 struct usb_board_data *override_data =
40 (struct usb_board_data *)board_data;
41
42 clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
43 UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
44
45 clrsetbits32(&hs_phy_reg->utmi_ctrl5, POR, POR);
46
47 clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common0, FSEL_MASK, 0);
48
49 clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common1, PLLBTUNE, PLLBTUNE);
50
51 clrsetbits32(&hs_phy_reg->refclk_ctrl, REFCLK_SEL_MASK,
52 REFCLK_SEL_DEFAULT);
53
54 clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common1, VBUSVLDEXTSEL0,
55 VBUSVLDEXTSEL0);
56
57 clrsetbits32(&hs_phy_reg->hs_phy_ctrl1, VBUSVLDEXT0, VBUSVLDEXT0);
58
59 if (board_data) {
60 clrsetbits32(&hs_phy_reg->hs_phy_override_x0,
61 PARAM_OVRD_MASK, override_data->parameter_override_x0);
62
63 clrsetbits32(&hs_phy_reg->hs_phy_override_x1,
64 PARAM_OVRD_MASK, override_data->parameter_override_x1);
65
66 clrsetbits32(&hs_phy_reg->hs_phy_override_x2,
67 PARAM_OVRD_MASK, override_data->parameter_override_x2);
68
69 clrsetbits32(&hs_phy_reg->hs_phy_override_x3,
70 PARAM_OVRD_MASK, override_data->parameter_override_x3);
71 }
72 clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common2, VREGBYPASS, VREGBYPASS);
73
74 clrsetbits32(&hs_phy_reg->hs_phy_ctrl2,
75 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
76 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
77
78 clrsetbits32(&hs_phy_reg->utmi_ctrl0, SLEEPM, SLEEPM);
79
80 clrsetbits32(&hs_phy_reg->utmi_ctrl5, POR, 0);
81
82 clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, USB2_SUSPEND_N_SEL, 0);
83
84 clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
85
86 printk(BIOS_DEBUG, "USB HS PHY initialized\n");
87 }
88