1 #ifndef __BDK_CSRS_RVU_H__
2 #define __BDK_CSRS_RVU_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
36 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
39 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium RVU.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration rvu_af_int_vec_e
57 *
58 * RVU Admin Function Interrupt Vector Enumeration
59 * Enumerates the MSI-X interrupt vectors.
60 * Internal:
61 * RVU maintains the state of these vectors internally, and generates GIB
62 * messages for it without accessing the MSI-X table region in LLC/DRAM.
63 */
64 #define BDK_RVU_AF_INT_VEC_E_GEN (3)
65 #define BDK_RVU_AF_INT_VEC_E_MBOX (4)
66 #define BDK_RVU_AF_INT_VEC_E_PFFLR (1)
67 #define BDK_RVU_AF_INT_VEC_E_PFME (2)
68 #define BDK_RVU_AF_INT_VEC_E_POISON (0)
69
70 /**
71 * Enumeration rvu_bar_e
72 *
73 * RVU Base Address Register Enumeration
74 * Enumerates the base address registers.
75 * Internal:
76 * For documentation only.
77 */
78 #define BDK_RVU_BAR_E_RVU_PFX_BAR0(a) (0x850000000000ll + 0x1000000000ll * (a))
79 #define BDK_RVU_BAR_E_RVU_PFX_BAR0_SIZE 0x200000000ull
80 #define BDK_RVU_BAR_E_RVU_PFX_FUNCX_BAR2(a,b) (0x850200000000ll + 0x1000000000ll * (a) + 0x2000000ll * (b))
81 #define BDK_RVU_BAR_E_RVU_PFX_FUNCX_BAR2_SIZE 0x2000000ull
82
83 /**
84 * Enumeration rvu_block_addr_e
85 *
86 * RVU Block Address Enumeration
87 * Enumerates addressing of RVU resource blocks within each RVU BAR, i.e. values
88 * of RVU_FUNC_ADDR_S[BLOCK] and RVU_AF_ADDR_S[BLOCK].
89 */
90 #define BDK_RVU_BLOCK_ADDR_E_CPTX(a) (0xa + (a))
91 #define BDK_RVU_BLOCK_ADDR_E_LMT (1)
92 #define BDK_RVU_BLOCK_ADDR_E_MSIX (2)
93 #define BDK_RVU_BLOCK_ADDR_E_NDCX(a) (0xc + (a))
94 #define BDK_RVU_BLOCK_ADDR_E_NIXX(a) (4 + (a))
95 #define BDK_RVU_BLOCK_ADDR_E_NPA (3)
96 #define BDK_RVU_BLOCK_ADDR_E_NPC (6)
97 #define BDK_RVU_BLOCK_ADDR_E_RX(a) (0 + (a))
98 #define BDK_RVU_BLOCK_ADDR_E_RVUM (0)
99 #define BDK_RVU_BLOCK_ADDR_E_SSO (7)
100 #define BDK_RVU_BLOCK_ADDR_E_SSOW (8)
101 #define BDK_RVU_BLOCK_ADDR_E_TIM (9)
102
103 /**
104 * Enumeration rvu_block_type_e
105 *
106 * RVU Block Type Enumeration
107 * Enumerates values of RVU_PF/RVU_VF_BLOCK_ADDR()_DISC[BTYPE].
108 */
109 #define BDK_RVU_BLOCK_TYPE_E_CPT (9)
110 #define BDK_RVU_BLOCK_TYPE_E_DDF (0xb)
111 #define BDK_RVU_BLOCK_TYPE_E_DFA (0xe)
112 #define BDK_RVU_BLOCK_TYPE_E_HNA (0xf)
113 #define BDK_RVU_BLOCK_TYPE_E_LMT (2)
114 #define BDK_RVU_BLOCK_TYPE_E_MSIX (1)
115 #define BDK_RVU_BLOCK_TYPE_E_NDC (0xa)
116 #define BDK_RVU_BLOCK_TYPE_E_NIX (3)
117 #define BDK_RVU_BLOCK_TYPE_E_NPA (4)
118 #define BDK_RVU_BLOCK_TYPE_E_NPC (5)
119 #define BDK_RVU_BLOCK_TYPE_E_RAD (0xd)
120 #define BDK_RVU_BLOCK_TYPE_E_RVUM (0)
121 #define BDK_RVU_BLOCK_TYPE_E_SSO (6)
122 #define BDK_RVU_BLOCK_TYPE_E_SSOW (7)
123 #define BDK_RVU_BLOCK_TYPE_E_TIM (8)
124 #define BDK_RVU_BLOCK_TYPE_E_ZIP (0xc)
125
126 /**
127 * Enumeration rvu_bus_lf_e
128 *
129 * INTERNAL: RVU Bus LF Range Enumeration
130 *
131 * Enumerates the LF range for the RVU bus.
132 * Internal:
133 * This is an enum used in csr3 virtual equations.
134 */
135 #define BDK_RVU_BUS_LF_E_RVU_BUS_LFX(a) (0 + 0x2000000 * (a))
136
137 /**
138 * Enumeration rvu_bus_pf_e
139 *
140 * INTERNAL: RVU Bus PF Range Enumeration
141 *
142 * Enumerates the PF range for the RVU bus.
143 * Internal:
144 * This is an enum used in csr3 virtual equations.
145 */
146 #define BDK_RVU_BUS_PF_E_RVU_BUS_PFX(a) (0ll + 0x1000000000ll * (a))
147
148 /**
149 * Enumeration rvu_bus_pfvf_e
150 *
151 * INTERNAL: RVU Bus PFVF Range Enumeration
152 *
153 * Enumerates the PF and VF ranges for the RVU bus.
154 * Internal:
155 * This is an enum used in csr3 virtual equations.
156 */
157 #define BDK_RVU_BUS_PFVF_E_RVU_BUS_PFX(a) (0 + 0x2000000 * (a))
158 #define BDK_RVU_BUS_PFVF_E_RVU_BUS_VFX(a) (0 + 0x2000000 * (a))
159
160 /**
161 * Enumeration rvu_busbar_e
162 *
163 * INTERNAL: RVU Bus Base Address Region Enumeration
164 *
165 * Enumerates the base address region for the RVU bus.
166 * Internal:
167 * This is an enum used in csr3 virtual equations.
168 */
169 #define BDK_RVU_BUSBAR_E_RVU_BUSBAR0 (0)
170 #define BDK_RVU_BUSBAR_E_RVU_BUSBAR2 (0x200000000ll)
171
172 /**
173 * Enumeration rvu_busdid_e
174 *
175 * INTERNAL: RVU Bus DID Enumeration
176 *
177 * Enumerates the DID offset for the RVU bus.
178 * Internal:
179 * This is an enum used in csr3 virtual equations.
180 */
181 #define BDK_RVU_BUSDID_E_RVU_BUSDID (0x850000000000ll)
182
183 /**
184 * Enumeration rvu_ndc_idx_e
185 *
186 * RVU NDC Index Enumeration
187 * Enumerates NDC instances and index of RVU_BLOCK_ADDR_E::NDC().
188 */
189 #define BDK_RVU_NDC_IDX_E_NIXX_RX(a) (0 + 4 * (a))
190 #define BDK_RVU_NDC_IDX_E_NIXX_TX(a) (1 + 4 * (a))
191 #define BDK_RVU_NDC_IDX_E_NPA_UX(a) (2 + 0 * (a))
192
193 /**
194 * Enumeration rvu_pf_int_vec_e
195 *
196 * RVU PF Interrupt Vector Enumeration
197 * Enumerates the MSI-X interrupt vectors.
198 */
199 #define BDK_RVU_PF_INT_VEC_E_AFPF_MBOX (0xc)
200 #define BDK_RVU_PF_INT_VEC_E_VFFLRX(a) (0 + (a))
201 #define BDK_RVU_PF_INT_VEC_E_VFMEX(a) (4 + (a))
202 #define BDK_RVU_PF_INT_VEC_E_VFPF_MBOXX(a) (8 + (a))
203
204 /**
205 * Enumeration rvu_vf_int_vec_e
206 *
207 * RVU VF Interrupt Vector Enumeration
208 * Enumerates the MSI-X interrupt vectors.
209 */
210 #define BDK_RVU_VF_INT_VEC_E_MBOX (0)
211
212 /**
213 * Structure rvu_af_addr_s
214 *
215 * RVU Admin Function Register Address Structure
216 * Address format for accessing shared Admin Function (AF) registers in
217 * RVU PF BAR0. These registers may be accessed by all RVU PFs whose
218 * RVU_PRIV_PF()_CFG[AF_ENA] bit is set.
219 */
220 union bdk_rvu_af_addr_s
221 {
222 uint64_t u;
223 struct bdk_rvu_af_addr_s_s
224 {
225 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
226 uint64_t reserved_33_63 : 31;
227 uint64_t block : 5; /**< [ 32: 28] Resource block enumerated by RVU_BLOCK_ADDR_E. */
228 uint64_t addr : 28; /**< [ 27: 0] Register address within [BLOCK]. */
229 #else /* Word 0 - Little Endian */
230 uint64_t addr : 28; /**< [ 27: 0] Register address within [BLOCK]. */
231 uint64_t block : 5; /**< [ 32: 28] Resource block enumerated by RVU_BLOCK_ADDR_E. */
232 uint64_t reserved_33_63 : 31;
233 #endif /* Word 0 - End */
234 } s;
235 /* struct bdk_rvu_af_addr_s_s cn; */
236 };
237
238 /**
239 * Structure rvu_func_addr_s
240 *
241 * RVU Function-unique Address Structure
242 * Address format for accessing function-unique registers in RVU PF/FUNC BAR2.
243 */
244 union bdk_rvu_func_addr_s
245 {
246 uint32_t u;
247 struct bdk_rvu_func_addr_s_s
248 {
249 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
250 uint32_t reserved_25_31 : 7;
251 uint32_t block : 5; /**< [ 24: 20] Resource block enumerated by RVU_BLOCK_ADDR_E. */
252 uint32_t lf_slot : 8; /**< [ 19: 12] Local function slot, or extended register address within the block's LF
253 slot 0, depending on [BLOCK]. */
254 uint32_t addr : 12; /**< [ 11: 0] Register address within the block and LF slot. */
255 #else /* Word 0 - Little Endian */
256 uint32_t addr : 12; /**< [ 11: 0] Register address within the block and LF slot. */
257 uint32_t lf_slot : 8; /**< [ 19: 12] Local function slot, or extended register address within the block's LF
258 slot 0, depending on [BLOCK]. */
259 uint32_t block : 5; /**< [ 24: 20] Resource block enumerated by RVU_BLOCK_ADDR_E. */
260 uint32_t reserved_25_31 : 7;
261 #endif /* Word 0 - End */
262 } s;
263 /* struct bdk_rvu_func_addr_s_s cn; */
264 };
265
266 /**
267 * Structure rvu_msix_vec_s
268 *
269 * RVU MSI-X Vector Structure
270 * Format of entries in the RVU MSI-X table region in LLC/DRAM. See
271 * RVU_PRIV_PF()_MSIX_CFG.
272 */
273 union bdk_rvu_msix_vec_s
274 {
275 uint64_t u[2];
276 struct bdk_rvu_msix_vec_s_s
277 {
278 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
279 uint64_t addr : 64; /**< [ 63: 0] IOVA to use for MSI-X delivery of this vector. Bits \<63:53\> are reserved.
280 Bit \<1:0\> are reserved for alignment. */
281 #else /* Word 0 - Little Endian */
282 uint64_t addr : 64; /**< [ 63: 0] IOVA to use for MSI-X delivery of this vector. Bits \<63:53\> are reserved.
283 Bit \<1:0\> are reserved for alignment. */
284 #endif /* Word 0 - End */
285 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 1 - Big Endian */
286 uint64_t reserved_98_127 : 30;
287 uint64_t pend : 1; /**< [ 97: 97] Vector's pending bit in the MSI-X PBA. */
288 uint64_t mask : 1; /**< [ 96: 96] When set, no MSI-X interrupts are sent to this vector. */
289 uint64_t data : 32; /**< [ 95: 64] Data to use for MSI-X delivery of this vector. */
290 #else /* Word 1 - Little Endian */
291 uint64_t data : 32; /**< [ 95: 64] Data to use for MSI-X delivery of this vector. */
292 uint64_t mask : 1; /**< [ 96: 96] When set, no MSI-X interrupts are sent to this vector. */
293 uint64_t pend : 1; /**< [ 97: 97] Vector's pending bit in the MSI-X PBA. */
294 uint64_t reserved_98_127 : 30;
295 #endif /* Word 1 - End */
296 } s;
297 /* struct bdk_rvu_msix_vec_s_s cn; */
298 };
299
300 /**
301 * Structure rvu_pf_func_s
302 *
303 * RVU PF Function Identification Structure
304 * Identifies an RVU PF/VF, and format of *_PRIV_LF()_CFG[PF_FUNC] in RVU
305 * resource blocks, e.g. NPA_PRIV_LF()_CFG[PF_FUNC].
306 *
307 * Internal:
308 * Also used for PF/VF identification on inter-coprocessor hardware
309 * interfaces (NPA, SSO, CPT, ...).
310 */
311 union bdk_rvu_pf_func_s
312 {
313 uint32_t u;
314 struct bdk_rvu_pf_func_s_s
315 {
316 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
317 uint32_t reserved_16_31 : 16;
318 uint32_t pf : 6; /**< [ 15: 10] RVU PF number. */
319 uint32_t func : 10; /**< [ 9: 0] Function within [PF]; 0 for the PF itself, else VF number plus 1. */
320 #else /* Word 0 - Little Endian */
321 uint32_t func : 10; /**< [ 9: 0] Function within [PF]; 0 for the PF itself, else VF number plus 1. */
322 uint32_t pf : 6; /**< [ 15: 10] RVU PF number. */
323 uint32_t reserved_16_31 : 16;
324 #endif /* Word 0 - End */
325 } s;
326 /* struct bdk_rvu_pf_func_s_s cn; */
327 };
328
329 /**
330 * Register (RVU_PF_BAR0) rvu_af_afpf#_mbox#
331 *
332 * RVU Admin Function AF/PF Mailbox Registers
333 */
334 union bdk_rvu_af_afpfx_mboxx
335 {
336 uint64_t u;
337 struct bdk_rvu_af_afpfx_mboxx_s
338 {
339 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
340 uint64_t data : 64; /**< [ 63: 0](R/W/H) Mailbox data. These AF registers access the 16-byte-per-PF PF/AF
341 mailbox. Each corresponding PF may access the same storage using
342 RVU_PF_PFAF_MBOX(). MBOX(0) is typically used for AF to PF
343 signaling, MBOX(1) for PF to AF.
344 Writing RVU_AF_AFPF()_MBOX(0) (but not RVU_PF_PFAF_MBOX(0)) will
345 set the corresponding
346 RVU_PF_INT[MBOX] which if appropriately enabled will send an
347 interrupt to the PF. */
348 #else /* Word 0 - Little Endian */
349 uint64_t data : 64; /**< [ 63: 0](R/W/H) Mailbox data. These AF registers access the 16-byte-per-PF PF/AF
350 mailbox. Each corresponding PF may access the same storage using
351 RVU_PF_PFAF_MBOX(). MBOX(0) is typically used for AF to PF
352 signaling, MBOX(1) for PF to AF.
353 Writing RVU_AF_AFPF()_MBOX(0) (but not RVU_PF_PFAF_MBOX(0)) will
354 set the corresponding
355 RVU_PF_INT[MBOX] which if appropriately enabled will send an
356 interrupt to the PF. */
357 #endif /* Word 0 - End */
358 } s;
359 /* struct bdk_rvu_af_afpfx_mboxx_s cn; */
360 };
361 typedef union bdk_rvu_af_afpfx_mboxx bdk_rvu_af_afpfx_mboxx_t;
362
363 static inline uint64_t BDK_RVU_AF_AFPFX_MBOXX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_RVU_AF_AFPFX_MBOXX(unsigned long a,unsigned long b)364 static inline uint64_t BDK_RVU_AF_AFPFX_MBOXX(unsigned long a, unsigned long b)
365 {
366 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=15) && (b<=1)))
367 return 0x850000002000ll + 0x10ll * ((a) & 0xf) + 8ll * ((b) & 0x1);
368 __bdk_csr_fatal("RVU_AF_AFPFX_MBOXX", 2, a, b, 0, 0);
369 }
370
371 #define typedef_BDK_RVU_AF_AFPFX_MBOXX(a,b) bdk_rvu_af_afpfx_mboxx_t
372 #define bustype_BDK_RVU_AF_AFPFX_MBOXX(a,b) BDK_CSR_TYPE_RVU_PF_BAR0
373 #define basename_BDK_RVU_AF_AFPFX_MBOXX(a,b) "RVU_AF_AFPFX_MBOXX"
374 #define device_bar_BDK_RVU_AF_AFPFX_MBOXX(a,b) 0x0 /* BAR0 */
375 #define busnum_BDK_RVU_AF_AFPFX_MBOXX(a,b) (a)
376 #define arguments_BDK_RVU_AF_AFPFX_MBOXX(a,b) (a),(b),-1,-1
377
378 /**
379 * Register (RVU_PF_BAR0) rvu_af_blk_rst
380 *
381 * RVU Master Admin Function Block Reset Register
382 */
383 union bdk_rvu_af_blk_rst
384 {
385 uint64_t u;
386 struct bdk_rvu_af_blk_rst_s
387 {
388 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
389 uint64_t reserved_2_63 : 62;
390 uint64_t busy : 1; /**< [ 1: 1](RO/H) When one, RVUM is busy completing reset. No access except the reading of this
391 bit should occur to RVUM until this is clear. */
392 uint64_t rst : 1; /**< [ 0: 0](WO) Write one to reset RVUM, except for privileged AF registers (RVU_PRIV_*).
393 Software must ensure that all RVUM activity is quiesced before writing one. */
394 #else /* Word 0 - Little Endian */
395 uint64_t rst : 1; /**< [ 0: 0](WO) Write one to reset RVUM, except for privileged AF registers (RVU_PRIV_*).
396 Software must ensure that all RVUM activity is quiesced before writing one. */
397 uint64_t busy : 1; /**< [ 1: 1](RO/H) When one, RVUM is busy completing reset. No access except the reading of this
398 bit should occur to RVUM until this is clear. */
399 uint64_t reserved_2_63 : 62;
400 #endif /* Word 0 - End */
401 } s;
402 /* struct bdk_rvu_af_blk_rst_s cn; */
403 };
404 typedef union bdk_rvu_af_blk_rst bdk_rvu_af_blk_rst_t;
405
406 #define BDK_RVU_AF_BLK_RST BDK_RVU_AF_BLK_RST_FUNC()
407 static inline uint64_t BDK_RVU_AF_BLK_RST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_BLK_RST_FUNC(void)408 static inline uint64_t BDK_RVU_AF_BLK_RST_FUNC(void)
409 {
410 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
411 return 0x850000000030ll;
412 __bdk_csr_fatal("RVU_AF_BLK_RST", 0, 0, 0, 0, 0);
413 }
414
415 #define typedef_BDK_RVU_AF_BLK_RST bdk_rvu_af_blk_rst_t
416 #define bustype_BDK_RVU_AF_BLK_RST BDK_CSR_TYPE_RVU_PF_BAR0
417 #define basename_BDK_RVU_AF_BLK_RST "RVU_AF_BLK_RST"
418 #define device_bar_BDK_RVU_AF_BLK_RST 0x0 /* BAR0 */
419 #define busnum_BDK_RVU_AF_BLK_RST 0
420 #define arguments_BDK_RVU_AF_BLK_RST -1,-1,-1,-1
421
422 /**
423 * Register (RVU_PF_BAR0) rvu_af_eco
424 *
425 * INTERNAL: RVU Admin Function ECO Register
426 */
427 union bdk_rvu_af_eco
428 {
429 uint64_t u;
430 struct bdk_rvu_af_eco_s
431 {
432 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
433 uint64_t reserved_32_63 : 32;
434 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) Internal:
435 Reserved for ECO usage. */
436 #else /* Word 0 - Little Endian */
437 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) Internal:
438 Reserved for ECO usage. */
439 uint64_t reserved_32_63 : 32;
440 #endif /* Word 0 - End */
441 } s;
442 /* struct bdk_rvu_af_eco_s cn; */
443 };
444 typedef union bdk_rvu_af_eco bdk_rvu_af_eco_t;
445
446 #define BDK_RVU_AF_ECO BDK_RVU_AF_ECO_FUNC()
447 static inline uint64_t BDK_RVU_AF_ECO_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_ECO_FUNC(void)448 static inline uint64_t BDK_RVU_AF_ECO_FUNC(void)
449 {
450 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
451 return 0x850000000020ll;
452 __bdk_csr_fatal("RVU_AF_ECO", 0, 0, 0, 0, 0);
453 }
454
455 #define typedef_BDK_RVU_AF_ECO bdk_rvu_af_eco_t
456 #define bustype_BDK_RVU_AF_ECO BDK_CSR_TYPE_RVU_PF_BAR0
457 #define basename_BDK_RVU_AF_ECO "RVU_AF_ECO"
458 #define device_bar_BDK_RVU_AF_ECO 0x0 /* BAR0 */
459 #define busnum_BDK_RVU_AF_ECO 0
460 #define arguments_BDK_RVU_AF_ECO -1,-1,-1,-1
461
462 /**
463 * Register (RVU_PF_BAR0) rvu_af_gen_int
464 *
465 * RVU Admin Function General Interrupt Register
466 * This register contains General interrupt summary bits.
467 */
468 union bdk_rvu_af_gen_int
469 {
470 uint64_t u;
471 struct bdk_rvu_af_gen_int_s
472 {
473 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
474 uint64_t reserved_2_63 : 62;
475 uint64_t msix_fault : 1; /**< [ 1: 1](R/W1C/H) Received MSIX-X table read response with fault data */
476 uint64_t unmapped : 1; /**< [ 0: 0](R/W1C/H) Received a register read or write request to an unmapped or disabled PF or
477 VF. Specifically:
478 * A PF/VF BAR2 access in a PF whose RVU_PRIV_PF()_CFG[ENA] is
479 clear.
480 * A VF BAR2 access to a VF number that is greater than or equal to the
481 associated PF's RVU_PRIV_PF()_CFG[NVF]. */
482 #else /* Word 0 - Little Endian */
483 uint64_t unmapped : 1; /**< [ 0: 0](R/W1C/H) Received a register read or write request to an unmapped or disabled PF or
484 VF. Specifically:
485 * A PF/VF BAR2 access in a PF whose RVU_PRIV_PF()_CFG[ENA] is
486 clear.
487 * A VF BAR2 access to a VF number that is greater than or equal to the
488 associated PF's RVU_PRIV_PF()_CFG[NVF]. */
489 uint64_t msix_fault : 1; /**< [ 1: 1](R/W1C/H) Received MSIX-X table read response with fault data */
490 uint64_t reserved_2_63 : 62;
491 #endif /* Word 0 - End */
492 } s;
493 /* struct bdk_rvu_af_gen_int_s cn; */
494 };
495 typedef union bdk_rvu_af_gen_int bdk_rvu_af_gen_int_t;
496
497 #define BDK_RVU_AF_GEN_INT BDK_RVU_AF_GEN_INT_FUNC()
498 static inline uint64_t BDK_RVU_AF_GEN_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_GEN_INT_FUNC(void)499 static inline uint64_t BDK_RVU_AF_GEN_INT_FUNC(void)
500 {
501 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
502 return 0x850000000120ll;
503 __bdk_csr_fatal("RVU_AF_GEN_INT", 0, 0, 0, 0, 0);
504 }
505
506 #define typedef_BDK_RVU_AF_GEN_INT bdk_rvu_af_gen_int_t
507 #define bustype_BDK_RVU_AF_GEN_INT BDK_CSR_TYPE_RVU_PF_BAR0
508 #define basename_BDK_RVU_AF_GEN_INT "RVU_AF_GEN_INT"
509 #define device_bar_BDK_RVU_AF_GEN_INT 0x0 /* BAR0 */
510 #define busnum_BDK_RVU_AF_GEN_INT 0
511 #define arguments_BDK_RVU_AF_GEN_INT -1,-1,-1,-1
512
513 /**
514 * Register (RVU_PF_BAR0) rvu_af_gen_int_ena_w1c
515 *
516 * RVU Admin Function General Interrupt Enable Clear Register
517 * This register clears interrupt enable bits.
518 */
519 union bdk_rvu_af_gen_int_ena_w1c
520 {
521 uint64_t u;
522 struct bdk_rvu_af_gen_int_ena_w1c_s
523 {
524 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
525 uint64_t reserved_2_63 : 62;
526 uint64_t msix_fault : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for RVU_AF_GEN_INT[MSIX_FAULT]. */
527 uint64_t unmapped : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RVU_AF_GEN_INT[UNMAPPED]. */
528 #else /* Word 0 - Little Endian */
529 uint64_t unmapped : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RVU_AF_GEN_INT[UNMAPPED]. */
530 uint64_t msix_fault : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for RVU_AF_GEN_INT[MSIX_FAULT]. */
531 uint64_t reserved_2_63 : 62;
532 #endif /* Word 0 - End */
533 } s;
534 /* struct bdk_rvu_af_gen_int_ena_w1c_s cn; */
535 };
536 typedef union bdk_rvu_af_gen_int_ena_w1c bdk_rvu_af_gen_int_ena_w1c_t;
537
538 #define BDK_RVU_AF_GEN_INT_ENA_W1C BDK_RVU_AF_GEN_INT_ENA_W1C_FUNC()
539 static inline uint64_t BDK_RVU_AF_GEN_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_GEN_INT_ENA_W1C_FUNC(void)540 static inline uint64_t BDK_RVU_AF_GEN_INT_ENA_W1C_FUNC(void)
541 {
542 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
543 return 0x850000000138ll;
544 __bdk_csr_fatal("RVU_AF_GEN_INT_ENA_W1C", 0, 0, 0, 0, 0);
545 }
546
547 #define typedef_BDK_RVU_AF_GEN_INT_ENA_W1C bdk_rvu_af_gen_int_ena_w1c_t
548 #define bustype_BDK_RVU_AF_GEN_INT_ENA_W1C BDK_CSR_TYPE_RVU_PF_BAR0
549 #define basename_BDK_RVU_AF_GEN_INT_ENA_W1C "RVU_AF_GEN_INT_ENA_W1C"
550 #define device_bar_BDK_RVU_AF_GEN_INT_ENA_W1C 0x0 /* BAR0 */
551 #define busnum_BDK_RVU_AF_GEN_INT_ENA_W1C 0
552 #define arguments_BDK_RVU_AF_GEN_INT_ENA_W1C -1,-1,-1,-1
553
554 /**
555 * Register (RVU_PF_BAR0) rvu_af_gen_int_ena_w1s
556 *
557 * RVU Admin Function General Interrupt Enable Set Register
558 * This register sets interrupt enable bits.
559 */
560 union bdk_rvu_af_gen_int_ena_w1s
561 {
562 uint64_t u;
563 struct bdk_rvu_af_gen_int_ena_w1s_s
564 {
565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
566 uint64_t reserved_2_63 : 62;
567 uint64_t msix_fault : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for RVU_AF_GEN_INT[MSIX_FAULT]. */
568 uint64_t unmapped : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RVU_AF_GEN_INT[UNMAPPED]. */
569 #else /* Word 0 - Little Endian */
570 uint64_t unmapped : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RVU_AF_GEN_INT[UNMAPPED]. */
571 uint64_t msix_fault : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for RVU_AF_GEN_INT[MSIX_FAULT]. */
572 uint64_t reserved_2_63 : 62;
573 #endif /* Word 0 - End */
574 } s;
575 /* struct bdk_rvu_af_gen_int_ena_w1s_s cn; */
576 };
577 typedef union bdk_rvu_af_gen_int_ena_w1s bdk_rvu_af_gen_int_ena_w1s_t;
578
579 #define BDK_RVU_AF_GEN_INT_ENA_W1S BDK_RVU_AF_GEN_INT_ENA_W1S_FUNC()
580 static inline uint64_t BDK_RVU_AF_GEN_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_GEN_INT_ENA_W1S_FUNC(void)581 static inline uint64_t BDK_RVU_AF_GEN_INT_ENA_W1S_FUNC(void)
582 {
583 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
584 return 0x850000000130ll;
585 __bdk_csr_fatal("RVU_AF_GEN_INT_ENA_W1S", 0, 0, 0, 0, 0);
586 }
587
588 #define typedef_BDK_RVU_AF_GEN_INT_ENA_W1S bdk_rvu_af_gen_int_ena_w1s_t
589 #define bustype_BDK_RVU_AF_GEN_INT_ENA_W1S BDK_CSR_TYPE_RVU_PF_BAR0
590 #define basename_BDK_RVU_AF_GEN_INT_ENA_W1S "RVU_AF_GEN_INT_ENA_W1S"
591 #define device_bar_BDK_RVU_AF_GEN_INT_ENA_W1S 0x0 /* BAR0 */
592 #define busnum_BDK_RVU_AF_GEN_INT_ENA_W1S 0
593 #define arguments_BDK_RVU_AF_GEN_INT_ENA_W1S -1,-1,-1,-1
594
595 /**
596 * Register (RVU_PF_BAR0) rvu_af_gen_int_w1s
597 *
598 * RVU Admin Function General Interrupt Set Register
599 * This register sets interrupt bits.
600 */
601 union bdk_rvu_af_gen_int_w1s
602 {
603 uint64_t u;
604 struct bdk_rvu_af_gen_int_w1s_s
605 {
606 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
607 uint64_t reserved_2_63 : 62;
608 uint64_t msix_fault : 1; /**< [ 1: 1](R/W1S/H) Reads or sets RVU_AF_GEN_INT[MSIX_FAULT]. */
609 uint64_t unmapped : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RVU_AF_GEN_INT[UNMAPPED]. */
610 #else /* Word 0 - Little Endian */
611 uint64_t unmapped : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RVU_AF_GEN_INT[UNMAPPED]. */
612 uint64_t msix_fault : 1; /**< [ 1: 1](R/W1S/H) Reads or sets RVU_AF_GEN_INT[MSIX_FAULT]. */
613 uint64_t reserved_2_63 : 62;
614 #endif /* Word 0 - End */
615 } s;
616 /* struct bdk_rvu_af_gen_int_w1s_s cn; */
617 };
618 typedef union bdk_rvu_af_gen_int_w1s bdk_rvu_af_gen_int_w1s_t;
619
620 #define BDK_RVU_AF_GEN_INT_W1S BDK_RVU_AF_GEN_INT_W1S_FUNC()
621 static inline uint64_t BDK_RVU_AF_GEN_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_GEN_INT_W1S_FUNC(void)622 static inline uint64_t BDK_RVU_AF_GEN_INT_W1S_FUNC(void)
623 {
624 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
625 return 0x850000000128ll;
626 __bdk_csr_fatal("RVU_AF_GEN_INT_W1S", 0, 0, 0, 0, 0);
627 }
628
629 #define typedef_BDK_RVU_AF_GEN_INT_W1S bdk_rvu_af_gen_int_w1s_t
630 #define bustype_BDK_RVU_AF_GEN_INT_W1S BDK_CSR_TYPE_RVU_PF_BAR0
631 #define basename_BDK_RVU_AF_GEN_INT_W1S "RVU_AF_GEN_INT_W1S"
632 #define device_bar_BDK_RVU_AF_GEN_INT_W1S 0x0 /* BAR0 */
633 #define busnum_BDK_RVU_AF_GEN_INT_W1S 0
634 #define arguments_BDK_RVU_AF_GEN_INT_W1S -1,-1,-1,-1
635
636 /**
637 * Register (RVU_PF_BAR0) rvu_af_hwvf_rst
638 *
639 * RVU Admin Function Hardware VF Soft Reset Register
640 */
641 union bdk_rvu_af_hwvf_rst
642 {
643 uint64_t u;
644 struct bdk_rvu_af_hwvf_rst_s
645 {
646 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
647 uint64_t reserved_13_63 : 51;
648 uint64_t exec : 1; /**< [ 12: 12](R/W1S/H) Execute HWVF soft reset. When software writes a one to set this bit, hardware
649 resets the RVUM resources of the hardware VF selected by [HWVF] and the
650 associated MSI-X table in LLC/DRAM specified by
651 RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_OFFSET,VF_MSIXT_SIZEM1].
652 Hardware clears this bit when done. */
653 uint64_t reserved_8_11 : 4;
654 uint64_t hwvf : 8; /**< [ 7: 0](R/W) Hardware VF that is reset when [EXEC] is set. */
655 #else /* Word 0 - Little Endian */
656 uint64_t hwvf : 8; /**< [ 7: 0](R/W) Hardware VF that is reset when [EXEC] is set. */
657 uint64_t reserved_8_11 : 4;
658 uint64_t exec : 1; /**< [ 12: 12](R/W1S/H) Execute HWVF soft reset. When software writes a one to set this bit, hardware
659 resets the RVUM resources of the hardware VF selected by [HWVF] and the
660 associated MSI-X table in LLC/DRAM specified by
661 RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_OFFSET,VF_MSIXT_SIZEM1].
662 Hardware clears this bit when done. */
663 uint64_t reserved_13_63 : 51;
664 #endif /* Word 0 - End */
665 } s;
666 /* struct bdk_rvu_af_hwvf_rst_s cn; */
667 };
668 typedef union bdk_rvu_af_hwvf_rst bdk_rvu_af_hwvf_rst_t;
669
670 #define BDK_RVU_AF_HWVF_RST BDK_RVU_AF_HWVF_RST_FUNC()
671 static inline uint64_t BDK_RVU_AF_HWVF_RST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_HWVF_RST_FUNC(void)672 static inline uint64_t BDK_RVU_AF_HWVF_RST_FUNC(void)
673 {
674 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
675 return 0x850000002850ll;
676 __bdk_csr_fatal("RVU_AF_HWVF_RST", 0, 0, 0, 0, 0);
677 }
678
679 #define typedef_BDK_RVU_AF_HWVF_RST bdk_rvu_af_hwvf_rst_t
680 #define bustype_BDK_RVU_AF_HWVF_RST BDK_CSR_TYPE_RVU_PF_BAR0
681 #define basename_BDK_RVU_AF_HWVF_RST "RVU_AF_HWVF_RST"
682 #define device_bar_BDK_RVU_AF_HWVF_RST 0x0 /* BAR0 */
683 #define busnum_BDK_RVU_AF_HWVF_RST 0
684 #define arguments_BDK_RVU_AF_HWVF_RST -1,-1,-1,-1
685
686 /**
687 * Register (RVU_PF_BAR0) rvu_af_msixtr_base
688 *
689 * RVU Admin Function MSI-X Table Region Base-Address Register
690 */
691 union bdk_rvu_af_msixtr_base
692 {
693 uint64_t u;
694 struct bdk_rvu_af_msixtr_base_s
695 {
696 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
697 uint64_t reserved_53_63 : 11;
698 uint64_t addr : 46; /**< [ 52: 7](R/W) Base IOVA of MSI-X table region in LLC/DRAM. IOVA bits \<6:0\> are always zero.
699 See RVU_PRIV_PF()_MSIX_CFG. */
700 uint64_t reserved_0_6 : 7;
701 #else /* Word 0 - Little Endian */
702 uint64_t reserved_0_6 : 7;
703 uint64_t addr : 46; /**< [ 52: 7](R/W) Base IOVA of MSI-X table region in LLC/DRAM. IOVA bits \<6:0\> are always zero.
704 See RVU_PRIV_PF()_MSIX_CFG. */
705 uint64_t reserved_53_63 : 11;
706 #endif /* Word 0 - End */
707 } s;
708 /* struct bdk_rvu_af_msixtr_base_s cn; */
709 };
710 typedef union bdk_rvu_af_msixtr_base bdk_rvu_af_msixtr_base_t;
711
712 #define BDK_RVU_AF_MSIXTR_BASE BDK_RVU_AF_MSIXTR_BASE_FUNC()
713 static inline uint64_t BDK_RVU_AF_MSIXTR_BASE_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_MSIXTR_BASE_FUNC(void)714 static inline uint64_t BDK_RVU_AF_MSIXTR_BASE_FUNC(void)
715 {
716 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
717 return 0x850000000010ll;
718 __bdk_csr_fatal("RVU_AF_MSIXTR_BASE", 0, 0, 0, 0, 0);
719 }
720
721 #define typedef_BDK_RVU_AF_MSIXTR_BASE bdk_rvu_af_msixtr_base_t
722 #define bustype_BDK_RVU_AF_MSIXTR_BASE BDK_CSR_TYPE_RVU_PF_BAR0
723 #define basename_BDK_RVU_AF_MSIXTR_BASE "RVU_AF_MSIXTR_BASE"
724 #define device_bar_BDK_RVU_AF_MSIXTR_BASE 0x0 /* BAR0 */
725 #define busnum_BDK_RVU_AF_MSIXTR_BASE 0
726 #define arguments_BDK_RVU_AF_MSIXTR_BASE -1,-1,-1,-1
727
728 /**
729 * Register (RVU_PF_BAR0) rvu_af_pf_bar4_addr
730 *
731 * RVU Admin Function PF BAR4 Address Registers
732 */
733 union bdk_rvu_af_pf_bar4_addr
734 {
735 uint64_t u;
736 struct bdk_rvu_af_pf_bar4_addr_s
737 {
738 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
739 uint64_t addr : 48; /**< [ 63: 16](R/W) Programmable base address of up to 16 consecutive 64 KB
740 pages in DRAM (one per PF). May be used as PF/AF mailbox memory in addition to
741 RVU_AF_AFPF()_MBOX()/RVU_PF_PFAF_MBOX().
742 Provides PCC_EA_ENTRY_S[BASEH,BASEL] value advertised by PF BAR4's entry in
743 PCCPF_XXX_EA_ENTRY(). */
744 uint64_t reserved_0_15 : 16;
745 #else /* Word 0 - Little Endian */
746 uint64_t reserved_0_15 : 16;
747 uint64_t addr : 48; /**< [ 63: 16](R/W) Programmable base address of up to 16 consecutive 64 KB
748 pages in DRAM (one per PF). May be used as PF/AF mailbox memory in addition to
749 RVU_AF_AFPF()_MBOX()/RVU_PF_PFAF_MBOX().
750 Provides PCC_EA_ENTRY_S[BASEH,BASEL] value advertised by PF BAR4's entry in
751 PCCPF_XXX_EA_ENTRY(). */
752 #endif /* Word 0 - End */
753 } s;
754 /* struct bdk_rvu_af_pf_bar4_addr_s cn; */
755 };
756 typedef union bdk_rvu_af_pf_bar4_addr bdk_rvu_af_pf_bar4_addr_t;
757
758 #define BDK_RVU_AF_PF_BAR4_ADDR BDK_RVU_AF_PF_BAR4_ADDR_FUNC()
759 static inline uint64_t BDK_RVU_AF_PF_BAR4_ADDR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PF_BAR4_ADDR_FUNC(void)760 static inline uint64_t BDK_RVU_AF_PF_BAR4_ADDR_FUNC(void)
761 {
762 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
763 return 0x850000000040ll;
764 __bdk_csr_fatal("RVU_AF_PF_BAR4_ADDR", 0, 0, 0, 0, 0);
765 }
766
767 #define typedef_BDK_RVU_AF_PF_BAR4_ADDR bdk_rvu_af_pf_bar4_addr_t
768 #define bustype_BDK_RVU_AF_PF_BAR4_ADDR BDK_CSR_TYPE_RVU_PF_BAR0
769 #define basename_BDK_RVU_AF_PF_BAR4_ADDR "RVU_AF_PF_BAR4_ADDR"
770 #define device_bar_BDK_RVU_AF_PF_BAR4_ADDR 0x0 /* BAR0 */
771 #define busnum_BDK_RVU_AF_PF_BAR4_ADDR 0
772 #define arguments_BDK_RVU_AF_PF_BAR4_ADDR -1,-1,-1,-1
773
774 /**
775 * Register (RVU_PF_BAR0) rvu_af_pf_rst
776 *
777 * RVU Admin Function PF Soft Reset Register
778 */
779 union bdk_rvu_af_pf_rst
780 {
781 uint64_t u;
782 struct bdk_rvu_af_pf_rst_s
783 {
784 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
785 uint64_t reserved_13_63 : 51;
786 uint64_t exec : 1; /**< [ 12: 12](R/W1S/H) Execute PF soft reset. When software writes a one to set this bit, hardware
787 resets the RVUM resources of the physical function selected by [PF] and the
788 associated MSI-X table in LLC/DRAM specified by
789 RVU_PRIV_PF()_MSIX_CFG[PF_MSIXT_OFFSET,PF_MSIXT_SIZEM1].
790 Hardware clears this bit when done.
791 Note this does not reset HWVFs which are mapped to the PF. */
792 uint64_t reserved_4_11 : 8;
793 uint64_t pf : 4; /**< [ 3: 0](R/W) Physical function that is reset when [EXEC] is set. */
794 #else /* Word 0 - Little Endian */
795 uint64_t pf : 4; /**< [ 3: 0](R/W) Physical function that is reset when [EXEC] is set. */
796 uint64_t reserved_4_11 : 8;
797 uint64_t exec : 1; /**< [ 12: 12](R/W1S/H) Execute PF soft reset. When software writes a one to set this bit, hardware
798 resets the RVUM resources of the physical function selected by [PF] and the
799 associated MSI-X table in LLC/DRAM specified by
800 RVU_PRIV_PF()_MSIX_CFG[PF_MSIXT_OFFSET,PF_MSIXT_SIZEM1].
801 Hardware clears this bit when done.
802 Note this does not reset HWVFs which are mapped to the PF. */
803 uint64_t reserved_13_63 : 51;
804 #endif /* Word 0 - End */
805 } s;
806 /* struct bdk_rvu_af_pf_rst_s cn; */
807 };
808 typedef union bdk_rvu_af_pf_rst bdk_rvu_af_pf_rst_t;
809
810 #define BDK_RVU_AF_PF_RST BDK_RVU_AF_PF_RST_FUNC()
811 static inline uint64_t BDK_RVU_AF_PF_RST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PF_RST_FUNC(void)812 static inline uint64_t BDK_RVU_AF_PF_RST_FUNC(void)
813 {
814 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
815 return 0x850000002840ll;
816 __bdk_csr_fatal("RVU_AF_PF_RST", 0, 0, 0, 0, 0);
817 }
818
819 #define typedef_BDK_RVU_AF_PF_RST bdk_rvu_af_pf_rst_t
820 #define bustype_BDK_RVU_AF_PF_RST BDK_CSR_TYPE_RVU_PF_BAR0
821 #define basename_BDK_RVU_AF_PF_RST "RVU_AF_PF_RST"
822 #define device_bar_BDK_RVU_AF_PF_RST 0x0 /* BAR0 */
823 #define busnum_BDK_RVU_AF_PF_RST 0
824 #define arguments_BDK_RVU_AF_PF_RST -1,-1,-1,-1
825
826 /**
827 * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int
828 *
829 * RVU Admin Function PF to AF Mailbox Interrupt Registers
830 */
831 union bdk_rvu_af_pfaf_mbox_int
832 {
833 uint64_t u;
834 struct bdk_rvu_af_pfaf_mbox_int_s
835 {
836 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
837 uint64_t mbox : 64; /**< [ 63: 0](R/W1C/H) Mailbox interrupt bit per PF.
838 Each bit is set when the PF writes to the corresponding
839 RVU_PF_PFAF_MBOX(1) register. */
840 #else /* Word 0 - Little Endian */
841 uint64_t mbox : 64; /**< [ 63: 0](R/W1C/H) Mailbox interrupt bit per PF.
842 Each bit is set when the PF writes to the corresponding
843 RVU_PF_PFAF_MBOX(1) register. */
844 #endif /* Word 0 - End */
845 } s;
846 /* struct bdk_rvu_af_pfaf_mbox_int_s cn; */
847 };
848 typedef union bdk_rvu_af_pfaf_mbox_int bdk_rvu_af_pfaf_mbox_int_t;
849
850 #define BDK_RVU_AF_PFAF_MBOX_INT BDK_RVU_AF_PFAF_MBOX_INT_FUNC()
851 static inline uint64_t BDK_RVU_AF_PFAF_MBOX_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFAF_MBOX_INT_FUNC(void)852 static inline uint64_t BDK_RVU_AF_PFAF_MBOX_INT_FUNC(void)
853 {
854 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
855 return 0x850000002880ll;
856 __bdk_csr_fatal("RVU_AF_PFAF_MBOX_INT", 0, 0, 0, 0, 0);
857 }
858
859 #define typedef_BDK_RVU_AF_PFAF_MBOX_INT bdk_rvu_af_pfaf_mbox_int_t
860 #define bustype_BDK_RVU_AF_PFAF_MBOX_INT BDK_CSR_TYPE_RVU_PF_BAR0
861 #define basename_BDK_RVU_AF_PFAF_MBOX_INT "RVU_AF_PFAF_MBOX_INT"
862 #define device_bar_BDK_RVU_AF_PFAF_MBOX_INT 0x0 /* BAR0 */
863 #define busnum_BDK_RVU_AF_PFAF_MBOX_INT 0
864 #define arguments_BDK_RVU_AF_PFAF_MBOX_INT -1,-1,-1,-1
865
866 /**
867 * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_ena_w1c
868 *
869 * RVU Admin Function PF to AF Mailbox Interrupt Enable Clear Registers
870 * This register clears interrupt enable bits.
871 */
872 union bdk_rvu_af_pfaf_mbox_int_ena_w1c
873 {
874 uint64_t u;
875 struct bdk_rvu_af_pfaf_mbox_int_ena_w1c_s
876 {
877 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
878 uint64_t mbox : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_AF_PFAF_MBOX_INT[MBOX]. */
879 #else /* Word 0 - Little Endian */
880 uint64_t mbox : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_AF_PFAF_MBOX_INT[MBOX]. */
881 #endif /* Word 0 - End */
882 } s;
883 /* struct bdk_rvu_af_pfaf_mbox_int_ena_w1c_s cn; */
884 };
885 typedef union bdk_rvu_af_pfaf_mbox_int_ena_w1c bdk_rvu_af_pfaf_mbox_int_ena_w1c_t;
886
887 #define BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C_FUNC()
888 static inline uint64_t BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C_FUNC(void)889 static inline uint64_t BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C_FUNC(void)
890 {
891 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
892 return 0x850000002898ll;
893 __bdk_csr_fatal("RVU_AF_PFAF_MBOX_INT_ENA_W1C", 0, 0, 0, 0, 0);
894 }
895
896 #define typedef_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C bdk_rvu_af_pfaf_mbox_int_ena_w1c_t
897 #define bustype_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C BDK_CSR_TYPE_RVU_PF_BAR0
898 #define basename_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C "RVU_AF_PFAF_MBOX_INT_ENA_W1C"
899 #define device_bar_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C 0x0 /* BAR0 */
900 #define busnum_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C 0
901 #define arguments_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1C -1,-1,-1,-1
902
903 /**
904 * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_ena_w1s
905 *
906 * RVU Admin Function PF to AF Mailbox Interrupt Enable Set Registers
907 * This register sets interrupt enable bits.
908 */
909 union bdk_rvu_af_pfaf_mbox_int_ena_w1s
910 {
911 uint64_t u;
912 struct bdk_rvu_af_pfaf_mbox_int_ena_w1s_s
913 {
914 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
915 uint64_t mbox : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_AF_PFAF_MBOX_INT[MBOX]. */
916 #else /* Word 0 - Little Endian */
917 uint64_t mbox : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_AF_PFAF_MBOX_INT[MBOX]. */
918 #endif /* Word 0 - End */
919 } s;
920 /* struct bdk_rvu_af_pfaf_mbox_int_ena_w1s_s cn; */
921 };
922 typedef union bdk_rvu_af_pfaf_mbox_int_ena_w1s bdk_rvu_af_pfaf_mbox_int_ena_w1s_t;
923
924 #define BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S_FUNC()
925 static inline uint64_t BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S_FUNC(void)926 static inline uint64_t BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S_FUNC(void)
927 {
928 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
929 return 0x850000002890ll;
930 __bdk_csr_fatal("RVU_AF_PFAF_MBOX_INT_ENA_W1S", 0, 0, 0, 0, 0);
931 }
932
933 #define typedef_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S bdk_rvu_af_pfaf_mbox_int_ena_w1s_t
934 #define bustype_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S BDK_CSR_TYPE_RVU_PF_BAR0
935 #define basename_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S "RVU_AF_PFAF_MBOX_INT_ENA_W1S"
936 #define device_bar_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S 0x0 /* BAR0 */
937 #define busnum_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S 0
938 #define arguments_BDK_RVU_AF_PFAF_MBOX_INT_ENA_W1S -1,-1,-1,-1
939
940 /**
941 * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_w1s
942 *
943 * RVU Admin Function PF to AF Mailbox Interrupt Set Registers
944 * This register sets interrupt bits.
945 */
946 union bdk_rvu_af_pfaf_mbox_int_w1s
947 {
948 uint64_t u;
949 struct bdk_rvu_af_pfaf_mbox_int_w1s_s
950 {
951 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
952 uint64_t mbox : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_AF_PFAF_MBOX_INT[MBOX]. */
953 #else /* Word 0 - Little Endian */
954 uint64_t mbox : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_AF_PFAF_MBOX_INT[MBOX]. */
955 #endif /* Word 0 - End */
956 } s;
957 /* struct bdk_rvu_af_pfaf_mbox_int_w1s_s cn; */
958 };
959 typedef union bdk_rvu_af_pfaf_mbox_int_w1s bdk_rvu_af_pfaf_mbox_int_w1s_t;
960
961 #define BDK_RVU_AF_PFAF_MBOX_INT_W1S BDK_RVU_AF_PFAF_MBOX_INT_W1S_FUNC()
962 static inline uint64_t BDK_RVU_AF_PFAF_MBOX_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFAF_MBOX_INT_W1S_FUNC(void)963 static inline uint64_t BDK_RVU_AF_PFAF_MBOX_INT_W1S_FUNC(void)
964 {
965 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
966 return 0x850000002888ll;
967 __bdk_csr_fatal("RVU_AF_PFAF_MBOX_INT_W1S", 0, 0, 0, 0, 0);
968 }
969
970 #define typedef_BDK_RVU_AF_PFAF_MBOX_INT_W1S bdk_rvu_af_pfaf_mbox_int_w1s_t
971 #define bustype_BDK_RVU_AF_PFAF_MBOX_INT_W1S BDK_CSR_TYPE_RVU_PF_BAR0
972 #define basename_BDK_RVU_AF_PFAF_MBOX_INT_W1S "RVU_AF_PFAF_MBOX_INT_W1S"
973 #define device_bar_BDK_RVU_AF_PFAF_MBOX_INT_W1S 0x0 /* BAR0 */
974 #define busnum_BDK_RVU_AF_PFAF_MBOX_INT_W1S 0
975 #define arguments_BDK_RVU_AF_PFAF_MBOX_INT_W1S -1,-1,-1,-1
976
977 /**
978 * Register (RVU_PF_BAR0) rvu_af_pfflr_int
979 *
980 * RVU Admin Function PF Function Level Reset Interrupt Registers
981 */
982 union bdk_rvu_af_pfflr_int
983 {
984 uint64_t u;
985 struct bdk_rvu_af_pfflr_int_s
986 {
987 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
988 uint64_t flr : 64; /**< [ 63: 0](R/W1C/H) FLR interrupt bit per PF.
989
990 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, each bit is set along with
991 the corresponding bit in RVU_AF_PFTRPEND when function level reset is
992 initiated for the associated PF, i.e. a one is written to
993 PCCPF_XXX_E_DEV_CTL[BCR_FLR]. */
994 #else /* Word 0 - Little Endian */
995 uint64_t flr : 64; /**< [ 63: 0](R/W1C/H) FLR interrupt bit per PF.
996
997 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, each bit is set along with
998 the corresponding bit in RVU_AF_PFTRPEND when function level reset is
999 initiated for the associated PF, i.e. a one is written to
1000 PCCPF_XXX_E_DEV_CTL[BCR_FLR]. */
1001 #endif /* Word 0 - End */
1002 } s;
1003 /* struct bdk_rvu_af_pfflr_int_s cn; */
1004 };
1005 typedef union bdk_rvu_af_pfflr_int bdk_rvu_af_pfflr_int_t;
1006
1007 #define BDK_RVU_AF_PFFLR_INT BDK_RVU_AF_PFFLR_INT_FUNC()
1008 static inline uint64_t BDK_RVU_AF_PFFLR_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFFLR_INT_FUNC(void)1009 static inline uint64_t BDK_RVU_AF_PFFLR_INT_FUNC(void)
1010 {
1011 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1012 return 0x8500000028a0ll;
1013 __bdk_csr_fatal("RVU_AF_PFFLR_INT", 0, 0, 0, 0, 0);
1014 }
1015
1016 #define typedef_BDK_RVU_AF_PFFLR_INT bdk_rvu_af_pfflr_int_t
1017 #define bustype_BDK_RVU_AF_PFFLR_INT BDK_CSR_TYPE_RVU_PF_BAR0
1018 #define basename_BDK_RVU_AF_PFFLR_INT "RVU_AF_PFFLR_INT"
1019 #define device_bar_BDK_RVU_AF_PFFLR_INT 0x0 /* BAR0 */
1020 #define busnum_BDK_RVU_AF_PFFLR_INT 0
1021 #define arguments_BDK_RVU_AF_PFFLR_INT -1,-1,-1,-1
1022
1023 /**
1024 * Register (RVU_PF_BAR0) rvu_af_pfflr_int_ena_w1c
1025 *
1026 * RVU Admin Function PF Function Level Reset Interrupt Enable Clear Registers
1027 * This register clears interrupt enable bits.
1028 */
1029 union bdk_rvu_af_pfflr_int_ena_w1c
1030 {
1031 uint64_t u;
1032 struct bdk_rvu_af_pfflr_int_ena_w1c_s
1033 {
1034 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1035 uint64_t flr : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_AF_PFFLR_INT[FLR]. */
1036 #else /* Word 0 - Little Endian */
1037 uint64_t flr : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_AF_PFFLR_INT[FLR]. */
1038 #endif /* Word 0 - End */
1039 } s;
1040 /* struct bdk_rvu_af_pfflr_int_ena_w1c_s cn; */
1041 };
1042 typedef union bdk_rvu_af_pfflr_int_ena_w1c bdk_rvu_af_pfflr_int_ena_w1c_t;
1043
1044 #define BDK_RVU_AF_PFFLR_INT_ENA_W1C BDK_RVU_AF_PFFLR_INT_ENA_W1C_FUNC()
1045 static inline uint64_t BDK_RVU_AF_PFFLR_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFFLR_INT_ENA_W1C_FUNC(void)1046 static inline uint64_t BDK_RVU_AF_PFFLR_INT_ENA_W1C_FUNC(void)
1047 {
1048 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1049 return 0x8500000028b8ll;
1050 __bdk_csr_fatal("RVU_AF_PFFLR_INT_ENA_W1C", 0, 0, 0, 0, 0);
1051 }
1052
1053 #define typedef_BDK_RVU_AF_PFFLR_INT_ENA_W1C bdk_rvu_af_pfflr_int_ena_w1c_t
1054 #define bustype_BDK_RVU_AF_PFFLR_INT_ENA_W1C BDK_CSR_TYPE_RVU_PF_BAR0
1055 #define basename_BDK_RVU_AF_PFFLR_INT_ENA_W1C "RVU_AF_PFFLR_INT_ENA_W1C"
1056 #define device_bar_BDK_RVU_AF_PFFLR_INT_ENA_W1C 0x0 /* BAR0 */
1057 #define busnum_BDK_RVU_AF_PFFLR_INT_ENA_W1C 0
1058 #define arguments_BDK_RVU_AF_PFFLR_INT_ENA_W1C -1,-1,-1,-1
1059
1060 /**
1061 * Register (RVU_PF_BAR0) rvu_af_pfflr_int_ena_w1s
1062 *
1063 * RVU Admin Function PF Function Level Reset Interrupt Enable Set Registers
1064 * This register sets interrupt enable bits.
1065 */
1066 union bdk_rvu_af_pfflr_int_ena_w1s
1067 {
1068 uint64_t u;
1069 struct bdk_rvu_af_pfflr_int_ena_w1s_s
1070 {
1071 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1072 uint64_t flr : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_AF_PFFLR_INT[FLR]. */
1073 #else /* Word 0 - Little Endian */
1074 uint64_t flr : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_AF_PFFLR_INT[FLR]. */
1075 #endif /* Word 0 - End */
1076 } s;
1077 /* struct bdk_rvu_af_pfflr_int_ena_w1s_s cn; */
1078 };
1079 typedef union bdk_rvu_af_pfflr_int_ena_w1s bdk_rvu_af_pfflr_int_ena_w1s_t;
1080
1081 #define BDK_RVU_AF_PFFLR_INT_ENA_W1S BDK_RVU_AF_PFFLR_INT_ENA_W1S_FUNC()
1082 static inline uint64_t BDK_RVU_AF_PFFLR_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFFLR_INT_ENA_W1S_FUNC(void)1083 static inline uint64_t BDK_RVU_AF_PFFLR_INT_ENA_W1S_FUNC(void)
1084 {
1085 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1086 return 0x8500000028b0ll;
1087 __bdk_csr_fatal("RVU_AF_PFFLR_INT_ENA_W1S", 0, 0, 0, 0, 0);
1088 }
1089
1090 #define typedef_BDK_RVU_AF_PFFLR_INT_ENA_W1S bdk_rvu_af_pfflr_int_ena_w1s_t
1091 #define bustype_BDK_RVU_AF_PFFLR_INT_ENA_W1S BDK_CSR_TYPE_RVU_PF_BAR0
1092 #define basename_BDK_RVU_AF_PFFLR_INT_ENA_W1S "RVU_AF_PFFLR_INT_ENA_W1S"
1093 #define device_bar_BDK_RVU_AF_PFFLR_INT_ENA_W1S 0x0 /* BAR0 */
1094 #define busnum_BDK_RVU_AF_PFFLR_INT_ENA_W1S 0
1095 #define arguments_BDK_RVU_AF_PFFLR_INT_ENA_W1S -1,-1,-1,-1
1096
1097 /**
1098 * Register (RVU_PF_BAR0) rvu_af_pfflr_int_w1s
1099 *
1100 * RVU Admin Function PF Function Level Reset Interrupt Set Registers
1101 * This register sets interrupt bits.
1102 */
1103 union bdk_rvu_af_pfflr_int_w1s
1104 {
1105 uint64_t u;
1106 struct bdk_rvu_af_pfflr_int_w1s_s
1107 {
1108 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1109 uint64_t flr : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_AF_PFFLR_INT[FLR]. */
1110 #else /* Word 0 - Little Endian */
1111 uint64_t flr : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_AF_PFFLR_INT[FLR]. */
1112 #endif /* Word 0 - End */
1113 } s;
1114 /* struct bdk_rvu_af_pfflr_int_w1s_s cn; */
1115 };
1116 typedef union bdk_rvu_af_pfflr_int_w1s bdk_rvu_af_pfflr_int_w1s_t;
1117
1118 #define BDK_RVU_AF_PFFLR_INT_W1S BDK_RVU_AF_PFFLR_INT_W1S_FUNC()
1119 static inline uint64_t BDK_RVU_AF_PFFLR_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFFLR_INT_W1S_FUNC(void)1120 static inline uint64_t BDK_RVU_AF_PFFLR_INT_W1S_FUNC(void)
1121 {
1122 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1123 return 0x8500000028a8ll;
1124 __bdk_csr_fatal("RVU_AF_PFFLR_INT_W1S", 0, 0, 0, 0, 0);
1125 }
1126
1127 #define typedef_BDK_RVU_AF_PFFLR_INT_W1S bdk_rvu_af_pfflr_int_w1s_t
1128 #define bustype_BDK_RVU_AF_PFFLR_INT_W1S BDK_CSR_TYPE_RVU_PF_BAR0
1129 #define basename_BDK_RVU_AF_PFFLR_INT_W1S "RVU_AF_PFFLR_INT_W1S"
1130 #define device_bar_BDK_RVU_AF_PFFLR_INT_W1S 0x0 /* BAR0 */
1131 #define busnum_BDK_RVU_AF_PFFLR_INT_W1S 0
1132 #define arguments_BDK_RVU_AF_PFFLR_INT_W1S -1,-1,-1,-1
1133
1134 /**
1135 * Register (RVU_PF_BAR0) rvu_af_pfme_int
1136 *
1137 * RVU Admin Function PF Bus Master Enable Interrupt Registers
1138 */
1139 union bdk_rvu_af_pfme_int
1140 {
1141 uint64_t u;
1142 struct bdk_rvu_af_pfme_int_s
1143 {
1144 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1145 uint64_t me : 64; /**< [ 63: 0](R/W1C/H) Master enable interrupt bit per PF.
1146 A device-dependent AF driver typically uses these bits to handle state
1147 changes to PCCPF_XXX_CMD[ME], which are typically modified by
1148 non-device-dependent software only.
1149
1150 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, each bit is set when the
1151 corresponding PCCPF_XXX_CMD[ME] bit is either set or cleared for the
1152 associated PF. The corresponding bit in RVU_AF_PFME_STATUS returns the
1153 current value of PCCPF_XXX_CMD[ME].
1154
1155 Note that if RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, the corresponding
1156 bit in RVU_AF_PFTRPEND is also set when PCCPF_XXX_CMD[ME] is set, but not
1157 when PCCPF_XXX_CMD[ME] is cleared. */
1158 #else /* Word 0 - Little Endian */
1159 uint64_t me : 64; /**< [ 63: 0](R/W1C/H) Master enable interrupt bit per PF.
1160 A device-dependent AF driver typically uses these bits to handle state
1161 changes to PCCPF_XXX_CMD[ME], which are typically modified by
1162 non-device-dependent software only.
1163
1164 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, each bit is set when the
1165 corresponding PCCPF_XXX_CMD[ME] bit is either set or cleared for the
1166 associated PF. The corresponding bit in RVU_AF_PFME_STATUS returns the
1167 current value of PCCPF_XXX_CMD[ME].
1168
1169 Note that if RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, the corresponding
1170 bit in RVU_AF_PFTRPEND is also set when PCCPF_XXX_CMD[ME] is set, but not
1171 when PCCPF_XXX_CMD[ME] is cleared. */
1172 #endif /* Word 0 - End */
1173 } s;
1174 /* struct bdk_rvu_af_pfme_int_s cn; */
1175 };
1176 typedef union bdk_rvu_af_pfme_int bdk_rvu_af_pfme_int_t;
1177
1178 #define BDK_RVU_AF_PFME_INT BDK_RVU_AF_PFME_INT_FUNC()
1179 static inline uint64_t BDK_RVU_AF_PFME_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFME_INT_FUNC(void)1180 static inline uint64_t BDK_RVU_AF_PFME_INT_FUNC(void)
1181 {
1182 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1183 return 0x8500000028c0ll;
1184 __bdk_csr_fatal("RVU_AF_PFME_INT", 0, 0, 0, 0, 0);
1185 }
1186
1187 #define typedef_BDK_RVU_AF_PFME_INT bdk_rvu_af_pfme_int_t
1188 #define bustype_BDK_RVU_AF_PFME_INT BDK_CSR_TYPE_RVU_PF_BAR0
1189 #define basename_BDK_RVU_AF_PFME_INT "RVU_AF_PFME_INT"
1190 #define device_bar_BDK_RVU_AF_PFME_INT 0x0 /* BAR0 */
1191 #define busnum_BDK_RVU_AF_PFME_INT 0
1192 #define arguments_BDK_RVU_AF_PFME_INT -1,-1,-1,-1
1193
1194 /**
1195 * Register (RVU_PF_BAR0) rvu_af_pfme_int_ena_w1c
1196 *
1197 * RVU Admin Function PF Bus Master Enable Interrupt Enable Clear Registers
1198 * This register clears interrupt enable bits.
1199 */
1200 union bdk_rvu_af_pfme_int_ena_w1c
1201 {
1202 uint64_t u;
1203 struct bdk_rvu_af_pfme_int_ena_w1c_s
1204 {
1205 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1206 uint64_t me : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_AF_PFME_INT[ME]. */
1207 #else /* Word 0 - Little Endian */
1208 uint64_t me : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_AF_PFME_INT[ME]. */
1209 #endif /* Word 0 - End */
1210 } s;
1211 /* struct bdk_rvu_af_pfme_int_ena_w1c_s cn; */
1212 };
1213 typedef union bdk_rvu_af_pfme_int_ena_w1c bdk_rvu_af_pfme_int_ena_w1c_t;
1214
1215 #define BDK_RVU_AF_PFME_INT_ENA_W1C BDK_RVU_AF_PFME_INT_ENA_W1C_FUNC()
1216 static inline uint64_t BDK_RVU_AF_PFME_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFME_INT_ENA_W1C_FUNC(void)1217 static inline uint64_t BDK_RVU_AF_PFME_INT_ENA_W1C_FUNC(void)
1218 {
1219 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1220 return 0x8500000028d8ll;
1221 __bdk_csr_fatal("RVU_AF_PFME_INT_ENA_W1C", 0, 0, 0, 0, 0);
1222 }
1223
1224 #define typedef_BDK_RVU_AF_PFME_INT_ENA_W1C bdk_rvu_af_pfme_int_ena_w1c_t
1225 #define bustype_BDK_RVU_AF_PFME_INT_ENA_W1C BDK_CSR_TYPE_RVU_PF_BAR0
1226 #define basename_BDK_RVU_AF_PFME_INT_ENA_W1C "RVU_AF_PFME_INT_ENA_W1C"
1227 #define device_bar_BDK_RVU_AF_PFME_INT_ENA_W1C 0x0 /* BAR0 */
1228 #define busnum_BDK_RVU_AF_PFME_INT_ENA_W1C 0
1229 #define arguments_BDK_RVU_AF_PFME_INT_ENA_W1C -1,-1,-1,-1
1230
1231 /**
1232 * Register (RVU_PF_BAR0) rvu_af_pfme_int_ena_w1s
1233 *
1234 * RVU Admin Function PF Bus Master Enable Interrupt Enable Set Registers
1235 * This register sets interrupt enable bits.
1236 */
1237 union bdk_rvu_af_pfme_int_ena_w1s
1238 {
1239 uint64_t u;
1240 struct bdk_rvu_af_pfme_int_ena_w1s_s
1241 {
1242 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1243 uint64_t me : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_AF_PFME_INT[ME]. */
1244 #else /* Word 0 - Little Endian */
1245 uint64_t me : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_AF_PFME_INT[ME]. */
1246 #endif /* Word 0 - End */
1247 } s;
1248 /* struct bdk_rvu_af_pfme_int_ena_w1s_s cn; */
1249 };
1250 typedef union bdk_rvu_af_pfme_int_ena_w1s bdk_rvu_af_pfme_int_ena_w1s_t;
1251
1252 #define BDK_RVU_AF_PFME_INT_ENA_W1S BDK_RVU_AF_PFME_INT_ENA_W1S_FUNC()
1253 static inline uint64_t BDK_RVU_AF_PFME_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFME_INT_ENA_W1S_FUNC(void)1254 static inline uint64_t BDK_RVU_AF_PFME_INT_ENA_W1S_FUNC(void)
1255 {
1256 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1257 return 0x8500000028d0ll;
1258 __bdk_csr_fatal("RVU_AF_PFME_INT_ENA_W1S", 0, 0, 0, 0, 0);
1259 }
1260
1261 #define typedef_BDK_RVU_AF_PFME_INT_ENA_W1S bdk_rvu_af_pfme_int_ena_w1s_t
1262 #define bustype_BDK_RVU_AF_PFME_INT_ENA_W1S BDK_CSR_TYPE_RVU_PF_BAR0
1263 #define basename_BDK_RVU_AF_PFME_INT_ENA_W1S "RVU_AF_PFME_INT_ENA_W1S"
1264 #define device_bar_BDK_RVU_AF_PFME_INT_ENA_W1S 0x0 /* BAR0 */
1265 #define busnum_BDK_RVU_AF_PFME_INT_ENA_W1S 0
1266 #define arguments_BDK_RVU_AF_PFME_INT_ENA_W1S -1,-1,-1,-1
1267
1268 /**
1269 * Register (RVU_PF_BAR0) rvu_af_pfme_int_w1s
1270 *
1271 * RVU Admin Function PF Bus Master Enable Interrupt Set Registers
1272 * This register sets interrupt bits.
1273 */
1274 union bdk_rvu_af_pfme_int_w1s
1275 {
1276 uint64_t u;
1277 struct bdk_rvu_af_pfme_int_w1s_s
1278 {
1279 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1280 uint64_t me : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_AF_PFME_INT[ME]. */
1281 #else /* Word 0 - Little Endian */
1282 uint64_t me : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_AF_PFME_INT[ME]. */
1283 #endif /* Word 0 - End */
1284 } s;
1285 /* struct bdk_rvu_af_pfme_int_w1s_s cn; */
1286 };
1287 typedef union bdk_rvu_af_pfme_int_w1s bdk_rvu_af_pfme_int_w1s_t;
1288
1289 #define BDK_RVU_AF_PFME_INT_W1S BDK_RVU_AF_PFME_INT_W1S_FUNC()
1290 static inline uint64_t BDK_RVU_AF_PFME_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFME_INT_W1S_FUNC(void)1291 static inline uint64_t BDK_RVU_AF_PFME_INT_W1S_FUNC(void)
1292 {
1293 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1294 return 0x8500000028c8ll;
1295 __bdk_csr_fatal("RVU_AF_PFME_INT_W1S", 0, 0, 0, 0, 0);
1296 }
1297
1298 #define typedef_BDK_RVU_AF_PFME_INT_W1S bdk_rvu_af_pfme_int_w1s_t
1299 #define bustype_BDK_RVU_AF_PFME_INT_W1S BDK_CSR_TYPE_RVU_PF_BAR0
1300 #define basename_BDK_RVU_AF_PFME_INT_W1S "RVU_AF_PFME_INT_W1S"
1301 #define device_bar_BDK_RVU_AF_PFME_INT_W1S 0x0 /* BAR0 */
1302 #define busnum_BDK_RVU_AF_PFME_INT_W1S 0
1303 #define arguments_BDK_RVU_AF_PFME_INT_W1S -1,-1,-1,-1
1304
1305 /**
1306 * Register (RVU_PF_BAR0) rvu_af_pfme_status
1307 *
1308 * RVU Admin Function PF Bus Master Enable Status Registers
1309 */
1310 union bdk_rvu_af_pfme_status
1311 {
1312 uint64_t u;
1313 struct bdk_rvu_af_pfme_status_s
1314 {
1315 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1316 uint64_t me : 64; /**< [ 63: 0](RO/H) Bus master enable bit per PF. Each bit returns the PF's
1317 PCCPF_XXX_CMD[ME] value. */
1318 #else /* Word 0 - Little Endian */
1319 uint64_t me : 64; /**< [ 63: 0](RO/H) Bus master enable bit per PF. Each bit returns the PF's
1320 PCCPF_XXX_CMD[ME] value. */
1321 #endif /* Word 0 - End */
1322 } s;
1323 /* struct bdk_rvu_af_pfme_status_s cn; */
1324 };
1325 typedef union bdk_rvu_af_pfme_status bdk_rvu_af_pfme_status_t;
1326
1327 #define BDK_RVU_AF_PFME_STATUS BDK_RVU_AF_PFME_STATUS_FUNC()
1328 static inline uint64_t BDK_RVU_AF_PFME_STATUS_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFME_STATUS_FUNC(void)1329 static inline uint64_t BDK_RVU_AF_PFME_STATUS_FUNC(void)
1330 {
1331 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1332 return 0x850000002800ll;
1333 __bdk_csr_fatal("RVU_AF_PFME_STATUS", 0, 0, 0, 0, 0);
1334 }
1335
1336 #define typedef_BDK_RVU_AF_PFME_STATUS bdk_rvu_af_pfme_status_t
1337 #define bustype_BDK_RVU_AF_PFME_STATUS BDK_CSR_TYPE_RVU_PF_BAR0
1338 #define basename_BDK_RVU_AF_PFME_STATUS "RVU_AF_PFME_STATUS"
1339 #define device_bar_BDK_RVU_AF_PFME_STATUS 0x0 /* BAR0 */
1340 #define busnum_BDK_RVU_AF_PFME_STATUS 0
1341 #define arguments_BDK_RVU_AF_PFME_STATUS -1,-1,-1,-1
1342
1343 /**
1344 * Register (RVU_PF_BAR0) rvu_af_pftrpend
1345 *
1346 * RVU Admin Function PF Transaction Pending Registers
1347 */
1348 union bdk_rvu_af_pftrpend
1349 {
1350 uint64_t u;
1351 struct bdk_rvu_af_pftrpend_s
1352 {
1353 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1354 uint64_t trpend : 64; /**< [ 63: 0](R/W1C/H) Transaction pending bit per PF.
1355
1356 A PF's bit is set when RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set and:
1357 * A one is written to the corresponding PCCPF_XXX_E_DEV_CTL[BCR_FLR], or
1358 * PCCPF_XXX_CMD[ME] is set or cleared.
1359
1360 When a PF's bit is set, forces the corresponding
1361 PCCPF_XXX_E_DEV_CTL[TRPEND] to be set.
1362
1363 Software (typically a device-dependent AF driver) can clear the bit by
1364 writing a 1. */
1365 #else /* Word 0 - Little Endian */
1366 uint64_t trpend : 64; /**< [ 63: 0](R/W1C/H) Transaction pending bit per PF.
1367
1368 A PF's bit is set when RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set and:
1369 * A one is written to the corresponding PCCPF_XXX_E_DEV_CTL[BCR_FLR], or
1370 * PCCPF_XXX_CMD[ME] is set or cleared.
1371
1372 When a PF's bit is set, forces the corresponding
1373 PCCPF_XXX_E_DEV_CTL[TRPEND] to be set.
1374
1375 Software (typically a device-dependent AF driver) can clear the bit by
1376 writing a 1. */
1377 #endif /* Word 0 - End */
1378 } s;
1379 /* struct bdk_rvu_af_pftrpend_s cn; */
1380 };
1381 typedef union bdk_rvu_af_pftrpend bdk_rvu_af_pftrpend_t;
1382
1383 #define BDK_RVU_AF_PFTRPEND BDK_RVU_AF_PFTRPEND_FUNC()
1384 static inline uint64_t BDK_RVU_AF_PFTRPEND_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFTRPEND_FUNC(void)1385 static inline uint64_t BDK_RVU_AF_PFTRPEND_FUNC(void)
1386 {
1387 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1388 return 0x850000002810ll;
1389 __bdk_csr_fatal("RVU_AF_PFTRPEND", 0, 0, 0, 0, 0);
1390 }
1391
1392 #define typedef_BDK_RVU_AF_PFTRPEND bdk_rvu_af_pftrpend_t
1393 #define bustype_BDK_RVU_AF_PFTRPEND BDK_CSR_TYPE_RVU_PF_BAR0
1394 #define basename_BDK_RVU_AF_PFTRPEND "RVU_AF_PFTRPEND"
1395 #define device_bar_BDK_RVU_AF_PFTRPEND 0x0 /* BAR0 */
1396 #define busnum_BDK_RVU_AF_PFTRPEND 0
1397 #define arguments_BDK_RVU_AF_PFTRPEND -1,-1,-1,-1
1398
1399 /**
1400 * Register (RVU_PF_BAR0) rvu_af_pftrpend_w1s
1401 *
1402 * RVU Admin Function PF Transaction Pending Set Registers
1403 * This register reads or sets bits.
1404 */
1405 union bdk_rvu_af_pftrpend_w1s
1406 {
1407 uint64_t u;
1408 struct bdk_rvu_af_pftrpend_w1s_s
1409 {
1410 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1411 uint64_t trpend : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_AF_PFTRPEND[TRPEND]. */
1412 #else /* Word 0 - Little Endian */
1413 uint64_t trpend : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_AF_PFTRPEND[TRPEND]. */
1414 #endif /* Word 0 - End */
1415 } s;
1416 /* struct bdk_rvu_af_pftrpend_w1s_s cn; */
1417 };
1418 typedef union bdk_rvu_af_pftrpend_w1s bdk_rvu_af_pftrpend_w1s_t;
1419
1420 #define BDK_RVU_AF_PFTRPEND_W1S BDK_RVU_AF_PFTRPEND_W1S_FUNC()
1421 static inline uint64_t BDK_RVU_AF_PFTRPEND_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_PFTRPEND_W1S_FUNC(void)1422 static inline uint64_t BDK_RVU_AF_PFTRPEND_W1S_FUNC(void)
1423 {
1424 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1425 return 0x850000002820ll;
1426 __bdk_csr_fatal("RVU_AF_PFTRPEND_W1S", 0, 0, 0, 0, 0);
1427 }
1428
1429 #define typedef_BDK_RVU_AF_PFTRPEND_W1S bdk_rvu_af_pftrpend_w1s_t
1430 #define bustype_BDK_RVU_AF_PFTRPEND_W1S BDK_CSR_TYPE_RVU_PF_BAR0
1431 #define basename_BDK_RVU_AF_PFTRPEND_W1S "RVU_AF_PFTRPEND_W1S"
1432 #define device_bar_BDK_RVU_AF_PFTRPEND_W1S 0x0 /* BAR0 */
1433 #define busnum_BDK_RVU_AF_PFTRPEND_W1S 0
1434 #define arguments_BDK_RVU_AF_PFTRPEND_W1S -1,-1,-1,-1
1435
1436 /**
1437 * Register (RVU_PF_BAR0) rvu_af_ras
1438 *
1439 * RVU Admin Function RAS Interrupt Register
1440 * This register is intended for delivery of RAS events to the SCP, so should be
1441 * ignored by OS drivers.
1442 */
1443 union bdk_rvu_af_ras
1444 {
1445 uint64_t u;
1446 struct bdk_rvu_af_ras_s
1447 {
1448 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1449 uint64_t reserved_1_63 : 63;
1450 uint64_t msix_poison : 1; /**< [ 0: 0](R/W1C/H) Received MSI-X table read response with poisoned data. */
1451 #else /* Word 0 - Little Endian */
1452 uint64_t msix_poison : 1; /**< [ 0: 0](R/W1C/H) Received MSI-X table read response with poisoned data. */
1453 uint64_t reserved_1_63 : 63;
1454 #endif /* Word 0 - End */
1455 } s;
1456 /* struct bdk_rvu_af_ras_s cn; */
1457 };
1458 typedef union bdk_rvu_af_ras bdk_rvu_af_ras_t;
1459
1460 #define BDK_RVU_AF_RAS BDK_RVU_AF_RAS_FUNC()
1461 static inline uint64_t BDK_RVU_AF_RAS_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_RAS_FUNC(void)1462 static inline uint64_t BDK_RVU_AF_RAS_FUNC(void)
1463 {
1464 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1465 return 0x850000000100ll;
1466 __bdk_csr_fatal("RVU_AF_RAS", 0, 0, 0, 0, 0);
1467 }
1468
1469 #define typedef_BDK_RVU_AF_RAS bdk_rvu_af_ras_t
1470 #define bustype_BDK_RVU_AF_RAS BDK_CSR_TYPE_RVU_PF_BAR0
1471 #define basename_BDK_RVU_AF_RAS "RVU_AF_RAS"
1472 #define device_bar_BDK_RVU_AF_RAS 0x0 /* BAR0 */
1473 #define busnum_BDK_RVU_AF_RAS 0
1474 #define arguments_BDK_RVU_AF_RAS -1,-1,-1,-1
1475
1476 /**
1477 * Register (RVU_PF_BAR0) rvu_af_ras_ena_w1c
1478 *
1479 * RVU Admin Function RAS Interrupt Enable Clear Register
1480 * This register clears interrupt enable bits.
1481 */
1482 union bdk_rvu_af_ras_ena_w1c
1483 {
1484 uint64_t u;
1485 struct bdk_rvu_af_ras_ena_w1c_s
1486 {
1487 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1488 uint64_t reserved_1_63 : 63;
1489 uint64_t msix_poison : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RVU_AF_RAS[MSIX_POISON]. */
1490 #else /* Word 0 - Little Endian */
1491 uint64_t msix_poison : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RVU_AF_RAS[MSIX_POISON]. */
1492 uint64_t reserved_1_63 : 63;
1493 #endif /* Word 0 - End */
1494 } s;
1495 /* struct bdk_rvu_af_ras_ena_w1c_s cn; */
1496 };
1497 typedef union bdk_rvu_af_ras_ena_w1c bdk_rvu_af_ras_ena_w1c_t;
1498
1499 #define BDK_RVU_AF_RAS_ENA_W1C BDK_RVU_AF_RAS_ENA_W1C_FUNC()
1500 static inline uint64_t BDK_RVU_AF_RAS_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_RAS_ENA_W1C_FUNC(void)1501 static inline uint64_t BDK_RVU_AF_RAS_ENA_W1C_FUNC(void)
1502 {
1503 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1504 return 0x850000000118ll;
1505 __bdk_csr_fatal("RVU_AF_RAS_ENA_W1C", 0, 0, 0, 0, 0);
1506 }
1507
1508 #define typedef_BDK_RVU_AF_RAS_ENA_W1C bdk_rvu_af_ras_ena_w1c_t
1509 #define bustype_BDK_RVU_AF_RAS_ENA_W1C BDK_CSR_TYPE_RVU_PF_BAR0
1510 #define basename_BDK_RVU_AF_RAS_ENA_W1C "RVU_AF_RAS_ENA_W1C"
1511 #define device_bar_BDK_RVU_AF_RAS_ENA_W1C 0x0 /* BAR0 */
1512 #define busnum_BDK_RVU_AF_RAS_ENA_W1C 0
1513 #define arguments_BDK_RVU_AF_RAS_ENA_W1C -1,-1,-1,-1
1514
1515 /**
1516 * Register (RVU_PF_BAR0) rvu_af_ras_ena_w1s
1517 *
1518 * RVU Admin Function RAS Interrupt Enable Set Register
1519 * This register sets interrupt enable bits.
1520 */
1521 union bdk_rvu_af_ras_ena_w1s
1522 {
1523 uint64_t u;
1524 struct bdk_rvu_af_ras_ena_w1s_s
1525 {
1526 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1527 uint64_t reserved_1_63 : 63;
1528 uint64_t msix_poison : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RVU_AF_RAS[MSIX_POISON]. */
1529 #else /* Word 0 - Little Endian */
1530 uint64_t msix_poison : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RVU_AF_RAS[MSIX_POISON]. */
1531 uint64_t reserved_1_63 : 63;
1532 #endif /* Word 0 - End */
1533 } s;
1534 /* struct bdk_rvu_af_ras_ena_w1s_s cn; */
1535 };
1536 typedef union bdk_rvu_af_ras_ena_w1s bdk_rvu_af_ras_ena_w1s_t;
1537
1538 #define BDK_RVU_AF_RAS_ENA_W1S BDK_RVU_AF_RAS_ENA_W1S_FUNC()
1539 static inline uint64_t BDK_RVU_AF_RAS_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_RAS_ENA_W1S_FUNC(void)1540 static inline uint64_t BDK_RVU_AF_RAS_ENA_W1S_FUNC(void)
1541 {
1542 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1543 return 0x850000000110ll;
1544 __bdk_csr_fatal("RVU_AF_RAS_ENA_W1S", 0, 0, 0, 0, 0);
1545 }
1546
1547 #define typedef_BDK_RVU_AF_RAS_ENA_W1S bdk_rvu_af_ras_ena_w1s_t
1548 #define bustype_BDK_RVU_AF_RAS_ENA_W1S BDK_CSR_TYPE_RVU_PF_BAR0
1549 #define basename_BDK_RVU_AF_RAS_ENA_W1S "RVU_AF_RAS_ENA_W1S"
1550 #define device_bar_BDK_RVU_AF_RAS_ENA_W1S 0x0 /* BAR0 */
1551 #define busnum_BDK_RVU_AF_RAS_ENA_W1S 0
1552 #define arguments_BDK_RVU_AF_RAS_ENA_W1S -1,-1,-1,-1
1553
1554 /**
1555 * Register (RVU_PF_BAR0) rvu_af_ras_w1s
1556 *
1557 * RVU Admin Function RAS Interrupt Set Register
1558 * This register sets interrupt bits.
1559 */
1560 union bdk_rvu_af_ras_w1s
1561 {
1562 uint64_t u;
1563 struct bdk_rvu_af_ras_w1s_s
1564 {
1565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1566 uint64_t reserved_1_63 : 63;
1567 uint64_t msix_poison : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RVU_AF_RAS[MSIX_POISON]. */
1568 #else /* Word 0 - Little Endian */
1569 uint64_t msix_poison : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RVU_AF_RAS[MSIX_POISON]. */
1570 uint64_t reserved_1_63 : 63;
1571 #endif /* Word 0 - End */
1572 } s;
1573 /* struct bdk_rvu_af_ras_w1s_s cn; */
1574 };
1575 typedef union bdk_rvu_af_ras_w1s bdk_rvu_af_ras_w1s_t;
1576
1577 #define BDK_RVU_AF_RAS_W1S BDK_RVU_AF_RAS_W1S_FUNC()
1578 static inline uint64_t BDK_RVU_AF_RAS_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_AF_RAS_W1S_FUNC(void)1579 static inline uint64_t BDK_RVU_AF_RAS_W1S_FUNC(void)
1580 {
1581 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1582 return 0x850000000108ll;
1583 __bdk_csr_fatal("RVU_AF_RAS_W1S", 0, 0, 0, 0, 0);
1584 }
1585
1586 #define typedef_BDK_RVU_AF_RAS_W1S bdk_rvu_af_ras_w1s_t
1587 #define bustype_BDK_RVU_AF_RAS_W1S BDK_CSR_TYPE_RVU_PF_BAR0
1588 #define basename_BDK_RVU_AF_RAS_W1S "RVU_AF_RAS_W1S"
1589 #define device_bar_BDK_RVU_AF_RAS_W1S 0x0 /* BAR0 */
1590 #define busnum_BDK_RVU_AF_RAS_W1S 0
1591 #define arguments_BDK_RVU_AF_RAS_W1S -1,-1,-1,-1
1592
1593 /**
1594 * Register (RVU_PF_BAR2) rvu_pf_block_addr#_disc
1595 *
1596 * RVU PF Block Address Discovery Registers
1597 * These registers allow each PF driver to discover block resources that are
1598 * provisioned to its PF. The register's block address index is enumerated by
1599 * RVU_BLOCK_ADDR_E.
1600 */
1601 union bdk_rvu_pf_block_addrx_disc
1602 {
1603 uint64_t u;
1604 struct bdk_rvu_pf_block_addrx_disc_s
1605 {
1606 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1607 uint64_t reserved_28_63 : 36;
1608 uint64_t btype : 8; /**< [ 27: 20](RO/H) Block type enumerated by RVU_BLOCK_TYPE_E. */
1609 uint64_t rid : 8; /**< [ 19: 12](RO/H) Revision ID of the block from RVU_PRIV_BLOCK_TYPE()_REV[RID]. */
1610 uint64_t imp : 1; /**< [ 11: 11](RO/H) Implemented. When set, a block is present at this block address index as
1611 enumerated by RVU_BLOCK_ADDR_E. When clear, a block is not present and the
1612 remaining fields in the register are RAZ.
1613
1614 Internal:
1615 Returns zero if the block is implemented but fused out. */
1616 uint64_t reserved_9_10 : 2;
1617 uint64_t num_lfs : 9; /**< [ 8: 0](RO/H) Number of local functions from the block that are provisioned to the VF/PF.
1618 When non-zero, the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in
1619 the block.
1620 Returns 0 for block types that do not have local functions, 0 or 1 for
1621 single-slot blocks; see RVU_BLOCK_TYPE_E. */
1622 #else /* Word 0 - Little Endian */
1623 uint64_t num_lfs : 9; /**< [ 8: 0](RO/H) Number of local functions from the block that are provisioned to the VF/PF.
1624 When non-zero, the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in
1625 the block.
1626 Returns 0 for block types that do not have local functions, 0 or 1 for
1627 single-slot blocks; see RVU_BLOCK_TYPE_E. */
1628 uint64_t reserved_9_10 : 2;
1629 uint64_t imp : 1; /**< [ 11: 11](RO/H) Implemented. When set, a block is present at this block address index as
1630 enumerated by RVU_BLOCK_ADDR_E. When clear, a block is not present and the
1631 remaining fields in the register are RAZ.
1632
1633 Internal:
1634 Returns zero if the block is implemented but fused out. */
1635 uint64_t rid : 8; /**< [ 19: 12](RO/H) Revision ID of the block from RVU_PRIV_BLOCK_TYPE()_REV[RID]. */
1636 uint64_t btype : 8; /**< [ 27: 20](RO/H) Block type enumerated by RVU_BLOCK_TYPE_E. */
1637 uint64_t reserved_28_63 : 36;
1638 #endif /* Word 0 - End */
1639 } s;
1640 /* struct bdk_rvu_pf_block_addrx_disc_s cn; */
1641 };
1642 typedef union bdk_rvu_pf_block_addrx_disc bdk_rvu_pf_block_addrx_disc_t;
1643
1644 static inline uint64_t BDK_RVU_PF_BLOCK_ADDRX_DISC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_BLOCK_ADDRX_DISC(unsigned long a)1645 static inline uint64_t BDK_RVU_PF_BLOCK_ADDRX_DISC(unsigned long a)
1646 {
1647 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=31))
1648 return 0x850200000200ll + 8ll * ((a) & 0x1f);
1649 __bdk_csr_fatal("RVU_PF_BLOCK_ADDRX_DISC", 1, a, 0, 0, 0);
1650 }
1651
1652 #define typedef_BDK_RVU_PF_BLOCK_ADDRX_DISC(a) bdk_rvu_pf_block_addrx_disc_t
1653 #define bustype_BDK_RVU_PF_BLOCK_ADDRX_DISC(a) BDK_CSR_TYPE_RVU_PF_BAR2
1654 #define basename_BDK_RVU_PF_BLOCK_ADDRX_DISC(a) "RVU_PF_BLOCK_ADDRX_DISC"
1655 #define device_bar_BDK_RVU_PF_BLOCK_ADDRX_DISC(a) 0x2 /* BAR2 */
1656 #define busnum_BDK_RVU_PF_BLOCK_ADDRX_DISC(a) (a)
1657 #define arguments_BDK_RVU_PF_BLOCK_ADDRX_DISC(a) (a),-1,-1,-1
1658
1659 /**
1660 * Register (RVU_PF_BAR2) rvu_pf_int
1661 *
1662 * RVU PF Interrupt Registers
1663 */
1664 union bdk_rvu_pf_int
1665 {
1666 uint64_t u;
1667 struct bdk_rvu_pf_int_s
1668 {
1669 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1670 uint64_t reserved_1_63 : 63;
1671 uint64_t mbox : 1; /**< [ 0: 0](R/W1C/H) AF to PF mailbox interrupt. Set when RVU_AF_AFPF()_MBOX(0) is written. */
1672 #else /* Word 0 - Little Endian */
1673 uint64_t mbox : 1; /**< [ 0: 0](R/W1C/H) AF to PF mailbox interrupt. Set when RVU_AF_AFPF()_MBOX(0) is written. */
1674 uint64_t reserved_1_63 : 63;
1675 #endif /* Word 0 - End */
1676 } s;
1677 /* struct bdk_rvu_pf_int_s cn; */
1678 };
1679 typedef union bdk_rvu_pf_int bdk_rvu_pf_int_t;
1680
1681 #define BDK_RVU_PF_INT BDK_RVU_PF_INT_FUNC()
1682 static inline uint64_t BDK_RVU_PF_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PF_INT_FUNC(void)1683 static inline uint64_t BDK_RVU_PF_INT_FUNC(void)
1684 {
1685 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1686 return 0x850200000c20ll;
1687 __bdk_csr_fatal("RVU_PF_INT", 0, 0, 0, 0, 0);
1688 }
1689
1690 #define typedef_BDK_RVU_PF_INT bdk_rvu_pf_int_t
1691 #define bustype_BDK_RVU_PF_INT BDK_CSR_TYPE_RVU_PF_BAR2
1692 #define basename_BDK_RVU_PF_INT "RVU_PF_INT"
1693 #define device_bar_BDK_RVU_PF_INT 0x2 /* BAR2 */
1694 #define busnum_BDK_RVU_PF_INT 0
1695 #define arguments_BDK_RVU_PF_INT -1,-1,-1,-1
1696
1697 /**
1698 * Register (RVU_PF_BAR2) rvu_pf_int_ena_w1c
1699 *
1700 * RVU PF Interrupt Enable Clear Register
1701 * This register clears interrupt enable bits.
1702 */
1703 union bdk_rvu_pf_int_ena_w1c
1704 {
1705 uint64_t u;
1706 struct bdk_rvu_pf_int_ena_w1c_s
1707 {
1708 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1709 uint64_t reserved_1_63 : 63;
1710 uint64_t mbox : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RVU_PF_INT[MBOX]. */
1711 #else /* Word 0 - Little Endian */
1712 uint64_t mbox : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RVU_PF_INT[MBOX]. */
1713 uint64_t reserved_1_63 : 63;
1714 #endif /* Word 0 - End */
1715 } s;
1716 /* struct bdk_rvu_pf_int_ena_w1c_s cn; */
1717 };
1718 typedef union bdk_rvu_pf_int_ena_w1c bdk_rvu_pf_int_ena_w1c_t;
1719
1720 #define BDK_RVU_PF_INT_ENA_W1C BDK_RVU_PF_INT_ENA_W1C_FUNC()
1721 static inline uint64_t BDK_RVU_PF_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PF_INT_ENA_W1C_FUNC(void)1722 static inline uint64_t BDK_RVU_PF_INT_ENA_W1C_FUNC(void)
1723 {
1724 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1725 return 0x850200000c38ll;
1726 __bdk_csr_fatal("RVU_PF_INT_ENA_W1C", 0, 0, 0, 0, 0);
1727 }
1728
1729 #define typedef_BDK_RVU_PF_INT_ENA_W1C bdk_rvu_pf_int_ena_w1c_t
1730 #define bustype_BDK_RVU_PF_INT_ENA_W1C BDK_CSR_TYPE_RVU_PF_BAR2
1731 #define basename_BDK_RVU_PF_INT_ENA_W1C "RVU_PF_INT_ENA_W1C"
1732 #define device_bar_BDK_RVU_PF_INT_ENA_W1C 0x2 /* BAR2 */
1733 #define busnum_BDK_RVU_PF_INT_ENA_W1C 0
1734 #define arguments_BDK_RVU_PF_INT_ENA_W1C -1,-1,-1,-1
1735
1736 /**
1737 * Register (RVU_PF_BAR2) rvu_pf_int_ena_w1s
1738 *
1739 * RVU PF Interrupt Enable Set Register
1740 * This register sets interrupt enable bits.
1741 */
1742 union bdk_rvu_pf_int_ena_w1s
1743 {
1744 uint64_t u;
1745 struct bdk_rvu_pf_int_ena_w1s_s
1746 {
1747 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1748 uint64_t reserved_1_63 : 63;
1749 uint64_t mbox : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RVU_PF_INT[MBOX]. */
1750 #else /* Word 0 - Little Endian */
1751 uint64_t mbox : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RVU_PF_INT[MBOX]. */
1752 uint64_t reserved_1_63 : 63;
1753 #endif /* Word 0 - End */
1754 } s;
1755 /* struct bdk_rvu_pf_int_ena_w1s_s cn; */
1756 };
1757 typedef union bdk_rvu_pf_int_ena_w1s bdk_rvu_pf_int_ena_w1s_t;
1758
1759 #define BDK_RVU_PF_INT_ENA_W1S BDK_RVU_PF_INT_ENA_W1S_FUNC()
1760 static inline uint64_t BDK_RVU_PF_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PF_INT_ENA_W1S_FUNC(void)1761 static inline uint64_t BDK_RVU_PF_INT_ENA_W1S_FUNC(void)
1762 {
1763 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1764 return 0x850200000c30ll;
1765 __bdk_csr_fatal("RVU_PF_INT_ENA_W1S", 0, 0, 0, 0, 0);
1766 }
1767
1768 #define typedef_BDK_RVU_PF_INT_ENA_W1S bdk_rvu_pf_int_ena_w1s_t
1769 #define bustype_BDK_RVU_PF_INT_ENA_W1S BDK_CSR_TYPE_RVU_PF_BAR2
1770 #define basename_BDK_RVU_PF_INT_ENA_W1S "RVU_PF_INT_ENA_W1S"
1771 #define device_bar_BDK_RVU_PF_INT_ENA_W1S 0x2 /* BAR2 */
1772 #define busnum_BDK_RVU_PF_INT_ENA_W1S 0
1773 #define arguments_BDK_RVU_PF_INT_ENA_W1S -1,-1,-1,-1
1774
1775 /**
1776 * Register (RVU_PF_BAR2) rvu_pf_int_w1s
1777 *
1778 * RVU PF Interrupt Set Register
1779 * This register sets interrupt bits.
1780 */
1781 union bdk_rvu_pf_int_w1s
1782 {
1783 uint64_t u;
1784 struct bdk_rvu_pf_int_w1s_s
1785 {
1786 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1787 uint64_t reserved_1_63 : 63;
1788 uint64_t mbox : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RVU_PF_INT[MBOX]. */
1789 #else /* Word 0 - Little Endian */
1790 uint64_t mbox : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RVU_PF_INT[MBOX]. */
1791 uint64_t reserved_1_63 : 63;
1792 #endif /* Word 0 - End */
1793 } s;
1794 /* struct bdk_rvu_pf_int_w1s_s cn; */
1795 };
1796 typedef union bdk_rvu_pf_int_w1s bdk_rvu_pf_int_w1s_t;
1797
1798 #define BDK_RVU_PF_INT_W1S BDK_RVU_PF_INT_W1S_FUNC()
1799 static inline uint64_t BDK_RVU_PF_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PF_INT_W1S_FUNC(void)1800 static inline uint64_t BDK_RVU_PF_INT_W1S_FUNC(void)
1801 {
1802 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1803 return 0x850200000c28ll;
1804 __bdk_csr_fatal("RVU_PF_INT_W1S", 0, 0, 0, 0, 0);
1805 }
1806
1807 #define typedef_BDK_RVU_PF_INT_W1S bdk_rvu_pf_int_w1s_t
1808 #define bustype_BDK_RVU_PF_INT_W1S BDK_CSR_TYPE_RVU_PF_BAR2
1809 #define basename_BDK_RVU_PF_INT_W1S "RVU_PF_INT_W1S"
1810 #define device_bar_BDK_RVU_PF_INT_W1S 0x2 /* BAR2 */
1811 #define busnum_BDK_RVU_PF_INT_W1S 0
1812 #define arguments_BDK_RVU_PF_INT_W1S -1,-1,-1,-1
1813
1814 /**
1815 * Register (RVU_PF_BAR2) rvu_pf_msix_pba#
1816 *
1817 * RVU PF MSI-X Pending-Bit-Array Registers
1818 * This register is the MSI-X PF PBA table.
1819 */
1820 union bdk_rvu_pf_msix_pbax
1821 {
1822 uint64_t u;
1823 struct bdk_rvu_pf_msix_pbax_s
1824 {
1825 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1826 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message bit for each MSI-X vector, i.e. one bit per
1827 RVU_PF_MSIX_VEC()_CTL register.
1828 The total number of bits for a given PF (and thus the number of PBA
1829 registers) is determined by RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1]
1830 (plus 1). */
1831 #else /* Word 0 - Little Endian */
1832 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message bit for each MSI-X vector, i.e. one bit per
1833 RVU_PF_MSIX_VEC()_CTL register.
1834 The total number of bits for a given PF (and thus the number of PBA
1835 registers) is determined by RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1]
1836 (plus 1). */
1837 #endif /* Word 0 - End */
1838 } s;
1839 /* struct bdk_rvu_pf_msix_pbax_s cn; */
1840 };
1841 typedef union bdk_rvu_pf_msix_pbax bdk_rvu_pf_msix_pbax_t;
1842
1843 static inline uint64_t BDK_RVU_PF_MSIX_PBAX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_MSIX_PBAX(unsigned long a)1844 static inline uint64_t BDK_RVU_PF_MSIX_PBAX(unsigned long a)
1845 {
1846 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a==0))
1847 return 0x8502002f0000ll + 8ll * ((a) & 0x0);
1848 __bdk_csr_fatal("RVU_PF_MSIX_PBAX", 1, a, 0, 0, 0);
1849 }
1850
1851 #define typedef_BDK_RVU_PF_MSIX_PBAX(a) bdk_rvu_pf_msix_pbax_t
1852 #define bustype_BDK_RVU_PF_MSIX_PBAX(a) BDK_CSR_TYPE_RVU_PF_BAR2
1853 #define basename_BDK_RVU_PF_MSIX_PBAX(a) "RVU_PF_MSIX_PBAX"
1854 #define device_bar_BDK_RVU_PF_MSIX_PBAX(a) 0x2 /* BAR2 */
1855 #define busnum_BDK_RVU_PF_MSIX_PBAX(a) (a)
1856 #define arguments_BDK_RVU_PF_MSIX_PBAX(a) (a),-1,-1,-1
1857
1858 /**
1859 * Register (RVU_PF_BAR2) rvu_pf_msix_vec#_addr
1860 *
1861 * RVU PF MSI-X Vector-Table Address Registers
1862 * These registers and RVU_PF_MSIX_VEC()_CTL form the PF MSI-X vector table.
1863 * The number of MSI-X vectors for a given PF is specified by
1864 * RVU_PRIV_PF()_MSIX_CFG[PF_MSIXT_SIZEM1] (plus 1).
1865 *
1866 * Internal:
1867 * PF vector count of 256 is sized to allow up to 120 for AF, 4 for PF/VF
1868 * mailboxes, and 128 for LF resources from various blocks that are directly
1869 * provisioned to the PF.
1870 */
1871 union bdk_rvu_pf_msix_vecx_addr
1872 {
1873 uint64_t u;
1874 struct bdk_rvu_pf_msix_vecx_addr_s
1875 {
1876 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1877 uint64_t reserved_53_63 : 11;
1878 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1879 uint64_t reserved_1 : 1;
1880 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1881 0 = This vector may be read or written by either secure or nonsecure states.
1882 1 = This vector's RVU_PF_MSIX_VEC()_ADDR, RVU_PF_MSIX_VEC()_CTL, and
1883 corresponding bit of RVU_PF_MSIX_PBA() are RAZ/WI and does not cause a
1884 fault when accessed by the nonsecure world.
1885
1886 If PCCPF_RVU_VSEC_SCTL[MSIX_SEC] (for documentation, see
1887 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors of the function are
1888 secure as if [SECVEC] was set. */
1889 #else /* Word 0 - Little Endian */
1890 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1891 0 = This vector may be read or written by either secure or nonsecure states.
1892 1 = This vector's RVU_PF_MSIX_VEC()_ADDR, RVU_PF_MSIX_VEC()_CTL, and
1893 corresponding bit of RVU_PF_MSIX_PBA() are RAZ/WI and does not cause a
1894 fault when accessed by the nonsecure world.
1895
1896 If PCCPF_RVU_VSEC_SCTL[MSIX_SEC] (for documentation, see
1897 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors of the function are
1898 secure as if [SECVEC] was set. */
1899 uint64_t reserved_1 : 1;
1900 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1901 uint64_t reserved_53_63 : 11;
1902 #endif /* Word 0 - End */
1903 } s;
1904 /* struct bdk_rvu_pf_msix_vecx_addr_s cn; */
1905 };
1906 typedef union bdk_rvu_pf_msix_vecx_addr bdk_rvu_pf_msix_vecx_addr_t;
1907
1908 static inline uint64_t BDK_RVU_PF_MSIX_VECX_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_MSIX_VECX_ADDR(unsigned long a)1909 static inline uint64_t BDK_RVU_PF_MSIX_VECX_ADDR(unsigned long a)
1910 {
1911 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a==0))
1912 return 0x850200200000ll + 0x10ll * ((a) & 0x0);
1913 __bdk_csr_fatal("RVU_PF_MSIX_VECX_ADDR", 1, a, 0, 0, 0);
1914 }
1915
1916 #define typedef_BDK_RVU_PF_MSIX_VECX_ADDR(a) bdk_rvu_pf_msix_vecx_addr_t
1917 #define bustype_BDK_RVU_PF_MSIX_VECX_ADDR(a) BDK_CSR_TYPE_RVU_PF_BAR2
1918 #define basename_BDK_RVU_PF_MSIX_VECX_ADDR(a) "RVU_PF_MSIX_VECX_ADDR"
1919 #define device_bar_BDK_RVU_PF_MSIX_VECX_ADDR(a) 0x2 /* BAR2 */
1920 #define busnum_BDK_RVU_PF_MSIX_VECX_ADDR(a) (a)
1921 #define arguments_BDK_RVU_PF_MSIX_VECX_ADDR(a) (a),-1,-1,-1
1922
1923 /**
1924 * Register (RVU_PF_BAR2) rvu_pf_msix_vec#_ctl
1925 *
1926 * RVU PF MSI-X Vector-Table Control and Data Registers
1927 * These registers and RVU_PF_MSIX_VEC()_ADDR form the PF MSI-X vector table.
1928 */
1929 union bdk_rvu_pf_msix_vecx_ctl
1930 {
1931 uint64_t u;
1932 struct bdk_rvu_pf_msix_vecx_ctl_s
1933 {
1934 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1935 uint64_t reserved_33_63 : 31;
1936 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
1937 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
1938 #else /* Word 0 - Little Endian */
1939 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
1940 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
1941 uint64_t reserved_33_63 : 31;
1942 #endif /* Word 0 - End */
1943 } s;
1944 /* struct bdk_rvu_pf_msix_vecx_ctl_s cn; */
1945 };
1946 typedef union bdk_rvu_pf_msix_vecx_ctl bdk_rvu_pf_msix_vecx_ctl_t;
1947
1948 static inline uint64_t BDK_RVU_PF_MSIX_VECX_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_MSIX_VECX_CTL(unsigned long a)1949 static inline uint64_t BDK_RVU_PF_MSIX_VECX_CTL(unsigned long a)
1950 {
1951 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a==0))
1952 return 0x850200200008ll + 0x10ll * ((a) & 0x0);
1953 __bdk_csr_fatal("RVU_PF_MSIX_VECX_CTL", 1, a, 0, 0, 0);
1954 }
1955
1956 #define typedef_BDK_RVU_PF_MSIX_VECX_CTL(a) bdk_rvu_pf_msix_vecx_ctl_t
1957 #define bustype_BDK_RVU_PF_MSIX_VECX_CTL(a) BDK_CSR_TYPE_RVU_PF_BAR2
1958 #define basename_BDK_RVU_PF_MSIX_VECX_CTL(a) "RVU_PF_MSIX_VECX_CTL"
1959 #define device_bar_BDK_RVU_PF_MSIX_VECX_CTL(a) 0x2 /* BAR2 */
1960 #define busnum_BDK_RVU_PF_MSIX_VECX_CTL(a) (a)
1961 #define arguments_BDK_RVU_PF_MSIX_VECX_CTL(a) (a),-1,-1,-1
1962
1963 /**
1964 * Register (RVU_PF_BAR2) rvu_pf_pfaf_mbox#
1965 *
1966 * RVU PF/AF Mailbox Registers
1967 */
1968 union bdk_rvu_pf_pfaf_mboxx
1969 {
1970 uint64_t u;
1971 struct bdk_rvu_pf_pfaf_mboxx_s
1972 {
1973 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1974 uint64_t data : 64; /**< [ 63: 0](R/W/H) Mailbox data. These PF registers access the 16-byte-per-PF PF/AF
1975 mailbox. The AF may access the same storage using
1976 RVU_AF_AFPF()_MBOX(). MBOX(0) is typically used for AF to PF
1977 signaling, MBOX(1) for PF to AF.
1978 Writing RVU_PF_PFAF_MBOX(1) (but not RVU_AF_AFPF()_MBOX(1))
1979 will set the corresponding RVU_AF_PFAF_MBOX_INT bit, which if appropriately
1980 enabled will send an interrupt to the AF. */
1981 #else /* Word 0 - Little Endian */
1982 uint64_t data : 64; /**< [ 63: 0](R/W/H) Mailbox data. These PF registers access the 16-byte-per-PF PF/AF
1983 mailbox. The AF may access the same storage using
1984 RVU_AF_AFPF()_MBOX(). MBOX(0) is typically used for AF to PF
1985 signaling, MBOX(1) for PF to AF.
1986 Writing RVU_PF_PFAF_MBOX(1) (but not RVU_AF_AFPF()_MBOX(1))
1987 will set the corresponding RVU_AF_PFAF_MBOX_INT bit, which if appropriately
1988 enabled will send an interrupt to the AF. */
1989 #endif /* Word 0 - End */
1990 } s;
1991 /* struct bdk_rvu_pf_pfaf_mboxx_s cn; */
1992 };
1993 typedef union bdk_rvu_pf_pfaf_mboxx bdk_rvu_pf_pfaf_mboxx_t;
1994
1995 static inline uint64_t BDK_RVU_PF_PFAF_MBOXX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_PFAF_MBOXX(unsigned long a)1996 static inline uint64_t BDK_RVU_PF_PFAF_MBOXX(unsigned long a)
1997 {
1998 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
1999 return 0x850200000c00ll + 8ll * ((a) & 0x1);
2000 __bdk_csr_fatal("RVU_PF_PFAF_MBOXX", 1, a, 0, 0, 0);
2001 }
2002
2003 #define typedef_BDK_RVU_PF_PFAF_MBOXX(a) bdk_rvu_pf_pfaf_mboxx_t
2004 #define bustype_BDK_RVU_PF_PFAF_MBOXX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2005 #define basename_BDK_RVU_PF_PFAF_MBOXX(a) "RVU_PF_PFAF_MBOXX"
2006 #define device_bar_BDK_RVU_PF_PFAF_MBOXX(a) 0x2 /* BAR2 */
2007 #define busnum_BDK_RVU_PF_PFAF_MBOXX(a) (a)
2008 #define arguments_BDK_RVU_PF_PFAF_MBOXX(a) (a),-1,-1,-1
2009
2010 /**
2011 * Register (RVU_PF_BAR2) rvu_pf_vf#_pfvf_mbox#
2012 *
2013 * RVU PF/VF Mailbox Registers
2014 */
2015 union bdk_rvu_pf_vfx_pfvf_mboxx
2016 {
2017 uint64_t u;
2018 struct bdk_rvu_pf_vfx_pfvf_mboxx_s
2019 {
2020 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2021 uint64_t data : 64; /**< [ 63: 0](R/W/H) Mailbox data. These PF registers access the 16-byte-per-VF VF/PF mailbox
2022 RAM. Each corresponding VF may access the same storage using
2023 RVU_VF_VFPF_MBOX(). MBOX(0) is typically used for PF to VF
2024 signaling, MBOX(1) for VF to PF. Writing RVU_PF_VF()_PFVF_MBOX(0) (but
2025 not RVU_VF_VFPF_MBOX(0)) will set the corresponding
2026 RVU_VF_INT[MBOX] which if appropriately enabled will send an
2027 interrupt to the VF. */
2028 #else /* Word 0 - Little Endian */
2029 uint64_t data : 64; /**< [ 63: 0](R/W/H) Mailbox data. These PF registers access the 16-byte-per-VF VF/PF mailbox
2030 RAM. Each corresponding VF may access the same storage using
2031 RVU_VF_VFPF_MBOX(). MBOX(0) is typically used for PF to VF
2032 signaling, MBOX(1) for VF to PF. Writing RVU_PF_VF()_PFVF_MBOX(0) (but
2033 not RVU_VF_VFPF_MBOX(0)) will set the corresponding
2034 RVU_VF_INT[MBOX] which if appropriately enabled will send an
2035 interrupt to the VF. */
2036 #endif /* Word 0 - End */
2037 } s;
2038 /* struct bdk_rvu_pf_vfx_pfvf_mboxx_s cn; */
2039 };
2040 typedef union bdk_rvu_pf_vfx_pfvf_mboxx bdk_rvu_pf_vfx_pfvf_mboxx_t;
2041
2042 static inline uint64_t BDK_RVU_PF_VFX_PFVF_MBOXX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFX_PFVF_MBOXX(unsigned long a,unsigned long b)2043 static inline uint64_t BDK_RVU_PF_VFX_PFVF_MBOXX(unsigned long a, unsigned long b)
2044 {
2045 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=127) && (b<=1)))
2046 return 0x850200000000ll + 0x1000ll * ((a) & 0x7f) + 8ll * ((b) & 0x1);
2047 __bdk_csr_fatal("RVU_PF_VFX_PFVF_MBOXX", 2, a, b, 0, 0);
2048 }
2049
2050 #define typedef_BDK_RVU_PF_VFX_PFVF_MBOXX(a,b) bdk_rvu_pf_vfx_pfvf_mboxx_t
2051 #define bustype_BDK_RVU_PF_VFX_PFVF_MBOXX(a,b) BDK_CSR_TYPE_RVU_PF_BAR2
2052 #define basename_BDK_RVU_PF_VFX_PFVF_MBOXX(a,b) "RVU_PF_VFX_PFVF_MBOXX"
2053 #define device_bar_BDK_RVU_PF_VFX_PFVF_MBOXX(a,b) 0x2 /* BAR2 */
2054 #define busnum_BDK_RVU_PF_VFX_PFVF_MBOXX(a,b) (a)
2055 #define arguments_BDK_RVU_PF_VFX_PFVF_MBOXX(a,b) (a),(b),-1,-1
2056
2057 /**
2058 * Register (RVU_PF_BAR2) rvu_pf_vf_bar4_addr
2059 *
2060 * RVU PF VF BAR4 Address Registers
2061 */
2062 union bdk_rvu_pf_vf_bar4_addr
2063 {
2064 uint64_t u;
2065 struct bdk_rvu_pf_vf_bar4_addr_s
2066 {
2067 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2068 uint64_t addr : 48; /**< [ 63: 16](R/W) Programmable base address of RVU_PRIV_PF()_CFG[NVF] consecutive 64 KB
2069 pages in DRAM. May be used as VF/PF mailbox memory in addition to
2070 RVU_PF_VF()_PFVF_MBOX()/RVU_VF_VFPF_MBOX().
2071 Provides PCC_EA_ENTRY_S[BASEH,BASEL] value advertised by VF BAR4's entry in
2072 PCCPF_XXX_EA_ENTRY(). */
2073 uint64_t reserved_0_15 : 16;
2074 #else /* Word 0 - Little Endian */
2075 uint64_t reserved_0_15 : 16;
2076 uint64_t addr : 48; /**< [ 63: 16](R/W) Programmable base address of RVU_PRIV_PF()_CFG[NVF] consecutive 64 KB
2077 pages in DRAM. May be used as VF/PF mailbox memory in addition to
2078 RVU_PF_VF()_PFVF_MBOX()/RVU_VF_VFPF_MBOX().
2079 Provides PCC_EA_ENTRY_S[BASEH,BASEL] value advertised by VF BAR4's entry in
2080 PCCPF_XXX_EA_ENTRY(). */
2081 #endif /* Word 0 - End */
2082 } s;
2083 /* struct bdk_rvu_pf_vf_bar4_addr_s cn; */
2084 };
2085 typedef union bdk_rvu_pf_vf_bar4_addr bdk_rvu_pf_vf_bar4_addr_t;
2086
2087 #define BDK_RVU_PF_VF_BAR4_ADDR BDK_RVU_PF_VF_BAR4_ADDR_FUNC()
2088 static inline uint64_t BDK_RVU_PF_VF_BAR4_ADDR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VF_BAR4_ADDR_FUNC(void)2089 static inline uint64_t BDK_RVU_PF_VF_BAR4_ADDR_FUNC(void)
2090 {
2091 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2092 return 0x850200000010ll;
2093 __bdk_csr_fatal("RVU_PF_VF_BAR4_ADDR", 0, 0, 0, 0, 0);
2094 }
2095
2096 #define typedef_BDK_RVU_PF_VF_BAR4_ADDR bdk_rvu_pf_vf_bar4_addr_t
2097 #define bustype_BDK_RVU_PF_VF_BAR4_ADDR BDK_CSR_TYPE_RVU_PF_BAR2
2098 #define basename_BDK_RVU_PF_VF_BAR4_ADDR "RVU_PF_VF_BAR4_ADDR"
2099 #define device_bar_BDK_RVU_PF_VF_BAR4_ADDR 0x2 /* BAR2 */
2100 #define busnum_BDK_RVU_PF_VF_BAR4_ADDR 0
2101 #define arguments_BDK_RVU_PF_VF_BAR4_ADDR -1,-1,-1,-1
2102
2103 /**
2104 * Register (RVU_PF_BAR2) rvu_pf_vfflr_int#
2105 *
2106 * RVU PF VF Function Level Reset Interrupt Registers
2107 */
2108 union bdk_rvu_pf_vfflr_intx
2109 {
2110 uint64_t u;
2111 struct bdk_rvu_pf_vfflr_intx_s
2112 {
2113 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2114 uint64_t flr : 64; /**< [ 63: 0](R/W1C/H) FLR interrupt bit per VF (RVU_PF_VFFLR_INT({a})[FLR]\<{b}\> for VF
2115 number 64*{a} + {b}).
2116 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, each bit is set along with
2117 the corresponding bit in RVU_PF_VFTRPEND() when function level reset is
2118 initiated for the associated VF, i.e. a one is written to
2119 PCCVF_XXX_E_DEV_CTL[BCR_FLR]. */
2120 #else /* Word 0 - Little Endian */
2121 uint64_t flr : 64; /**< [ 63: 0](R/W1C/H) FLR interrupt bit per VF (RVU_PF_VFFLR_INT({a})[FLR]\<{b}\> for VF
2122 number 64*{a} + {b}).
2123 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, each bit is set along with
2124 the corresponding bit in RVU_PF_VFTRPEND() when function level reset is
2125 initiated for the associated VF, i.e. a one is written to
2126 PCCVF_XXX_E_DEV_CTL[BCR_FLR]. */
2127 #endif /* Word 0 - End */
2128 } s;
2129 /* struct bdk_rvu_pf_vfflr_intx_s cn; */
2130 };
2131 typedef union bdk_rvu_pf_vfflr_intx bdk_rvu_pf_vfflr_intx_t;
2132
2133 static inline uint64_t BDK_RVU_PF_VFFLR_INTX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFFLR_INTX(unsigned long a)2134 static inline uint64_t BDK_RVU_PF_VFFLR_INTX(unsigned long a)
2135 {
2136 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2137 return 0x850200000900ll + 8ll * ((a) & 0x3);
2138 __bdk_csr_fatal("RVU_PF_VFFLR_INTX", 1, a, 0, 0, 0);
2139 }
2140
2141 #define typedef_BDK_RVU_PF_VFFLR_INTX(a) bdk_rvu_pf_vfflr_intx_t
2142 #define bustype_BDK_RVU_PF_VFFLR_INTX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2143 #define basename_BDK_RVU_PF_VFFLR_INTX(a) "RVU_PF_VFFLR_INTX"
2144 #define device_bar_BDK_RVU_PF_VFFLR_INTX(a) 0x2 /* BAR2 */
2145 #define busnum_BDK_RVU_PF_VFFLR_INTX(a) (a)
2146 #define arguments_BDK_RVU_PF_VFFLR_INTX(a) (a),-1,-1,-1
2147
2148 /**
2149 * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_ena_w1c#
2150 *
2151 * RVU PF VF Function Level Reset Interrupt Enable Clear Registers
2152 * This register clears interrupt enable bits.
2153 */
2154 union bdk_rvu_pf_vfflr_int_ena_w1cx
2155 {
2156 uint64_t u;
2157 struct bdk_rvu_pf_vfflr_int_ena_w1cx_s
2158 {
2159 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2160 uint64_t flr : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_PF_VFFLR_INT(0..3)[FLR]. */
2161 #else /* Word 0 - Little Endian */
2162 uint64_t flr : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_PF_VFFLR_INT(0..3)[FLR]. */
2163 #endif /* Word 0 - End */
2164 } s;
2165 /* struct bdk_rvu_pf_vfflr_int_ena_w1cx_s cn; */
2166 };
2167 typedef union bdk_rvu_pf_vfflr_int_ena_w1cx bdk_rvu_pf_vfflr_int_ena_w1cx_t;
2168
2169 static inline uint64_t BDK_RVU_PF_VFFLR_INT_ENA_W1CX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFFLR_INT_ENA_W1CX(unsigned long a)2170 static inline uint64_t BDK_RVU_PF_VFFLR_INT_ENA_W1CX(unsigned long a)
2171 {
2172 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2173 return 0x850200000960ll + 8ll * ((a) & 0x3);
2174 __bdk_csr_fatal("RVU_PF_VFFLR_INT_ENA_W1CX", 1, a, 0, 0, 0);
2175 }
2176
2177 #define typedef_BDK_RVU_PF_VFFLR_INT_ENA_W1CX(a) bdk_rvu_pf_vfflr_int_ena_w1cx_t
2178 #define bustype_BDK_RVU_PF_VFFLR_INT_ENA_W1CX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2179 #define basename_BDK_RVU_PF_VFFLR_INT_ENA_W1CX(a) "RVU_PF_VFFLR_INT_ENA_W1CX"
2180 #define device_bar_BDK_RVU_PF_VFFLR_INT_ENA_W1CX(a) 0x2 /* BAR2 */
2181 #define busnum_BDK_RVU_PF_VFFLR_INT_ENA_W1CX(a) (a)
2182 #define arguments_BDK_RVU_PF_VFFLR_INT_ENA_W1CX(a) (a),-1,-1,-1
2183
2184 /**
2185 * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_ena_w1s#
2186 *
2187 * RVU PF VF Function Level Reset Interrupt Enable Set Registers
2188 * This register sets interrupt enable bits.
2189 */
2190 union bdk_rvu_pf_vfflr_int_ena_w1sx
2191 {
2192 uint64_t u;
2193 struct bdk_rvu_pf_vfflr_int_ena_w1sx_s
2194 {
2195 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2196 uint64_t flr : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_PF_VFFLR_INT(0..3)[FLR]. */
2197 #else /* Word 0 - Little Endian */
2198 uint64_t flr : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_PF_VFFLR_INT(0..3)[FLR]. */
2199 #endif /* Word 0 - End */
2200 } s;
2201 /* struct bdk_rvu_pf_vfflr_int_ena_w1sx_s cn; */
2202 };
2203 typedef union bdk_rvu_pf_vfflr_int_ena_w1sx bdk_rvu_pf_vfflr_int_ena_w1sx_t;
2204
2205 static inline uint64_t BDK_RVU_PF_VFFLR_INT_ENA_W1SX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFFLR_INT_ENA_W1SX(unsigned long a)2206 static inline uint64_t BDK_RVU_PF_VFFLR_INT_ENA_W1SX(unsigned long a)
2207 {
2208 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2209 return 0x850200000940ll + 8ll * ((a) & 0x3);
2210 __bdk_csr_fatal("RVU_PF_VFFLR_INT_ENA_W1SX", 1, a, 0, 0, 0);
2211 }
2212
2213 #define typedef_BDK_RVU_PF_VFFLR_INT_ENA_W1SX(a) bdk_rvu_pf_vfflr_int_ena_w1sx_t
2214 #define bustype_BDK_RVU_PF_VFFLR_INT_ENA_W1SX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2215 #define basename_BDK_RVU_PF_VFFLR_INT_ENA_W1SX(a) "RVU_PF_VFFLR_INT_ENA_W1SX"
2216 #define device_bar_BDK_RVU_PF_VFFLR_INT_ENA_W1SX(a) 0x2 /* BAR2 */
2217 #define busnum_BDK_RVU_PF_VFFLR_INT_ENA_W1SX(a) (a)
2218 #define arguments_BDK_RVU_PF_VFFLR_INT_ENA_W1SX(a) (a),-1,-1,-1
2219
2220 /**
2221 * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_w1s#
2222 *
2223 * RVU PF VF Function Level Reset Interrupt Set Registers
2224 * This register sets interrupt bits.
2225 */
2226 union bdk_rvu_pf_vfflr_int_w1sx
2227 {
2228 uint64_t u;
2229 struct bdk_rvu_pf_vfflr_int_w1sx_s
2230 {
2231 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2232 uint64_t flr : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_PF_VFFLR_INT(0..3)[FLR]. */
2233 #else /* Word 0 - Little Endian */
2234 uint64_t flr : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_PF_VFFLR_INT(0..3)[FLR]. */
2235 #endif /* Word 0 - End */
2236 } s;
2237 /* struct bdk_rvu_pf_vfflr_int_w1sx_s cn; */
2238 };
2239 typedef union bdk_rvu_pf_vfflr_int_w1sx bdk_rvu_pf_vfflr_int_w1sx_t;
2240
2241 static inline uint64_t BDK_RVU_PF_VFFLR_INT_W1SX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFFLR_INT_W1SX(unsigned long a)2242 static inline uint64_t BDK_RVU_PF_VFFLR_INT_W1SX(unsigned long a)
2243 {
2244 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2245 return 0x850200000920ll + 8ll * ((a) & 0x3);
2246 __bdk_csr_fatal("RVU_PF_VFFLR_INT_W1SX", 1, a, 0, 0, 0);
2247 }
2248
2249 #define typedef_BDK_RVU_PF_VFFLR_INT_W1SX(a) bdk_rvu_pf_vfflr_int_w1sx_t
2250 #define bustype_BDK_RVU_PF_VFFLR_INT_W1SX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2251 #define basename_BDK_RVU_PF_VFFLR_INT_W1SX(a) "RVU_PF_VFFLR_INT_W1SX"
2252 #define device_bar_BDK_RVU_PF_VFFLR_INT_W1SX(a) 0x2 /* BAR2 */
2253 #define busnum_BDK_RVU_PF_VFFLR_INT_W1SX(a) (a)
2254 #define arguments_BDK_RVU_PF_VFFLR_INT_W1SX(a) (a),-1,-1,-1
2255
2256 /**
2257 * Register (RVU_PF_BAR2) rvu_pf_vfme_int#
2258 *
2259 * RVU PF VF Bus Master Enable Interrupt Registers
2260 */
2261 union bdk_rvu_pf_vfme_intx
2262 {
2263 uint64_t u;
2264 struct bdk_rvu_pf_vfme_intx_s
2265 {
2266 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2267 uint64_t me : 64; /**< [ 63: 0](R/W1C/H) Master enable interrupt bit per VF (RVU_PF_VFME_INT({a})[ME]\<{b}\> for VF
2268 number 64*{a} + {b}).
2269 A device-dependent PF driver typically uses these bits to handle state
2270 changes to PCCPF_XXX_CMD[ME], which are typically modified by
2271 non-device-dependent software only.
2272
2273 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, each bit is set when the
2274 corresponding PCCVF_XXX_CMD[ME] bit is either set or cleared for the
2275 associated PF. The corresponding bit in RVU_PF_VFME_STATUS() returns the
2276 current value of PCCVF_XXX_CMD[ME].
2277
2278 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, the corresponding bit in
2279 RVU_PF_VFTRPEND() is also set when PCCVF_XXX_CMD[ME] is set, but not
2280 when PCCVF_XXX_CMD[ME] is cleared. */
2281 #else /* Word 0 - Little Endian */
2282 uint64_t me : 64; /**< [ 63: 0](R/W1C/H) Master enable interrupt bit per VF (RVU_PF_VFME_INT({a})[ME]\<{b}\> for VF
2283 number 64*{a} + {b}).
2284 A device-dependent PF driver typically uses these bits to handle state
2285 changes to PCCPF_XXX_CMD[ME], which are typically modified by
2286 non-device-dependent software only.
2287
2288 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, each bit is set when the
2289 corresponding PCCVF_XXX_CMD[ME] bit is either set or cleared for the
2290 associated PF. The corresponding bit in RVU_PF_VFME_STATUS() returns the
2291 current value of PCCVF_XXX_CMD[ME].
2292
2293 If RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set, the corresponding bit in
2294 RVU_PF_VFTRPEND() is also set when PCCVF_XXX_CMD[ME] is set, but not
2295 when PCCVF_XXX_CMD[ME] is cleared. */
2296 #endif /* Word 0 - End */
2297 } s;
2298 /* struct bdk_rvu_pf_vfme_intx_s cn; */
2299 };
2300 typedef union bdk_rvu_pf_vfme_intx bdk_rvu_pf_vfme_intx_t;
2301
2302 static inline uint64_t BDK_RVU_PF_VFME_INTX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFME_INTX(unsigned long a)2303 static inline uint64_t BDK_RVU_PF_VFME_INTX(unsigned long a)
2304 {
2305 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2306 return 0x850200000980ll + 8ll * ((a) & 0x3);
2307 __bdk_csr_fatal("RVU_PF_VFME_INTX", 1, a, 0, 0, 0);
2308 }
2309
2310 #define typedef_BDK_RVU_PF_VFME_INTX(a) bdk_rvu_pf_vfme_intx_t
2311 #define bustype_BDK_RVU_PF_VFME_INTX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2312 #define basename_BDK_RVU_PF_VFME_INTX(a) "RVU_PF_VFME_INTX"
2313 #define device_bar_BDK_RVU_PF_VFME_INTX(a) 0x2 /* BAR2 */
2314 #define busnum_BDK_RVU_PF_VFME_INTX(a) (a)
2315 #define arguments_BDK_RVU_PF_VFME_INTX(a) (a),-1,-1,-1
2316
2317 /**
2318 * Register (RVU_PF_BAR2) rvu_pf_vfme_int_ena_w1c#
2319 *
2320 * RVU PF VF Bus Master Enable Interrupt Enable Clear Registers
2321 * This register clears interrupt enable bits.
2322 */
2323 union bdk_rvu_pf_vfme_int_ena_w1cx
2324 {
2325 uint64_t u;
2326 struct bdk_rvu_pf_vfme_int_ena_w1cx_s
2327 {
2328 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2329 uint64_t me : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_PF_VFME_INT(0..3)[ME]. */
2330 #else /* Word 0 - Little Endian */
2331 uint64_t me : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_PF_VFME_INT(0..3)[ME]. */
2332 #endif /* Word 0 - End */
2333 } s;
2334 /* struct bdk_rvu_pf_vfme_int_ena_w1cx_s cn; */
2335 };
2336 typedef union bdk_rvu_pf_vfme_int_ena_w1cx bdk_rvu_pf_vfme_int_ena_w1cx_t;
2337
2338 static inline uint64_t BDK_RVU_PF_VFME_INT_ENA_W1CX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFME_INT_ENA_W1CX(unsigned long a)2339 static inline uint64_t BDK_RVU_PF_VFME_INT_ENA_W1CX(unsigned long a)
2340 {
2341 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2342 return 0x8502000009e0ll + 8ll * ((a) & 0x3);
2343 __bdk_csr_fatal("RVU_PF_VFME_INT_ENA_W1CX", 1, a, 0, 0, 0);
2344 }
2345
2346 #define typedef_BDK_RVU_PF_VFME_INT_ENA_W1CX(a) bdk_rvu_pf_vfme_int_ena_w1cx_t
2347 #define bustype_BDK_RVU_PF_VFME_INT_ENA_W1CX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2348 #define basename_BDK_RVU_PF_VFME_INT_ENA_W1CX(a) "RVU_PF_VFME_INT_ENA_W1CX"
2349 #define device_bar_BDK_RVU_PF_VFME_INT_ENA_W1CX(a) 0x2 /* BAR2 */
2350 #define busnum_BDK_RVU_PF_VFME_INT_ENA_W1CX(a) (a)
2351 #define arguments_BDK_RVU_PF_VFME_INT_ENA_W1CX(a) (a),-1,-1,-1
2352
2353 /**
2354 * Register (RVU_PF_BAR2) rvu_pf_vfme_int_ena_w1s#
2355 *
2356 * RVU PF VF Bus Master Enable Interrupt Enable Set Registers
2357 * This register sets interrupt enable bits.
2358 */
2359 union bdk_rvu_pf_vfme_int_ena_w1sx
2360 {
2361 uint64_t u;
2362 struct bdk_rvu_pf_vfme_int_ena_w1sx_s
2363 {
2364 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2365 uint64_t me : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_PF_VFME_INT(0..3)[ME]. */
2366 #else /* Word 0 - Little Endian */
2367 uint64_t me : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_PF_VFME_INT(0..3)[ME]. */
2368 #endif /* Word 0 - End */
2369 } s;
2370 /* struct bdk_rvu_pf_vfme_int_ena_w1sx_s cn; */
2371 };
2372 typedef union bdk_rvu_pf_vfme_int_ena_w1sx bdk_rvu_pf_vfme_int_ena_w1sx_t;
2373
2374 static inline uint64_t BDK_RVU_PF_VFME_INT_ENA_W1SX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFME_INT_ENA_W1SX(unsigned long a)2375 static inline uint64_t BDK_RVU_PF_VFME_INT_ENA_W1SX(unsigned long a)
2376 {
2377 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2378 return 0x8502000009c0ll + 8ll * ((a) & 0x3);
2379 __bdk_csr_fatal("RVU_PF_VFME_INT_ENA_W1SX", 1, a, 0, 0, 0);
2380 }
2381
2382 #define typedef_BDK_RVU_PF_VFME_INT_ENA_W1SX(a) bdk_rvu_pf_vfme_int_ena_w1sx_t
2383 #define bustype_BDK_RVU_PF_VFME_INT_ENA_W1SX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2384 #define basename_BDK_RVU_PF_VFME_INT_ENA_W1SX(a) "RVU_PF_VFME_INT_ENA_W1SX"
2385 #define device_bar_BDK_RVU_PF_VFME_INT_ENA_W1SX(a) 0x2 /* BAR2 */
2386 #define busnum_BDK_RVU_PF_VFME_INT_ENA_W1SX(a) (a)
2387 #define arguments_BDK_RVU_PF_VFME_INT_ENA_W1SX(a) (a),-1,-1,-1
2388
2389 /**
2390 * Register (RVU_PF_BAR2) rvu_pf_vfme_int_w1s#
2391 *
2392 * RVU PF VF Bus Master Enable Interrupt Set Registers
2393 * This register sets interrupt bits.
2394 */
2395 union bdk_rvu_pf_vfme_int_w1sx
2396 {
2397 uint64_t u;
2398 struct bdk_rvu_pf_vfme_int_w1sx_s
2399 {
2400 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2401 uint64_t me : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_PF_VFME_INT(0..3)[ME]. */
2402 #else /* Word 0 - Little Endian */
2403 uint64_t me : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_PF_VFME_INT(0..3)[ME]. */
2404 #endif /* Word 0 - End */
2405 } s;
2406 /* struct bdk_rvu_pf_vfme_int_w1sx_s cn; */
2407 };
2408 typedef union bdk_rvu_pf_vfme_int_w1sx bdk_rvu_pf_vfme_int_w1sx_t;
2409
2410 static inline uint64_t BDK_RVU_PF_VFME_INT_W1SX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFME_INT_W1SX(unsigned long a)2411 static inline uint64_t BDK_RVU_PF_VFME_INT_W1SX(unsigned long a)
2412 {
2413 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2414 return 0x8502000009a0ll + 8ll * ((a) & 0x3);
2415 __bdk_csr_fatal("RVU_PF_VFME_INT_W1SX", 1, a, 0, 0, 0);
2416 }
2417
2418 #define typedef_BDK_RVU_PF_VFME_INT_W1SX(a) bdk_rvu_pf_vfme_int_w1sx_t
2419 #define bustype_BDK_RVU_PF_VFME_INT_W1SX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2420 #define basename_BDK_RVU_PF_VFME_INT_W1SX(a) "RVU_PF_VFME_INT_W1SX"
2421 #define device_bar_BDK_RVU_PF_VFME_INT_W1SX(a) 0x2 /* BAR2 */
2422 #define busnum_BDK_RVU_PF_VFME_INT_W1SX(a) (a)
2423 #define arguments_BDK_RVU_PF_VFME_INT_W1SX(a) (a),-1,-1,-1
2424
2425 /**
2426 * Register (RVU_PF_BAR2) rvu_pf_vfme_status#
2427 *
2428 * RVU PF VF Bus Master Enable Status Registers
2429 */
2430 union bdk_rvu_pf_vfme_statusx
2431 {
2432 uint64_t u;
2433 struct bdk_rvu_pf_vfme_statusx_s
2434 {
2435 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2436 uint64_t me : 64; /**< [ 63: 0](RO/H) Bus master enable bit per VF (RVU_PF_VFME_STATUS({a})[ME]\<{b}\> for VF
2437 number 64*{a} + {b}).
2438 Each bit returns the VF's PCCVF_XXX_CMD[ME] value. */
2439 #else /* Word 0 - Little Endian */
2440 uint64_t me : 64; /**< [ 63: 0](RO/H) Bus master enable bit per VF (RVU_PF_VFME_STATUS({a})[ME]\<{b}\> for VF
2441 number 64*{a} + {b}).
2442 Each bit returns the VF's PCCVF_XXX_CMD[ME] value. */
2443 #endif /* Word 0 - End */
2444 } s;
2445 /* struct bdk_rvu_pf_vfme_statusx_s cn; */
2446 };
2447 typedef union bdk_rvu_pf_vfme_statusx bdk_rvu_pf_vfme_statusx_t;
2448
2449 static inline uint64_t BDK_RVU_PF_VFME_STATUSX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFME_STATUSX(unsigned long a)2450 static inline uint64_t BDK_RVU_PF_VFME_STATUSX(unsigned long a)
2451 {
2452 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2453 return 0x850200000800ll + 8ll * ((a) & 0x3);
2454 __bdk_csr_fatal("RVU_PF_VFME_STATUSX", 1, a, 0, 0, 0);
2455 }
2456
2457 #define typedef_BDK_RVU_PF_VFME_STATUSX(a) bdk_rvu_pf_vfme_statusx_t
2458 #define bustype_BDK_RVU_PF_VFME_STATUSX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2459 #define basename_BDK_RVU_PF_VFME_STATUSX(a) "RVU_PF_VFME_STATUSX"
2460 #define device_bar_BDK_RVU_PF_VFME_STATUSX(a) 0x2 /* BAR2 */
2461 #define busnum_BDK_RVU_PF_VFME_STATUSX(a) (a)
2462 #define arguments_BDK_RVU_PF_VFME_STATUSX(a) (a),-1,-1,-1
2463
2464 /**
2465 * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int#
2466 *
2467 * RVU VF to PF Mailbox Interrupt Registers
2468 */
2469 union bdk_rvu_pf_vfpf_mbox_intx
2470 {
2471 uint64_t u;
2472 struct bdk_rvu_pf_vfpf_mbox_intx_s
2473 {
2474 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2475 uint64_t mbox : 64; /**< [ 63: 0](R/W1C/H) Mailbox interrupt bit per VF (RVU_PF_VFPF_MBOX_INT({a})[MBOX]\<{b}\> for VF
2476 number 64*{a} + {b}).
2477 Each bit is set when the VF writes to the corresponding
2478 RVU_VF_VFPF_MBOX(1) register. */
2479 #else /* Word 0 - Little Endian */
2480 uint64_t mbox : 64; /**< [ 63: 0](R/W1C/H) Mailbox interrupt bit per VF (RVU_PF_VFPF_MBOX_INT({a})[MBOX]\<{b}\> for VF
2481 number 64*{a} + {b}).
2482 Each bit is set when the VF writes to the corresponding
2483 RVU_VF_VFPF_MBOX(1) register. */
2484 #endif /* Word 0 - End */
2485 } s;
2486 /* struct bdk_rvu_pf_vfpf_mbox_intx_s cn; */
2487 };
2488 typedef union bdk_rvu_pf_vfpf_mbox_intx bdk_rvu_pf_vfpf_mbox_intx_t;
2489
2490 static inline uint64_t BDK_RVU_PF_VFPF_MBOX_INTX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFPF_MBOX_INTX(unsigned long a)2491 static inline uint64_t BDK_RVU_PF_VFPF_MBOX_INTX(unsigned long a)
2492 {
2493 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2494 return 0x850200000880ll + 8ll * ((a) & 0x3);
2495 __bdk_csr_fatal("RVU_PF_VFPF_MBOX_INTX", 1, a, 0, 0, 0);
2496 }
2497
2498 #define typedef_BDK_RVU_PF_VFPF_MBOX_INTX(a) bdk_rvu_pf_vfpf_mbox_intx_t
2499 #define bustype_BDK_RVU_PF_VFPF_MBOX_INTX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2500 #define basename_BDK_RVU_PF_VFPF_MBOX_INTX(a) "RVU_PF_VFPF_MBOX_INTX"
2501 #define device_bar_BDK_RVU_PF_VFPF_MBOX_INTX(a) 0x2 /* BAR2 */
2502 #define busnum_BDK_RVU_PF_VFPF_MBOX_INTX(a) (a)
2503 #define arguments_BDK_RVU_PF_VFPF_MBOX_INTX(a) (a),-1,-1,-1
2504
2505 /**
2506 * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_ena_w1c#
2507 *
2508 * RVU VF to PF Mailbox Interrupt Enable Clear Registers
2509 * This register clears interrupt enable bits.
2510 */
2511 union bdk_rvu_pf_vfpf_mbox_int_ena_w1cx
2512 {
2513 uint64_t u;
2514 struct bdk_rvu_pf_vfpf_mbox_int_ena_w1cx_s
2515 {
2516 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2517 uint64_t mbox : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_PF_VFPF_MBOX_INT(0..3)[MBOX]. */
2518 #else /* Word 0 - Little Endian */
2519 uint64_t mbox : 64; /**< [ 63: 0](R/W1C/H) Reads or clears enable for RVU_PF_VFPF_MBOX_INT(0..3)[MBOX]. */
2520 #endif /* Word 0 - End */
2521 } s;
2522 /* struct bdk_rvu_pf_vfpf_mbox_int_ena_w1cx_s cn; */
2523 };
2524 typedef union bdk_rvu_pf_vfpf_mbox_int_ena_w1cx bdk_rvu_pf_vfpf_mbox_int_ena_w1cx_t;
2525
2526 static inline uint64_t BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(unsigned long a)2527 static inline uint64_t BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(unsigned long a)
2528 {
2529 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2530 return 0x8502000008e0ll + 8ll * ((a) & 0x3);
2531 __bdk_csr_fatal("RVU_PF_VFPF_MBOX_INT_ENA_W1CX", 1, a, 0, 0, 0);
2532 }
2533
2534 #define typedef_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) bdk_rvu_pf_vfpf_mbox_int_ena_w1cx_t
2535 #define bustype_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2536 #define basename_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) "RVU_PF_VFPF_MBOX_INT_ENA_W1CX"
2537 #define device_bar_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) 0x2 /* BAR2 */
2538 #define busnum_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (a)
2539 #define arguments_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (a),-1,-1,-1
2540
2541 /**
2542 * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_ena_w1s#
2543 *
2544 * RVU VF to PF Mailbox Interrupt Enable Set Registers
2545 * This register sets interrupt enable bits.
2546 */
2547 union bdk_rvu_pf_vfpf_mbox_int_ena_w1sx
2548 {
2549 uint64_t u;
2550 struct bdk_rvu_pf_vfpf_mbox_int_ena_w1sx_s
2551 {
2552 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2553 uint64_t mbox : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_PF_VFPF_MBOX_INT(0..3)[MBOX]. */
2554 #else /* Word 0 - Little Endian */
2555 uint64_t mbox : 64; /**< [ 63: 0](R/W1S/H) Reads or sets enable for RVU_PF_VFPF_MBOX_INT(0..3)[MBOX]. */
2556 #endif /* Word 0 - End */
2557 } s;
2558 /* struct bdk_rvu_pf_vfpf_mbox_int_ena_w1sx_s cn; */
2559 };
2560 typedef union bdk_rvu_pf_vfpf_mbox_int_ena_w1sx bdk_rvu_pf_vfpf_mbox_int_ena_w1sx_t;
2561
2562 static inline uint64_t BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(unsigned long a)2563 static inline uint64_t BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(unsigned long a)
2564 {
2565 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2566 return 0x8502000008c0ll + 8ll * ((a) & 0x3);
2567 __bdk_csr_fatal("RVU_PF_VFPF_MBOX_INT_ENA_W1SX", 1, a, 0, 0, 0);
2568 }
2569
2570 #define typedef_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) bdk_rvu_pf_vfpf_mbox_int_ena_w1sx_t
2571 #define bustype_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2572 #define basename_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) "RVU_PF_VFPF_MBOX_INT_ENA_W1SX"
2573 #define device_bar_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) 0x2 /* BAR2 */
2574 #define busnum_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (a)
2575 #define arguments_BDK_RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (a),-1,-1,-1
2576
2577 /**
2578 * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_w1s#
2579 *
2580 * RVU VF to PF Mailbox Interrupt Set Registers
2581 * This register sets interrupt bits.
2582 */
2583 union bdk_rvu_pf_vfpf_mbox_int_w1sx
2584 {
2585 uint64_t u;
2586 struct bdk_rvu_pf_vfpf_mbox_int_w1sx_s
2587 {
2588 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2589 uint64_t mbox : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_PF_VFPF_MBOX_INT(0..3)[MBOX]. */
2590 #else /* Word 0 - Little Endian */
2591 uint64_t mbox : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_PF_VFPF_MBOX_INT(0..3)[MBOX]. */
2592 #endif /* Word 0 - End */
2593 } s;
2594 /* struct bdk_rvu_pf_vfpf_mbox_int_w1sx_s cn; */
2595 };
2596 typedef union bdk_rvu_pf_vfpf_mbox_int_w1sx bdk_rvu_pf_vfpf_mbox_int_w1sx_t;
2597
2598 static inline uint64_t BDK_RVU_PF_VFPF_MBOX_INT_W1SX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFPF_MBOX_INT_W1SX(unsigned long a)2599 static inline uint64_t BDK_RVU_PF_VFPF_MBOX_INT_W1SX(unsigned long a)
2600 {
2601 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2602 return 0x8502000008a0ll + 8ll * ((a) & 0x3);
2603 __bdk_csr_fatal("RVU_PF_VFPF_MBOX_INT_W1SX", 1, a, 0, 0, 0);
2604 }
2605
2606 #define typedef_BDK_RVU_PF_VFPF_MBOX_INT_W1SX(a) bdk_rvu_pf_vfpf_mbox_int_w1sx_t
2607 #define bustype_BDK_RVU_PF_VFPF_MBOX_INT_W1SX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2608 #define basename_BDK_RVU_PF_VFPF_MBOX_INT_W1SX(a) "RVU_PF_VFPF_MBOX_INT_W1SX"
2609 #define device_bar_BDK_RVU_PF_VFPF_MBOX_INT_W1SX(a) 0x2 /* BAR2 */
2610 #define busnum_BDK_RVU_PF_VFPF_MBOX_INT_W1SX(a) (a)
2611 #define arguments_BDK_RVU_PF_VFPF_MBOX_INT_W1SX(a) (a),-1,-1,-1
2612
2613 /**
2614 * Register (RVU_PF_BAR2) rvu_pf_vftrpend#
2615 *
2616 * RVU PF VF Transaction Pending Registers
2617 */
2618 union bdk_rvu_pf_vftrpendx
2619 {
2620 uint64_t u;
2621 struct bdk_rvu_pf_vftrpendx_s
2622 {
2623 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2624 uint64_t trpend : 64; /**< [ 63: 0](R/W1C/H) Transaction pending bit per VF (RVU_PF_VFTRPEND({a})[TRPEND]\<{b}\> for VF
2625 number 64*{a} + {b}).
2626
2627 A VF's bit is set when RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set and:
2628 * A one is written to the corresponding PCCVF_XXX_E_DEV_CTL[BCR_FLR], or
2629 * PCCVF_XXX_CMD[ME] is set or cleared.
2630
2631 When a VF's bit is set, forces the corresponding
2632 PCCVF_XXX_E_DEV_CTL[TRPEND] to be set.
2633
2634 Software (typically a device-dependent PF driver) can clear the bit by
2635 writing a 1. */
2636 #else /* Word 0 - Little Endian */
2637 uint64_t trpend : 64; /**< [ 63: 0](R/W1C/H) Transaction pending bit per VF (RVU_PF_VFTRPEND({a})[TRPEND]\<{b}\> for VF
2638 number 64*{a} + {b}).
2639
2640 A VF's bit is set when RVU_PRIV_PF()_CFG[ME_FLR_ENA] is set and:
2641 * A one is written to the corresponding PCCVF_XXX_E_DEV_CTL[BCR_FLR], or
2642 * PCCVF_XXX_CMD[ME] is set or cleared.
2643
2644 When a VF's bit is set, forces the corresponding
2645 PCCVF_XXX_E_DEV_CTL[TRPEND] to be set.
2646
2647 Software (typically a device-dependent PF driver) can clear the bit by
2648 writing a 1. */
2649 #endif /* Word 0 - End */
2650 } s;
2651 /* struct bdk_rvu_pf_vftrpendx_s cn; */
2652 };
2653 typedef union bdk_rvu_pf_vftrpendx bdk_rvu_pf_vftrpendx_t;
2654
2655 static inline uint64_t BDK_RVU_PF_VFTRPENDX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFTRPENDX(unsigned long a)2656 static inline uint64_t BDK_RVU_PF_VFTRPENDX(unsigned long a)
2657 {
2658 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2659 return 0x850200000820ll + 8ll * ((a) & 0x3);
2660 __bdk_csr_fatal("RVU_PF_VFTRPENDX", 1, a, 0, 0, 0);
2661 }
2662
2663 #define typedef_BDK_RVU_PF_VFTRPENDX(a) bdk_rvu_pf_vftrpendx_t
2664 #define bustype_BDK_RVU_PF_VFTRPENDX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2665 #define basename_BDK_RVU_PF_VFTRPENDX(a) "RVU_PF_VFTRPENDX"
2666 #define device_bar_BDK_RVU_PF_VFTRPENDX(a) 0x2 /* BAR2 */
2667 #define busnum_BDK_RVU_PF_VFTRPENDX(a) (a)
2668 #define arguments_BDK_RVU_PF_VFTRPENDX(a) (a),-1,-1,-1
2669
2670 /**
2671 * Register (RVU_PF_BAR2) rvu_pf_vftrpend_w1s#
2672 *
2673 * RVU PF VF Transaction Pending Set Registers
2674 * This register reads or sets bits.
2675 */
2676 union bdk_rvu_pf_vftrpend_w1sx
2677 {
2678 uint64_t u;
2679 struct bdk_rvu_pf_vftrpend_w1sx_s
2680 {
2681 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2682 uint64_t trpend : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_PF_VFTRPEND(0..3)[TRPEND]. */
2683 #else /* Word 0 - Little Endian */
2684 uint64_t trpend : 64; /**< [ 63: 0](R/W1S/H) Reads or sets RVU_PF_VFTRPEND(0..3)[TRPEND]. */
2685 #endif /* Word 0 - End */
2686 } s;
2687 /* struct bdk_rvu_pf_vftrpend_w1sx_s cn; */
2688 };
2689 typedef union bdk_rvu_pf_vftrpend_w1sx bdk_rvu_pf_vftrpend_w1sx_t;
2690
2691 static inline uint64_t BDK_RVU_PF_VFTRPEND_W1SX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PF_VFTRPEND_W1SX(unsigned long a)2692 static inline uint64_t BDK_RVU_PF_VFTRPEND_W1SX(unsigned long a)
2693 {
2694 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2695 return 0x850200000840ll + 8ll * ((a) & 0x3);
2696 __bdk_csr_fatal("RVU_PF_VFTRPEND_W1SX", 1, a, 0, 0, 0);
2697 }
2698
2699 #define typedef_BDK_RVU_PF_VFTRPEND_W1SX(a) bdk_rvu_pf_vftrpend_w1sx_t
2700 #define bustype_BDK_RVU_PF_VFTRPEND_W1SX(a) BDK_CSR_TYPE_RVU_PF_BAR2
2701 #define basename_BDK_RVU_PF_VFTRPEND_W1SX(a) "RVU_PF_VFTRPEND_W1SX"
2702 #define device_bar_BDK_RVU_PF_VFTRPEND_W1SX(a) 0x2 /* BAR2 */
2703 #define busnum_BDK_RVU_PF_VFTRPEND_W1SX(a) (a)
2704 #define arguments_BDK_RVU_PF_VFTRPEND_W1SX(a) (a),-1,-1,-1
2705
2706 /**
2707 * Register (RVU_PF_BAR0) rvu_priv_active_pc
2708 *
2709 * RVU Active Program Counter Register
2710 */
2711 union bdk_rvu_priv_active_pc
2712 {
2713 uint64_t u;
2714 struct bdk_rvu_priv_active_pc_s
2715 {
2716 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2717 uint64_t active_pc : 64; /**< [ 63: 0](R/W/H) This register increments on every coprocessor-clock cycle that the RVU conditional clocks
2718 are enabled. */
2719 #else /* Word 0 - Little Endian */
2720 uint64_t active_pc : 64; /**< [ 63: 0](R/W/H) This register increments on every coprocessor-clock cycle that the RVU conditional clocks
2721 are enabled. */
2722 #endif /* Word 0 - End */
2723 } s;
2724 /* struct bdk_rvu_priv_active_pc_s cn; */
2725 };
2726 typedef union bdk_rvu_priv_active_pc bdk_rvu_priv_active_pc_t;
2727
2728 #define BDK_RVU_PRIV_ACTIVE_PC BDK_RVU_PRIV_ACTIVE_PC_FUNC()
2729 static inline uint64_t BDK_RVU_PRIV_ACTIVE_PC_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_ACTIVE_PC_FUNC(void)2730 static inline uint64_t BDK_RVU_PRIV_ACTIVE_PC_FUNC(void)
2731 {
2732 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2733 return 0x850008000030ll;
2734 __bdk_csr_fatal("RVU_PRIV_ACTIVE_PC", 0, 0, 0, 0, 0);
2735 }
2736
2737 #define typedef_BDK_RVU_PRIV_ACTIVE_PC bdk_rvu_priv_active_pc_t
2738 #define bustype_BDK_RVU_PRIV_ACTIVE_PC BDK_CSR_TYPE_RVU_PF_BAR0
2739 #define basename_BDK_RVU_PRIV_ACTIVE_PC "RVU_PRIV_ACTIVE_PC"
2740 #define device_bar_BDK_RVU_PRIV_ACTIVE_PC 0x0 /* BAR0 */
2741 #define busnum_BDK_RVU_PRIV_ACTIVE_PC 0
2742 #define arguments_BDK_RVU_PRIV_ACTIVE_PC -1,-1,-1,-1
2743
2744 /**
2745 * Register (RVU_PF_BAR0) rvu_priv_block_type#_rev
2746 *
2747 * RVU Privileged Block Type Revision Registers
2748 * These registers are used by configuration software to specify the revision ID
2749 * of each block type enumerated by RVU_BLOCK_TYPE_E, to assist VF/PF software
2750 * discovery.
2751 */
2752 union bdk_rvu_priv_block_typex_rev
2753 {
2754 uint64_t u;
2755 struct bdk_rvu_priv_block_typex_rev_s
2756 {
2757 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2758 uint64_t reserved_8_63 : 56;
2759 uint64_t rid : 8; /**< [ 7: 0](R/W) Revision ID of the block. This is the read value returned by
2760 RVU_VF_BLOCK_ADDR()_DISC[RID]. */
2761 #else /* Word 0 - Little Endian */
2762 uint64_t rid : 8; /**< [ 7: 0](R/W) Revision ID of the block. This is the read value returned by
2763 RVU_VF_BLOCK_ADDR()_DISC[RID]. */
2764 uint64_t reserved_8_63 : 56;
2765 #endif /* Word 0 - End */
2766 } s;
2767 /* struct bdk_rvu_priv_block_typex_rev_s cn; */
2768 };
2769 typedef union bdk_rvu_priv_block_typex_rev bdk_rvu_priv_block_typex_rev_t;
2770
2771 static inline uint64_t BDK_RVU_PRIV_BLOCK_TYPEX_REV(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_BLOCK_TYPEX_REV(unsigned long a)2772 static inline uint64_t BDK_RVU_PRIV_BLOCK_TYPEX_REV(unsigned long a)
2773 {
2774 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
2775 return 0x850008000400ll + 8ll * ((a) & 0xf);
2776 __bdk_csr_fatal("RVU_PRIV_BLOCK_TYPEX_REV", 1, a, 0, 0, 0);
2777 }
2778
2779 #define typedef_BDK_RVU_PRIV_BLOCK_TYPEX_REV(a) bdk_rvu_priv_block_typex_rev_t
2780 #define bustype_BDK_RVU_PRIV_BLOCK_TYPEX_REV(a) BDK_CSR_TYPE_RVU_PF_BAR0
2781 #define basename_BDK_RVU_PRIV_BLOCK_TYPEX_REV(a) "RVU_PRIV_BLOCK_TYPEX_REV"
2782 #define device_bar_BDK_RVU_PRIV_BLOCK_TYPEX_REV(a) 0x0 /* BAR0 */
2783 #define busnum_BDK_RVU_PRIV_BLOCK_TYPEX_REV(a) (a)
2784 #define arguments_BDK_RVU_PRIV_BLOCK_TYPEX_REV(a) (a),-1,-1,-1
2785
2786 /**
2787 * Register (RVU_PF_BAR0) rvu_priv_clk_cfg
2788 *
2789 * RVU Privileged General Configuration Register
2790 */
2791 union bdk_rvu_priv_clk_cfg
2792 {
2793 uint64_t u;
2794 struct bdk_rvu_priv_clk_cfg_s
2795 {
2796 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2797 uint64_t reserved_1_63 : 63;
2798 uint64_t clk_ena : 1; /**< [ 0: 0](R/W) Force conditional clock to always be enabled. For diagnostic use only. */
2799 #else /* Word 0 - Little Endian */
2800 uint64_t clk_ena : 1; /**< [ 0: 0](R/W) Force conditional clock to always be enabled. For diagnostic use only. */
2801 uint64_t reserved_1_63 : 63;
2802 #endif /* Word 0 - End */
2803 } s;
2804 /* struct bdk_rvu_priv_clk_cfg_s cn; */
2805 };
2806 typedef union bdk_rvu_priv_clk_cfg bdk_rvu_priv_clk_cfg_t;
2807
2808 #define BDK_RVU_PRIV_CLK_CFG BDK_RVU_PRIV_CLK_CFG_FUNC()
2809 static inline uint64_t BDK_RVU_PRIV_CLK_CFG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_CLK_CFG_FUNC(void)2810 static inline uint64_t BDK_RVU_PRIV_CLK_CFG_FUNC(void)
2811 {
2812 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2813 return 0x850008000020ll;
2814 __bdk_csr_fatal("RVU_PRIV_CLK_CFG", 0, 0, 0, 0, 0);
2815 }
2816
2817 #define typedef_BDK_RVU_PRIV_CLK_CFG bdk_rvu_priv_clk_cfg_t
2818 #define bustype_BDK_RVU_PRIV_CLK_CFG BDK_CSR_TYPE_RVU_PF_BAR0
2819 #define basename_BDK_RVU_PRIV_CLK_CFG "RVU_PRIV_CLK_CFG"
2820 #define device_bar_BDK_RVU_PRIV_CLK_CFG 0x0 /* BAR0 */
2821 #define busnum_BDK_RVU_PRIV_CLK_CFG 0
2822 #define arguments_BDK_RVU_PRIV_CLK_CFG -1,-1,-1,-1
2823
2824 /**
2825 * Register (RVU_PF_BAR0) rvu_priv_const
2826 *
2827 * RVU Privileged Constants Register
2828 * This register contains constants for software discovery.
2829 */
2830 union bdk_rvu_priv_const
2831 {
2832 uint64_t u;
2833 struct bdk_rvu_priv_const_s
2834 {
2835 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2836 uint64_t reserved_48_63 : 16;
2837 uint64_t max_vfs_per_pf : 8; /**< [ 47: 40](RO) Maximum number of VFs per RVU PF. */
2838 uint64_t pfs : 8; /**< [ 39: 32](RO) Number of RVU PFs. */
2839 uint64_t hwvfs : 12; /**< [ 31: 20](RO) Number of RVU hardware VFs (HWVFs). */
2840 uint64_t max_msix : 20; /**< [ 19: 0](RO) Combined maximum number of MSI-X vectors that may be provisioned to the RVU
2841 PFs and VFs. Also the maximum number of 16-byte RVU_MSIX_VEC_S structures
2842 in RVU's MSI-X table region in LLC/DRAM. See RVU_PRIV_PF()_MSIX_CFG.
2843
2844 Internal:
2845 Also, size of RVU's internal PBA memory.
2846
2847 Sized as follows:
2848 \<pre\>
2849 AP cores 24
2850 Vectors per LF:
2851 NIX CINT 32
2852 NIX QINT 32
2853 NIX GINT 1
2854 NPA QINT 32
2855 NPA GINT 1
2856 SSO 1
2857 TIM 1
2858 CPT 1
2859 RVU 1
2860 Total per LF: \<128
2861 Num LFs 256
2862 Total LF vectors \<32K
2863 Total AF vectors 64 (budget 16 blocks * 4)
2864 Total vectors budget 32K
2865 \</pre\> */
2866 #else /* Word 0 - Little Endian */
2867 uint64_t max_msix : 20; /**< [ 19: 0](RO) Combined maximum number of MSI-X vectors that may be provisioned to the RVU
2868 PFs and VFs. Also the maximum number of 16-byte RVU_MSIX_VEC_S structures
2869 in RVU's MSI-X table region in LLC/DRAM. See RVU_PRIV_PF()_MSIX_CFG.
2870
2871 Internal:
2872 Also, size of RVU's internal PBA memory.
2873
2874 Sized as follows:
2875 \<pre\>
2876 AP cores 24
2877 Vectors per LF:
2878 NIX CINT 32
2879 NIX QINT 32
2880 NIX GINT 1
2881 NPA QINT 32
2882 NPA GINT 1
2883 SSO 1
2884 TIM 1
2885 CPT 1
2886 RVU 1
2887 Total per LF: \<128
2888 Num LFs 256
2889 Total LF vectors \<32K
2890 Total AF vectors 64 (budget 16 blocks * 4)
2891 Total vectors budget 32K
2892 \</pre\> */
2893 uint64_t hwvfs : 12; /**< [ 31: 20](RO) Number of RVU hardware VFs (HWVFs). */
2894 uint64_t pfs : 8; /**< [ 39: 32](RO) Number of RVU PFs. */
2895 uint64_t max_vfs_per_pf : 8; /**< [ 47: 40](RO) Maximum number of VFs per RVU PF. */
2896 uint64_t reserved_48_63 : 16;
2897 #endif /* Word 0 - End */
2898 } s;
2899 /* struct bdk_rvu_priv_const_s cn; */
2900 };
2901 typedef union bdk_rvu_priv_const bdk_rvu_priv_const_t;
2902
2903 #define BDK_RVU_PRIV_CONST BDK_RVU_PRIV_CONST_FUNC()
2904 static inline uint64_t BDK_RVU_PRIV_CONST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_CONST_FUNC(void)2905 static inline uint64_t BDK_RVU_PRIV_CONST_FUNC(void)
2906 {
2907 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2908 return 0x850008000000ll;
2909 __bdk_csr_fatal("RVU_PRIV_CONST", 0, 0, 0, 0, 0);
2910 }
2911
2912 #define typedef_BDK_RVU_PRIV_CONST bdk_rvu_priv_const_t
2913 #define bustype_BDK_RVU_PRIV_CONST BDK_CSR_TYPE_RVU_PF_BAR0
2914 #define basename_BDK_RVU_PRIV_CONST "RVU_PRIV_CONST"
2915 #define device_bar_BDK_RVU_PRIV_CONST 0x0 /* BAR0 */
2916 #define busnum_BDK_RVU_PRIV_CONST 0
2917 #define arguments_BDK_RVU_PRIV_CONST -1,-1,-1,-1
2918
2919 /**
2920 * Register (RVU_PF_BAR0) rvu_priv_gen_cfg
2921 *
2922 * RVU Privileged General Configuration Register
2923 */
2924 union bdk_rvu_priv_gen_cfg
2925 {
2926 uint64_t u;
2927 struct bdk_rvu_priv_gen_cfg_s
2928 {
2929 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2930 uint64_t reserved_1_63 : 63;
2931 uint64_t lock : 1; /**< [ 0: 0](R/W1S) Lock privileged registers. When set, all privileged registers in RVU and
2932 its resource blocks are locked down and cannot be modified. Writing a 1
2933 sets this bit; once set, the bit can only be cleared by core reset. */
2934 #else /* Word 0 - Little Endian */
2935 uint64_t lock : 1; /**< [ 0: 0](R/W1S) Lock privileged registers. When set, all privileged registers in RVU and
2936 its resource blocks are locked down and cannot be modified. Writing a 1
2937 sets this bit; once set, the bit can only be cleared by core reset. */
2938 uint64_t reserved_1_63 : 63;
2939 #endif /* Word 0 - End */
2940 } s;
2941 /* struct bdk_rvu_priv_gen_cfg_s cn; */
2942 };
2943 typedef union bdk_rvu_priv_gen_cfg bdk_rvu_priv_gen_cfg_t;
2944
2945 #define BDK_RVU_PRIV_GEN_CFG BDK_RVU_PRIV_GEN_CFG_FUNC()
2946 static inline uint64_t BDK_RVU_PRIV_GEN_CFG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_GEN_CFG_FUNC(void)2947 static inline uint64_t BDK_RVU_PRIV_GEN_CFG_FUNC(void)
2948 {
2949 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2950 return 0x850008000010ll;
2951 __bdk_csr_fatal("RVU_PRIV_GEN_CFG", 0, 0, 0, 0, 0);
2952 }
2953
2954 #define typedef_BDK_RVU_PRIV_GEN_CFG bdk_rvu_priv_gen_cfg_t
2955 #define bustype_BDK_RVU_PRIV_GEN_CFG BDK_CSR_TYPE_RVU_PF_BAR0
2956 #define basename_BDK_RVU_PRIV_GEN_CFG "RVU_PRIV_GEN_CFG"
2957 #define device_bar_BDK_RVU_PRIV_GEN_CFG 0x0 /* BAR0 */
2958 #define busnum_BDK_RVU_PRIV_GEN_CFG 0
2959 #define arguments_BDK_RVU_PRIV_GEN_CFG -1,-1,-1,-1
2960
2961 /**
2962 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_cpt#_cfg
2963 *
2964 * RVU Privileged Hardware VF CPT Configuration Registers
2965 * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for CPT({a}) block.
2966 */
2967 union bdk_rvu_priv_hwvfx_cptx_cfg
2968 {
2969 uint64_t u;
2970 struct bdk_rvu_priv_hwvfx_cptx_cfg_s
2971 {
2972 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2973 uint64_t reserved_9_63 : 55;
2974 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
2975 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
2976 #else /* Word 0 - Little Endian */
2977 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
2978 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
2979 uint64_t reserved_9_63 : 55;
2980 #endif /* Word 0 - End */
2981 } s;
2982 /* struct bdk_rvu_priv_hwvfx_cptx_cfg_s cn; */
2983 };
2984 typedef union bdk_rvu_priv_hwvfx_cptx_cfg bdk_rvu_priv_hwvfx_cptx_cfg_t;
2985
2986 static inline uint64_t BDK_RVU_PRIV_HWVFX_CPTX_CFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_HWVFX_CPTX_CFG(unsigned long a,unsigned long b)2987 static inline uint64_t BDK_RVU_PRIV_HWVFX_CPTX_CFG(unsigned long a, unsigned long b)
2988 {
2989 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=255) && (b==0)))
2990 return 0x850008001350ll + 0x10000ll * ((a) & 0xff) + 8ll * ((b) & 0x0);
2991 __bdk_csr_fatal("RVU_PRIV_HWVFX_CPTX_CFG", 2, a, b, 0, 0);
2992 }
2993
2994 #define typedef_BDK_RVU_PRIV_HWVFX_CPTX_CFG(a,b) bdk_rvu_priv_hwvfx_cptx_cfg_t
2995 #define bustype_BDK_RVU_PRIV_HWVFX_CPTX_CFG(a,b) BDK_CSR_TYPE_RVU_PF_BAR0
2996 #define basename_BDK_RVU_PRIV_HWVFX_CPTX_CFG(a,b) "RVU_PRIV_HWVFX_CPTX_CFG"
2997 #define device_bar_BDK_RVU_PRIV_HWVFX_CPTX_CFG(a,b) 0x0 /* BAR0 */
2998 #define busnum_BDK_RVU_PRIV_HWVFX_CPTX_CFG(a,b) (a)
2999 #define arguments_BDK_RVU_PRIV_HWVFX_CPTX_CFG(a,b) (a),(b),-1,-1
3000
3001 /**
3002 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_int_cfg
3003 *
3004 * RVU Privileged Hardware VF Interrupt Configuration Registers
3005 */
3006 union bdk_rvu_priv_hwvfx_int_cfg
3007 {
3008 uint64_t u;
3009 struct bdk_rvu_priv_hwvfx_int_cfg_s
3010 {
3011 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3012 uint64_t reserved_20_63 : 44;
3013 uint64_t msix_size : 8; /**< [ 19: 12](RO) Number of interrupt vectors enumerated by RVU_VF_INT_VEC_E. */
3014 uint64_t reserved_11 : 1;
3015 uint64_t msix_offset : 11; /**< [ 10: 0](R/W) MSI-X offset. Offset of VF interrupt vectors enumerated by RVU_VF_INT_VEC_E
3016 in the HWVF's MSI-X table. This is added to each enumerated value to obtain
3017 the corresponding MSI-X vector index.
3018 The highest enumerated value plus [MSIX_OFFSET] must be less than or equal
3019 to RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1]. */
3020 #else /* Word 0 - Little Endian */
3021 uint64_t msix_offset : 11; /**< [ 10: 0](R/W) MSI-X offset. Offset of VF interrupt vectors enumerated by RVU_VF_INT_VEC_E
3022 in the HWVF's MSI-X table. This is added to each enumerated value to obtain
3023 the corresponding MSI-X vector index.
3024 The highest enumerated value plus [MSIX_OFFSET] must be less than or equal
3025 to RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1]. */
3026 uint64_t reserved_11 : 1;
3027 uint64_t msix_size : 8; /**< [ 19: 12](RO) Number of interrupt vectors enumerated by RVU_VF_INT_VEC_E. */
3028 uint64_t reserved_20_63 : 44;
3029 #endif /* Word 0 - End */
3030 } s;
3031 /* struct bdk_rvu_priv_hwvfx_int_cfg_s cn; */
3032 };
3033 typedef union bdk_rvu_priv_hwvfx_int_cfg bdk_rvu_priv_hwvfx_int_cfg_t;
3034
3035 static inline uint64_t BDK_RVU_PRIV_HWVFX_INT_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_HWVFX_INT_CFG(unsigned long a)3036 static inline uint64_t BDK_RVU_PRIV_HWVFX_INT_CFG(unsigned long a)
3037 {
3038 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=255))
3039 return 0x850008001280ll + 0x10000ll * ((a) & 0xff);
3040 __bdk_csr_fatal("RVU_PRIV_HWVFX_INT_CFG", 1, a, 0, 0, 0);
3041 }
3042
3043 #define typedef_BDK_RVU_PRIV_HWVFX_INT_CFG(a) bdk_rvu_priv_hwvfx_int_cfg_t
3044 #define bustype_BDK_RVU_PRIV_HWVFX_INT_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3045 #define basename_BDK_RVU_PRIV_HWVFX_INT_CFG(a) "RVU_PRIV_HWVFX_INT_CFG"
3046 #define device_bar_BDK_RVU_PRIV_HWVFX_INT_CFG(a) 0x0 /* BAR0 */
3047 #define busnum_BDK_RVU_PRIV_HWVFX_INT_CFG(a) (a)
3048 #define arguments_BDK_RVU_PRIV_HWVFX_INT_CFG(a) (a),-1,-1,-1
3049
3050 /**
3051 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_nix#_cfg
3052 *
3053 * RVU Privileged Hardware VF NIX Configuration Registers
3054 * These registers are used to assist VF software discovery. For each HWVF, if the
3055 * HWVF is mapped to a VF by RVU_PRIV_PF()_CFG[FIRST_HWVF,NVF], software
3056 * writes NIX block's resource configuration for the VF in this register. The VF
3057 * driver can read RVU_VF_BLOCK_ADDR()_DISC to discover the configuration.
3058 */
3059 union bdk_rvu_priv_hwvfx_nixx_cfg
3060 {
3061 uint64_t u;
3062 struct bdk_rvu_priv_hwvfx_nixx_cfg_s
3063 {
3064 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3065 uint64_t reserved_1_63 : 63;
3066 uint64_t has_lf : 1; /**< [ 0: 0](R/W) Set when an LF from the block is provisioned to the VF, clear otherwise. */
3067 #else /* Word 0 - Little Endian */
3068 uint64_t has_lf : 1; /**< [ 0: 0](R/W) Set when an LF from the block is provisioned to the VF, clear otherwise. */
3069 uint64_t reserved_1_63 : 63;
3070 #endif /* Word 0 - End */
3071 } s;
3072 /* struct bdk_rvu_priv_hwvfx_nixx_cfg_s cn; */
3073 };
3074 typedef union bdk_rvu_priv_hwvfx_nixx_cfg bdk_rvu_priv_hwvfx_nixx_cfg_t;
3075
3076 static inline uint64_t BDK_RVU_PRIV_HWVFX_NIXX_CFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_HWVFX_NIXX_CFG(unsigned long a,unsigned long b)3077 static inline uint64_t BDK_RVU_PRIV_HWVFX_NIXX_CFG(unsigned long a, unsigned long b)
3078 {
3079 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=255) && (b==0)))
3080 return 0x850008001300ll + 0x10000ll * ((a) & 0xff) + 8ll * ((b) & 0x0);
3081 __bdk_csr_fatal("RVU_PRIV_HWVFX_NIXX_CFG", 2, a, b, 0, 0);
3082 }
3083
3084 #define typedef_BDK_RVU_PRIV_HWVFX_NIXX_CFG(a,b) bdk_rvu_priv_hwvfx_nixx_cfg_t
3085 #define bustype_BDK_RVU_PRIV_HWVFX_NIXX_CFG(a,b) BDK_CSR_TYPE_RVU_PF_BAR0
3086 #define basename_BDK_RVU_PRIV_HWVFX_NIXX_CFG(a,b) "RVU_PRIV_HWVFX_NIXX_CFG"
3087 #define device_bar_BDK_RVU_PRIV_HWVFX_NIXX_CFG(a,b) 0x0 /* BAR0 */
3088 #define busnum_BDK_RVU_PRIV_HWVFX_NIXX_CFG(a,b) (a)
3089 #define arguments_BDK_RVU_PRIV_HWVFX_NIXX_CFG(a,b) (a),(b),-1,-1
3090
3091 /**
3092 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_npa_cfg
3093 *
3094 * RVU Privileged Hardware VF NPA Configuration Registers
3095 * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for NPA block.
3096 */
3097 union bdk_rvu_priv_hwvfx_npa_cfg
3098 {
3099 uint64_t u;
3100 struct bdk_rvu_priv_hwvfx_npa_cfg_s
3101 {
3102 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3103 uint64_t reserved_1_63 : 63;
3104 uint64_t has_lf : 1; /**< [ 0: 0](R/W) Set when an LF from the block is provisioned to the VF, clear otherwise. */
3105 #else /* Word 0 - Little Endian */
3106 uint64_t has_lf : 1; /**< [ 0: 0](R/W) Set when an LF from the block is provisioned to the VF, clear otherwise. */
3107 uint64_t reserved_1_63 : 63;
3108 #endif /* Word 0 - End */
3109 } s;
3110 /* struct bdk_rvu_priv_hwvfx_npa_cfg_s cn; */
3111 };
3112 typedef union bdk_rvu_priv_hwvfx_npa_cfg bdk_rvu_priv_hwvfx_npa_cfg_t;
3113
3114 static inline uint64_t BDK_RVU_PRIV_HWVFX_NPA_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_HWVFX_NPA_CFG(unsigned long a)3115 static inline uint64_t BDK_RVU_PRIV_HWVFX_NPA_CFG(unsigned long a)
3116 {
3117 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=255))
3118 return 0x850008001310ll + 0x10000ll * ((a) & 0xff);
3119 __bdk_csr_fatal("RVU_PRIV_HWVFX_NPA_CFG", 1, a, 0, 0, 0);
3120 }
3121
3122 #define typedef_BDK_RVU_PRIV_HWVFX_NPA_CFG(a) bdk_rvu_priv_hwvfx_npa_cfg_t
3123 #define bustype_BDK_RVU_PRIV_HWVFX_NPA_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3124 #define basename_BDK_RVU_PRIV_HWVFX_NPA_CFG(a) "RVU_PRIV_HWVFX_NPA_CFG"
3125 #define device_bar_BDK_RVU_PRIV_HWVFX_NPA_CFG(a) 0x0 /* BAR0 */
3126 #define busnum_BDK_RVU_PRIV_HWVFX_NPA_CFG(a) (a)
3127 #define arguments_BDK_RVU_PRIV_HWVFX_NPA_CFG(a) (a),-1,-1,-1
3128
3129 /**
3130 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_sso_cfg
3131 *
3132 * RVU Privileged Hardware VF SSO Configuration Registers
3133 * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for SSO block.
3134 */
3135 union bdk_rvu_priv_hwvfx_sso_cfg
3136 {
3137 uint64_t u;
3138 struct bdk_rvu_priv_hwvfx_sso_cfg_s
3139 {
3140 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3141 uint64_t reserved_9_63 : 55;
3142 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3143 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3144 #else /* Word 0 - Little Endian */
3145 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3146 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3147 uint64_t reserved_9_63 : 55;
3148 #endif /* Word 0 - End */
3149 } s;
3150 /* struct bdk_rvu_priv_hwvfx_sso_cfg_s cn; */
3151 };
3152 typedef union bdk_rvu_priv_hwvfx_sso_cfg bdk_rvu_priv_hwvfx_sso_cfg_t;
3153
3154 static inline uint64_t BDK_RVU_PRIV_HWVFX_SSO_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_HWVFX_SSO_CFG(unsigned long a)3155 static inline uint64_t BDK_RVU_PRIV_HWVFX_SSO_CFG(unsigned long a)
3156 {
3157 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=255))
3158 return 0x850008001320ll + 0x10000ll * ((a) & 0xff);
3159 __bdk_csr_fatal("RVU_PRIV_HWVFX_SSO_CFG", 1, a, 0, 0, 0);
3160 }
3161
3162 #define typedef_BDK_RVU_PRIV_HWVFX_SSO_CFG(a) bdk_rvu_priv_hwvfx_sso_cfg_t
3163 #define bustype_BDK_RVU_PRIV_HWVFX_SSO_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3164 #define basename_BDK_RVU_PRIV_HWVFX_SSO_CFG(a) "RVU_PRIV_HWVFX_SSO_CFG"
3165 #define device_bar_BDK_RVU_PRIV_HWVFX_SSO_CFG(a) 0x0 /* BAR0 */
3166 #define busnum_BDK_RVU_PRIV_HWVFX_SSO_CFG(a) (a)
3167 #define arguments_BDK_RVU_PRIV_HWVFX_SSO_CFG(a) (a),-1,-1,-1
3168
3169 /**
3170 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_ssow_cfg
3171 *
3172 * RVU Privileged Hardware VF SSO Work Slot Configuration Registers
3173 * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for SSOW block.
3174 */
3175 union bdk_rvu_priv_hwvfx_ssow_cfg
3176 {
3177 uint64_t u;
3178 struct bdk_rvu_priv_hwvfx_ssow_cfg_s
3179 {
3180 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3181 uint64_t reserved_9_63 : 55;
3182 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3183 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3184 #else /* Word 0 - Little Endian */
3185 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3186 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3187 uint64_t reserved_9_63 : 55;
3188 #endif /* Word 0 - End */
3189 } s;
3190 /* struct bdk_rvu_priv_hwvfx_ssow_cfg_s cn; */
3191 };
3192 typedef union bdk_rvu_priv_hwvfx_ssow_cfg bdk_rvu_priv_hwvfx_ssow_cfg_t;
3193
3194 static inline uint64_t BDK_RVU_PRIV_HWVFX_SSOW_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_HWVFX_SSOW_CFG(unsigned long a)3195 static inline uint64_t BDK_RVU_PRIV_HWVFX_SSOW_CFG(unsigned long a)
3196 {
3197 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=255))
3198 return 0x850008001330ll + 0x10000ll * ((a) & 0xff);
3199 __bdk_csr_fatal("RVU_PRIV_HWVFX_SSOW_CFG", 1, a, 0, 0, 0);
3200 }
3201
3202 #define typedef_BDK_RVU_PRIV_HWVFX_SSOW_CFG(a) bdk_rvu_priv_hwvfx_ssow_cfg_t
3203 #define bustype_BDK_RVU_PRIV_HWVFX_SSOW_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3204 #define basename_BDK_RVU_PRIV_HWVFX_SSOW_CFG(a) "RVU_PRIV_HWVFX_SSOW_CFG"
3205 #define device_bar_BDK_RVU_PRIV_HWVFX_SSOW_CFG(a) 0x0 /* BAR0 */
3206 #define busnum_BDK_RVU_PRIV_HWVFX_SSOW_CFG(a) (a)
3207 #define arguments_BDK_RVU_PRIV_HWVFX_SSOW_CFG(a) (a),-1,-1,-1
3208
3209 /**
3210 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_tim_cfg
3211 *
3212 * RVU Privileged Hardware VF SSO Work Slot Configuration Registers
3213 * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for TIM block.
3214 */
3215 union bdk_rvu_priv_hwvfx_tim_cfg
3216 {
3217 uint64_t u;
3218 struct bdk_rvu_priv_hwvfx_tim_cfg_s
3219 {
3220 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3221 uint64_t reserved_9_63 : 55;
3222 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3223 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3224 #else /* Word 0 - Little Endian */
3225 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3226 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3227 uint64_t reserved_9_63 : 55;
3228 #endif /* Word 0 - End */
3229 } s;
3230 /* struct bdk_rvu_priv_hwvfx_tim_cfg_s cn; */
3231 };
3232 typedef union bdk_rvu_priv_hwvfx_tim_cfg bdk_rvu_priv_hwvfx_tim_cfg_t;
3233
3234 static inline uint64_t BDK_RVU_PRIV_HWVFX_TIM_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_HWVFX_TIM_CFG(unsigned long a)3235 static inline uint64_t BDK_RVU_PRIV_HWVFX_TIM_CFG(unsigned long a)
3236 {
3237 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=255))
3238 return 0x850008001340ll + 0x10000ll * ((a) & 0xff);
3239 __bdk_csr_fatal("RVU_PRIV_HWVFX_TIM_CFG", 1, a, 0, 0, 0);
3240 }
3241
3242 #define typedef_BDK_RVU_PRIV_HWVFX_TIM_CFG(a) bdk_rvu_priv_hwvfx_tim_cfg_t
3243 #define bustype_BDK_RVU_PRIV_HWVFX_TIM_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3244 #define basename_BDK_RVU_PRIV_HWVFX_TIM_CFG(a) "RVU_PRIV_HWVFX_TIM_CFG"
3245 #define device_bar_BDK_RVU_PRIV_HWVFX_TIM_CFG(a) 0x0 /* BAR0 */
3246 #define busnum_BDK_RVU_PRIV_HWVFX_TIM_CFG(a) (a)
3247 #define arguments_BDK_RVU_PRIV_HWVFX_TIM_CFG(a) (a),-1,-1,-1
3248
3249 /**
3250 * Register (RVU_PF_BAR0) rvu_priv_pf#_cfg
3251 *
3252 * RVU Privileged PF Configuration Registers
3253 */
3254 union bdk_rvu_priv_pfx_cfg
3255 {
3256 uint64_t u;
3257 struct bdk_rvu_priv_pfx_cfg_s
3258 {
3259 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3260 uint64_t reserved_23_63 : 41;
3261 uint64_t me_flr_ena : 1; /**< [ 22: 22](R/W) Bus master enable (ME) and function level reset (FLR) enable. This bit
3262 should be set when the PF is configured and associated PF and/or AF drivers
3263 that manage VF and/or PF ME/FLR are loaded.
3264
3265 When clear, PCCPF/PCCVF_XXX_CMD[ME] state changes are ignored, and
3266 PCCPF/PCCVF_XXX_E_DEV_CTL[BCR_FLR] reset the PF/VF configuration space and
3267 MSI-X tables only.
3268
3269 When set, hardware updates to the following registers in response to ME/FLR
3270 events are additionally enabled:
3271 RVU_PF_VFTRPEND(), RVU_PF_VFFLR_INT(), RVU_PF_VFME_INT(),
3272 RVU_AF_PFTRPEND, RVU_AF_PFFLR_INT, and RVU_AF_PFFLR_INT. */
3273 uint64_t af_ena : 1; /**< [ 21: 21](R/W) Admin function enable. When set, the PF is allowed to access AF
3274 (RVU PF BAR0) registers in all RVU blocks. When clear, the PF is not
3275 allowed to access AF registers. Must be clear when [ENA] is clear.
3276
3277 Software should keep this bit set for PF(0) when RVU is used. */
3278 uint64_t ena : 1; /**< [ 20: 20](R/W) Enable the PF. When clear, the PF is unused and hidden in the PCI config
3279 space, and access to the PF's MSI-X tables in RVU PF/FUNC BAR2 is
3280 disabled.
3281 When set, the PF is enabled and remaining fields in this register are
3282 valid.
3283
3284 Software should keep this bit set for PF(0) when RVU is used. Hardware
3285 delivers all AF interrupts to PF(0). */
3286 uint64_t nvf : 8; /**< [ 19: 12](R/W) Number of VFs in the PF. Must be less than or equal to
3287 RVU_PRIV_CONST[MAX_VFS_PER_PF]. */
3288 uint64_t first_hwvf : 12; /**< [ 11: 0](R/W) HWVF index of the PF's first VF. Valid when [NVF] is non-zero. The HWVF
3289 index range for the PF is [FIRST_HWVF] to [FIRST_HWVF]+[NVF]-1, inclusive.
3290 Different PFs must have non-overlapping HWVF ranges, and the maximum HWVF
3291 index in any range must be less than RVU_PRIV_CONST[HWVFS]. */
3292 #else /* Word 0 - Little Endian */
3293 uint64_t first_hwvf : 12; /**< [ 11: 0](R/W) HWVF index of the PF's first VF. Valid when [NVF] is non-zero. The HWVF
3294 index range for the PF is [FIRST_HWVF] to [FIRST_HWVF]+[NVF]-1, inclusive.
3295 Different PFs must have non-overlapping HWVF ranges, and the maximum HWVF
3296 index in any range must be less than RVU_PRIV_CONST[HWVFS]. */
3297 uint64_t nvf : 8; /**< [ 19: 12](R/W) Number of VFs in the PF. Must be less than or equal to
3298 RVU_PRIV_CONST[MAX_VFS_PER_PF]. */
3299 uint64_t ena : 1; /**< [ 20: 20](R/W) Enable the PF. When clear, the PF is unused and hidden in the PCI config
3300 space, and access to the PF's MSI-X tables in RVU PF/FUNC BAR2 is
3301 disabled.
3302 When set, the PF is enabled and remaining fields in this register are
3303 valid.
3304
3305 Software should keep this bit set for PF(0) when RVU is used. Hardware
3306 delivers all AF interrupts to PF(0). */
3307 uint64_t af_ena : 1; /**< [ 21: 21](R/W) Admin function enable. When set, the PF is allowed to access AF
3308 (RVU PF BAR0) registers in all RVU blocks. When clear, the PF is not
3309 allowed to access AF registers. Must be clear when [ENA] is clear.
3310
3311 Software should keep this bit set for PF(0) when RVU is used. */
3312 uint64_t me_flr_ena : 1; /**< [ 22: 22](R/W) Bus master enable (ME) and function level reset (FLR) enable. This bit
3313 should be set when the PF is configured and associated PF and/or AF drivers
3314 that manage VF and/or PF ME/FLR are loaded.
3315
3316 When clear, PCCPF/PCCVF_XXX_CMD[ME] state changes are ignored, and
3317 PCCPF/PCCVF_XXX_E_DEV_CTL[BCR_FLR] reset the PF/VF configuration space and
3318 MSI-X tables only.
3319
3320 When set, hardware updates to the following registers in response to ME/FLR
3321 events are additionally enabled:
3322 RVU_PF_VFTRPEND(), RVU_PF_VFFLR_INT(), RVU_PF_VFME_INT(),
3323 RVU_AF_PFTRPEND, RVU_AF_PFFLR_INT, and RVU_AF_PFFLR_INT. */
3324 uint64_t reserved_23_63 : 41;
3325 #endif /* Word 0 - End */
3326 } s;
3327 /* struct bdk_rvu_priv_pfx_cfg_s cn; */
3328 };
3329 typedef union bdk_rvu_priv_pfx_cfg bdk_rvu_priv_pfx_cfg_t;
3330
3331 static inline uint64_t BDK_RVU_PRIV_PFX_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_CFG(unsigned long a)3332 static inline uint64_t BDK_RVU_PRIV_PFX_CFG(unsigned long a)
3333 {
3334 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
3335 return 0x850008000100ll + 0x10000ll * ((a) & 0xf);
3336 __bdk_csr_fatal("RVU_PRIV_PFX_CFG", 1, a, 0, 0, 0);
3337 }
3338
3339 #define typedef_BDK_RVU_PRIV_PFX_CFG(a) bdk_rvu_priv_pfx_cfg_t
3340 #define bustype_BDK_RVU_PRIV_PFX_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3341 #define basename_BDK_RVU_PRIV_PFX_CFG(a) "RVU_PRIV_PFX_CFG"
3342 #define device_bar_BDK_RVU_PRIV_PFX_CFG(a) 0x0 /* BAR0 */
3343 #define busnum_BDK_RVU_PRIV_PFX_CFG(a) (a)
3344 #define arguments_BDK_RVU_PRIV_PFX_CFG(a) (a),-1,-1,-1
3345
3346 /**
3347 * Register (RVU_PF_BAR0) rvu_priv_pf#_cpt#_cfg
3348 *
3349 * RVU Privileged PF CPT Configuration Registers
3350 * Similar to RVU_PRIV_PF()_NIX()_CFG, but for CPT({a}) block.
3351 */
3352 union bdk_rvu_priv_pfx_cptx_cfg
3353 {
3354 uint64_t u;
3355 struct bdk_rvu_priv_pfx_cptx_cfg_s
3356 {
3357 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3358 uint64_t reserved_9_63 : 55;
3359 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3360 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3361 #else /* Word 0 - Little Endian */
3362 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3363 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3364 uint64_t reserved_9_63 : 55;
3365 #endif /* Word 0 - End */
3366 } s;
3367 /* struct bdk_rvu_priv_pfx_cptx_cfg_s cn; */
3368 };
3369 typedef union bdk_rvu_priv_pfx_cptx_cfg bdk_rvu_priv_pfx_cptx_cfg_t;
3370
3371 static inline uint64_t BDK_RVU_PRIV_PFX_CPTX_CFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_CPTX_CFG(unsigned long a,unsigned long b)3372 static inline uint64_t BDK_RVU_PRIV_PFX_CPTX_CFG(unsigned long a, unsigned long b)
3373 {
3374 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=15) && (b==0)))
3375 return 0x850008000350ll + 0x10000ll * ((a) & 0xf) + 8ll * ((b) & 0x0);
3376 __bdk_csr_fatal("RVU_PRIV_PFX_CPTX_CFG", 2, a, b, 0, 0);
3377 }
3378
3379 #define typedef_BDK_RVU_PRIV_PFX_CPTX_CFG(a,b) bdk_rvu_priv_pfx_cptx_cfg_t
3380 #define bustype_BDK_RVU_PRIV_PFX_CPTX_CFG(a,b) BDK_CSR_TYPE_RVU_PF_BAR0
3381 #define basename_BDK_RVU_PRIV_PFX_CPTX_CFG(a,b) "RVU_PRIV_PFX_CPTX_CFG"
3382 #define device_bar_BDK_RVU_PRIV_PFX_CPTX_CFG(a,b) 0x0 /* BAR0 */
3383 #define busnum_BDK_RVU_PRIV_PFX_CPTX_CFG(a,b) (a)
3384 #define arguments_BDK_RVU_PRIV_PFX_CPTX_CFG(a,b) (a),(b),-1,-1
3385
3386 /**
3387 * Register (RVU_PF_BAR0) rvu_priv_pf#_id_cfg
3388 *
3389 * RVU Privileged PF ID Configuration Registers
3390 */
3391 union bdk_rvu_priv_pfx_id_cfg
3392 {
3393 uint64_t u;
3394 struct bdk_rvu_priv_pfx_id_cfg_s
3395 {
3396 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3397 uint64_t reserved_40_63 : 24;
3398 uint64_t class_code : 24; /**< [ 39: 16](R/W) Class code to be presented in PCCPF_XXX_REV[BCC,SC,PI] and
3399 PCCVF_XXX_REV[BCC,SC,PI]. Format specified by PCC_CLASS_CODE_S.
3400 Resets to PCC_DEV_IDL_E::RVU's class code. */
3401 uint64_t vf_devid : 8; /**< [ 15: 8](R/W) Lower bits of VF device ID to be presented in PCCPF_XXX_SRIOV_DEV[VFDEV]\<7:0\>.
3402 Resets to PCC_DEV_IDL_E::RVU_VF. */
3403 uint64_t pf_devid : 8; /**< [ 7: 0](R/W) Lower bits of PF device ID to be presented in PCCPF_XXX_ID[DEVID]\<7:0\>.
3404 Resets to PCC_DEV_IDL_E::RVU_AF for PF(0), PCC_DEV_IDL_E::RVU for other
3405 PFs. */
3406 #else /* Word 0 - Little Endian */
3407 uint64_t pf_devid : 8; /**< [ 7: 0](R/W) Lower bits of PF device ID to be presented in PCCPF_XXX_ID[DEVID]\<7:0\>.
3408 Resets to PCC_DEV_IDL_E::RVU_AF for PF(0), PCC_DEV_IDL_E::RVU for other
3409 PFs. */
3410 uint64_t vf_devid : 8; /**< [ 15: 8](R/W) Lower bits of VF device ID to be presented in PCCPF_XXX_SRIOV_DEV[VFDEV]\<7:0\>.
3411 Resets to PCC_DEV_IDL_E::RVU_VF. */
3412 uint64_t class_code : 24; /**< [ 39: 16](R/W) Class code to be presented in PCCPF_XXX_REV[BCC,SC,PI] and
3413 PCCVF_XXX_REV[BCC,SC,PI]. Format specified by PCC_CLASS_CODE_S.
3414 Resets to PCC_DEV_IDL_E::RVU's class code. */
3415 uint64_t reserved_40_63 : 24;
3416 #endif /* Word 0 - End */
3417 } s;
3418 /* struct bdk_rvu_priv_pfx_id_cfg_s cn; */
3419 };
3420 typedef union bdk_rvu_priv_pfx_id_cfg bdk_rvu_priv_pfx_id_cfg_t;
3421
3422 static inline uint64_t BDK_RVU_PRIV_PFX_ID_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_ID_CFG(unsigned long a)3423 static inline uint64_t BDK_RVU_PRIV_PFX_ID_CFG(unsigned long a)
3424 {
3425 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
3426 return 0x850008000120ll + 0x10000ll * ((a) & 0xf);
3427 __bdk_csr_fatal("RVU_PRIV_PFX_ID_CFG", 1, a, 0, 0, 0);
3428 }
3429
3430 #define typedef_BDK_RVU_PRIV_PFX_ID_CFG(a) bdk_rvu_priv_pfx_id_cfg_t
3431 #define bustype_BDK_RVU_PRIV_PFX_ID_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3432 #define basename_BDK_RVU_PRIV_PFX_ID_CFG(a) "RVU_PRIV_PFX_ID_CFG"
3433 #define device_bar_BDK_RVU_PRIV_PFX_ID_CFG(a) 0x0 /* BAR0 */
3434 #define busnum_BDK_RVU_PRIV_PFX_ID_CFG(a) (a)
3435 #define arguments_BDK_RVU_PRIV_PFX_ID_CFG(a) (a),-1,-1,-1
3436
3437 /**
3438 * Register (RVU_PF_BAR0) rvu_priv_pf#_int_cfg
3439 *
3440 * RVU Privileged PF Interrupt Configuration Registers
3441 */
3442 union bdk_rvu_priv_pfx_int_cfg
3443 {
3444 uint64_t u;
3445 struct bdk_rvu_priv_pfx_int_cfg_s
3446 {
3447 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3448 uint64_t reserved_20_63 : 44;
3449 uint64_t msix_size : 8; /**< [ 19: 12](RO) Number of interrupt vectors enumerated by RVU_PF_INT_VEC_E. */
3450 uint64_t reserved_11 : 1;
3451 uint64_t msix_offset : 11; /**< [ 10: 0](R/W) MSI-X offset. Offset of PF interrupt vectors enumerated by RVU_PF_INT_VEC_E
3452 in the PF's MSI-X table. This is added to each enumerated value to obtain
3453 the corresponding MSI-X vector index.
3454 The highest enumerated value plus [MSIX_OFFSET] must be less than or equal
3455 to RVU_PRIV_PF()_MSIX_CFG[PF_MSIXT_SIZEM1].
3456
3457 Note that the AF interrupt vectors enumerated by RVU_AF_INT_VEC_E have a
3458 fixed starting offset of 0 in RVU PF(0)'s MSI-X table. Other PF
3459 interrupt vectors should not be mapped at the offsets used by RVU_AF_INT_VEC_E. */
3460 #else /* Word 0 - Little Endian */
3461 uint64_t msix_offset : 11; /**< [ 10: 0](R/W) MSI-X offset. Offset of PF interrupt vectors enumerated by RVU_PF_INT_VEC_E
3462 in the PF's MSI-X table. This is added to each enumerated value to obtain
3463 the corresponding MSI-X vector index.
3464 The highest enumerated value plus [MSIX_OFFSET] must be less than or equal
3465 to RVU_PRIV_PF()_MSIX_CFG[PF_MSIXT_SIZEM1].
3466
3467 Note that the AF interrupt vectors enumerated by RVU_AF_INT_VEC_E have a
3468 fixed starting offset of 0 in RVU PF(0)'s MSI-X table. Other PF
3469 interrupt vectors should not be mapped at the offsets used by RVU_AF_INT_VEC_E. */
3470 uint64_t reserved_11 : 1;
3471 uint64_t msix_size : 8; /**< [ 19: 12](RO) Number of interrupt vectors enumerated by RVU_PF_INT_VEC_E. */
3472 uint64_t reserved_20_63 : 44;
3473 #endif /* Word 0 - End */
3474 } s;
3475 /* struct bdk_rvu_priv_pfx_int_cfg_s cn; */
3476 };
3477 typedef union bdk_rvu_priv_pfx_int_cfg bdk_rvu_priv_pfx_int_cfg_t;
3478
3479 static inline uint64_t BDK_RVU_PRIV_PFX_INT_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_INT_CFG(unsigned long a)3480 static inline uint64_t BDK_RVU_PRIV_PFX_INT_CFG(unsigned long a)
3481 {
3482 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
3483 return 0x850008000200ll + 0x10000ll * ((a) & 0xf);
3484 __bdk_csr_fatal("RVU_PRIV_PFX_INT_CFG", 1, a, 0, 0, 0);
3485 }
3486
3487 #define typedef_BDK_RVU_PRIV_PFX_INT_CFG(a) bdk_rvu_priv_pfx_int_cfg_t
3488 #define bustype_BDK_RVU_PRIV_PFX_INT_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3489 #define basename_BDK_RVU_PRIV_PFX_INT_CFG(a) "RVU_PRIV_PFX_INT_CFG"
3490 #define device_bar_BDK_RVU_PRIV_PFX_INT_CFG(a) 0x0 /* BAR0 */
3491 #define busnum_BDK_RVU_PRIV_PFX_INT_CFG(a) (a)
3492 #define arguments_BDK_RVU_PRIV_PFX_INT_CFG(a) (a),-1,-1,-1
3493
3494 /**
3495 * Register (RVU_PF_BAR0) rvu_priv_pf#_msix_cfg
3496 *
3497 * RVU Privileged PF MSI-X Configuration Registers
3498 * These registers specify MSI-X table sizes and locations for RVU PFs and
3499 * associated VFs. Hardware maintains all RVU MSI-X tables in a contiguous memory
3500 * region in LLC/DRAM called the MSI-X table region. The table region's base IOVA
3501 * is specified by RVU_AF_MSIXTR_BASE, and its size as a multiple of
3502 * 16-byte RVU_MSIX_VEC_S structures must be less than or equal to
3503 * RVU_PRIV_CONST[MAX_MSIX].
3504 *
3505 * A PF's MSI-X table consists of the following range of RVU_MSIX_VEC_S structures
3506 * in the table region:
3507 * * First index: [PF_MSIXT_OFFSET].
3508 * * Last index: [PF_MSIXT_OFFSET] + [PF_MSIXT_SIZEM1].
3509 *
3510 * If a PF has enabled VFs (associated RVU_PRIV_PF()_CFG[NVF] is nonzero),
3511 * then each VF's MSI-X table consumes the following range of RVU_MSIX_VEC_S structures:
3512 * * First index: [VF_MSIXT_OFFSET] + N*([VF_MSIXT_SIZEM1] + 1).
3513 * * Last index: [VF_MSIXT_OFFSET] + N*([VF_MSIXT_SIZEM1] + 1) + [VF_MSIXT_SIZEM1].
3514 *
3515 * N=0 for the first VF, N=1 for the second VF, etc.
3516 *
3517 * Different PFs and VFs must have non-overlapping vector ranges, and the last
3518 * index of any range must be less than RVU_PRIV_CONST[MAX_MSIX].
3519 */
3520 union bdk_rvu_priv_pfx_msix_cfg
3521 {
3522 uint64_t u;
3523 struct bdk_rvu_priv_pfx_msix_cfg_s
3524 {
3525 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3526 uint64_t pf_msixt_offset : 20; /**< [ 63: 44](R/W) Starting offset of PF's MSI-X table in the RVU MSI-X table region.
3527 Internal:
3528 Also, bit offset of the PF's PBA table in RVU's internal PBA memory. */
3529 uint64_t pf_msixt_sizem1 : 12; /**< [ 43: 32](R/W) PF's MSI-X table size (number of MSI-X vectors) minus one. */
3530 uint64_t vf_msixt_offset : 20; /**< [ 31: 12](R/W) Starting offset of first VF's MSI-X table in the RVU MSI-X table region.
3531 Valid when RVU_PRIV_PF()_CFG[NVF] is nonzero.
3532
3533 Internal:
3534 Also, bit offset of the first VF's PBA table in RVU's internal PBA memory. */
3535 uint64_t vf_msixt_sizem1 : 12; /**< [ 11: 0](R/W) Each VF's MSI-X table size (number of MSI-X vectors) minus one.
3536 Valid when RVU_PRIV_PF()_CFG[NVF] is nonzero. */
3537 #else /* Word 0 - Little Endian */
3538 uint64_t vf_msixt_sizem1 : 12; /**< [ 11: 0](R/W) Each VF's MSI-X table size (number of MSI-X vectors) minus one.
3539 Valid when RVU_PRIV_PF()_CFG[NVF] is nonzero. */
3540 uint64_t vf_msixt_offset : 20; /**< [ 31: 12](R/W) Starting offset of first VF's MSI-X table in the RVU MSI-X table region.
3541 Valid when RVU_PRIV_PF()_CFG[NVF] is nonzero.
3542
3543 Internal:
3544 Also, bit offset of the first VF's PBA table in RVU's internal PBA memory. */
3545 uint64_t pf_msixt_sizem1 : 12; /**< [ 43: 32](R/W) PF's MSI-X table size (number of MSI-X vectors) minus one. */
3546 uint64_t pf_msixt_offset : 20; /**< [ 63: 44](R/W) Starting offset of PF's MSI-X table in the RVU MSI-X table region.
3547 Internal:
3548 Also, bit offset of the PF's PBA table in RVU's internal PBA memory. */
3549 #endif /* Word 0 - End */
3550 } s;
3551 /* struct bdk_rvu_priv_pfx_msix_cfg_s cn; */
3552 };
3553 typedef union bdk_rvu_priv_pfx_msix_cfg bdk_rvu_priv_pfx_msix_cfg_t;
3554
3555 static inline uint64_t BDK_RVU_PRIV_PFX_MSIX_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_MSIX_CFG(unsigned long a)3556 static inline uint64_t BDK_RVU_PRIV_PFX_MSIX_CFG(unsigned long a)
3557 {
3558 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
3559 return 0x850008000110ll + 0x10000ll * ((a) & 0xf);
3560 __bdk_csr_fatal("RVU_PRIV_PFX_MSIX_CFG", 1, a, 0, 0, 0);
3561 }
3562
3563 #define typedef_BDK_RVU_PRIV_PFX_MSIX_CFG(a) bdk_rvu_priv_pfx_msix_cfg_t
3564 #define bustype_BDK_RVU_PRIV_PFX_MSIX_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3565 #define basename_BDK_RVU_PRIV_PFX_MSIX_CFG(a) "RVU_PRIV_PFX_MSIX_CFG"
3566 #define device_bar_BDK_RVU_PRIV_PFX_MSIX_CFG(a) 0x0 /* BAR0 */
3567 #define busnum_BDK_RVU_PRIV_PFX_MSIX_CFG(a) (a)
3568 #define arguments_BDK_RVU_PRIV_PFX_MSIX_CFG(a) (a),-1,-1,-1
3569
3570 /**
3571 * Register (RVU_PF_BAR0) rvu_priv_pf#_nix#_cfg
3572 *
3573 * RVU Privileged PF NIX Configuration Registers
3574 * These registers are used to assist PF software discovery. For each enabled RVU
3575 * PF, software writes the block's resource configuration for the PF in this
3576 * register. The PF driver can read RVU_PF_BLOCK_ADDR()_DISC to discover the
3577 * configuration.
3578 */
3579 union bdk_rvu_priv_pfx_nixx_cfg
3580 {
3581 uint64_t u;
3582 struct bdk_rvu_priv_pfx_nixx_cfg_s
3583 {
3584 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3585 uint64_t reserved_1_63 : 63;
3586 uint64_t has_lf : 1; /**< [ 0: 0](R/W) Set when an LF from the block is provisioned to the VF, clear otherwise. */
3587 #else /* Word 0 - Little Endian */
3588 uint64_t has_lf : 1; /**< [ 0: 0](R/W) Set when an LF from the block is provisioned to the VF, clear otherwise. */
3589 uint64_t reserved_1_63 : 63;
3590 #endif /* Word 0 - End */
3591 } s;
3592 /* struct bdk_rvu_priv_pfx_nixx_cfg_s cn; */
3593 };
3594 typedef union bdk_rvu_priv_pfx_nixx_cfg bdk_rvu_priv_pfx_nixx_cfg_t;
3595
3596 static inline uint64_t BDK_RVU_PRIV_PFX_NIXX_CFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_NIXX_CFG(unsigned long a,unsigned long b)3597 static inline uint64_t BDK_RVU_PRIV_PFX_NIXX_CFG(unsigned long a, unsigned long b)
3598 {
3599 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=15) && (b==0)))
3600 return 0x850008000300ll + 0x10000ll * ((a) & 0xf) + 8ll * ((b) & 0x0);
3601 __bdk_csr_fatal("RVU_PRIV_PFX_NIXX_CFG", 2, a, b, 0, 0);
3602 }
3603
3604 #define typedef_BDK_RVU_PRIV_PFX_NIXX_CFG(a,b) bdk_rvu_priv_pfx_nixx_cfg_t
3605 #define bustype_BDK_RVU_PRIV_PFX_NIXX_CFG(a,b) BDK_CSR_TYPE_RVU_PF_BAR0
3606 #define basename_BDK_RVU_PRIV_PFX_NIXX_CFG(a,b) "RVU_PRIV_PFX_NIXX_CFG"
3607 #define device_bar_BDK_RVU_PRIV_PFX_NIXX_CFG(a,b) 0x0 /* BAR0 */
3608 #define busnum_BDK_RVU_PRIV_PFX_NIXX_CFG(a,b) (a)
3609 #define arguments_BDK_RVU_PRIV_PFX_NIXX_CFG(a,b) (a),(b),-1,-1
3610
3611 /**
3612 * Register (RVU_PF_BAR0) rvu_priv_pf#_npa_cfg
3613 *
3614 * RVU Privileged PF NPA Configuration Registers
3615 * Similar to RVU_PRIV_PF()_NIX()_CFG, but for NPA block.
3616 */
3617 union bdk_rvu_priv_pfx_npa_cfg
3618 {
3619 uint64_t u;
3620 struct bdk_rvu_priv_pfx_npa_cfg_s
3621 {
3622 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3623 uint64_t reserved_1_63 : 63;
3624 uint64_t has_lf : 1; /**< [ 0: 0](R/W) Set when an LF from the block is provisioned to the VF, clear otherwise. */
3625 #else /* Word 0 - Little Endian */
3626 uint64_t has_lf : 1; /**< [ 0: 0](R/W) Set when an LF from the block is provisioned to the VF, clear otherwise. */
3627 uint64_t reserved_1_63 : 63;
3628 #endif /* Word 0 - End */
3629 } s;
3630 /* struct bdk_rvu_priv_pfx_npa_cfg_s cn; */
3631 };
3632 typedef union bdk_rvu_priv_pfx_npa_cfg bdk_rvu_priv_pfx_npa_cfg_t;
3633
3634 static inline uint64_t BDK_RVU_PRIV_PFX_NPA_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_NPA_CFG(unsigned long a)3635 static inline uint64_t BDK_RVU_PRIV_PFX_NPA_CFG(unsigned long a)
3636 {
3637 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
3638 return 0x850008000310ll + 0x10000ll * ((a) & 0xf);
3639 __bdk_csr_fatal("RVU_PRIV_PFX_NPA_CFG", 1, a, 0, 0, 0);
3640 }
3641
3642 #define typedef_BDK_RVU_PRIV_PFX_NPA_CFG(a) bdk_rvu_priv_pfx_npa_cfg_t
3643 #define bustype_BDK_RVU_PRIV_PFX_NPA_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3644 #define basename_BDK_RVU_PRIV_PFX_NPA_CFG(a) "RVU_PRIV_PFX_NPA_CFG"
3645 #define device_bar_BDK_RVU_PRIV_PFX_NPA_CFG(a) 0x0 /* BAR0 */
3646 #define busnum_BDK_RVU_PRIV_PFX_NPA_CFG(a) (a)
3647 #define arguments_BDK_RVU_PRIV_PFX_NPA_CFG(a) (a),-1,-1,-1
3648
3649 /**
3650 * Register (RVU_PF_BAR0) rvu_priv_pf#_sso_cfg
3651 *
3652 * RVU Privileged PF SSO Configuration Registers
3653 * Similar to RVU_PRIV_PF()_NIX()_CFG, but for SSO block.
3654 */
3655 union bdk_rvu_priv_pfx_sso_cfg
3656 {
3657 uint64_t u;
3658 struct bdk_rvu_priv_pfx_sso_cfg_s
3659 {
3660 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3661 uint64_t reserved_9_63 : 55;
3662 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3663 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3664 #else /* Word 0 - Little Endian */
3665 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3666 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3667 uint64_t reserved_9_63 : 55;
3668 #endif /* Word 0 - End */
3669 } s;
3670 /* struct bdk_rvu_priv_pfx_sso_cfg_s cn; */
3671 };
3672 typedef union bdk_rvu_priv_pfx_sso_cfg bdk_rvu_priv_pfx_sso_cfg_t;
3673
3674 static inline uint64_t BDK_RVU_PRIV_PFX_SSO_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_SSO_CFG(unsigned long a)3675 static inline uint64_t BDK_RVU_PRIV_PFX_SSO_CFG(unsigned long a)
3676 {
3677 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
3678 return 0x850008000320ll + 0x10000ll * ((a) & 0xf);
3679 __bdk_csr_fatal("RVU_PRIV_PFX_SSO_CFG", 1, a, 0, 0, 0);
3680 }
3681
3682 #define typedef_BDK_RVU_PRIV_PFX_SSO_CFG(a) bdk_rvu_priv_pfx_sso_cfg_t
3683 #define bustype_BDK_RVU_PRIV_PFX_SSO_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3684 #define basename_BDK_RVU_PRIV_PFX_SSO_CFG(a) "RVU_PRIV_PFX_SSO_CFG"
3685 #define device_bar_BDK_RVU_PRIV_PFX_SSO_CFG(a) 0x0 /* BAR0 */
3686 #define busnum_BDK_RVU_PRIV_PFX_SSO_CFG(a) (a)
3687 #define arguments_BDK_RVU_PRIV_PFX_SSO_CFG(a) (a),-1,-1,-1
3688
3689 /**
3690 * Register (RVU_PF_BAR0) rvu_priv_pf#_ssow_cfg
3691 *
3692 * RVU Privileged PF SSO Work Slot Configuration Registers
3693 * Similar to RVU_PRIV_PF()_NIX()_CFG, but for SSOW block.
3694 */
3695 union bdk_rvu_priv_pfx_ssow_cfg
3696 {
3697 uint64_t u;
3698 struct bdk_rvu_priv_pfx_ssow_cfg_s
3699 {
3700 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3701 uint64_t reserved_9_63 : 55;
3702 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3703 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3704 #else /* Word 0 - Little Endian */
3705 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3706 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3707 uint64_t reserved_9_63 : 55;
3708 #endif /* Word 0 - End */
3709 } s;
3710 /* struct bdk_rvu_priv_pfx_ssow_cfg_s cn; */
3711 };
3712 typedef union bdk_rvu_priv_pfx_ssow_cfg bdk_rvu_priv_pfx_ssow_cfg_t;
3713
3714 static inline uint64_t BDK_RVU_PRIV_PFX_SSOW_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_SSOW_CFG(unsigned long a)3715 static inline uint64_t BDK_RVU_PRIV_PFX_SSOW_CFG(unsigned long a)
3716 {
3717 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
3718 return 0x850008000330ll + 0x10000ll * ((a) & 0xf);
3719 __bdk_csr_fatal("RVU_PRIV_PFX_SSOW_CFG", 1, a, 0, 0, 0);
3720 }
3721
3722 #define typedef_BDK_RVU_PRIV_PFX_SSOW_CFG(a) bdk_rvu_priv_pfx_ssow_cfg_t
3723 #define bustype_BDK_RVU_PRIV_PFX_SSOW_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3724 #define basename_BDK_RVU_PRIV_PFX_SSOW_CFG(a) "RVU_PRIV_PFX_SSOW_CFG"
3725 #define device_bar_BDK_RVU_PRIV_PFX_SSOW_CFG(a) 0x0 /* BAR0 */
3726 #define busnum_BDK_RVU_PRIV_PFX_SSOW_CFG(a) (a)
3727 #define arguments_BDK_RVU_PRIV_PFX_SSOW_CFG(a) (a),-1,-1,-1
3728
3729 /**
3730 * Register (RVU_PF_BAR0) rvu_priv_pf#_tim_cfg
3731 *
3732 * RVU Privileged PF SSO Work Slot Configuration Registers
3733 * Similar to RVU_PRIV_PF()_NIX()_CFG, but for TIM block.
3734 */
3735 union bdk_rvu_priv_pfx_tim_cfg
3736 {
3737 uint64_t u;
3738 struct bdk_rvu_priv_pfx_tim_cfg_s
3739 {
3740 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3741 uint64_t reserved_9_63 : 55;
3742 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3743 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3744 #else /* Word 0 - Little Endian */
3745 uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero,
3746 the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */
3747 uint64_t reserved_9_63 : 55;
3748 #endif /* Word 0 - End */
3749 } s;
3750 /* struct bdk_rvu_priv_pfx_tim_cfg_s cn; */
3751 };
3752 typedef union bdk_rvu_priv_pfx_tim_cfg bdk_rvu_priv_pfx_tim_cfg_t;
3753
3754 static inline uint64_t BDK_RVU_PRIV_PFX_TIM_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_PRIV_PFX_TIM_CFG(unsigned long a)3755 static inline uint64_t BDK_RVU_PRIV_PFX_TIM_CFG(unsigned long a)
3756 {
3757 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=15))
3758 return 0x850008000340ll + 0x10000ll * ((a) & 0xf);
3759 __bdk_csr_fatal("RVU_PRIV_PFX_TIM_CFG", 1, a, 0, 0, 0);
3760 }
3761
3762 #define typedef_BDK_RVU_PRIV_PFX_TIM_CFG(a) bdk_rvu_priv_pfx_tim_cfg_t
3763 #define bustype_BDK_RVU_PRIV_PFX_TIM_CFG(a) BDK_CSR_TYPE_RVU_PF_BAR0
3764 #define basename_BDK_RVU_PRIV_PFX_TIM_CFG(a) "RVU_PRIV_PFX_TIM_CFG"
3765 #define device_bar_BDK_RVU_PRIV_PFX_TIM_CFG(a) 0x0 /* BAR0 */
3766 #define busnum_BDK_RVU_PRIV_PFX_TIM_CFG(a) (a)
3767 #define arguments_BDK_RVU_PRIV_PFX_TIM_CFG(a) (a),-1,-1,-1
3768
3769 /**
3770 * Register (RVU_VF_BAR2) rvu_vf_block_addr#_disc
3771 *
3772 * RVU VF Block Address Discovery Registers
3773 * These registers allow each VF driver to discover block resources that are
3774 * provisioned to its VF. The register's block address index is enumerated by
3775 * RVU_BLOCK_ADDR_E.
3776 */
3777 union bdk_rvu_vf_block_addrx_disc
3778 {
3779 uint64_t u;
3780 struct bdk_rvu_vf_block_addrx_disc_s
3781 {
3782 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3783 uint64_t reserved_28_63 : 36;
3784 uint64_t btype : 8; /**< [ 27: 20](RO/H) Block type enumerated by RVU_BLOCK_TYPE_E. */
3785 uint64_t rid : 8; /**< [ 19: 12](RO/H) Revision ID of the block from RVU_PRIV_BLOCK_TYPE()_REV[RID]. */
3786 uint64_t imp : 1; /**< [ 11: 11](RO/H) Implemented. When set, a block is present at this block address index as
3787 enumerated by RVU_BLOCK_ADDR_E. When clear, a block is not present and the
3788 remaining fields in the register are RAZ.
3789
3790 Internal:
3791 Returns zero if the block is implemented but fused out. */
3792 uint64_t reserved_9_10 : 2;
3793 uint64_t num_lfs : 9; /**< [ 8: 0](RO/H) Number of local functions from the block that are provisioned to the VF/PF.
3794 When non-zero, the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in
3795 the block.
3796 Returns 0 for block types that do not have local functions, 0 or 1 for
3797 single-slot blocks; see RVU_BLOCK_TYPE_E. */
3798 #else /* Word 0 - Little Endian */
3799 uint64_t num_lfs : 9; /**< [ 8: 0](RO/H) Number of local functions from the block that are provisioned to the VF/PF.
3800 When non-zero, the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in
3801 the block.
3802 Returns 0 for block types that do not have local functions, 0 or 1 for
3803 single-slot blocks; see RVU_BLOCK_TYPE_E. */
3804 uint64_t reserved_9_10 : 2;
3805 uint64_t imp : 1; /**< [ 11: 11](RO/H) Implemented. When set, a block is present at this block address index as
3806 enumerated by RVU_BLOCK_ADDR_E. When clear, a block is not present and the
3807 remaining fields in the register are RAZ.
3808
3809 Internal:
3810 Returns zero if the block is implemented but fused out. */
3811 uint64_t rid : 8; /**< [ 19: 12](RO/H) Revision ID of the block from RVU_PRIV_BLOCK_TYPE()_REV[RID]. */
3812 uint64_t btype : 8; /**< [ 27: 20](RO/H) Block type enumerated by RVU_BLOCK_TYPE_E. */
3813 uint64_t reserved_28_63 : 36;
3814 #endif /* Word 0 - End */
3815 } s;
3816 /* struct bdk_rvu_vf_block_addrx_disc_s cn; */
3817 };
3818 typedef union bdk_rvu_vf_block_addrx_disc bdk_rvu_vf_block_addrx_disc_t;
3819
3820 static inline uint64_t BDK_RVU_VF_BLOCK_ADDRX_DISC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_VF_BLOCK_ADDRX_DISC(unsigned long a)3821 static inline uint64_t BDK_RVU_VF_BLOCK_ADDRX_DISC(unsigned long a)
3822 {
3823 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=31))
3824 return 0x850200000200ll + 8ll * ((a) & 0x1f);
3825 __bdk_csr_fatal("RVU_VF_BLOCK_ADDRX_DISC", 1, a, 0, 0, 0);
3826 }
3827
3828 #define typedef_BDK_RVU_VF_BLOCK_ADDRX_DISC(a) bdk_rvu_vf_block_addrx_disc_t
3829 #define bustype_BDK_RVU_VF_BLOCK_ADDRX_DISC(a) BDK_CSR_TYPE_RVU_VF_BAR2
3830 #define basename_BDK_RVU_VF_BLOCK_ADDRX_DISC(a) "RVU_VF_BLOCK_ADDRX_DISC"
3831 #define device_bar_BDK_RVU_VF_BLOCK_ADDRX_DISC(a) 0x2 /* BAR2 */
3832 #define busnum_BDK_RVU_VF_BLOCK_ADDRX_DISC(a) (a)
3833 #define arguments_BDK_RVU_VF_BLOCK_ADDRX_DISC(a) (a),-1,-1,-1
3834
3835 /**
3836 * Register (RVU_VF_BAR2) rvu_vf_int
3837 *
3838 * RVU VF Interrupt Registers
3839 */
3840 union bdk_rvu_vf_int
3841 {
3842 uint64_t u;
3843 struct bdk_rvu_vf_int_s
3844 {
3845 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3846 uint64_t reserved_1_63 : 63;
3847 uint64_t mbox : 1; /**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when RVU_PF_VF()_PFVF_MBOX(0) is written. */
3848 #else /* Word 0 - Little Endian */
3849 uint64_t mbox : 1; /**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when RVU_PF_VF()_PFVF_MBOX(0) is written. */
3850 uint64_t reserved_1_63 : 63;
3851 #endif /* Word 0 - End */
3852 } s;
3853 /* struct bdk_rvu_vf_int_s cn; */
3854 };
3855 typedef union bdk_rvu_vf_int bdk_rvu_vf_int_t;
3856
3857 #define BDK_RVU_VF_INT BDK_RVU_VF_INT_FUNC()
3858 static inline uint64_t BDK_RVU_VF_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_VF_INT_FUNC(void)3859 static inline uint64_t BDK_RVU_VF_INT_FUNC(void)
3860 {
3861 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3862 return 0x850200000020ll;
3863 __bdk_csr_fatal("RVU_VF_INT", 0, 0, 0, 0, 0);
3864 }
3865
3866 #define typedef_BDK_RVU_VF_INT bdk_rvu_vf_int_t
3867 #define bustype_BDK_RVU_VF_INT BDK_CSR_TYPE_RVU_VF_BAR2
3868 #define basename_BDK_RVU_VF_INT "RVU_VF_INT"
3869 #define device_bar_BDK_RVU_VF_INT 0x2 /* BAR2 */
3870 #define busnum_BDK_RVU_VF_INT 0
3871 #define arguments_BDK_RVU_VF_INT -1,-1,-1,-1
3872
3873 /**
3874 * Register (RVU_VF_BAR2) rvu_vf_int_ena_w1c
3875 *
3876 * RVU VF Interrupt Enable Clear Register
3877 * This register clears interrupt enable bits.
3878 */
3879 union bdk_rvu_vf_int_ena_w1c
3880 {
3881 uint64_t u;
3882 struct bdk_rvu_vf_int_ena_w1c_s
3883 {
3884 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3885 uint64_t reserved_1_63 : 63;
3886 uint64_t mbox : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RVU_VF_INT[MBOX]. */
3887 #else /* Word 0 - Little Endian */
3888 uint64_t mbox : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RVU_VF_INT[MBOX]. */
3889 uint64_t reserved_1_63 : 63;
3890 #endif /* Word 0 - End */
3891 } s;
3892 /* struct bdk_rvu_vf_int_ena_w1c_s cn; */
3893 };
3894 typedef union bdk_rvu_vf_int_ena_w1c bdk_rvu_vf_int_ena_w1c_t;
3895
3896 #define BDK_RVU_VF_INT_ENA_W1C BDK_RVU_VF_INT_ENA_W1C_FUNC()
3897 static inline uint64_t BDK_RVU_VF_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_VF_INT_ENA_W1C_FUNC(void)3898 static inline uint64_t BDK_RVU_VF_INT_ENA_W1C_FUNC(void)
3899 {
3900 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3901 return 0x850200000038ll;
3902 __bdk_csr_fatal("RVU_VF_INT_ENA_W1C", 0, 0, 0, 0, 0);
3903 }
3904
3905 #define typedef_BDK_RVU_VF_INT_ENA_W1C bdk_rvu_vf_int_ena_w1c_t
3906 #define bustype_BDK_RVU_VF_INT_ENA_W1C BDK_CSR_TYPE_RVU_VF_BAR2
3907 #define basename_BDK_RVU_VF_INT_ENA_W1C "RVU_VF_INT_ENA_W1C"
3908 #define device_bar_BDK_RVU_VF_INT_ENA_W1C 0x2 /* BAR2 */
3909 #define busnum_BDK_RVU_VF_INT_ENA_W1C 0
3910 #define arguments_BDK_RVU_VF_INT_ENA_W1C -1,-1,-1,-1
3911
3912 /**
3913 * Register (RVU_VF_BAR2) rvu_vf_int_ena_w1s
3914 *
3915 * RVU VF Interrupt Enable Set Register
3916 * This register sets interrupt enable bits.
3917 */
3918 union bdk_rvu_vf_int_ena_w1s
3919 {
3920 uint64_t u;
3921 struct bdk_rvu_vf_int_ena_w1s_s
3922 {
3923 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3924 uint64_t reserved_1_63 : 63;
3925 uint64_t mbox : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RVU_VF_INT[MBOX]. */
3926 #else /* Word 0 - Little Endian */
3927 uint64_t mbox : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RVU_VF_INT[MBOX]. */
3928 uint64_t reserved_1_63 : 63;
3929 #endif /* Word 0 - End */
3930 } s;
3931 /* struct bdk_rvu_vf_int_ena_w1s_s cn; */
3932 };
3933 typedef union bdk_rvu_vf_int_ena_w1s bdk_rvu_vf_int_ena_w1s_t;
3934
3935 #define BDK_RVU_VF_INT_ENA_W1S BDK_RVU_VF_INT_ENA_W1S_FUNC()
3936 static inline uint64_t BDK_RVU_VF_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_VF_INT_ENA_W1S_FUNC(void)3937 static inline uint64_t BDK_RVU_VF_INT_ENA_W1S_FUNC(void)
3938 {
3939 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3940 return 0x850200000030ll;
3941 __bdk_csr_fatal("RVU_VF_INT_ENA_W1S", 0, 0, 0, 0, 0);
3942 }
3943
3944 #define typedef_BDK_RVU_VF_INT_ENA_W1S bdk_rvu_vf_int_ena_w1s_t
3945 #define bustype_BDK_RVU_VF_INT_ENA_W1S BDK_CSR_TYPE_RVU_VF_BAR2
3946 #define basename_BDK_RVU_VF_INT_ENA_W1S "RVU_VF_INT_ENA_W1S"
3947 #define device_bar_BDK_RVU_VF_INT_ENA_W1S 0x2 /* BAR2 */
3948 #define busnum_BDK_RVU_VF_INT_ENA_W1S 0
3949 #define arguments_BDK_RVU_VF_INT_ENA_W1S -1,-1,-1,-1
3950
3951 /**
3952 * Register (RVU_VF_BAR2) rvu_vf_int_w1s
3953 *
3954 * RVU VF Interrupt Set Register
3955 * This register sets interrupt bits.
3956 */
3957 union bdk_rvu_vf_int_w1s
3958 {
3959 uint64_t u;
3960 struct bdk_rvu_vf_int_w1s_s
3961 {
3962 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3963 uint64_t reserved_1_63 : 63;
3964 uint64_t mbox : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RVU_VF_INT[MBOX]. */
3965 #else /* Word 0 - Little Endian */
3966 uint64_t mbox : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RVU_VF_INT[MBOX]. */
3967 uint64_t reserved_1_63 : 63;
3968 #endif /* Word 0 - End */
3969 } s;
3970 /* struct bdk_rvu_vf_int_w1s_s cn; */
3971 };
3972 typedef union bdk_rvu_vf_int_w1s bdk_rvu_vf_int_w1s_t;
3973
3974 #define BDK_RVU_VF_INT_W1S BDK_RVU_VF_INT_W1S_FUNC()
3975 static inline uint64_t BDK_RVU_VF_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RVU_VF_INT_W1S_FUNC(void)3976 static inline uint64_t BDK_RVU_VF_INT_W1S_FUNC(void)
3977 {
3978 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3979 return 0x850200000028ll;
3980 __bdk_csr_fatal("RVU_VF_INT_W1S", 0, 0, 0, 0, 0);
3981 }
3982
3983 #define typedef_BDK_RVU_VF_INT_W1S bdk_rvu_vf_int_w1s_t
3984 #define bustype_BDK_RVU_VF_INT_W1S BDK_CSR_TYPE_RVU_VF_BAR2
3985 #define basename_BDK_RVU_VF_INT_W1S "RVU_VF_INT_W1S"
3986 #define device_bar_BDK_RVU_VF_INT_W1S 0x2 /* BAR2 */
3987 #define busnum_BDK_RVU_VF_INT_W1S 0
3988 #define arguments_BDK_RVU_VF_INT_W1S -1,-1,-1,-1
3989
3990 /**
3991 * Register (RVU_VF_BAR2) rvu_vf_msix_pba#
3992 *
3993 * RVU VF MSI-X Pending-Bit-Array Registers
3994 * This register is the MSI-X VF PBA table.
3995 */
3996 union bdk_rvu_vf_msix_pbax
3997 {
3998 uint64_t u;
3999 struct bdk_rvu_vf_msix_pbax_s
4000 {
4001 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4002 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message bit for each MSI-X vector, i.e. one bit per
4003 RVU_VF_MSIX_VEC()_CTL register.
4004 The total number of bits for a given VF (and thus the number of PBA
4005 registers) is determined by RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1]
4006 (plus 1). */
4007 #else /* Word 0 - Little Endian */
4008 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message bit for each MSI-X vector, i.e. one bit per
4009 RVU_VF_MSIX_VEC()_CTL register.
4010 The total number of bits for a given VF (and thus the number of PBA
4011 registers) is determined by RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1]
4012 (plus 1). */
4013 #endif /* Word 0 - End */
4014 } s;
4015 /* struct bdk_rvu_vf_msix_pbax_s cn; */
4016 };
4017 typedef union bdk_rvu_vf_msix_pbax bdk_rvu_vf_msix_pbax_t;
4018
4019 static inline uint64_t BDK_RVU_VF_MSIX_PBAX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_VF_MSIX_PBAX(unsigned long a)4020 static inline uint64_t BDK_RVU_VF_MSIX_PBAX(unsigned long a)
4021 {
4022 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a==0))
4023 return 0x8502002f0000ll + 8ll * ((a) & 0x0);
4024 __bdk_csr_fatal("RVU_VF_MSIX_PBAX", 1, a, 0, 0, 0);
4025 }
4026
4027 #define typedef_BDK_RVU_VF_MSIX_PBAX(a) bdk_rvu_vf_msix_pbax_t
4028 #define bustype_BDK_RVU_VF_MSIX_PBAX(a) BDK_CSR_TYPE_RVU_VF_BAR2
4029 #define basename_BDK_RVU_VF_MSIX_PBAX(a) "RVU_VF_MSIX_PBAX"
4030 #define device_bar_BDK_RVU_VF_MSIX_PBAX(a) 0x2 /* BAR2 */
4031 #define busnum_BDK_RVU_VF_MSIX_PBAX(a) (a)
4032 #define arguments_BDK_RVU_VF_MSIX_PBAX(a) (a),-1,-1,-1
4033
4034 /**
4035 * Register (RVU_VF_BAR2) rvu_vf_msix_vec#_addr
4036 *
4037 * RVU VF MSI-X Vector-Table Address Registers
4038 * These registers and RVU_VF_MSIX_VEC()_CTL form the VF MSI-X vector table.
4039 * The number of MSI-X vectors for a given VF is specified by
4040 * RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1] (plus 1).
4041 *
4042 * Internal:
4043 * VF vector count of 128 allows up to that number to be provisioned to the VF
4044 * from LF resources of various blocks.
4045 */
4046 union bdk_rvu_vf_msix_vecx_addr
4047 {
4048 uint64_t u;
4049 struct bdk_rvu_vf_msix_vecx_addr_s
4050 {
4051 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4052 uint64_t reserved_53_63 : 11;
4053 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
4054 uint64_t reserved_1 : 1;
4055 uint64_t secvec : 1; /**< [ 0: 0](RAZ) Secure vector. Zero as not supported for RVU vectors. */
4056 #else /* Word 0 - Little Endian */
4057 uint64_t secvec : 1; /**< [ 0: 0](RAZ) Secure vector. Zero as not supported for RVU vectors. */
4058 uint64_t reserved_1 : 1;
4059 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
4060 uint64_t reserved_53_63 : 11;
4061 #endif /* Word 0 - End */
4062 } s;
4063 /* struct bdk_rvu_vf_msix_vecx_addr_s cn; */
4064 };
4065 typedef union bdk_rvu_vf_msix_vecx_addr bdk_rvu_vf_msix_vecx_addr_t;
4066
4067 static inline uint64_t BDK_RVU_VF_MSIX_VECX_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_VF_MSIX_VECX_ADDR(unsigned long a)4068 static inline uint64_t BDK_RVU_VF_MSIX_VECX_ADDR(unsigned long a)
4069 {
4070 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a==0))
4071 return 0x850200200000ll + 0x10ll * ((a) & 0x0);
4072 __bdk_csr_fatal("RVU_VF_MSIX_VECX_ADDR", 1, a, 0, 0, 0);
4073 }
4074
4075 #define typedef_BDK_RVU_VF_MSIX_VECX_ADDR(a) bdk_rvu_vf_msix_vecx_addr_t
4076 #define bustype_BDK_RVU_VF_MSIX_VECX_ADDR(a) BDK_CSR_TYPE_RVU_VF_BAR2
4077 #define basename_BDK_RVU_VF_MSIX_VECX_ADDR(a) "RVU_VF_MSIX_VECX_ADDR"
4078 #define device_bar_BDK_RVU_VF_MSIX_VECX_ADDR(a) 0x2 /* BAR2 */
4079 #define busnum_BDK_RVU_VF_MSIX_VECX_ADDR(a) (a)
4080 #define arguments_BDK_RVU_VF_MSIX_VECX_ADDR(a) (a),-1,-1,-1
4081
4082 /**
4083 * Register (RVU_VF_BAR2) rvu_vf_msix_vec#_ctl
4084 *
4085 * RVU VF MSI-X Vector-Table Control and Data Registers
4086 * These registers and RVU_VF_MSIX_VEC()_ADDR form the VF MSI-X vector table.
4087 */
4088 union bdk_rvu_vf_msix_vecx_ctl
4089 {
4090 uint64_t u;
4091 struct bdk_rvu_vf_msix_vecx_ctl_s
4092 {
4093 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4094 uint64_t reserved_33_63 : 31;
4095 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
4096 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
4097 #else /* Word 0 - Little Endian */
4098 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
4099 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
4100 uint64_t reserved_33_63 : 31;
4101 #endif /* Word 0 - End */
4102 } s;
4103 /* struct bdk_rvu_vf_msix_vecx_ctl_s cn; */
4104 };
4105 typedef union bdk_rvu_vf_msix_vecx_ctl bdk_rvu_vf_msix_vecx_ctl_t;
4106
4107 static inline uint64_t BDK_RVU_VF_MSIX_VECX_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_VF_MSIX_VECX_CTL(unsigned long a)4108 static inline uint64_t BDK_RVU_VF_MSIX_VECX_CTL(unsigned long a)
4109 {
4110 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a==0))
4111 return 0x850200200008ll + 0x10ll * ((a) & 0x0);
4112 __bdk_csr_fatal("RVU_VF_MSIX_VECX_CTL", 1, a, 0, 0, 0);
4113 }
4114
4115 #define typedef_BDK_RVU_VF_MSIX_VECX_CTL(a) bdk_rvu_vf_msix_vecx_ctl_t
4116 #define bustype_BDK_RVU_VF_MSIX_VECX_CTL(a) BDK_CSR_TYPE_RVU_VF_BAR2
4117 #define basename_BDK_RVU_VF_MSIX_VECX_CTL(a) "RVU_VF_MSIX_VECX_CTL"
4118 #define device_bar_BDK_RVU_VF_MSIX_VECX_CTL(a) 0x2 /* BAR2 */
4119 #define busnum_BDK_RVU_VF_MSIX_VECX_CTL(a) (a)
4120 #define arguments_BDK_RVU_VF_MSIX_VECX_CTL(a) (a),-1,-1,-1
4121
4122 /**
4123 * Register (RVU_VF_BAR2) rvu_vf_vfpf_mbox#
4124 *
4125 * RVU VF/PF Mailbox Registers
4126 */
4127 union bdk_rvu_vf_vfpf_mboxx
4128 {
4129 uint64_t u;
4130 struct bdk_rvu_vf_vfpf_mboxx_s
4131 {
4132 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4133 uint64_t data : 64; /**< [ 63: 0](R/W/H) Mailbox data. These VF registers access the 16-byte-per-VF VF/PF mailbox
4134 RAM. The PF may access the same storage using RVU_PF_VF()_PFVF_MBOX().
4135 MBOX(0) is typically used for PF to VF signaling, MBOX(1) for VF to PF.
4136 Writing RVU_VF_VFPF_MBOX(1) (but not RVU_PF_VF()_PFVF_MBOX(1))
4137 will set the corresponding RVU_PF_VFPF_MBOX_INT() bit, which if appropriately
4138 enabled will send an interrupt to the PF. */
4139 #else /* Word 0 - Little Endian */
4140 uint64_t data : 64; /**< [ 63: 0](R/W/H) Mailbox data. These VF registers access the 16-byte-per-VF VF/PF mailbox
4141 RAM. The PF may access the same storage using RVU_PF_VF()_PFVF_MBOX().
4142 MBOX(0) is typically used for PF to VF signaling, MBOX(1) for VF to PF.
4143 Writing RVU_VF_VFPF_MBOX(1) (but not RVU_PF_VF()_PFVF_MBOX(1))
4144 will set the corresponding RVU_PF_VFPF_MBOX_INT() bit, which if appropriately
4145 enabled will send an interrupt to the PF. */
4146 #endif /* Word 0 - End */
4147 } s;
4148 /* struct bdk_rvu_vf_vfpf_mboxx_s cn; */
4149 };
4150 typedef union bdk_rvu_vf_vfpf_mboxx bdk_rvu_vf_vfpf_mboxx_t;
4151
4152 static inline uint64_t BDK_RVU_VF_VFPF_MBOXX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RVU_VF_VFPF_MBOXX(unsigned long a)4153 static inline uint64_t BDK_RVU_VF_VFPF_MBOXX(unsigned long a)
4154 {
4155 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4156 return 0x850200000000ll + 8ll * ((a) & 0x1);
4157 __bdk_csr_fatal("RVU_VF_VFPF_MBOXX", 1, a, 0, 0, 0);
4158 }
4159
4160 #define typedef_BDK_RVU_VF_VFPF_MBOXX(a) bdk_rvu_vf_vfpf_mboxx_t
4161 #define bustype_BDK_RVU_VF_VFPF_MBOXX(a) BDK_CSR_TYPE_RVU_VF_BAR2
4162 #define basename_BDK_RVU_VF_VFPF_MBOXX(a) "RVU_VF_VFPF_MBOXX"
4163 #define device_bar_BDK_RVU_VF_VFPF_MBOXX(a) 0x2 /* BAR2 */
4164 #define busnum_BDK_RVU_VF_VFPF_MBOXX(a) (a)
4165 #define arguments_BDK_RVU_VF_VFPF_MBOXX(a) (a),-1,-1,-1
4166
4167 #endif /* __BDK_CSRS_RVU_H__ */
4168