1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__ 4 #define __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__ 5 6 #include <spi-generic.h> 7 #include <stdint.h> 8 #include <soc/addressmap.h> 9 10 enum { 11 SFLASH_POLLINGREG_US = 500000, 12 SFLASH_WRBUF_SIZE = 128, 13 SFLASHNAME_LENGTH = 16, 14 SFLASH_WRITE_IN_PROGRESS = 1, 15 SFLASH_COMMAND_ENABLE = 0x30, 16 SFLASH_DMA_ALIGN = 0x10, 17 18 /* NOR flash controller commands */ 19 SFLASH_RD_TRIGGER = 1 << 0, 20 SFLASH_READSTATUS = 1 << 1, 21 SFLASH_PRG_CMD = 1 << 2, 22 SFLASH_WR_TRIGGER = 1 << 4, 23 SFLASH_WRITESTATUS = 1 << 5, 24 SFLASH_AUTOINC = 1 << 7, 25 /* NOR flash commands */ 26 SFLASH_OP_WREN = 0x6, 27 SECTOR_ERASE_CMD = 0x20, 28 SFLASH_UNPROTECTED = 0x0, 29 /* DMA commands */ 30 SFLASH_DMA_TRIGGER = 1 << 0, 31 SFLASH_DMA_SW_RESET = 1 << 1, 32 SFLASH_DMA_WDLE_EN = 1 << 2, 33 /* Dual mode */ 34 SFLASH_READ_DUAL_EN = 0x1, 35 SFLASH_1_1_2_READ = 0x3b 36 }; 37 38 /* register Offset */ 39 struct mtk_nor_regs { 40 u32 cmd; 41 u32 cnt; 42 u32 rdsr; 43 u32 rdata; 44 u32 radr[3]; 45 u32 wdata; 46 u32 prgdata[6]; 47 u32 shreg[10]; 48 u32 cfg[2]; 49 u32 shreg10; 50 u32 status[5]; 51 u32 timing; 52 u32 flash_cfg; 53 u32 reserved2[3]; 54 u32 sf_time; 55 u32 reserved3; 56 u32 diff_addr; 57 u32 del_sel[2]; 58 u32 intrstus; 59 u32 intren; 60 u32 pp_ctl; 61 u32 cfg3; 62 u32 chksum_ctl; 63 u32 chksum; 64 u32 aaicmd; 65 u32 wrprot; 66 u32 radr3; 67 u32 read_dual; 68 u32 delsel[3]; 69 u32 reserved[397]; 70 u32 cfg1_bri[2]; 71 u32 fdma_ctl; 72 u32 fdma_fadr; 73 u32 fdma_dadr; 74 u32 fdma_end_dadr; 75 }; 76 check_member(mtk_nor_regs, fdma_end_dadr, 0x724); 77 78 int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash); 79 80 #endif /* __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__ */ 81