1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef SOC_MEDIATEK_MT8173_GPIO_H 3 #define SOC_MEDIATEK_MT8173_GPIO_H 4 5 #include <stdint.h> 6 #include <soc/addressmap.h> 7 #include <soc/gpio_common.h> 8 9 enum { 10 MAX_GPIO_REG_BITS = 16, 11 MAX_GPIO_MODE_PER_REG = 5, 12 GPIO_MODE_BITS = 3, 13 }; 14 15 enum external_power { 16 GPIO_EINT_3P3V = 0, 17 GPIO_EINT_1P8V = 1, 18 }; 19 20 #define PIN(id, name, func1, func2, func3, func4, func5, func6, func7) \ 21 PAD_##name##_ID = id, \ 22 PAD_##name##_FUNC_##func1 = 1, \ 23 PAD_##name##_FUNC_##func2 = 2, \ 24 PAD_##name##_FUNC_##func3 = 3, \ 25 PAD_##name##_FUNC_##func4 = 4, \ 26 PAD_##name##_FUNC_##func5 = 5, \ 27 PAD_##name##_FUNC_##func6 = 6, \ 28 PAD_##name##_FUNC_##func7 = 7 29 30 #define GPIO(name) ((gpio_t){.id = PAD_##name##_ID}) 31 32 enum { 33 PIN(0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, 34 UTXD0, RES5, RES6, DBG_MON_A_20), 35 PIN(1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, 36 URXD0, RES5, RES6, DBG_MON_A_21), 37 PIN(2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, 38 UTXD3, RES5, RES6, DBG_MON_A_22), 39 PIN(3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, 40 URXD3, RES5, RES6, DBG_MON_A_23), 41 PIN(4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, 42 UCTS3, RES5, SFWP_B, RES7), 43 PIN(5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, 44 URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7), 45 PIN(6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, 46 RES4, AP_MD32_JTAG_TCK, SFCS0, RES7), 47 PIN(7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, 48 RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7), 49 PIN(8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, 50 AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7), 51 PIN(9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, 52 USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7), 53 PIN(10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, 54 PWM4, IRDA_RXD, RES6, RES7), 55 PIN(11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, 56 PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30), 57 PIN(12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, 58 RES4, I2S2_WS, RES6, DBG_MON_B_32), 59 PIN(13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, 60 RES4, I2S2_BCK, RES6, DBG_MON_A_32), 61 PIN(14, EINT14, CMDAT0, CMCSD0, RES3, 62 CLKM2, RES5, RES6, DBG_MON_B_6), 63 PIN(15, EINT15, CMDAT1, CMCSD1, CMFLASH, 64 CLKM3, RES5, RES6, DBG_MON_B_29), 65 PIN(16, IDDIG, IDDIG, CMFLASH, RES3, 66 PWM5, RES5, RES6, RES7), 67 PIN(17, WATCHDOG, WATCHDOG_AO, RES2, RES3, 68 RES4, RES5, RES6, RES7), 69 PIN(18, CEC, CEC, RES2, RES3, 70 RES4, RES5, RES6, RES7), 71 PIN(19, HDMISCK, HDMISCK, HDCP_SCL, RES3, 72 RES4, RES5, RES6, RES7), 73 PIN(20, HDMISD, HDMISD, HDCP_SDA, RES3, 74 RES4, RES5, RES6, RES7), 75 PIN(21, HTPLG, HTPLG, RES2, RES3, 76 RES4, RES5, RES6, RES7), 77 PIN(22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, 78 RES4, RES5, RES6, RES7), 79 PIN(23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, 80 RES4, RES5, RES6, RES7), 81 PIN(24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, 82 RES4, RES5, RES6, RES7), 83 PIN(25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, 84 RES4, RES5, RES6, RES7), 85 PIN(26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, 86 RES4, RES5, RES6, RES7), 87 PIN(27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, 88 RES4, RES5, RES6, RES7), 89 PIN(28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, 90 RES4, RES5, RES6, RES7), 91 PIN(29, UCTS2, UCTS2, RES2, RES3, 92 RES4, RES5, RES6, RES7), 93 PIN(30, URTS2, URTS2, RES2, RES3, 94 RES4, RES5, RES6, RES7), 95 PIN(31, URXD2, URXD2, UTXD2, RES3, 96 RES4, RES5, RES6, RES7), 97 PIN(32, UTXD2, UTXD2, URXD2, RES3, 98 RES4, RES5, RES6, RES7), 99 PIN(33, DAICLK, MRG_CLK, PCM0_CLK, RES3, 100 RES4, RES5, RES6, RES7), 101 PIN(34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, 102 RES4, RES5, RES6, RES7), 103 PIN(35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, 104 RES4, RES5, RES6, RES7), 105 PIN(36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, 106 RES4, RES5, RES6, RES7), 107 PIN(37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, 108 PWM1, PWM2, CLKM0, RES7), 109 PIN(38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, 110 RES4, RES5, CLKM1, RES7), 111 PIN(39, CM2MCLK, CM2MCLK, CMCSD0, RES3, 112 RES4, RES5, RES6, DBG_MON_A_17), 113 PIN(40, CMPCLK, CMPCLK, CMCSK, CMCSD2, 114 RES4, RES5, RES6, DBG_MON_A_18), 115 PIN(41, CMMCLK, CMMCLK, RES2, RES3, 116 RES4, RES5, RES6, DBG_MON_A_19), 117 PIN(42, DSI_TE, DSI_TE, RES2, RES3, 118 RES4, RES5, RES6, RES7), 119 PIN(43, SDA2, SDA2, RES2, RES3, 120 RES4, RES5, RES6, RES7), 121 PIN(44, SCL2, SCL2, RES2, RES3, 122 RES4, RES5, RES6, RES7), 123 PIN(45, SDA0, SDA0, RES2, RES3, 124 RES4, RES5, RES6, RES7), 125 PIN(46, SCL0, SCL0, RES2, RES3, 126 RES4, RES5, RES6, RES7), 127 PIN(47, RDN0_A, CMDAT2, RES2, RES3, 128 RES4, RES5, RES6, RES7), 129 PIN(48, RDP0_A, CMDAT3, RES2, RES3, 130 RES4, RES5, RES6, RES7), 131 PIN(49, RDN1_A, CMDAT4, RES2, RES3, 132 RES4, RES5, RES6, RES7), 133 PIN(50, RDP1_A, CMDAT5, RES2, RES3, 134 RES4, RES5, RES6, RES7), 135 PIN(51, RCN_A, CMDAT6, RES2, RES3, 136 RES4, RES5, RES6, RES7), 137 PIN(52, RCP_A, CMDAT7, RES2, RES3, 138 RES4, RES5, RES6, RES7), 139 PIN(53, RDN2_A, CMDAT8, CMCSD3, RES3, 140 RES4, RES5, RES6, RES7), 141 PIN(54, RDP2_A, CMDAT9, CMCSD2, RES3, 142 RES4, RES5, RES6, RES7), 143 PIN(55, RDN3_A, CMHSYNC, CMCSD1, RES3, 144 RES4, RES5, RES6, RES7), 145 PIN(56, RDP3_A, CMVSYNC, CMCSD0, RES3, 146 RES4, RES5, RES6, RES7), 147 PIN(57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, 148 RES4, RES5, RES6, DBG_MON_B_7), 149 PIN(58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, 150 RES4, RES5, RES6, DBG_MON_B_8), 151 PIN(59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, 152 RES4, RES5, RES6, DBG_MON_B_9), 153 PIN(60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, 154 RES4, RES5, RES6, DBG_MON_B_10), 155 PIN(61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, 156 RES4, RES5, RES6, DBG_MON_B_11), 157 PIN(62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, 158 RES4, RES5, RES6, DBG_MON_B_12), 159 PIN(63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, 160 RES4, RES5, RES6, DBG_MON_B_13), 161 PIN(64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, 162 RES4, RES5, RES6, DBG_MON_B_14), 163 PIN(65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, 164 RES4, RES5, RES6, DBG_MON_B_16), 165 PIN(66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, 166 RES4, RES5, RES6, DBG_MON_B_15), 167 PIN(67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, 168 RES4, RES5, RES6, DBG_MON_B_17), 169 PIN(68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, 170 RES4, RES5, RES6, DBG_MON_B_18), 171 PIN(69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, 172 PWM5, I2S2_MCK, RES6, DBG_MON_B_19), 173 PIN(70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, 174 SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20), 175 PIN(71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, 176 SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21), 177 PIN(72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, 178 PWM6, DISP_PWM1, RES6, DBG_MON_B_22), 179 PIN(73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, 180 RES4, RES5, RES6, DBG_MON_B_24), 181 PIN(74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, 182 RES4, RES5, RES6, DBG_MON_B_25), 183 PIN(75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, 184 RES4, RES5, RES6, DBG_MON_B_26), 185 PIN(76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, 186 RES4, RES5, RES6, DBG_MON_B_27), 187 PIN(77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, 188 RES4, RES5, RES6, DBG_MON_B_28), 189 PIN(78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, 190 RES4, RES5, RES6, DBG_MON_B_23), 191 PIN(79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, 192 RES4, RES5, RES6, RES7), 193 PIN(80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, 194 RES4, RES5, RES6, RES7), 195 PIN(81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, 196 RES4, RES5, RES6, RES7), 197 PIN(82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, 198 RES4, RES5, RES6, RES7), 199 PIN(83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, 200 RES4, RES5, RES6, RES7), 201 PIN(84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, 202 RES4, RES5, RES6, RES7), 203 PIN(85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, 204 RES4, RES5, RES6, RES7), 205 PIN(86, RTC32K_CK, RTC32K_CK, RES2, RES3, 206 RES4, RES5, RES6, RES7), 207 PIN(87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, 208 RES4, RES5, RES6, DBG_MON_B_31), 209 PIN(88, SRCLKENAI, SRCLKENAI, RES2, RES3, 210 RES4, RES5, RES6, RES7), 211 PIN(89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, 212 RES4, RES5, RES6, RES7), 213 PIN(90, SRCLKENA0, SRCLKENA0, RES2, RES3, 214 RES4, RES5, RES6, RES7), 215 PIN(91, SRCLKENA1, SRCLKENA1, RES2, RES3, 216 RES4, RES5, RES6, RES7), 217 PIN(92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, 218 RES4, RES5, RES6, DBG_MON_A_24), 219 PIN(93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, 220 RES4, RES5, RES6, DBG_MON_A_25), 221 PIN(94, PCM_RX, PCM1_DI, I2S0_DI, RES3, 222 RES4, RES5, RES6, DBG_MON_A_26), 223 PIN(95, PCM_TX, PCM1_DO, I2S0_DO, RES3, 224 RES4, RES5, RES6, DBG_MON_A_27), 225 PIN(96, URXD1, URXD1, UTXD1, RES3, 226 RES4, RES5, RES6, DBG_MON_A_28), 227 PIN(97, UTXD1, UTXD1, URXD1, RES3, 228 RES4, RES5, RES6, DBG_MON_A_29), 229 PIN(98, URTS1, URTS1, UCTS1, RES3, 230 RES4, RES5, RES6, DBG_MON_A_30), 231 PIN(99, UCTS1, UCTS1, URTS1, RES3, 232 RES4, RES5, RES6, DBG_MON_A_31), 233 PIN(100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, 234 SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0), 235 PIN(101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, 236 SCL5, RES5, RES6, DBG_MON_B_1), 237 PIN(102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, 238 RES4, PWM0, SPI_CK_1, DBG_MON_B_2), 239 PIN(103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, 240 RES4, PWM1, SPI_MI_1, DBG_MON_B_3), 241 PIN(104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, 242 SDA3, PWM2, SPI_MO_1, DBG_MON_B_4), 243 PIN(105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, 244 SCL3, PWM3, SPI_CS_1, DBG_MON_B_5), 245 PIN(106, SDA3, SDA3, RES2, RES3, 246 RES4, RES5, RES6, RES7), 247 PIN(107, SCL3, SCL3, RES2, RES3, 248 RES4, RES5, RES6, RES7), 249 PIN(108, JTMS, JTMS, MFG_JTAG_TMS, RES3, 250 RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7), 251 PIN(109, JTCK, JTCK, MFG_JTAG_TCK, RES3, 252 RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7), 253 PIN(110, JTDI, JTDI, MFG_JTAG_TDI, RES3, 254 RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7), 255 PIN(111, JTDO, JTDO, MFG_JTAG_TDO, RES3, 256 RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7), 257 PIN(112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, 258 RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7), 259 PIN(113, URXD0, URXD0, UTXD0, RES3, 260 RES4, RES5, I2S2_WS, DBG_MON_A_0), 261 PIN(114, UTXD0, UTXD0, URXD0, RES3, 262 RES4, RES5, I2S2_BCK, DBG_MON_A_1), 263 PIN(115, URTS0, URTS0, UCTS0, RES3, 264 RES4, RES5, I2S2_MCK, DBG_MON_A_2), 265 PIN(116, UCTS0, UCTS0, URTS0, RES3, 266 RES4, RES5, I2S2_DI_1, DBG_MON_A_3), 267 PIN(117, URXD3, URXD3, UTXD3, RES3, 268 RES4, RES5, RES6, DBG_MON_A_9), 269 PIN(118, UTXD3, UTXD3, URXD3, RES3, 270 RES4, RES5, RES6, DBG_MON_A_10), 271 PIN(119, KPROW0, KROW0, RES2, RES3, 272 RES4, RES5, RES6, DBG_MON_A_11), 273 PIN(120, KPROW1, KROW1, RES2, PWM6, 274 RES4, RES5, RES6, DBG_MON_A_12), 275 PIN(121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, 276 PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13), 277 PIN(122, KPCOL0, KCOL0, RES2, RES3, 278 RES4, RES5, RES6, DBG_MON_A_14), 279 PIN(123, KPCOL1, KCOL1, IRDA_RXD, PWM5, 280 RES4, RES5, RES6, DBG_MON_A_15), 281 PIN(124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, 282 PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16), 283 PIN(125, SDA1, SDA1, RES2, RES3, 284 RES4, RES5, RES6, RES7), 285 PIN(126, SCL1, SCL1, RES2, RES3, 286 RES4, RES5, RES6, RES7), 287 PIN(127, LCM_RST, LCM_RST, RES2, RES3, 288 RES4, RES5, RES6, RES7), 289 PIN(128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, 290 RES4, SPI_CK_2, RES6, DBG_MON_A_4), 291 PIN(129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, 292 RES4, SPI_MI_2, RES6, DBG_MON_A_5), 293 PIN(130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, 294 RES4, SPI_MO_2, RES6, DBG_MON_A_6), 295 PIN(131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, 296 RES4, SPI_CS_2, RES6, DBG_MON_A_7), 297 PIN(132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, 298 RES4, RES5, RES6, DBG_MON_A_8), 299 PIN(133, SDA4, SDA4, RES2, RES3, 300 RES4, RES5, RES6, RES7), 301 PIN(134, SCL4, SCL4, RES2, RES3, 302 RES4, RES5, RES6, RES7), 303 }; 304 305 struct val_regs { 306 uint32_t val; 307 uint32_t set; 308 uint32_t rst; 309 uint32_t align; 310 }; 311 312 struct gpio_regs { 313 struct val_regs dir[9]; 314 uint8_t rsv00[112]; 315 struct val_regs pullen[9]; 316 uint8_t rsv01[112]; 317 struct val_regs pullsel[9]; 318 uint8_t rsv02[112]; 319 uint8_t rsv03[256]; 320 struct val_regs dout[9]; 321 uint8_t rsv04[112]; 322 struct val_regs din[9]; 323 uint8_t rsv05[112]; 324 struct val_regs mode[27]; 325 uint8_t rsv06[336]; 326 struct val_regs ies[3]; 327 struct val_regs smt[3]; 328 uint8_t rsv07[160]; 329 struct val_regs tdsel[8]; 330 struct val_regs rdsel[6]; 331 uint8_t rsv08[32]; 332 struct val_regs drv_mode[10]; 333 uint8_t rsv09[96]; 334 struct val_regs msdc_rsv0[11]; 335 struct val_regs msdc2_ctrl5; 336 struct val_regs msdc_rsv1[12]; 337 uint8_t rsv10[64]; 338 struct val_regs exmd_ctrl[1]; 339 uint8_t rsv11[48]; 340 struct val_regs kpad_ctrl[2]; 341 struct val_regs hsic_ctrl[4]; 342 }; 343 344 check_member(gpio_regs, msdc2_ctrl5, 0xcb0); 345 check_member(gpio_regs, hsic_ctrl[3], 0xe50); 346 347 static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); 348 349 void gpio_init(enum external_power); 350 351 #endif /* SOC_MEDIATEK_MT8173_GPIO_H */ 352