1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Damien Lespiau <[email protected]>
25 */
26
27 /*
28 * The goal of this test is to ensure that we respect inter ring dependencies
29 *
30 * For each pair of rings R1, R2 where we have copy support (i.e. blt,
31 * rendercpy and mediafill) do:
32 * - Throw a busy load onto R1. gem_concurrent_blt just uses lots of buffers
33 * for this effect.
34 * - Fill three buffers A, B, C with unique data.
35 * - Copy A to B on ring R1
36 *
37 * Then come the three different variants.
38 * - Copy B to C on ring R2, check that C now contains what A originally
39 * contained. This is the write->read hazard. gem_concurrent_blt calls this
40 * early read.
41 * - Copy C to A on ring R2, check that B now contains what A originally
42 * contained. This is the read->write hazard, gem_concurrent_blt calls it
43 * overwrite_source.
44 * - Copy C to B on ring R2 and check that B contains what C originally
45 * contained. This is the write/write hazard. gem_concurrent_blt doesn't
46 * have that since for the cpu case it's too boring.
47 *
48 */
49
50 #include "igt.h"
51 #include <stdlib.h>
52 #include <stdbool.h>
53
54
55 IGT_TEST_DESCRIPTION("Ensure inter-ring dependencies are respected.");
56
57 #define WIDTH 512
58 #define HEIGHT 512
59 #define NUM_BUSY_BUFFERS 32
60
61 typedef struct {
62 int drm_fd;
63 uint32_t devid;
64 drm_intel_bufmgr *bufmgr;
65 struct intel_batchbuffer *batch;
66
67 /* number of buffers to keep the ring busy for a while */
68 unsigned int n_buffers_load;
69
70 uint32_t linear[WIDTH * HEIGHT];
71
72 struct {
73 igt_render_copyfunc_t copy;
74 struct igt_buf *srcs;
75 struct igt_buf *dsts;
76 } render;
77
78 struct {
79 drm_intel_bo **srcs;
80 drm_intel_bo **dsts;
81 } blitter;
82
83 } data_t;
84
85 enum ring {
86 RENDER,
87 BLITTER,
88 };
89
90 enum test {
91 TEST_WRITE_READ,
92 TEST_READ_WRITE,
93 TEST_WRITE_WRITE,
94 };
95
ring_name(enum ring ring)96 static const char *ring_name(enum ring ring)
97 {
98 const char *names[] = {
99 "render",
100 "blitter",
101 };
102
103 return names[ring];
104 }
105
bo_create(data_t * data,int width,int height,int val)106 static drm_intel_bo *bo_create(data_t *data, int width, int height, int val)
107 {
108 drm_intel_bo *bo;
109 int i;
110
111 bo = drm_intel_bo_alloc(data->bufmgr, "", 4 * width * height, 4096);
112 igt_assert(bo);
113
114 for (i = 0; i < width * height; i++)
115 data->linear[i] = val;
116 gem_write(data->drm_fd, bo->handle, 0, data->linear,
117 sizeof(data->linear));
118
119 return bo;
120 }
121
bo_check(data_t * data,drm_intel_bo * bo,uint32_t val)122 static void bo_check(data_t *data, drm_intel_bo *bo, uint32_t val)
123 {
124 int i;
125
126 gem_read(data->drm_fd, bo->handle, 0,
127 data->linear, sizeof(data->linear));
128 for (i = 0; i < WIDTH * HEIGHT; i++)
129 igt_assert_eq_u32(data->linear[i], val);
130 }
131
scratch_buf_init_from_bo(struct igt_buf * buf,drm_intel_bo * bo)132 static void scratch_buf_init_from_bo(struct igt_buf *buf, drm_intel_bo *bo)
133 {
134 memset(buf, 0, sizeof(*buf));
135
136 buf->bo = bo;
137 buf->stride = 4 * WIDTH;
138 buf->tiling = I915_TILING_NONE;
139 buf->size = 4 * WIDTH * HEIGHT;
140 buf->bpp = 32;
141 }
142
scratch_buf_init(data_t * data,struct igt_buf * buf,int width,int height,uint32_t color)143 static void scratch_buf_init(data_t *data, struct igt_buf *buf,
144 int width, int height, uint32_t color)
145 {
146 drm_intel_bo *bo;
147
148 bo = bo_create(data, width, height, color);
149 scratch_buf_init_from_bo(buf, bo);
150 }
151
152 /*
153 * Provide a few ring specific vfuncs for run_test().
154 *
155 * busy() Queue a n_buffers_load workloads onto the ring to keep it busy
156 * busy_fini() Clean up after busy
157 * copy() Copy one BO to another
158 */
159
160 /*
161 * Render ring
162 */
163
render_busy(data_t * data)164 static void render_busy(data_t *data)
165 {
166 size_t array_size;
167 int i;
168
169 /* allocate 32 buffer objects and re-use them as needed */
170 array_size = NUM_BUSY_BUFFERS * sizeof(struct igt_buf);
171
172 data->render.srcs = malloc(array_size);
173 data->render.dsts = malloc(array_size);
174
175 for (i = 0; i < NUM_BUSY_BUFFERS; i++) {
176 scratch_buf_init(data, &data->render.srcs[i], WIDTH, HEIGHT,
177 0xdeadbeef);
178 scratch_buf_init(data, &data->render.dsts[i], WIDTH, HEIGHT,
179 0xdeadbeef);
180 }
181
182 for (i = 0; i < data->n_buffers_load; i++) {
183 data->render.copy(data->batch,
184 NULL, /* context */
185 &data->render.srcs[i % NUM_BUSY_BUFFERS],
186 0, 0, /* src_x, src_y */
187 WIDTH, HEIGHT,
188 &data->render.dsts[i % NUM_BUSY_BUFFERS],
189 0, 0 /* dst_x, dst_y */);
190 }
191 }
192
render_busy_fini(data_t * data)193 static void render_busy_fini(data_t *data)
194 {
195 int i;
196
197 for (i = 0; i < NUM_BUSY_BUFFERS; i++) {
198 drm_intel_bo_unreference(data->render.srcs[i].bo);
199 drm_intel_bo_unreference(data->render.dsts[i].bo);
200 }
201
202 free(data->render.srcs);
203 free(data->render.dsts);
204 data->render.srcs = NULL;
205 data->render.dsts = NULL;
206 }
207
render_copy(data_t * data,drm_intel_bo * src,drm_intel_bo * dst)208 static void render_copy(data_t *data, drm_intel_bo *src, drm_intel_bo *dst)
209 {
210 struct igt_buf src_buf, dst_buf;
211
212 scratch_buf_init_from_bo(&src_buf, src);
213 scratch_buf_init_from_bo(&dst_buf, dst);
214
215 data->render.copy(data->batch,
216 NULL, /* context */
217 &src_buf,
218 0, 0, /* src_x, src_y */
219 WIDTH, HEIGHT,
220 &dst_buf,
221 0, 0 /* dst_x, dst_y */);
222 }
223
224 /*
225 * Blitter ring
226 */
227
blitter_busy(data_t * data)228 static void blitter_busy(data_t *data)
229 {
230 size_t array_size;
231 int i;
232
233 /* allocate 32 buffer objects and re-use them as needed */
234 array_size = NUM_BUSY_BUFFERS * sizeof(drm_intel_bo *);
235
236 data->blitter.srcs = malloc(array_size);
237 data->blitter.dsts = malloc(array_size);
238
239 for (i = 0; i < NUM_BUSY_BUFFERS; i++) {
240 data->blitter.srcs[i] = bo_create(data,
241 WIDTH, HEIGHT,
242 0xdeadbeef);
243 data->blitter.dsts[i] = bo_create(data,
244 WIDTH, HEIGHT,
245 0xdeadbeef);
246 }
247
248 for (i = 0; i < data->n_buffers_load; i++) {
249 intel_copy_bo(data->batch,
250 data->blitter.srcs[i % NUM_BUSY_BUFFERS],
251 data->blitter.dsts[i % NUM_BUSY_BUFFERS],
252 WIDTH*HEIGHT*4);
253 }
254 }
255
blitter_busy_fini(data_t * data)256 static void blitter_busy_fini(data_t *data)
257 {
258 int i;
259
260 for (i = 0; i < NUM_BUSY_BUFFERS; i++) {
261 drm_intel_bo_unreference(data->blitter.srcs[i]);
262 drm_intel_bo_unreference(data->blitter.dsts[i]);
263 }
264
265 free(data->blitter.srcs);
266 free(data->blitter.dsts);
267 data->blitter.srcs = NULL;
268 data->blitter.dsts = NULL;
269 }
270
blitter_copy(data_t * data,drm_intel_bo * src,drm_intel_bo * dst)271 static void blitter_copy(data_t *data, drm_intel_bo *src, drm_intel_bo *dst)
272 {
273 intel_copy_bo(data->batch, dst, src, WIDTH*HEIGHT*4);
274 }
275
276 struct ring_ops {
277 void (*busy)(data_t *data);
278 void (*busy_fini)(data_t *data);
279 void (*copy)(data_t *data, drm_intel_bo *src, drm_intel_bo *dst);
280 } ops [] = {
281 {
282 .busy = render_busy,
283 .busy_fini = render_busy_fini,
284 .copy = render_copy,
285 },
286 {
287 .busy = blitter_busy,
288 .busy_fini = blitter_busy_fini,
289 .copy = blitter_copy,
290 },
291 };
292
run_test(data_t * data,enum ring r1,enum ring r2,enum test test)293 static void run_test(data_t *data, enum ring r1, enum ring r2, enum test test)
294 {
295 struct ring_ops *r1_ops = &ops[r1];
296 struct ring_ops *r2_ops = &ops[r2];
297 drm_intel_bo *a, *b, *c;
298
299 a = bo_create(data, WIDTH, HEIGHT, 0xa);
300 b = bo_create(data, WIDTH, HEIGHT, 0xb);
301 c = bo_create(data, WIDTH, HEIGHT, 0xc);
302
303 r1_ops->busy(data);
304 r1_ops->copy(data, a, b);
305
306 switch (test) {
307 case TEST_WRITE_READ:
308 r2_ops->copy(data, b, c);
309 bo_check(data, c, 0xa);
310 break;
311 case TEST_READ_WRITE:
312 r2_ops->copy(data, c, a);
313 bo_check(data, b, 0xa);
314 break;
315 case TEST_WRITE_WRITE:
316 r2_ops->copy(data, c, b);
317 bo_check(data, b, 0xc);
318 break;
319 default:
320 igt_fail(IGT_EXIT_FAILURE);
321 }
322
323 r1_ops->busy_fini(data);
324 }
325
326 igt_main
327 {
328 data_t data = {0, };
329 int i;
330 struct combination {
331 int r1, r2;
332 } ring_combinations [] = {
333 { RENDER, BLITTER },
334 { BLITTER, RENDER },
335 };
336
337 igt_fixture {
338 data.drm_fd = drm_open_driver_render(DRIVER_INTEL);
339 data.devid = intel_get_drm_devid(data.drm_fd);
340
341 data.n_buffers_load = 1000;
342
343 data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
344 igt_assert(data.bufmgr);
345 drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
346
347 data.render.copy = igt_get_render_copyfunc(data.devid);
348 igt_require_f(data.render.copy,
349 "no render-copy function\n");
350
351 data.batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
352 igt_assert(data.batch);
353 }
354
355 for (i = 0; i < ARRAY_SIZE(ring_combinations); i++) {
356 struct combination *c = &ring_combinations[i];
357
358 igt_subtest_f("sync-%s-%s-write-read",
359 ring_name(c->r1), ring_name(c->r2))
360 run_test(&data, c->r1, c->r2, TEST_WRITE_READ);
361
362 igt_subtest_f("sync-%s-%s-read-write",
363 ring_name(c->r1), ring_name(c->r2))
364 run_test(&data, c->r1, c->r2, TEST_READ_WRITE);
365 igt_subtest_f("sync-%s-%s-write-write",
366 ring_name(c->r1), ring_name(c->r2))
367 run_test(&data, c->r1, c->r2, TEST_WRITE_WRITE);
368 }
369
370 igt_fixture {
371 intel_batchbuffer_free(data.batch);
372 drm_intel_bufmgr_destroy(data.bufmgr);
373 close(data.drm_fd);
374 }
375 }
376