1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_MT8173_EMI_H 4 #define SOC_MEDIATEK_MT8173_EMI_H 5 6 #include <soc/dramc_common.h> 7 #include <soc/dramc_soc.h> 8 #include <types.h> 9 10 /* DDR type */ 11 enum ram_type { 12 TYPE_INVALID, 13 TYPE_DDR1, 14 TYPE_LPDDR2, 15 TYPE_LPDDR3, 16 TYPE_PCDDR3 17 }; 18 19 enum { 20 /* 21 * Vmem voltage adjustment: 22 * 1) HV: high voltage 23 * 2) NV: normal voltage 24 * 3) LV: low voltage 25 */ 26 Vmem_HV_LPDDR3 = 0x50, /* 1.300V */ 27 Vmem_NV_LPDDR3 = 0x44, /* 1.225V */ 28 Vmem_LV_LPDDR3 = 0x36 /* 1.138V */ 29 }; 30 31 enum { 32 /* 33 * Vcore voltage adjustment: 34 * 1) HHV: extra high voltage 35 * 2) HV: high voltage 36 * 3) NV: normal voltage 37 * 4) LV: low voltage 38 * 5) LLV: extra low voltage 39 */ 40 Vcore_HHV_LPPDR3 = 0x60, /* 1.300V */ 41 Vcore_HV_LPPDR3 = 0x48, /* 1.150V */ 42 Vcore_NV_LPPDR3 = 0x44, /* 1.125V */ 43 Vcore_LV_LPPDR3 = 0x34, /* 1.025V */ 44 Vcore_LLV_LPPDR3 = 0x25 /* 0.931V */ 45 }; 46 47 struct mt8173_calib_params { 48 u8 impedance_drvp; 49 u8 impedance_drvn; 50 u8 datlat_ucfirst; 51 s8 ca_train[CHANNEL_NUM][CATRAINING_NUM]; 52 s8 ca_train_center[CHANNEL_NUM]; 53 s8 wr_level[CHANNEL_NUM][DQS_NUMBER]; 54 u8 gating_win[CHANNEL_NUM][DUAL_RANKS][GW_PARAM_NUM]; 55 u32 rx_dqs_dly[CHANNEL_NUM]; 56 u32 rx_dq_dly[CHANNEL_NUM][DQS_BIT_NUMBER]; 57 }; 58 59 struct mt8173_timing_params { 60 u32 actim; 61 u32 actim1; 62 u32 actim05t; 63 u32 conf1; 64 u32 conf2; 65 u32 ddr2ctl; 66 u32 gddr3ctl1; 67 u32 misctl0; 68 u32 pd_ctrl; 69 u32 rkcfg; 70 u32 test2_4; 71 u32 test2_3; 72 }; 73 74 struct mt8173_emi_params { 75 u32 cona; 76 u32 conb; 77 u32 conc; 78 u32 cond; 79 u32 cone; 80 u32 conf; 81 u32 cong; 82 u32 conh; 83 u32 conm_1; 84 u32 conm_2; 85 u32 mdct_1; 86 u32 mdct_2; 87 u32 test0; 88 u32 test1; 89 u32 testb; 90 u32 testc; 91 u32 testd; 92 u32 arba; 93 u32 arbc; 94 u32 arbd; 95 u32 arbe; 96 u32 arbf; 97 u32 arbg; 98 u32 arbi; 99 u32 arbj; 100 u32 arbk; 101 u32 slct_1; 102 u32 slct_2; 103 u32 bmen; 104 }; 105 106 struct mt8173_mrs_params { 107 u32 mrs_1; 108 u32 mrs_2; 109 u32 mrs_3; 110 u32 mrs_10; 111 u32 mrs_11; 112 u32 mrs_63; 113 }; 114 115 enum { 116 /* CONA = 0x000 */ 117 CONA_DUAL_CH_EN = BIT(0), 118 CONA_32BIT_EN = BIT(1), 119 CONA_DUAL_RANK_EN = BIT(17), 120 COL_ADDR_BITS_SHIFT = 4, 121 COL_ADDR_BITS_MASK = 3 << COL_ADDR_BITS_SHIFT, 122 ROW_ADDR_BITS_SHIFT = 12, 123 ROW_ADDR_BITS_MASK = 3 << ROW_ADDR_BITS_SHIFT 124 }; 125 126 struct mt8173_sdram_params { 127 struct mt8173_calib_params calib_params; 128 struct mt8173_timing_params ac_timing; 129 struct mt8173_emi_params emi_set; 130 struct mt8173_mrs_params mrs_set; 131 enum ram_type type; 132 unsigned int dram_freq; 133 }; 134 135 int complex_mem_test(u8 *start, unsigned int len); 136 void mt_set_emi(const struct mt8173_sdram_params *sdram_params); 137 void mt_mem_init(const struct mt8173_sdram_params *sdram_params); 138 const struct mt8173_sdram_params *get_sdram_config(void); 139 size_t sdram_size(void); 140 #endif 141