1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #include <types.h> 3 #include <soc/addressmap.h> 4 #include <spi-generic.h> 5 6 #ifndef __SOC_QUALCOMM_QSPI_H__ 7 #define __SOC_QUALCOMM_QSPI_H__ 8 9 struct qcom_qspi_regs { 10 u32 mstr_cfg; 11 u32 ahb_mstr_cfg; 12 u32 reserve_0; 13 u32 mstr_int_en; 14 u32 mstr_int_sts; 15 u32 pio_xfer_ctrl; 16 u32 pio_xfer_cfg; 17 u32 pio_xfer_sts; 18 u32 pio_dataout_1byte; 19 u32 pio_dataout_4byte; 20 u32 rd_fifo_cfg; 21 u32 rd_fifo_sts; 22 u32 rd_fifo_rst; 23 u32 reserve_1[3]; 24 u32 next_dma_desc_addr; 25 u32 current_dma_desc_addr; 26 u32 current_mem_addr; 27 u32 hw_version; 28 u32 rd_fifo[16]; 29 }; 30 31 check_member(qcom_qspi_regs, rd_fifo, 0x50); 32 static struct qcom_qspi_regs * const qcom_qspi = (void *)QSPI_BASE; 33 34 // MSTR_CONFIG register 35 36 #define TX_DATA_OE_DELAY_SHIFT 24 37 #define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT) 38 #define TX_CS_N_DELAY_SHIFT 22 39 #define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT) 40 #define TX_CLK_DELAY_SHIFT 20 41 #define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT) 42 #define TX_DATA_DELAY_SHIFT 18 43 #define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT) 44 #define LPA_BASE_SHIFT 14 45 #define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT) 46 #define SBL_EN BIT(13) 47 #define CHIP_SELECT_NUM BIT(12) 48 #define SPI_MODE_SHIFT 10 49 #define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT) 50 #define BIG_ENDIAN_MODE BIT(9) 51 #define DMA_ENABLE BIT(8) 52 #define PIN_WPN BIT(7) 53 #define PIN_HOLDN BIT(6) 54 #define FB_CLK_EN BIT(4) 55 #define FULL_CYCLE_MODE BIT(3) 56 57 // MSTR_INT_ENABLE and MSTR_INT_STATUS register 58 59 #define DMA_CHAIN_DONE BIT(31) 60 #define TRANSACTION_DONE BIT(16) 61 #define WRITE_FIFO_OVERRUN BIT(11) 62 #define WRITE_FIFO_FULL BIT(10) 63 #define HRESP_FROM_NOC_ERR BIT(3) 64 #define RESP_FIFO_RDY BIT(2) 65 #define RESP_FIFO_NOT_EMPTY BIT(1) 66 #define RESP_FIFO_UNDERRUN BIT(0) 67 68 // PIO_TRANSFER_CONFIG register 69 70 #define TRANSFER_FRAGMENT BIT(8) 71 #define MULTI_IO_MODE_SHIFT 1 72 #define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT) 73 #define TRANSFER_DIRECTION BIT(0) 74 75 // PIO_TRANSFER_STATUS register 76 77 #define WR_FIFO_BYTES_SHIFT 16 78 #define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT) 79 80 // RD_FIFO_CONFIG register 81 82 #define CONTINUOUS_MODE BIT(0) 83 84 // RD_FIFO_STATUS register 85 86 #define FIFO_EMPTY BIT(11) 87 #define WR_CNTS_SHIFT 4 88 #define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT) 89 #define RDY_64BYTE BIT(3) 90 #define RDY_32BYTE BIT(2) 91 #define RDY_16BYTE BIT(1) 92 #define FIFO_RDY BIT(0) 93 94 // RD_FIFO_RESET register 95 96 #define RESET_FIFO BIT(0) 97 98 #define QSPI_MAX_PACKET_COUNT 0xFFC0 99 100 void quadspi_init(uint32_t hz); 101 int qspi_claim_bus(const struct spi_slave *slave); 102 int qspi_setup_bus(const struct spi_slave *slave); 103 void qspi_release_bus(const struct spi_slave *slave); 104 int qspi_xfer(const struct spi_slave *slave, const void *dout, 105 size_t out_bytes, void *din, size_t in_bytes); 106 int qspi_xfer_dual(const struct spi_slave *slave, const void *dout, 107 size_t out_bytes, void *din, size_t in_bytes); 108 #endif /* __SOC_QUALCOMM_QSPI_H__ */ 109