1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_NVIDIA_TEGRA_I2C_H__ 4 #define __SOC_NVIDIA_TEGRA_I2C_H__ 5 6 #include <stdint.h> 7 8 void i2c_init(unsigned int bus); 9 void tegra_software_i2c_init(unsigned int bus); 10 void tegra_software_i2c_disable(unsigned int bus); 11 12 enum { 13 /* Word 0 */ 14 IOHEADER_PROTHDRSZ_SHIFT = 28, 15 IOHEADER_PROTHDRSZ_MASK = 0x3 << IOHEADER_PROTHDRSZ_SHIFT, 16 IOHEADER_PKTID_SHIFT = 16, 17 IOHEADER_PKTID_MASK = 0xff << IOHEADER_PKTID_SHIFT, 18 IOHEADER_CONTROLLER_ID_SHIFT = 12, 19 IOHEADER_CONTROLLER_ID_MASK = 0xf << IOHEADER_CONTROLLER_ID_SHIFT, 20 IOHEADER_PROTOCOL_SHIFT = 4, 21 IOHEADER_PROTOCOL_MASK = 0xf << IOHEADER_PROTOCOL_SHIFT, 22 IOHEADER_PROTOCOL_I2C = 1 << IOHEADER_PROTOCOL_SHIFT, 23 IOHEADER_PKTTYPE_SHIFT = 0, 24 IOHEADER_PKTTYPE_MASK = 0x7 << IOHEADER_PKTTYPE_SHIFT, 25 IOHEADER_PKTTYPE_REQUEST = 0 << IOHEADER_PKTTYPE_SHIFT, 26 IOHEADER_PKTTYPE_RESPONSE = 1 << IOHEADER_PKTTYPE_SHIFT, 27 IOHEADER_PKTTYPE_INTERRUPT = 2 << IOHEADER_PKTTYPE_SHIFT, 28 IOHEADER_PKTTYPE_STOP = 3 << IOHEADER_PKTTYPE_SHIFT, 29 30 /* Word 1 */ 31 IOHEADER_PAYLOADSIZE_SHIFT = 0, 32 IOHEADER_PAYLOADSIZE_MASK = 0xfff << IOHEADER_PAYLOADSIZE_SHIFT 33 }; 34 35 enum { 36 IOHEADER_I2C_REQ_RESP_FREQ_MASK = 0x1 << 25, 37 IOHEADER_I2C_REQ_RESP_FREQ_END = 0 << 25, 38 IOHEADER_I2C_REQ_RESP_FREQ_EACH = 1 << 25, 39 IOHEADER_I2C_REQ_RESP_ENABLE = 0x1 << 24, 40 IOHEADER_I2C_REQ_HS_MODE = 0x1 << 22, 41 IOHEADER_I2C_REQ_CONTINUE_ON_NACK = 0x1 << 21, 42 IOHEADER_I2C_REQ_SEND_START_BYTE = 0x1 << 20, 43 IOHEADER_I2C_REQ_READ = 0x1 << 19, 44 IOHEADER_I2C_REQ_ADDR_MODE_MASK = 0x1 << 18, 45 IOHEADER_I2C_REQ_ADDR_MODE_7BIT = 0 << 18, 46 IOHEADER_I2C_REQ_ADDR_MODE_10BIT = 1 << 18, 47 IOHEADER_I2C_REQ_IE = 0x1 << 17, 48 IOHEADER_I2C_REQ_REPEAT_START = 0x1 << 16, 49 IOHEADER_I2C_REQ_STOP = 0x0 << 16, 50 IOHEADER_I2C_REQ_CONTINUE_XFER = 0x1 << 15, 51 IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT = 12, 52 IOHEADER_I2C_REQ_HS_MASTER_ADDR_MASK = 53 0x7 << IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT, 54 IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT = 0, 55 IOHEADER_I2C_REQ_SLAVE_ADDR_MASK = 56 0x3ff << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT 57 }; 58 59 enum { 60 I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT = 0x1 << 15, 61 I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12, 62 I2C_CNFG_DEBOUNCE_CNT_MASK = 0x7 << I2C_CNFG_DEBOUNCE_CNT_SHIFT, 63 I2C_CNFG_NEW_MASTER_FSM = 0x1 << 11, 64 I2C_CNFG_PACKET_MODE_EN = 0x1 << 10, 65 I2C_CNFG_SEND = 0x1 << 9, 66 I2C_CNFG_NOACK = 0x1 << 8, 67 I2C_CNFG_CMD2 = 0x1 << 7, 68 I2C_CNFG_CMD1 = 0x1 << 6, 69 I2C_CNFG_START = 0x1 << 5, 70 I2C_CNFG_SLV2_SHIFT = 4, 71 I2C_CNFG_SLV2_MASK = 0x1 << I2C_CNFG_SLV2_SHIFT, 72 I2C_CNFG_LENGTH_SHIFT = 1, 73 I2C_CNFG_LENGTH_MASK = 0x7 << I2C_CNFG_LENGTH_SHIFT, 74 I2C_CNFG_A_MOD = 0x1 << 0, 75 }; 76 77 enum { 78 I2C_PKT_STATUS_COMPLETE = 0x1 << 24, 79 I2C_PKT_STATUS_PKT_ID_SHIFT = 16, 80 I2C_PKT_STATUS_PKT_ID_MASK = 0xff << I2C_PKT_STATUS_PKT_ID_SHIFT, 81 I2C_PKT_STATUS_BYTENUM_SHIFT = 4, 82 I2C_PKT_STATUS_BYTENUM_MASK = 0xfff << I2C_PKT_STATUS_BYTENUM_SHIFT, 83 I2C_PKT_STATUS_NOACK_ADDR = 0x1 << 3, 84 I2C_PKT_STATUS_NOACK_DATA = 0x1 << 2, 85 I2C_PKT_STATUS_ARB_LOST = 0x1 << 1, 86 I2C_PKT_STATUS_BUSY = 0x1 << 0 87 }; 88 89 enum { 90 I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4, 91 I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK = 92 0xf << I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT, 93 I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0, 94 I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK = 95 0xf << I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT 96 }; 97 98 enum { 99 I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT = 16, 100 I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_MASK = 101 0xff << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT, 102 I2C_BUS_CLEAR_CONFIG_BC_STOP_COND_STOP = 0x1 << 2, 103 I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE = 0x1 << 1, 104 I2C_BUS_CLEAR_CONFIG_BC_ENABLE = 0x1 << 0, 105 106 I2C_BUS_CLEAR_STATUS_CLEARED = 0x1 << 0, 107 108 I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE = 0x1 << 0 109 }; 110 111 struct tegra_i2c_bus_info { 112 void *base; 113 uint32_t reset_bit; 114 void (*reset_func)(u32 bit); 115 }; 116 117 extern struct tegra_i2c_bus_info tegra_i2c_info[]; 118 119 struct tegra_i2c_regs { 120 uint32_t cnfg; 121 uint32_t cmd_addr0; 122 uint32_t cmd_addr1; 123 uint32_t cmd_data1; 124 uint32_t cmd_data2; 125 uint8_t _rsv0[8]; 126 uint32_t status; 127 uint32_t sl_cnfg; 128 uint32_t sl_rcvd; 129 uint32_t sl_status; 130 uint32_t sl_addr1; 131 uint32_t sl_addr2; 132 uint32_t tlow_sext; 133 uint8_t _rsv1[4]; 134 uint32_t sl_delay_count; 135 uint32_t sl_int_mask; 136 uint32_t sl_int_source; 137 uint32_t sl_int_set; 138 uint8_t _rsv2[4]; 139 uint32_t tx_packet_fifo; 140 uint32_t rx_fifo; 141 uint32_t packet_transfer_status; 142 uint32_t fifo_control; 143 uint32_t fifo_status; 144 uint32_t interrupt_mask; 145 uint32_t interrupt_status; 146 uint32_t clk_divisor; 147 uint32_t interrupt_source; 148 uint32_t interrupt_set; 149 uint32_t slv_tx_packet_fifo; 150 uint32_t slv_rx_fifo; 151 uint32_t slv_packet_status; 152 uint32_t bus_clear_config; 153 uint32_t bus_clear_status; 154 uint32_t config_load; 155 }; 156 check_member(tegra_i2c_regs, config_load, 0x8C); 157 158 extern const unsigned int num_i2c_buses; 159 160 #endif /* __SOC_NVIDIA_TEGRA_I2C_H__ */ 161