1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 #include <emi_mpu_mt.h>
4 #include <mt8195.h>
5
6 #include <emi_hw.h>
7 #include <emi.h>
8
9 #define EMI_APB_BASE EMI_BASE
10 #define EMI_CHANNEL_APB_BASE CHN0_EMI_BASE
11
12
13 #if DRAM_AUXADC_CONFIG
14 #include <mtk_auxadc_sw.h>
15 #endif
16
17 #ifdef LAST_EMI
18 static LAST_EMI_INFO_T* last_emi_info_ptr;
19 #endif
20
mt_emi_sync_read(unsigned long long addr)21 static inline unsigned int mt_emi_sync_read(unsigned long long addr)
22 {
23 dsb();
24 return *((volatile unsigned int *)addr);
25 }
26
27 #define mt_emi_sync_write(addr, value) \
28 do { \
29 *((volatile unsigned int *)(addr)) = value; \
30 dsb(); \
31 } while (0)
32
33 #define mt_emi_sync_write_or(addr, or_value) \
34 do { \
35 mt_emi_sync_write(addr, \
36 mt_emi_sync_read(addr) | or_value); \
37 } while (0)
38
emi_cen_config(void)39 static void emi_cen_config(void) {
40
41 #ifndef ONE_CH
42 #ifdef RANK_512MB
43 mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a154);
44 #else
45 #ifdef RANK_1GB
46 mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f154);
47 #else
48 #ifdef RANK_2GB
49 mt_emi_sync_write(EMI_APB_BASE+0x00000000,0x00530154);
50 #endif
51 #endif
52 #endif
53 #else
54 #ifdef RANK_512MB
55 mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a054);
56 #else
57 mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f054);
58 #endif
59 #endif
60
61
62 mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33);
63 mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025);
64 mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027);
65 mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d);
66 mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33);
67 mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025);
68 mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027);
69 mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d);
70 mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c);
71 mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21);
72 mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23);
73 mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228);
74 mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28);
75 mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20);
76 mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24);
77 mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229);
78 mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28);
79 mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20);
80 mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24);
81 mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229);
82 mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28);
83 mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20);
84 mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24);
85 mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229);
86 mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28);
87 mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322);
88 mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a);
89 mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f);
90 mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28);
91 mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322);
92 mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a);
93 mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f);
94
95 mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57);
96 mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39);
97 mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e);
98 mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a);
99 mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241);
100 mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835);
101 mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542);
102 mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835);
103 mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542);
104 mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835);
105 mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542);
106 mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835);
107 mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034);
108 mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39);
109 mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034);
110 mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39);
111
112
113 mt_emi_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
114 mt_emi_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
115 mt_emi_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
116 #ifdef RANK_2GB
117 mt_emi_sync_write(EMI_APB_BASE+0x00000038,0x000000b3);
118 #else
119 mt_emi_sync_write(EMI_APB_BASE+0x00000038,0x00000083);
120 #endif
121 mt_emi_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
122 mt_emi_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
123 mt_emi_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
124 mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff);
125 mt_emi_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
126 mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f);
127 mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f);
128 mt_emi_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
129 mt_emi_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
130 mt_emi_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
131 mt_emi_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
132 mt_emi_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
133 mt_emi_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
134 mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037);
135 mt_emi_sync_write(EMI_APB_BASE+0x000000f0,0x384a0014);
136 mt_emi_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
137 mt_emi_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
138 mt_emi_sync_write(EMI_APB_BASE+0x00000108,0x10107044);
139 mt_emi_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
140 mt_emi_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
141 mt_emi_sync_write(EMI_APB_BASE+0x00000120,0x10106048);
142 mt_emi_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
143 mt_emi_sync_write(EMI_APB_BASE+0x00000130,0x83837044);
144 mt_emi_sync_write(EMI_APB_BASE+0x00000138,0x83837044);
145 mt_emi_sync_write(EMI_APB_BASE+0x00000140,0x00007108);
146 mt_emi_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
147 mt_emi_sync_write(EMI_APB_BASE+0x00000150,0x090a0000);
148 mt_emi_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
149 mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001);
150 mt_emi_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
151 mt_emi_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
152 mt_emi_sync_write(EMI_APB_BASE+0x00000820,0x24240101);
153 mt_emi_sync_write(EMI_APB_BASE+0x00000824,0x01012424);
154 mt_emi_sync_write(EMI_APB_BASE+0x00000828,0x50500101);
155 mt_emi_sync_write(EMI_APB_BASE+0x0000082c,0x01015050);
156 mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30);
157 mt_emi_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
158 mt_emi_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
159 mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c);
160 mt_emi_sync_write(EMI_APB_BASE+0x00000840,0x000003e8);
161 mt_emi_sync_write(EMI_APB_BASE+0x00000844,0x0000036b);
162 mt_emi_sync_write(EMI_APB_BASE+0x00000848,0x00000290);
163 mt_emi_sync_write(EMI_APB_BASE+0x0000084c,0x00000200);
164 mt_emi_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
165 mt_emi_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
166 mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff);
167 mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785);
168 mt_emi_sync_write(EMI_APB_BASE+0x00000874,0x000001b5);
169 mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000);
170 mt_emi_sync_write(EMI_APB_BASE+0x0000087c,0x0255250d);
171 mt_emi_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
172 mt_emi_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
173 mt_emi_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
174 mt_emi_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
175 mt_emi_sync_write(EMI_APB_BASE+0x000008c0,0x0000014b);
176 mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000);
177 mt_emi_sync_write(EMI_APB_BASE+0x000008c8,0x00000185);
178 mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000);
179 mt_emi_sync_write(EMI_APB_BASE+0x000008d0,0x00000185);
180 mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000);
181 mt_emi_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
182 mt_emi_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
183 mt_emi_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
184 mt_emi_sync_write(EMI_APB_BASE+0x00000920,0xffffffff);
185 mt_emi_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff);
186 mt_emi_sync_write(EMI_APB_BASE+0x00000930,0xffffffff);
187 mt_emi_sync_write(EMI_APB_BASE+0x00000934,0xffffffff);
188 mt_emi_sync_write(EMI_APB_BASE+0x00000938,0xffffffff);
189 mt_emi_sync_write(EMI_APB_BASE+0x000009f0,0x41547082);
190 mt_emi_sync_write(EMI_APB_BASE+0x000009f4,0x38382a38);
191 mt_emi_sync_write(EMI_APB_BASE+0x000009f8,0x000001d4);
192 mt_emi_sync_write(EMI_APB_BASE+0x000009fc,0x00000190);
193 mt_emi_sync_write(EMI_APB_BASE+0x00000b00,0x0000012c);
194 mt_emi_sync_write(EMI_APB_BASE+0x00000b04,0x000000ed);
195 mt_emi_sync_write(EMI_APB_BASE+0x00000b08,0x000000c8);
196 mt_emi_sync_write(EMI_APB_BASE+0x00000b0c,0x00000096);
197 mt_emi_sync_write(EMI_APB_BASE+0x00000b10,0x000000c8);
198 mt_emi_sync_write(EMI_APB_BASE+0x00000b14,0x000000c8);
199 mt_emi_sync_write(EMI_APB_BASE+0x00000b28,0x26304048);
200 mt_emi_sync_write(EMI_APB_BASE+0x00000b2c,0x20201820);
201
202 mt_emi_sync_write(EMI_APB_BASE+0x00000b60,0x181e282f);
203 mt_emi_sync_write(EMI_APB_BASE+0x00000b64,0x14140f18);
204 mt_emi_sync_write(EMI_APB_BASE+0x00000b98,0x7496c8ea);
205 mt_emi_sync_write(EMI_APB_BASE+0x00000b9c,0x64644b64);
206 mt_emi_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101);
207 mt_emi_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101);
208 mt_emi_sync_write(EMI_APB_BASE+0x00000c08,0x7496c8ea);
209 mt_emi_sync_write(EMI_APB_BASE+0x00000c0c,0x64644b64);
210 mt_emi_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
211 mt_emi_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
212 mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025);
213 mt_emi_sync_write(EMI_APB_BASE+0x00000c80,0x000003e8);
214 mt_emi_sync_write(EMI_APB_BASE+0x00000c84,0x0000036b);
215 mt_emi_sync_write(EMI_APB_BASE+0x00000c88,0x00000290);
216 mt_emi_sync_write(EMI_APB_BASE+0x00000c8c,0x00000200);
217 mt_emi_sync_write(EMI_APB_BASE+0x00000c90,0x000001b5);
218 mt_emi_sync_write(EMI_APB_BASE+0x00000c94,0x0000014b);
219 mt_emi_sync_write(EMI_APB_BASE+0x00000c98,0x00000185);
220 mt_emi_sync_write(EMI_APB_BASE+0x00000c9c,0x00000185);
221 mt_emi_sync_write(EMI_APB_BASE+0x00000cb0,0x52698ca0);
222 mt_emi_sync_write(EMI_APB_BASE+0x00000cb4,0x46463546);
223 mt_emi_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
224 mt_emi_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
225
226 mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009);
227 mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000);
228 mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000);
229 mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808);
230 mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028);
231 mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000);
232 mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000);
233 mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808);
234 mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080);
235 mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000);
236 mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008);
237 mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800);
238 mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000);
239 mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000);
240 mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000);
241 mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000);
242 mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000);
243 mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800);
244 mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000);
245 mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030);
246 mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000);
247 mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000);
248 mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000);
249 mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000);
250 mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000);
251 mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000);
252 mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040);
253 mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000);
254 mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000);
255 mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404);
256 mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000);
257 mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000);
258 mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000);
259 mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000);
260 mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010);
261 mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000);
262 mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000);
263 mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009);
264 mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080);
265 mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11);
266 mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7);
267 mt_emi_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
268 mt_emi_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
269 mt_emi_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
270 mt_emi_sync_write(EMI_APB_BASE+0x00000e14,0x00400166);
271 mt_emi_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff);
272 mt_emi_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff);
273 mt_emi_sync_write(EMI_APB_BASE+0x00000e24,0x00000266);
274 mt_emi_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff);
275 mt_emi_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff);
276 mt_emi_sync_write(EMI_APB_BASE+0x00000e34,0x00400266);
277 mt_emi_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
278 mt_emi_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
279
280
281 mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff);
282 mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85);
283 mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff);
284
285 mt_emi_sync_write(EMI_APB_BASE+0x0000034c,0xffffffff);
286 mt_emi_sync_write(EMI_APB_BASE+0x00000354,0x001ffc85);
287 mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff);
288
289 mt_emi_sync_write(EMI_APB_BASE+0x00000394,0xffffffff);
290 mt_emi_sync_write(EMI_APB_BASE+0x0000039c,0x001ffc85);
291 mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff);
292
293 mt_emi_sync_write(EMI_APB_BASE+0x000003d8,0xffffffff);
294 mt_emi_sync_write(EMI_APB_BASE+0x000003dc,0x001ffc85);
295 mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff);
296
297 mt_emi_sync_write(EMI_APB_BASE+0x000003fc,0xffffffff);
298 mt_emi_sync_write(EMI_APB_BASE+0x0000040c,0x001ffc85);
299 mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff);
300
301 mt_emi_sync_write(EMI_APB_BASE+0x0000044c,0xffffffff);
302 mt_emi_sync_write(EMI_APB_BASE+0x00000454,0x001ffc85);
303 mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff);
304
305 mt_emi_sync_write(EMI_APB_BASE+0x0000049c,0xffffffff);
306 mt_emi_sync_write(EMI_APB_BASE+0x000004a4,0x001ffc85);
307 mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff);
308
309 mt_emi_sync_write(EMI_APB_BASE+0x0000050c,0xffffffff);
310 mt_emi_sync_write(EMI_APB_BASE+0x00000514,0x001ffc85);
311 mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff);
312
313
314 mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000);
315
316
317 mt_emi_sync_write(EMI_APB_BASE+0x00000628,0x60606060);
318 mt_emi_sync_write(EMI_APB_BASE+0x0000062c,0x60606060);
319
320
321 mt_emi_sync_write(EMI_APB_BASE+0x00000050,0x00000000);
322
323
324 mt_emi_sync_write(EMI_APB_BASE+0x0000061c,0x08ffbbff);
325 mt_emi_sync_write(EMI_APB_BASE+0x00000624,0xffff5b3c);
326 mt_emi_sync_write(EMI_APB_BASE+0x00000774,0xffff00ff);
327 mt_emi_sync_write(EMI_APB_BASE+0x0000077c,0x00ffffff);
328 mt_emi_sync_write(EMI_APB_BASE+0x00000784,0xffff00ff);
329 mt_emi_sync_write(EMI_APB_BASE+0x0000078c,0x00ffffff);
330 mt_emi_sync_write(EMI_APB_BASE+0x00000958,0x00000000);
331
332
333 //mt_emi_sync_write(EMI_APB_BASE+0x000007a4,0xC0000000);
334 }
335
emi_chn_config(void)336 static void emi_chn_config(void) {
337
338 #ifdef RANK_512MB
339 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400a051);
340 #else
341 #ifdef RANK_1GB
342 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400f051);
343 #else
344 #ifdef RANK_2GB
345 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400005D);
346 #endif
347 #endif
348 #endif
349 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048);
350 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004);
351 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03);
352 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17);
353 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137);
354 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002);
355 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000);
356 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff);
357 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003111);
358 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188);
359 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188);
360 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x3719595e);
361 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x2719595e);
362 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3ff79);
363 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3ff79);
364 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868);
365 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0xa7414222);
366 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801);
367 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000);
368 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c802f);
369 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e);
370 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e);
371 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000003fc,0x00000000);
372 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff);
373 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa6168ff);
374 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa516cff);
375 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000408,0xaa0140ff);
376 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000040c,0x9f658633);
377 }
378
emi_sw_setting(void)379 static void emi_sw_setting(void)
380 {
381 //int emi_isu;
382 int emi_dcm;
383 //char *str;
384
385 enable_infra_emi_broadcast(1);
386
387
388 *((volatile unsigned int *) EMI_CONH) = *((volatile unsigned int *) EMI_CONH) | 0xC0;
389
390
391 *((volatile unsigned int *) EMI_BWCT0) = 0x05000305;
392 *((volatile unsigned int *) EMI_BWCT0_6TH) = 0x08FF0705;
393 *((volatile unsigned int *) EMI_BWCT0_3RD) = 0x0DFF0A05;
394 *((volatile unsigned int *) EMI_BWCT0_4TH) = 0x7FFF0F05;
395
396 enable_infra_emi_broadcast(0);
397
398 #ifdef LAST_EMI
399 last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
400 if (last_emi_info_ptr->isu_magic != LAST_EMI_MAGIC_PATTERN) {
401 last_emi_info_ptr->isu_magic = LAST_EMI_MAGIC_PATTERN;
402 last_emi_info_ptr->isu_version = 0xFFFFFFFF;
403 last_emi_info_ptr->isu_dram_type = 0;
404 last_emi_info_ptr->isu_diff_us = 0;
405 last_emi_info_ptr->os_flag_sspm = 0;
406 last_emi_info_ptr->os_flag_ap = 0;
407 }
408
409 str = dconfig_getenv("emi_isu");
410 emi_isu = (str) ? atoi(str) : 0;
411 emi_log("[EMI DOE] emi_isu %d\n", emi_isu);
412 if (emi_isu == 1)
413 last_emi_info_ptr->isu_ctrl = 0xDECDDECD;
414 else if (emi_isu == 2)
415 last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0;
416 else {
417 #if CFG_LAST_EMI_BW_DUMP
418 last_emi_info_ptr->isu_ctrl = 0xDECDDECD;
419 #else
420 last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0;
421 #endif
422 }
423 #endif
424
425
426 *((volatile unsigned int *)0x10219858) |= 0x1 << 11;
427
428
429 emi_dcm = 0;
430 emi_log("[EMI DOE] emi_dcm %d\n", emi_dcm);
431 if (emi_dcm == 1) {
432 *((volatile unsigned int *)EMI_CONM) &= ~0xFF000000;
433 *((volatile unsigned int *)EMI_CONN) &= ~0xFF000000;
434 } else if (emi_dcm == 2) {
435 *((volatile unsigned int *)EMI_CONM) |= 0xFF000000;
436 *((volatile unsigned int *)EMI_CONN) |= 0xFF000000;
437 }
438
439 dsb();
440 }
441
emi_init(void)442 void emi_init(void)
443 {
444 //unsigned int emi_mpu_slverr = 0;
445 //unsigned int domain = 0;
446 //char *str;
447
448 mt_emi_sync_write(EMI_BASE+0x000007a4, 0xC0000000);
449 #ifdef SUB_EMI_BASE
450 mt_emi_sync_write(SUB_EMI_BASE+0x000007a4, 0xD0000000);
451 #endif
452
453 enable_infra_emi_broadcast(1);
454
455 emi_cen_config();
456 emi_chn_config();
457
458 enable_infra_emi_broadcast(0);
459 }
460
emi_init2(void)461 void emi_init2(void)
462 {
463 unsigned int emi_temp_data;
464
465 enable_infra_emi_broadcast(1);
466
467 mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001);
468 mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400);
469
470 #ifdef REAL_CHIP_EMI_GOLDEN_SETTING
471
472
473 mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010);
474
475
476 emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x000001b0);
477 emi_temp_data = emi_temp_data & ~(0x1);
478 mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data);
479
480 emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x00000000);
481 emi_temp_data = emi_temp_data & 0x1;
482 mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data);
483
484 enable_infra_emi_broadcast(0);
485
486
487 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x100, 0xFFFFFFFF);
488 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x104, 0xFFFFFFFF);
489 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x108, 0xFFFFFFFF);
490 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x10C, 0xFFFFFFFF);
491 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x110, 0x06000003);
492 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x114, 0x40000000);
493 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x118, 0xC0201800);
494 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x11C, 0x00000000);
495 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x120, 0x180003FC);
496 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x124, 0x80000000);
497 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x128, 0x06000001);
498 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x12C, 0x00000600);
499 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x130, 0x20003C00);
500 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x134, 0x00000000);
501 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x138, 0x00080000);
502 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x13C, 0x00000000);
503 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x140, 0x60003C00);
504 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x144, 0x10000006);
505 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x148, 0x00090000);
506 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x14C, 0x02100800);
507 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x150, 0x80FF8000);
508 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x154, 0x00000001);
509 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x158, 0x3000E018);
510 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x15C, 0x0106019F);
511 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x160, 0x00000000);
512 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x164, 0x011FFFF8);
513 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x168, 0x084007E0);
514 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x16C, 0x00600006);
515 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x170, 0x00000000);
516 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x174, 0x00000000);
517 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x178, 0x000001A0);
518 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x17C, 0x1C800000);
519
520 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x020, 0xFFFFFFFF);
521 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x024, 0xFFFFFFFF);
522 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x210, 0x00000000);
523 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x214, 0x06007FE0);
524 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x218, 0x0000003F);
525 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x21C, 0x0003000C);
526 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x220, 0x00000380);
527 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x224, 0x00000000);
528 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x228, 0x00C08000);
529 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x22C, 0x01000000);
530 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x230, 0xCF3F3000);
531 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x234, 0x30008013);
532 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x238, 0x00000000);
533 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x23C, 0x00000000);
534
535 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x0018002F);
536 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0x40000000);
537 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x030, 0x00000044);
538 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x034, 0x00000000);
539
540 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x028, 0x000D007F);
541 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x02C, 0x40000000);
542 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x030, 0x00000044);
543 mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x034, 0x00000000);
544
545 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x038, 0xA00001FF);
546
547 mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000);
548
549 #ifdef EMI_MP_SETTING
550
551 mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000);
552
553
554 emi_temp_data = mt_emi_sync_read(0x40000000);
555 mt_emi_sync_write(0x40000000, emi_temp_data);
556 emi_temp_data = mt_emi_sync_read(0x40000100);
557 mt_emi_sync_write(0x40000100, emi_temp_data);
558 emi_temp_data = mt_emi_sync_read(0x40000200);
559 mt_emi_sync_write(0x40000200, emi_temp_data);
560 emi_temp_data = mt_emi_sync_read(0x40000300);
561 mt_emi_sync_write(0x40000300, emi_temp_data);
562
563 mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000004);
564
565
566 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021);
567 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021);
568
569
570 emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
571 emi_temp_data = emi_temp_data & 0xf;
572 mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
573
574
575 mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000);
576 mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000010);
577 #else
578 // MP_dsim_v02 test (from v01) - all fr
579 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x003F0000);
580 //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0xA0000000);
581 #endif
582
583 #endif
584
585
586
587 if (channel_num_auxadc == CHANNEL_FOURTH)
588 {
589 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021);
590 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021);
591 }
592 else
593 {
594 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000007);
595 mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007);
596 }
597
598
599
600 emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
601 emi_temp_data = emi_temp_data & 0xf;
602
603 enable_infra_emi_broadcast(1);
604 mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
605
606 mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040);
607 enable_infra_emi_broadcast(0);
608
609 emi_sw_setting();
610 }
611
get_row_width_by_emi(unsigned int rank)612 int get_row_width_by_emi(unsigned int rank)
613 {
614 unsigned int emi_cona;
615 unsigned int shift_row, shift_ext;
616 int row_width;
617
618 if (rank == 0) {
619 shift_row = 12;
620 shift_ext = 22;
621 } else if (rank == 1) {
622 shift_row = 14;
623 shift_ext = 23;
624 } else
625 return -1;
626
627 emi_cona = mt_emi_sync_read(EMI_CONA);
628 row_width =
629 ((emi_cona >> shift_row) & 0x3) |
630 ((emi_cona >> shift_ext) & 0x4);
631
632 return (row_width + 13);
633 }
634
get_channel_nr_by_emi(void)635 int get_channel_nr_by_emi(void)
636 {
637 int channel_nr;
638
639 channel_nr = 0x1 << ((mt_emi_sync_read(EMI_CONA) >> 8) & 0x3);
640
641 #ifdef SUB_EMI_BASE
642 channel_nr *= 2;
643 #endif
644 #if DRAM_AUXADC_CONFIG
645 U32 ret = 0, voltage = 0;
646 ret = iio_read_channel_processed(5, &voltage);
647 if (ret == 0)
648 if (voltage < 700)
649 channel_nr = CHANNEL_FOURTH;
650 else
651 channel_nr = CHANNEL_DUAL;
652 else
653 emi_log("Error! Read AUXADC value fail\n");
654 #endif
655
656 return channel_nr;
657 }
658
get_rank_nr_by_emi(void)659 int get_rank_nr_by_emi(void)
660 {
661 unsigned int cen_emi_cona = mt_emi_sync_read(EMI_CONA);
662
663 if (cen_emi_cona & (0x3 << 16))
664 return 2;
665 else
666 return 1;
667 }
668
669 _Static_assert(DRAMC_MAX_RK > 1, "rank number is violated");
get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK])670 void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK])
671 {
672 unsigned int quad_ch_ratio;
673 unsigned long long ch0_rank0_size, ch0_rank1_size;
674 unsigned long long ch1_rank0_size, ch1_rank1_size;
675 unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH);
676
677 dram_rank_size[0] = 0;
678 dram_rank_size[1] = 0;
679
680 ch0_rank0_size = (cen_emi_conh >> 16) & 0xF;
681 ch0_rank1_size = (cen_emi_conh >> 20) & 0xF;
682 ch1_rank0_size = (cen_emi_conh >> 24) & 0xF;
683 ch1_rank1_size = (cen_emi_conh >> 28) & 0xF;
684
685 quad_ch_ratio = (get_channel_nr_by_emi() == 4)? 2 : 1;
686
687 ch0_rank0_size = (ch0_rank0_size * quad_ch_ratio) << 28;
688 ch0_rank1_size = (ch0_rank1_size * quad_ch_ratio) << 28;
689 ch1_rank0_size = (ch1_rank0_size * quad_ch_ratio) << 28;
690 ch1_rank1_size = (ch1_rank1_size * quad_ch_ratio) << 28;
691
692 if(ch0_rank0_size == 0) {
693 emi_log("[EMI] undefined CONH for CH0 RANK0\n");
694 ASSERT(0);
695 }
696 dram_rank_size[0] += ch0_rank0_size;
697
698 if (get_rank_nr_by_emi() > 1) {
699 if(ch0_rank1_size == 0) {
700 emi_log("[EMI] undefined CONH for CH0 RANK1\n");
701 ASSERT(0);
702 }
703 dram_rank_size[1] += ch0_rank1_size;
704 }
705
706 if(get_channel_nr_by_emi() > 1) {
707 if(ch1_rank0_size == 0) {
708 emi_log("[EMI] undefined CONH for CH1 RANK0\n");
709 ASSERT(0);
710 }
711 dram_rank_size[0] += ch1_rank0_size;
712
713 if (get_rank_nr_by_emi() > 1) {
714 if(ch1_rank1_size == 0) {
715 emi_log("[EMI] undefined CONH for CH1 RANK1\n");
716 ASSERT(0);
717 }
718 dram_rank_size[1] += ch1_rank1_size;
719 }
720 }
721
722 emi_log("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n",
723 dram_rank_size[0], dram_rank_size[1]);
724 }
725
set_cen_emi_cona(unsigned int cona_val)726 void set_cen_emi_cona(unsigned int cona_val)
727 {
728 mt_emi_sync_write(EMI_CONA, cona_val);
729 }
730
set_cen_emi_conf(unsigned int conf_val)731 void set_cen_emi_conf(unsigned int conf_val)
732 {
733 mt_emi_sync_write(EMI_CONF, conf_val);
734 }
735
set_cen_emi_conh(unsigned int conh_val)736 void set_cen_emi_conh(unsigned int conh_val)
737 {
738 mt_emi_sync_write(EMI_CONH, conh_val);
739 }
740
set_chn_emi_cona(unsigned int cona_val)741 void set_chn_emi_cona(unsigned int cona_val)
742 {
743 mt_emi_sync_write(CHN_EMI_CONA(CHN0_EMI_BASE), cona_val);
744 mt_emi_sync_write(CHN_EMI_CONA(CHN1_EMI_BASE), cona_val);
745 }
746
set_chn_emi_conc(unsigned int conc_val)747 void set_chn_emi_conc(unsigned int conc_val)
748 {
749 mt_emi_sync_write(CHN_EMI_CONC(CHN0_EMI_BASE), conc_val);
750 mt_emi_sync_write(CHN_EMI_CONC(CHN1_EMI_BASE), conc_val);
751 }
752
enable_infra_emi_broadcast(unsigned int enable)753 void enable_infra_emi_broadcast(unsigned int enable)
754 {
755 if (enable)
756 mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00027f7f);
757 else
758 mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00000000);
759 }
760
get_cen_emi_cona(void)761 unsigned int get_cen_emi_cona(void)
762 {
763 return mt_emi_sync_read(EMI_CONA);
764 }
765
766
get_chn_emi_cona(void)767 unsigned int get_chn_emi_cona(void)
768 {
769 unsigned int ch0_emi_cona;
770
771 ch0_emi_cona = mt_emi_sync_read(CHN0_EMI_BASE);
772
773 return ch0_emi_cona;
774 }
775
phy_addr_to_dram_addr(dram_addr_t * dram_addr,unsigned long long phy_addr)776 void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr)
777 {
778 unsigned int cen_emi_cona, cen_emi_conf;
779 unsigned long long rank_size[DRAMC_MAX_RK];
780 unsigned int channel_num, rank_num;
781 unsigned int bit_scramble, bit_xor, bit_shift, channel_pos, channel_width;
782 unsigned int temp;
783 unsigned int index;
784
785 cen_emi_cona = mt_emi_sync_read(EMI_CONA);
786 cen_emi_conf = mt_emi_sync_read(EMI_CONF) >> 8;
787 get_rank_size_by_emi(rank_size);
788 rank_num = (unsigned int) get_rank_nr_by_emi();
789 channel_num = (unsigned int) get_channel_nr_by_emi();
790
791 phy_addr -= 0x40000000;
792 for (index = 0; index < rank_num; index++) {
793 if (phy_addr >= rank_size[index])
794 phy_addr -= rank_size[index];
795 else
796 break;
797 }
798
799 for (bit_scramble = 11; bit_scramble < 17; bit_scramble++) {
800 bit_xor = (cen_emi_conf >> (4 * (bit_scramble - 11))) & 0xf;
801 bit_xor &= phy_addr >> 16;
802 for (bit_shift = 0; bit_shift < 4; bit_shift++)
803 phy_addr ^= ((bit_xor>>bit_shift)&0x1) << bit_scramble;
804 }
805
806 if (channel_num > 1) {
807 channel_pos = ((cen_emi_cona >> 2) & 0x3) + 7;
808
809 for (channel_width = bit_shift = 0; bit_shift < 4; bit_shift++) {
810 if ((unsigned int)(1 << bit_shift) >= channel_num)
811 break;
812 channel_width++;
813 }
814
815 switch (channel_width) {
816 case 2:
817 dram_addr->addr = ((phy_addr & ~(((0x1 << 2) << channel_pos) - 1)) >> 2);
818 break;
819 default:
820 dram_addr->addr = ((phy_addr & ~(((0x1 << 1) << channel_pos) - 1)) >> 1);
821 break;
822 }
823 dram_addr->addr |= (phy_addr & ((0x1 << channel_pos) - 1));
824 }
825
826 temp = dram_addr->addr >> 1;
827 switch ((cen_emi_cona >> 4) & 0x3) {
828 case 0:
829 dram_addr->col = temp & 0x1FF;
830 temp = temp >> 9;
831 break;
832 case 1:
833 dram_addr->col = temp & 0x3FF;
834 temp = temp >> 10;
835 break;
836 case 2:
837 default:
838 dram_addr->col = temp & 0x7FF;
839 temp = temp >> 11;
840 break;
841 }
842 dram_addr->bk = temp & 0x7;
843 temp = temp >> 3;
844
845 dram_addr->row = temp;
846
847 emi_log("[EMI] ch%d, rk%d, dram addr: %x\n", dram_addr->ch, dram_addr->rk, dram_addr->addr);
848 emi_log("[EMI] bk%x, row%x, col%x\n", dram_addr->bk, dram_addr->row, dram_addr->col);
849 }
850
851 static unsigned int cen_emi_conh_backup = 0;
852 static unsigned int chn_emi_cona_backup = 0;
853
854
set_emi_before_rank1_mem_test(void)855 unsigned int set_emi_before_rank1_mem_test(void)
856 {
857 cen_emi_conh_backup = mt_emi_sync_read(EMI_CONH);
858 chn_emi_cona_backup = get_chn_emi_cona();
859
860 enable_infra_emi_broadcast(1);
861 if (get_rank_nr_by_emi() == 2) {
862
863 mt_emi_sync_write(EMI_CONH,
864 (cen_emi_conh_backup & 0x0000ffff) | 0x22220000);
865 set_chn_emi_cona(
866 (chn_emi_cona_backup & 0xff00ffff) | 0x00220000);
867 } else {
868
869 mt_emi_sync_write(EMI_CONH,
870 (cen_emi_conh_backup & 0x0000ffff) | 0x44440000);
871 set_chn_emi_cona(
872 (chn_emi_cona_backup & 0xff00ffff) | 0x00440000);
873 }
874 enable_infra_emi_broadcast(0);
875
876 return 0x40000000;
877 }
878
restore_emi_after_rank1_mem_test(void)879 void restore_emi_after_rank1_mem_test(void)
880 {
881 enable_infra_emi_broadcast(1);
882 mt_emi_sync_write(EMI_CONH, cen_emi_conh_backup);
883 set_chn_emi_cona(chn_emi_cona_backup);
884 enable_infra_emi_broadcast(0);
885 }
886
get_emi_isu_info(struct isu_info_t * isu_info_ptr)887 void get_emi_isu_info(struct isu_info_t *isu_info_ptr)
888 {
889 #ifdef LAST_EMI
890 last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
891 isu_info_ptr->buf_size = EMI_ISU_BUF_SIZE;
892 isu_info_ptr->buf_addr = (unsigned long long)last_emi_info_ptr->isu_buf_h;
893 isu_info_ptr->buf_addr <<= 32;
894 isu_info_ptr->buf_addr += (unsigned long long)last_emi_info_ptr->isu_buf_l;
895 isu_info_ptr->ver_addr = (unsigned long long)(&(last_emi_info_ptr->isu_version));
896 isu_info_ptr->con_addr = (unsigned long long)(&(last_emi_info_ptr->isu_ctrl));
897 #endif
898 }
899
clr_emi_mpu_prot(void)900 void clr_emi_mpu_prot(void)
901 {
902 }
903
dis_emi_apb_prot(void)904 void dis_emi_apb_prot(void)
905 {
906 mt_emi_sync_write(EMI_MPU_CTRL, 0xFFFFFFFE);
907
908 emi_log("[EMI] EMI_MPU_CTRL 0x%x\n", mt_emi_sync_read(EMI_MPU_CTRL));
909 }
910
update_emi_setting(EMI_SETTINGS * default_emi_setting,EMI_INFO_T * emi_info)911 int update_emi_setting(EMI_SETTINGS *default_emi_setting, EMI_INFO_T *emi_info)
912 {
913 unsigned int ddr_type;
914 unsigned int cen_cona_val, cen_conf_val, cen_conh_val, cen_conk_val;
915 unsigned int chn_cona_val;
916 unsigned int cen_conf_shf;
917 unsigned int col, row, row_ext, rk_size, rk_size_ext, rk_size_chn_ext;
918 unsigned int temp_val;
919 int i;
920
921 ddr_type = default_emi_setting->type & 0xFF;
922 cen_conh_val = 0x00000003;
923 cen_conk_val = mt_emi_sync_read(EMI_CONK) & 0x0000FFFF;
924 if (u1IsLP4Family(ddr_type)) {
925 cen_cona_val = 0x00000104;
926 chn_cona_val = 0x04000000;
927 } else {
928 cen_cona_val = 0x00000006;
929 chn_cona_val = 0x00000002;
930 }
931
932 for (i = 0; i < emi_info->rk_num; i++) {
933 row = emi_info->row_width[i] - 13;
934 row_ext = row >> 2;
935 row &= 0x3;
936
937 col = emi_info->col_width[i] - 9;
938
939 rk_size = emi_info->rank_size[i] >> 28;
940 if (u1IsLP4Family(ddr_type))
941 rk_size >>= 1;
942 rk_size_ext = rk_size >> 4;
943 rk_size_chn_ext = rk_size_ext & 0x1;
944 rk_size &= 0xF;
945
946 if (i == 1) {
947 col <<= 2;
948 row <<= 2;
949 row_ext <<= 1;
950 rk_size <<= 4;
951 rk_size_ext <<= 4;
952 rk_size_chn_ext <<= 1;
953 cen_cona_val |= 0x00030000;
954 chn_cona_val |= 0x00000001;
955 }
956
957 cen_cona_val |=
958 (col << 4) | (row << 12) | (col << 20) |
959 (row_ext << 24) | (row << 28);
960 cen_conh_val |=
961 (row_ext << 4) | (rk_size << 16) | (rk_size << 24);
962 cen_conk_val |=
963 (rk_size_ext << 16) | (rk_size_ext << 24);
964 chn_cona_val |=
965 (row_ext << 2) | (col << 4) | (row << 12) |
966 (rk_size << 16) | (rk_size_chn_ext << 8);
967 }
968
969 cen_conf_shf = 0;
970 for (i = 0; i < emi_info->rk_num; i++) {
971 temp_val = 2 + emi_info->col_width[i];
972 if (cen_conf_shf < temp_val)
973 cen_conf_shf = temp_val;
974 }
975
976 if (((cen_conf_shf - 9) * 4) < 21)
977 cen_conf_val = 0x421 << ((cen_conf_shf - 9) * 4);
978 else
979 return -1;
980
981 emi_log("[EMI] %s(0x%x),%s(0x%x),%s(0x%x),%s(0x%x),%s(0x%x)\n",
982 "CEN_CONA", cen_cona_val,
983 "CEN_CONF", cen_conf_val,
984 "CEN_CONH", cen_conh_val,
985 "CEN_CONK", cen_conk_val,
986 "CHN_CONA", chn_cona_val);
987
988 default_emi_setting->EMI_CONA_VAL = cen_cona_val;
989 default_emi_setting->EMI_CONF_VAL = cen_conf_val;
990 default_emi_setting->EMI_CONH_VAL = cen_conh_val;
991 default_emi_setting->EMI_CONK_VAL = cen_conk_val;
992 default_emi_setting->CHN0_EMI_CONA_VAL = chn_cona_val;
993 default_emi_setting->CHN1_EMI_CONA_VAL = chn_cona_val;
994
995 return 0;
996 }
997
998 #if !__ETT__
record_emi_snst(void)999 void record_emi_snst(void)
1000 {
1001 #ifdef LAST_EMI
1002 if (!last_emi_info_ptr)
1003 last_emi_info_ptr =
1004 (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
1005
1006 last_emi_info_ptr->snst_past = last_emi_info_ptr->snst_last;
1007 last_emi_info_ptr->snst_last = mt_emi_sync_read(EMI_SNST);
1008 emi_log("[EMI] SNST: 0x%x\n", last_emi_info_ptr->snst_last);
1009
1010
1011 mt_emi_sync_write(EMI_SNST, 0x85000000);
1012 #endif
1013 }
1014
platform_memory_size(void)1015 unsigned long long platform_memory_size(void)
1016 {
1017 static unsigned long long mem_size = 0;
1018 int nr_rank;
1019 int i;
1020 unsigned long long rank_size[DRAMC_MAX_RK] = {0};
1021
1022 if (!mem_size) {
1023 nr_rank = get_dram_rank_nr();
1024
1025 get_dram_rank_size(rank_size);
1026
1027 for (i = 0; i < nr_rank; i++)
1028 mem_size += rank_size[i];
1029 }
1030
1031 return mem_size;
1032 }
1033 #endif
1034
1035