1 /*
2 * Copyright © 2015 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "vc4_qir.h"
25 #include "kernel/vc4_packet.h"
26 #include "compiler/nir/nir_builder.h"
27
28 /** @file vc4_nir_lower_txf_ms.c
29 * Walks the NIR generated by TGSI-to-NIR to lower its nir_texop_txf_ms
30 * coordinates to do the math necessary and use a plain nir_texop_txf instead.
31 *
32 * MSAA textures are laid out as 32x32-aligned blocks of RGBA8888 or Z24S8.
33 * We can't load them through the normal sampler path because of the lack of
34 * linear support in the hardware. So, we treat MSAA textures as a giant UBO
35 * and do the math in the shader.
36 */
37
38 static nir_def *
vc4_nir_lower_txf_ms_instr(nir_builder * b,nir_instr * instr,void * data)39 vc4_nir_lower_txf_ms_instr(nir_builder *b, nir_instr *instr, void *data)
40 {
41 nir_tex_instr *txf_ms = nir_instr_as_tex(instr);
42 const struct vc4_compile *c = data;
43
44 nir_tex_instr *txf = nir_tex_instr_create(c->s, 1);
45 txf->op = nir_texop_txf;
46 txf->texture_index = txf_ms->texture_index;
47 txf->coord_components = txf_ms->coord_components;
48 txf->is_shadow = txf_ms->is_shadow;
49 txf->is_new_style_shadow = txf_ms->is_new_style_shadow;
50 txf->dest_type = txf_ms->dest_type;
51
52 nir_def *coord = NULL, *sample_index = NULL;
53 for (int i = 0; i < txf_ms->num_srcs; i++) {
54 switch (txf_ms->src[i].src_type) {
55 case nir_tex_src_coord:
56 coord = txf_ms->src[i].src.ssa;
57 break;
58 case nir_tex_src_ms_index:
59 sample_index = txf_ms->src[i].src.ssa;
60 break;
61 default:
62 unreachable("Unknown txf_ms src\n");
63 }
64 }
65 assert(coord);
66 assert(sample_index);
67
68 nir_def *x = nir_channel(b, coord, 0);
69 nir_def *y = nir_channel(b, coord, 1);
70
71 uint32_t tile_w = 32;
72 uint32_t tile_h = 32;
73 uint32_t tile_w_shift = 5;
74 uint32_t tile_h_shift = 5;
75 uint32_t tile_size = (tile_h * tile_w *
76 VC4_MAX_SAMPLES * sizeof(uint32_t));
77 unsigned unit = txf_ms->texture_index;
78 uint32_t w = align(c->key->tex[unit].msaa_width, tile_w);
79 uint32_t w_tiles = w / tile_w;
80
81 nir_def *x_tile = nir_ushr_imm(b, x, tile_w_shift);
82 nir_def *y_tile = nir_ushr_imm(b, y, tile_h_shift);
83 nir_def *tile_addr = nir_iadd(b,
84 nir_imul_imm(b, x_tile, tile_size),
85 nir_imul_imm(b, y_tile, w_tiles *
86 tile_size));
87 nir_def *x_subspan = nir_iand_imm(b, x, (tile_w - 1) & ~1);
88 nir_def *y_subspan = nir_iand_imm(b, y, (tile_h - 1) & ~1);
89 nir_def *subspan_addr = nir_iadd(b,
90 nir_imul_imm(b, x_subspan,
91 2 * VC4_MAX_SAMPLES * sizeof(uint32_t)),
92 nir_imul_imm(b, y_subspan,
93 tile_w * VC4_MAX_SAMPLES *
94 sizeof(uint32_t)));
95
96 nir_def *pixel_addr = nir_ior(b,
97 nir_iand_imm(b,
98 nir_ishl_imm(b, x, 2),
99 1 << 2),
100 nir_iand_imm(b,
101 nir_ishl_imm(b, y, 3),
102 1 << 3));
103
104 nir_def *sample_addr = nir_ishl_imm(b, sample_index, 4);
105
106 nir_def *addr = nir_iadd(b,
107 nir_ior(b, sample_addr, pixel_addr),
108 nir_iadd(b, subspan_addr, tile_addr));
109
110 txf->src[0] = nir_tex_src_for_ssa(nir_tex_src_coord,
111 nir_vec2(b, addr, nir_imm_int(b, 0)));
112 nir_def_init(&txf->instr, &txf->def, 4, 32);
113 nir_builder_instr_insert(b, &txf->instr);
114
115 return &txf->def;
116 }
117
118 static bool
vc4_nir_lower_txf_ms_filter(const nir_instr * instr,const void * data)119 vc4_nir_lower_txf_ms_filter(const nir_instr *instr, const void *data)
120 {
121 return (instr->type == nir_instr_type_tex &&
122 nir_instr_as_tex(instr)->op == nir_texop_txf_ms);
123 }
124
125 void
vc4_nir_lower_txf_ms(nir_shader * s,struct vc4_compile * c)126 vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c)
127 {
128 nir_shader_lower_instructions(s,
129 vc4_nir_lower_txf_ms_filter,
130 vc4_nir_lower_txf_ms_instr,
131 c);
132 }
133