1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <soc/addressmap.h> 4 #include <types.h> 5 #include <soc/clock_common.h> 6 7 #ifndef __SOC_QUALCOMM_SC7280_CLOCK_H__ 8 #define __SOC_QUALCOMM_SC7280_CLOCK_H__ 9 10 #define SRC_XO_HZ (19200 * KHz) 11 #define GPLL0_EVEN_HZ (300 * MHz) 12 #define GPLL0_MAIN_HZ (600 * MHz) 13 #define CLK_100MHZ (100 * MHz) 14 15 /* CPU PLL */ 16 #define L_VAL_1516P8MHz 0x4F 17 #define L_VAL_1190P4MHz 0x3E 18 19 #define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) 20 #define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) 21 #define QUPV3_WRAP1_CLK_ENA_1_S(idx) (7 + idx) 22 23 enum clk_pll_src { 24 SRC_XO_19_2MHZ = 0, 25 SRC_GPLL0_MAIN_600MHZ = 1, 26 SRC_GPLL9_MAIN_808MHZ = 2, 27 SRC_GCC_DISP_GPLL0_CLK = 4, 28 SRC_GPLL10_MAIN_384MHZ = 5, 29 SRC_GPLL0_EVEN_300MHZ = 6, 30 }; 31 32 enum clk_pcie_src_sel { 33 PCIE_1_PIPE_SRC_SEL = 0, 34 PCIE_1_XO_SRC_SEL = 2, 35 }; 36 37 enum apcs_branch_en_vote { 38 QUPV3_WRAP_0_M_AHB_CLK_ENA = 6, 39 QUPV3_WRAP_0_S_AHB_CLK_ENA = 7, 40 QUPV3_WRAP0_CORE_CLK_ENA = 8, 41 QUPV3_WRAP0_CORE_2X_CLK_ENA = 9, 42 AGGRE_NOC_PCIE_1_AXI_CLK_ENA = 11, 43 QUPV3_WRAP1_CORE_2X_CLK_ENA = 18, 44 AGGRE_NOC_PCIE_TBU_CLK_ENA = 18, 45 QUPV3_WRAP1_CORE_CLK_ENA = 19, 46 DDRSS_PCIE_SF_CLK_ENA = 19, 47 QUPV3_WRAP_1_M_AHB_CLK_ENA = 20, 48 QUPV3_WRAP_1_S_AHB_CLK_ENA = 21, 49 PCIE1_PHY_RCHNG_CLK_ENA = 23, 50 PCIE_1_SLV_Q2A_AXI_CLK_ENA = 25, 51 PCIE_1_SLV_AXI_CLK_ENA = 26, 52 PCIE_1_MSTR_AXI_CLK_ENA = 27, 53 PCIE_1_CFG_AHB_CLK_ENA = 28, 54 AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK_ENA = 28, 55 PCIE_1_AUX_CLK_ENA = 29, 56 PCIE_1_PIPE_CLK_ENA = 30, 57 NO_VOTE_BIT = -1, 58 }; 59 60 struct sc7280_gpll { 61 u32 mode; 62 u32 l; 63 u32 cal_l; 64 u32 user_ctl; 65 u32 user_ctl_u; 66 u32 user_ctl_u1; 67 u32 config_ctl; 68 u32 config_ctl_u; 69 u32 config_ctl_u1; 70 u32 test_ctl; 71 u32 test_ctl_u; 72 u32 test_ctl_u1; 73 u8 _res0[0x38 - 0x30]; 74 u32 opmode; 75 u8 _res1[0x40 - 0x3c]; 76 u32 alpha; 77 }; 78 79 struct sc7280_disp_cc { 80 u8 _res0[0x1004]; 81 u32 core_gdsc; 82 u8 _res1[0x1010 - 0x1008]; 83 u32 pclk0_cbcr; 84 u32 mdp_cbcr; 85 u8 _res2[0x102c - 0x1018]; 86 u32 vsync_cbcr; 87 u32 byte0_cbcr; 88 u32 byte0_intf_cbcr; 89 u32 esc0_cbcr; 90 u8 _res3[0x1050 - 0x103c]; 91 u32 ahb_cbcr; 92 u32 edp_pixel_cbcr; 93 u32 edp_link_cbcr; 94 u32 edp_link_intf_cbcr; 95 u32 edp_aux_cbcr; 96 u8 _res4[0x1078 - 0x1064]; 97 struct clock_rcg_mnd pclk0; 98 u8 _res5[0x1090 - 0x108c]; 99 struct clock_rcg mdp; 100 u8 _res6[0x10c0 - 0x1098]; 101 struct clock_rcg vsync; 102 u8 _res7[0x10d8 - 0x10c8]; 103 struct clock_rcg byte0; 104 u8 _res8[0x10f4 - 0x10e0]; 105 struct clock_rcg esc0; 106 u8 _res9[0x1170 - 0x10fc]; 107 struct clock_rcg mdss_ahb; 108 u8 _res10[0x1188 - 0x1178]; 109 struct clock_rcg_mnd edp_pixel; 110 u8 _res11[0x11a0 - 0x119c]; 111 struct clock_rcg edp_link; 112 u8 _res12[0x11d0 - 0x11a8]; 113 struct clock_rcg edp_aux; 114 u8 _res13[0x20000 - 0x11d8]; 115 }; 116 check_member(sc7280_disp_cc, pclk0_cbcr, 0x1010); 117 check_member(sc7280_disp_cc, vsync_cbcr, 0x102c); 118 check_member(sc7280_disp_cc, ahb_cbcr, 0x1050); 119 check_member(sc7280_disp_cc, edp_aux_cbcr, 0x1060); 120 121 struct sc7280_pcie { 122 u32 pcie_1_bcr; 123 u32 gdscr; 124 u8 _res1[0x18d010 - 0x18d008]; 125 u32 slv_q2a_axi_cbcr; 126 u32 slv_axi_cbcr; 127 u8 _res2[0x18d01c - 0x18d018]; 128 u32 mstr_axi_cbcr; 129 u8 _res3[0x18d024 - 0x18d020]; 130 u32 cfg_ahb_cbcr; 131 u32 aux_cbcr; 132 u8 _res4[0x18d030 - 0x18d02c]; 133 u32 pipe_cbcr; 134 u8 _res5[0x18d038 - 0x18d034]; 135 u32 phy_rchng_cbcr; 136 u8 _res6[0x18d054 - 0x18d03c]; 137 u32 pipe_muxr; 138 u8 _res7[0x18d080 - 0x18d058]; 139 u32 ddrss_pcie_sf_cbcr; 140 u32 aggre_noc_pcie_axi_cbcr; 141 u32 aggre_noc_pcie_center_sf_axi_cbcr; 142 u8 _res8[0x18e01c - 0x18d08c]; 143 u32 phy_bcr; 144 }; 145 check_member(sc7280_pcie, slv_q2a_axi_cbcr, 0x10); 146 check_member(sc7280_pcie, mstr_axi_cbcr, 0x1c); 147 check_member(sc7280_pcie, pipe_cbcr, 0x30); 148 check_member(sc7280_pcie, ddrss_pcie_sf_cbcr, 0x80); 149 check_member(sc7280_pcie, phy_bcr, 0x101c); 150 151 struct sc7280_gcc { 152 struct sc7280_gpll gpll0; 153 u8 _res0[0xf000 - 0x44]; 154 u32 usb30_prim_bcr; 155 u8 _res1[0x12000 - 0xf004]; 156 u32 qusb2phy_prim_bcr; 157 u32 qusb2phy_sec_bcr; 158 u8 _res2[0x14004 - 0x12008]; 159 u32 sdcc2_apps_cbcr; 160 u32 sdcc2_ahb_cbcr; 161 struct clock_rcg_mnd sdcc2; 162 u8 _res3[0x16004 - 0x14020]; 163 u32 sdcc4_apps_cbcr; 164 u32 sdcc4_ahb_cbcr; 165 struct clock_rcg_mnd sdcc4; 166 u8 _res4[0x17000 - 0x16020]; 167 u32 qup_wrap0_bcr; 168 u32 qup_wrap0_m_ahb_cbcr; 169 u32 qup_wrap0_s_ahb_cbcr; 170 struct qupv3_clock qup_wrap0_s[8]; 171 u8 _res5[0x18000 - 0x1798c]; 172 u32 qup_wrap1_bcr; 173 u32 qup_wrap1_m_ahb_cbcr; 174 u32 qup_wrap1_s_ahb_cbcr; 175 struct qupv3_clock qup_wrap1_s[8]; 176 u8 _res6[0x1c000 - 0x1898c]; 177 struct sc7280_gpll gpll9; 178 u8 _res7[0x1e000 - 0x1c044]; 179 struct sc7280_gpll gpll10; 180 u8 _res8[0x23000 - 0x1e044]; 181 u32 qup_wrap0_core_cbcr; 182 u32 qup_wrap0_core_cdivr; 183 u32 qup_wrap0_core_2x_cbcr; 184 struct clock_rcg qup_wrap0_core_2x; 185 u8 _res9[0x23138 - 0x23014]; 186 u32 qup_wrap1_core_cbcr; 187 u32 qup_wrap1_core_cdivr; 188 u32 qup_wrap1_core_2x_cbcr; 189 struct clock_rcg qup_wrap1_core_2x; 190 u8 _res10[0x27004 - 0x2314c]; 191 u32 disp_ahb_cbcr; 192 u8 _res11[0x2700c - 0x27008]; 193 u32 disp_hf_axi_cbcr; 194 u8 _res12[0x27014 - 0x27010]; 195 u32 disp_sf_axi_cbcr; 196 u8 _res13[0x4b000 - 0x27018]; 197 u32 qspi_bcr; 198 u32 qspi_cnoc_ahb_cbcr; 199 u32 qspi_core_cbcr; 200 struct clock_rcg qspi_core; 201 u8 _res14[0x50000 - 0x4b014]; 202 u32 usb3_phy_prim_bcr; 203 u32 usb3phy_phy_prim_bcr; 204 u32 usb3_dp_phy_prim_bcr; 205 u8 _res15[0x52000 - 0x5000c]; 206 u32 apcs_clk_br_en; 207 u8 _res16[0x52008 - 0x52004]; 208 u32 apcs_clk_br_en1; 209 u8 _res17[0x52010 - 0x5200c]; 210 u32 apcs_pll_br_en; 211 u8 _res18[0x6a000 - 0x52014]; 212 u32 usb_phy_cfg_ahb2phy_bcr; 213 u8 _res19[0x75004 - 0x6a004]; 214 u32 sdcc1_ahb_cbcr; 215 u32 sdcc1_apps_cbcr; 216 struct clock_rcg_mnd sdcc1; 217 u8 _res20[0x8c004 - 0x75020]; 218 u32 pcie_clkref_en; 219 u32 edp_clkref_en; 220 u8 _res21[0x8d000 - 0x8c00c]; 221 struct sc7280_pcie pcie_1; 222 u8 _res22[0x90010 - 0x8e020]; 223 u32 aggre_noc_pcie_tbu_cbcr; 224 u8 _res23[0x9e000 - 0x90014]; 225 u32 usb30_sec_bcr; 226 u8 _res24[0x1000000 - 0x90014]; 227 }; 228 check_member(sc7280_gcc, qusb2phy_prim_bcr, 0x12000); 229 check_member(sc7280_gcc, sdcc2_apps_cbcr, 0x14004); 230 check_member(sc7280_gcc, sdcc4_apps_cbcr, 0x16004); 231 check_member(sc7280_gcc, qup_wrap0_bcr, 0x17000); 232 check_member(sc7280_gcc, qup_wrap1_bcr, 0x18000); 233 check_member(sc7280_gcc, qup_wrap1_core_cbcr, 0x23138); 234 check_member(sc7280_gcc, qspi_bcr, 0x4b000); 235 check_member(sc7280_gcc, usb3_phy_prim_bcr, 0x50000); 236 check_member(sc7280_gcc, apcs_clk_br_en1, 0x52008); 237 check_member(sc7280_gcc, apcs_pll_br_en, 0x52010); 238 check_member(sc7280_gcc, usb_phy_cfg_ahb2phy_bcr, 0x6a000); 239 check_member(sc7280_gcc, sdcc1_ahb_cbcr, 0x75004); 240 check_member(sc7280_gcc, pcie_clkref_en, 0x8c004); 241 check_member(sc7280_gcc, edp_clkref_en, 0x8c008); 242 check_member(sc7280_gcc, aggre_noc_pcie_tbu_cbcr, 0x90010); 243 check_member(sc7280_gcc, usb30_sec_bcr, 0x9e000); 244 245 246 struct sc7280_apss_pll { 247 u32 mode; 248 u32 l; 249 u32 alpha; 250 u32 user_ctl; 251 u32 config_ctl_lo; 252 u32 config_ctl_hi; 253 u32 config_ctl_u1; 254 u32 test_ctl_lo; 255 u32 test_ctl_hi; 256 u32 test_ctl_u1; 257 u32 opmode; 258 u8 _res0[0x38 - 0x2c]; 259 u32 status; 260 }; 261 262 struct sc7280_apss_clock { 263 struct sc7280_apss_pll pll; 264 u8 _res0[0x84 - 0x3c]; 265 u32 cfg_gfmux; 266 }; 267 268 struct pcie { 269 uint32_t *gdscr; 270 uint32_t *clk; 271 uint32_t *clk_br_en; 272 int vote_bit; 273 }; 274 275 enum clk_qup { 276 QUP_WRAP0_S0, 277 QUP_WRAP0_S1, 278 QUP_WRAP0_S2, 279 QUP_WRAP0_S3, 280 QUP_WRAP0_S4, 281 QUP_WRAP0_S5, 282 QUP_WRAP0_S6, 283 QUP_WRAP0_S7, 284 QUP_WRAP1_S0, 285 QUP_WRAP1_S1, 286 QUP_WRAP1_S2, 287 QUP_WRAP1_S3, 288 QUP_WRAP1_S4, 289 QUP_WRAP1_S5, 290 QUP_WRAP1_S6, 291 QUP_WRAP1_S7, 292 }; 293 294 enum clk_gdsc { 295 MDSS_CORE_GDSC, 296 PCIE_1_GDSC, 297 MAX_GDSC 298 }; 299 300 enum clk_mdss { 301 GCC_DISP_AHB, 302 GCC_DISP_HF_AXI, 303 GCC_DISP_SF_AXI, 304 GCC_EDP_CLKREF_EN, 305 MDSS_CLK_PCLK0, 306 MDSS_CLK_MDP, 307 MDSS_CLK_VSYNC, 308 MDSS_CLK_BYTE0, 309 MDSS_CLK_BYTE0_INTF, 310 MDSS_CLK_ESC0, 311 MDSS_CLK_AHB, 312 MDSS_CLK_EDP_PIXEL, 313 MDSS_CLK_EDP_LINK, 314 MDSS_CLK_EDP_LINK_INTF, 315 MDSS_CLK_EDP_AUX, 316 MDSS_CLK_COUNT 317 }; 318 319 enum clk_pcie { 320 PCIE_1_SLV_Q2A_AXI_CLK, 321 PCIE_1_SLV_AXI_CLK, 322 PCIE_1_MSTR_AXI_CLK, 323 PCIE_1_CFG_AHB_CLK, 324 PCIE_1_AUX_CLK, 325 AGGRE_NOC_PCIE_TBU_CLK, 326 AGGRE_NOC_PCIE_1_AXI_CLK, 327 DDRSS_PCIE_SF_CLK, 328 PCIE1_PHY_RCHNG_CLK, 329 AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 330 PCIE_1_PIPE_CLK, 331 PCIE_CLKREF_EN, 332 GCC_PCIE_1_PIPE_MUXR, 333 PCIE_CLK_COUNT, 334 }; 335 336 enum subsystem_reset { 337 AOP_RESET_SHFT = 0, 338 SHRM_RUN_STALL = 0, 339 }; 340 341 enum pll_config_ctl_lo { 342 CTUNE_SHFT = 2, 343 K_I_SHFT = 4, 344 K_P_SHFT = 7, 345 PFA_MSB_SHFT = 10, 346 RES_BIT_SHFT = 14, 347 RON_DEGEN_MUL_SHFT = 18, 348 ALPHA_CAL_SHFT = 20, 349 DCO_ADDER_EN_SHFT = 22, 350 PLL_COUNTER_EN = 27, 351 }; 352 353 enum pll_config_ctl_hi { 354 CUR_TRIM_SHFT = 0, 355 FREQ_DOUBLE_SHFT = 4, 356 ADJ_ENABLE_SHFT = 5, 357 ADJ_VALUE_SHFT = 6, 358 KLSB_SHFT = 13, 359 RON_MODE_SHFT = 17, 360 CHP_REF_SHFT = 19, 361 CHP_STARTUP = 21, 362 ADC_KMSB_VAL = 23, 363 }; 364 365 enum pll_config_ctl_u1 { 366 FAST_LOCK_LOW_L_SHFT = 4, 367 DCO_BIAS_ADJ_SHFT = 26, 368 }; 369 370 enum apss_gfmux { 371 GFMUX_SRC_SEL_BMSK = 0x3, 372 APCS_SRC_EARLY = 0x2, 373 }; 374 375 static struct sc7280_gcc *const gcc = (void *)GCC_BASE; 376 static struct sc7280_apss_clock *const apss_silver = (void *)SILVER_PLL_BASE; 377 static struct sc7280_apss_clock *const apss_l3 = (void *)L3_PLL_BASE; 378 static struct sc7280_disp_cc *const mdss = (void *)DISP_CC_BASE; 379 380 void clock_init(void); 381 void clock_configure_qspi(uint32_t hz); 382 void clock_enable_qup(int qup); 383 void clock_configure_sdcc1(uint32_t hz); 384 void clock_configure_sdcc2(uint32_t hz); 385 void clock_configure_dfsr(int qup); 386 enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type); 387 388 enum cb_err mdss_clock_configure(enum clk_mdss clk_type, uint32_t hz, 389 uint32_t source, uint32_t divider, 390 uint32_t m, uint32_t n, uint32_t d); 391 enum cb_err mdss_clock_enable(enum clk_mdss clk_type); 392 enum cb_err clock_enable_pcie(enum clk_pcie clk_type); 393 enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type); 394 395 /* Subsystem Reset */ 396 static struct aoss *const aoss = (void *)AOSS_CC_BASE; 397 static struct shrm *const shrm = (void *)SHRM_SPROC_BASE; 398 399 #define clock_reset_aop() \ 400 clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT) 401 #define clock_reset_shrm() \ 402 clock_reset_subsystem(&shrm->shrm_sproc_ctrl, SHRM_RUN_STALL) 403 404 #endif // __SOC_QUALCOMM_SC7280_CLOCK_H__ 405