1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 3 /* 4 * This file is created based on MT8188 Functional Specification 5 * Chapter number: 5.11 6 */ 7 8 #ifndef SOC_MEDIATEK_MT8188_I2C_H 9 #define SOC_MEDIATEK_MT8188_I2C_H 10 11 #include <soc/i2c_common.h> 12 #include <soc/pll.h> 13 14 /* I2C Register */ 15 struct mt_i2c_regs { 16 uint32_t data_port; 17 uint32_t reserved0[1]; 18 uint32_t intr_mask; 19 uint32_t intr_stat; 20 uint32_t control; 21 uint32_t transfer_len; 22 uint32_t transac_len; 23 uint32_t delay_len; 24 uint32_t timing; 25 uint32_t start; 26 uint32_t ext_conf; 27 uint32_t ltiming; 28 uint32_t hs; 29 uint32_t io_config; 30 uint32_t fifo_addr_clr; 31 uint32_t reserved1[2]; 32 uint32_t transfer_aux_len; 33 uint32_t clock_div; 34 uint32_t time_out; 35 uint32_t softreset; 36 uint32_t reserved2[16]; 37 uint32_t slave_addr; 38 uint32_t reserved3[19]; 39 uint32_t debug_stat; 40 uint32_t debug_ctrl; 41 uint32_t reserved4[2]; 42 uint32_t fifo_stat; 43 uint32_t fifo_thresh; 44 uint32_t reserved5[897]; 45 uint32_t sec_control; 46 uint32_t reserved6[31]; 47 uint32_t channel_lock; 48 uint32_t channel_sec; 49 uint32_t hw_cg_en; 50 uint32_t reserved7[1]; 51 uint32_t dma_req; 52 uint32_t dma_nreq; 53 }; 54 55 /* I2C ID Number*/ 56 enum { 57 I2C0, 58 I2C1, 59 I2C2, 60 I2C3, 61 I2C4, 62 I2C5, 63 I2C6, 64 }; 65 66 #define I2C_BUS_NUMBER 7 67 #define MAX_CLOCK_DIV 32 68 #define I2C_CLK_HZ (124800000) 69 70 check_member(mt_i2c_regs, dma_nreq, 0xf94); 71 72 void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); 73 74 #endif /* SOC_MEDIATEK_MT8188_I2C_H */ 75