xref: /aosp_15_r20/external/coreboot/src/soc/mediatek/common/include/soc/gpio_common.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_MEDIATEK_COMMON_GPIO_H
4 #define SOC_MEDIATEK_COMMON_GPIO_H
5 
6 #include <soc/addressmap.h>
7 #include <soc/gpio_base.h>
8 #include <stddef.h>
9 #include <stdint.h>
10 
11 enum pull_enable {
12 	GPIO_PULL_DISABLE = 0,
13 	GPIO_PULL_ENABLE = 1,
14 };
15 
16 enum pull_select {
17 	GPIO_PULL_DOWN = 0,
18 	GPIO_PULL_UP = 1,
19 };
20 
21 /*
22  * GPIO DRIVING
23  * Special IO(I2C, HDMI...) advanced drive strength:
24  * GPIO_DRV_ADV_125_UA: 0.125mA
25  * GPIO_DRV_ADV_250_UA: 0.25mA
26  * GPIO_DRV_ADV_500_UA: 0.5mA
27  * GPIO_DRV_ADV_1_MA: 1mA
28  */
29 enum gpio_drv_adv {
30 	GPIO_DRV_ADV_125_UA = 0,
31 	GPIO_DRV_ADV_250_UA = 1,
32 	GPIO_DRV_ADV_500_UA = 2,
33 	GPIO_DRV_ADV_1_MA = 3,
34 };
35 
36 enum gpio_drv {
37 	GPIO_DRV_2_MA = 0,
38 	GPIO_DRV_4_MA = 1,
39 	GPIO_DRV_6_MA = 2,
40 	GPIO_DRV_8_MA = 3,
41 	GPIO_DRV_10_MA = 4,
42 	GPIO_DRV_12_MA = 5,
43 	GPIO_DRV_14_MA = 6,
44 	GPIO_DRV_16_MA = 7,
45 };
46 
47 struct gpio_drv_info {
48 	uint8_t offset;
49 	uint8_t shift;
50 	uint8_t width;
51 };
52 
53 void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
54 		   enum pull_select select);
55 void gpio_set_mode(gpio_t gpio, int mode);
56 void *gpio_find_reg_addr(gpio_t gpio);
57 
58 const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id);
59 const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id);
60 
61 /* Normal driving function */
62 int gpio_set_driving(gpio_t gpio, uint8_t drv);
63 int gpio_get_driving(gpio_t gpio);
64 
65 /* Advanced driving function */
66 int gpio_set_driving_adv(gpio_t gpio, enum gpio_drv_adv drv);
67 int gpio_get_driving_adv(gpio_t gpio);
68 
69 enum gpio_irq_type {
70 	IRQ_TYPE_EDGE_RISING,
71 	IRQ_TYPE_EDGE_FALLING,
72 	IRQ_TYPE_LEVEL_HIGH,
73 	IRQ_TYPE_LEVEL_LOW,
74 };
75 
76 struct eint_section {
77 	uint32_t	regs[7];
78 	uint32_t	align1[9];
79 };
80 
81 struct eint_regs {
82 	struct eint_section sta;
83 	struct eint_section ack;
84 	struct eint_section mask;
85 	struct eint_section mask_set;
86 	struct eint_section mask_clr;
87 	struct eint_section sens;
88 	struct eint_section sens_set;
89 	struct eint_section sens_clr;
90 	struct eint_section soft;
91 	struct eint_section soft_set;
92 	struct eint_section soft_clr;
93 	struct eint_section rsv00;
94 	struct eint_section pol;
95 	struct eint_section pol_set;
96 	struct eint_section pol_clr;
97 	struct eint_section rsv01;
98 	uint32_t	    d0en[7];
99 	uint32_t	    rsv02;
100 	uint32_t	    d1en[7];
101 };
102 
103 check_member(eint_regs, d1en, 0x420);
104 
105 static struct eint_regs *const mtk_eint = (void *)(EINT_BASE);
106 
107 /*
108  * Firmware never enables interrupts on this platform.  This function
109  * reads current EINT status and clears the pending interrupt.
110  *
111  * Returns 1 if the interrupt was pending, else 0.
112  */
113 int gpio_eint_poll(gpio_t gpio);
114 
115 /*
116  * Configure a GPIO to handle external interrupts (EINT) of given irq type.
117  */
118 void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type);
119 
120 #endif
121