1 #ifndef __BDK_CSRS_OCLA_H__
2 #define __BDK_CSRS_OCLA_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
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31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium OCLA.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration ocla_bar_e
57 *
58 * OCLA Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_OCLA_BAR_E_OCLAX_PF_BAR0_CN8(a) (0x87e0a8000000ll + 0x1000000ll * (a))
62 #define BDK_OCLA_BAR_E_OCLAX_PF_BAR0_CN8_SIZE 0x800000ull
63 #define BDK_OCLA_BAR_E_OCLAX_PF_BAR0_CN9(a) (0x87e0b0000000ll + 0x1000000ll * (a))
64 #define BDK_OCLA_BAR_E_OCLAX_PF_BAR0_CN9_SIZE 0x800000ull
65 #define BDK_OCLA_BAR_E_OCLAX_PF_BAR4_CN8(a) (0x87e0a8f00000ll + 0x1000000ll * (a))
66 #define BDK_OCLA_BAR_E_OCLAX_PF_BAR4_CN8_SIZE 0x100000ull
67 #define BDK_OCLA_BAR_E_OCLAX_PF_BAR4_CN9(a) (0x87e0b0f00000ll + 0x1000000ll * (a))
68 #define BDK_OCLA_BAR_E_OCLAX_PF_BAR4_CN9_SIZE 0x100000ull
69
70 /**
71 * Enumeration ocla_int_vec_e
72 *
73 * OCLA MSI-X Vector Enumeration
74 * Enumerates the MSI-X interrupt vectors.
75 */
76 #define BDK_OCLA_INT_VEC_E_INTS (0)
77
78 /**
79 * Structure ocla_cap_ctl_s
80 *
81 * OCLA Capture Control Structure
82 * Control packets are indicated by an entry's bit 37 being set, and described by the
83 * OCLA_CAP_CTL_S structure:
84 */
85 union bdk_ocla_cap_ctl_s
86 {
87 uint64_t u;
88 struct bdk_ocla_cap_ctl_s_s
89 {
90 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
91 uint64_t reserved_38_63 : 26;
92 uint64_t ctl : 1; /**< [ 37: 37] Indicates a control word. Always set for control structures. */
93 uint64_t sinfo : 1; /**< [ 36: 36] Indicates OCLA()_FSM()_STATE()[SINFO_SET] was set for the state that led to the
94 capture state. This allows the FSM to optionally communicate its current state
95 to observing software; [SINFO] is otherwise opaque to reassembling the trace
96 information. */
97 uint64_t eot1 : 1; /**< [ 35: 35] End of duplicated capture for high data. Symmetric with EOT0 description; see [EOT0]. */
98 uint64_t eot0 : 1; /**< [ 34: 34] End of duplicated capture for low data. When set, [CYCLE] indicates the cycle at which the
99 previous entry of low data stopped being replicated. This may be set along with SOT0 to
100 indicate a repeat followed by new sequence. */
101 uint64_t sot1 : 1; /**< [ 33: 33] Start transition from no-capture to capture or duplicated data stopped while capturing for
102 high data. When set, [CYCLE] indicates the cycle number of the next new high data, minus one
103 cycle. */
104 uint64_t sot0 : 1; /**< [ 32: 32] Start transition from no-capture to capture or duplicated data stopped while capturing for
105 low data. When set, [CYCLE] indicates the cycle number of the next new low data, minus one
106 cycle. */
107 uint64_t cycle : 32; /**< [ 31: 0] Cycle at which this control entry was written, from OCLA()_TIME. */
108 #else /* Word 0 - Little Endian */
109 uint64_t cycle : 32; /**< [ 31: 0] Cycle at which this control entry was written, from OCLA()_TIME. */
110 uint64_t sot0 : 1; /**< [ 32: 32] Start transition from no-capture to capture or duplicated data stopped while capturing for
111 low data. When set, [CYCLE] indicates the cycle number of the next new low data, minus one
112 cycle. */
113 uint64_t sot1 : 1; /**< [ 33: 33] Start transition from no-capture to capture or duplicated data stopped while capturing for
114 high data. When set, [CYCLE] indicates the cycle number of the next new high data, minus one
115 cycle. */
116 uint64_t eot0 : 1; /**< [ 34: 34] End of duplicated capture for low data. When set, [CYCLE] indicates the cycle at which the
117 previous entry of low data stopped being replicated. This may be set along with SOT0 to
118 indicate a repeat followed by new sequence. */
119 uint64_t eot1 : 1; /**< [ 35: 35] End of duplicated capture for high data. Symmetric with EOT0 description; see [EOT0]. */
120 uint64_t sinfo : 1; /**< [ 36: 36] Indicates OCLA()_FSM()_STATE()[SINFO_SET] was set for the state that led to the
121 capture state. This allows the FSM to optionally communicate its current state
122 to observing software; [SINFO] is otherwise opaque to reassembling the trace
123 information. */
124 uint64_t ctl : 1; /**< [ 37: 37] Indicates a control word. Always set for control structures. */
125 uint64_t reserved_38_63 : 26;
126 #endif /* Word 0 - End */
127 } s;
128 /* struct bdk_ocla_cap_ctl_s_s cn; */
129 };
130
131 /**
132 * Structure ocla_cap_dat_s
133 *
134 * OCLA Capture Data Structure
135 * Data packets are indicated by an entry's bit 37 being clear, and described by the
136 * OCLA_CAP_DAT_S structure:
137 */
138 union bdk_ocla_cap_dat_s
139 {
140 uint64_t u;
141 struct bdk_ocla_cap_dat_s_s
142 {
143 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
144 uint64_t reserved_38_63 : 26;
145 uint64_t ctl : 1; /**< [ 37: 37] Indicates a control word. Always clear for data structures. */
146 uint64_t hi : 1; /**< [ 36: 36] Set to indicate a sample of high data, clear for a sample of low data. */
147 uint64_t data : 36; /**< [ 35: 0] Captured trace data. */
148 #else /* Word 0 - Little Endian */
149 uint64_t data : 36; /**< [ 35: 0] Captured trace data. */
150 uint64_t hi : 1; /**< [ 36: 36] Set to indicate a sample of high data, clear for a sample of low data. */
151 uint64_t ctl : 1; /**< [ 37: 37] Indicates a control word. Always clear for data structures. */
152 uint64_t reserved_38_63 : 26;
153 #endif /* Word 0 - End */
154 } s;
155 /* struct bdk_ocla_cap_dat_s_s cn; */
156 };
157
158 /**
159 * Register (RSL) ocla#_active_pc
160 *
161 * OCLA Conditional Clock Counter Register
162 * This register counts conditional clocks for power management.
163 *
164 * This register is reset on ocla domain reset.
165 */
166 union bdk_oclax_active_pc
167 {
168 uint64_t u;
169 struct bdk_oclax_active_pc_s
170 {
171 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
172 uint64_t count : 64; /**< [ 63: 0](R/W/H) Count of conditional clock cycles since reset. */
173 #else /* Word 0 - Little Endian */
174 uint64_t count : 64; /**< [ 63: 0](R/W/H) Count of conditional clock cycles since reset. */
175 #endif /* Word 0 - End */
176 } s;
177 /* struct bdk_oclax_active_pc_s cn; */
178 };
179 typedef union bdk_oclax_active_pc bdk_oclax_active_pc_t;
180
181 static inline uint64_t BDK_OCLAX_ACTIVE_PC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_ACTIVE_PC(unsigned long a)182 static inline uint64_t BDK_OCLAX_ACTIVE_PC(unsigned long a)
183 {
184 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
185 return 0x87e0b0000620ll + 0x1000000ll * ((a) & 0x7);
186 __bdk_csr_fatal("OCLAX_ACTIVE_PC", 1, a, 0, 0, 0);
187 }
188
189 #define typedef_BDK_OCLAX_ACTIVE_PC(a) bdk_oclax_active_pc_t
190 #define bustype_BDK_OCLAX_ACTIVE_PC(a) BDK_CSR_TYPE_RSL
191 #define basename_BDK_OCLAX_ACTIVE_PC(a) "OCLAX_ACTIVE_PC"
192 #define device_bar_BDK_OCLAX_ACTIVE_PC(a) 0x0 /* PF_BAR0 */
193 #define busnum_BDK_OCLAX_ACTIVE_PC(a) (a)
194 #define arguments_BDK_OCLAX_ACTIVE_PC(a) (a),-1,-1,-1
195
196 /**
197 * Register (RSL) ocla#_bist_result
198 *
199 * OCLA BIST Result Registers
200 * This register provides access to the internal BIST results. Each bit is the BIST result of an
201 * individual memory (per bit, 0 = pass and 1 = fail).
202 *
203 * Internal:
204 * FIXME remove fields and add deprecated: "RAZ" per MDC common changes.
205 */
206 union bdk_oclax_bist_result
207 {
208 uint64_t u;
209 struct bdk_oclax_bist_result_s
210 {
211 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
212 uint64_t reserved_1_63 : 63;
213 uint64_t dat : 1; /**< [ 0: 0](RO) BIST result of the DAT memory. */
214 #else /* Word 0 - Little Endian */
215 uint64_t dat : 1; /**< [ 0: 0](RO) BIST result of the DAT memory. */
216 uint64_t reserved_1_63 : 63;
217 #endif /* Word 0 - End */
218 } s;
219 /* struct bdk_oclax_bist_result_s cn; */
220 };
221 typedef union bdk_oclax_bist_result bdk_oclax_bist_result_t;
222
223 static inline uint64_t BDK_OCLAX_BIST_RESULT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_BIST_RESULT(unsigned long a)224 static inline uint64_t BDK_OCLAX_BIST_RESULT(unsigned long a)
225 {
226 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
227 return 0x87e0a8000040ll + 0x1000000ll * ((a) & 0x1);
228 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
229 return 0x87e0a8000040ll + 0x1000000ll * ((a) & 0x3);
230 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
231 return 0x87e0a8000040ll + 0x1000000ll * ((a) & 0x7);
232 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
233 return 0x87e0b0000040ll + 0x1000000ll * ((a) & 0x7);
234 __bdk_csr_fatal("OCLAX_BIST_RESULT", 1, a, 0, 0, 0);
235 }
236
237 #define typedef_BDK_OCLAX_BIST_RESULT(a) bdk_oclax_bist_result_t
238 #define bustype_BDK_OCLAX_BIST_RESULT(a) BDK_CSR_TYPE_RSL
239 #define basename_BDK_OCLAX_BIST_RESULT(a) "OCLAX_BIST_RESULT"
240 #define device_bar_BDK_OCLAX_BIST_RESULT(a) 0x0 /* PF_BAR0 */
241 #define busnum_BDK_OCLAX_BIST_RESULT(a) (a)
242 #define arguments_BDK_OCLAX_BIST_RESULT(a) (a),-1,-1,-1
243
244 /**
245 * Register (RSL) ocla#_cdh#_ctl
246 *
247 * OCLA Capture Data Half Control Registers
248 */
249 union bdk_oclax_cdhx_ctl
250 {
251 uint64_t u;
252 struct bdk_oclax_cdhx_ctl_s
253 {
254 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
255 uint64_t reserved_6_63 : 58;
256 uint64_t dup : 1; /**< [ 5: 5](R/W) Retain duplicates in the data stream. */
257 uint64_t dis_stamp : 1; /**< [ 4: 4](R/W) Remove time stamps from data stream. */
258 uint64_t cap_ctl : 4; /**< [ 3: 0](R/W) Minterms that will cause data to be captured. These minterms are the four inputs
259 to a four-to-one mux selected by PLA1 and zero. The output is thus calculated
260 from the equation:
261
262 \<pre\>
263 fsmcap0 = OCLA(0..1)_FSM(0)_STATE[state0][CAP].
264 fsmcap1 = OCLA(0..1)_FSM(1)_STATE[state1][CAP].
265 out = ( (\<3\> & fsmcap1 & fsmcap0)
266 || (\<2\> & fsmcap1 & !fsmcap0)
267 || (\<1\> & !fsmcap1 & fsmcap0)
268 || (\<0\> & !fsmcap1 & !fsmcap0)).
269 \</pre\>
270
271 Common examples:
272 0x0 = No capture.
273 0xA = Capture when fsmcap0 requests capture.
274 0xC = Capture when fsmcap1 requests capture.
275 0x6 = Capture on fsmcap0 EXOR fsmcap1.
276 0x8 = Capture on fsmcap0 & fsmcap1.
277 0xE = Capture on fsmcap0 | fsmcap1.
278 0xF = Always capture. */
279 #else /* Word 0 - Little Endian */
280 uint64_t cap_ctl : 4; /**< [ 3: 0](R/W) Minterms that will cause data to be captured. These minterms are the four inputs
281 to a four-to-one mux selected by PLA1 and zero. The output is thus calculated
282 from the equation:
283
284 \<pre\>
285 fsmcap0 = OCLA(0..1)_FSM(0)_STATE[state0][CAP].
286 fsmcap1 = OCLA(0..1)_FSM(1)_STATE[state1][CAP].
287 out = ( (\<3\> & fsmcap1 & fsmcap0)
288 || (\<2\> & fsmcap1 & !fsmcap0)
289 || (\<1\> & !fsmcap1 & fsmcap0)
290 || (\<0\> & !fsmcap1 & !fsmcap0)).
291 \</pre\>
292
293 Common examples:
294 0x0 = No capture.
295 0xA = Capture when fsmcap0 requests capture.
296 0xC = Capture when fsmcap1 requests capture.
297 0x6 = Capture on fsmcap0 EXOR fsmcap1.
298 0x8 = Capture on fsmcap0 & fsmcap1.
299 0xE = Capture on fsmcap0 | fsmcap1.
300 0xF = Always capture. */
301 uint64_t dis_stamp : 1; /**< [ 4: 4](R/W) Remove time stamps from data stream. */
302 uint64_t dup : 1; /**< [ 5: 5](R/W) Retain duplicates in the data stream. */
303 uint64_t reserved_6_63 : 58;
304 #endif /* Word 0 - End */
305 } s;
306 struct bdk_oclax_cdhx_ctl_cn9
307 {
308 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
309 uint64_t reserved_6_63 : 58;
310 uint64_t dup : 1; /**< [ 5: 5](R/W) Retain duplicates in the data stream. */
311 uint64_t dis_stamp : 1; /**< [ 4: 4](R/W) Remove time stamps from data stream. */
312 uint64_t cap_ctl : 4; /**< [ 3: 0](R/W) Minterms that will cause data to be captured. These minterms are the four inputs
313 to a four-to-one mux selected by PLA1 and zero. The output is thus calculated
314 from the equation:
315
316 \<pre\>
317 fsmcap0 = OCLA(0..4)_FSM(0)_STATE[state0][CAP].
318 fsmcap1 = OCLA(0..4)_FSM(1)_STATE[state1][CAP].
319 out = ( (\<3\> & fsmcap1 & fsmcap0)
320 || (\<2\> & fsmcap1 & !fsmcap0)
321 || (\<1\> & !fsmcap1 & fsmcap0)
322 || (\<0\> & !fsmcap1 & !fsmcap0)).
323 \</pre\>
324
325 Common examples:
326 0x0 = No capture.
327 0xA = Capture when fsmcap0 requests capture.
328 0xC = Capture when fsmcap1 requests capture.
329 0x6 = Capture on fsmcap0 EXOR fsmcap1.
330 0x8 = Capture on fsmcap0 & fsmcap1.
331 0xE = Capture on fsmcap0 | fsmcap1.
332 0xF = Always capture. */
333 #else /* Word 0 - Little Endian */
334 uint64_t cap_ctl : 4; /**< [ 3: 0](R/W) Minterms that will cause data to be captured. These minterms are the four inputs
335 to a four-to-one mux selected by PLA1 and zero. The output is thus calculated
336 from the equation:
337
338 \<pre\>
339 fsmcap0 = OCLA(0..4)_FSM(0)_STATE[state0][CAP].
340 fsmcap1 = OCLA(0..4)_FSM(1)_STATE[state1][CAP].
341 out = ( (\<3\> & fsmcap1 & fsmcap0)
342 || (\<2\> & fsmcap1 & !fsmcap0)
343 || (\<1\> & !fsmcap1 & fsmcap0)
344 || (\<0\> & !fsmcap1 & !fsmcap0)).
345 \</pre\>
346
347 Common examples:
348 0x0 = No capture.
349 0xA = Capture when fsmcap0 requests capture.
350 0xC = Capture when fsmcap1 requests capture.
351 0x6 = Capture on fsmcap0 EXOR fsmcap1.
352 0x8 = Capture on fsmcap0 & fsmcap1.
353 0xE = Capture on fsmcap0 | fsmcap1.
354 0xF = Always capture. */
355 uint64_t dis_stamp : 1; /**< [ 4: 4](R/W) Remove time stamps from data stream. */
356 uint64_t dup : 1; /**< [ 5: 5](R/W) Retain duplicates in the data stream. */
357 uint64_t reserved_6_63 : 58;
358 #endif /* Word 0 - End */
359 } cn9;
360 /* struct bdk_oclax_cdhx_ctl_s cn81xx; */
361 /* struct bdk_oclax_cdhx_ctl_cn9 cn88xx; */
362 struct bdk_oclax_cdhx_ctl_cn83xx
363 {
364 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
365 uint64_t reserved_6_63 : 58;
366 uint64_t dup : 1; /**< [ 5: 5](R/W) Retain duplicates in the data stream. */
367 uint64_t dis_stamp : 1; /**< [ 4: 4](R/W) Remove time stamps from data stream. */
368 uint64_t cap_ctl : 4; /**< [ 3: 0](R/W) Minterms that will cause data to be captured. These minterms are the four inputs
369 to a four-to-one mux selected by PLA1 and zero. The output is thus calculated
370 from the equation:
371
372 \<pre\>
373 fsmcap0 = OCLA(0..2)_FSM(0)_STATE[state0][CAP].
374 fsmcap1 = OCLA(0..2)_FSM(1)_STATE[state1][CAP].
375 out = ( (\<3\> & fsmcap1 & fsmcap0)
376 || (\<2\> & fsmcap1 & !fsmcap0)
377 || (\<1\> & !fsmcap1 & fsmcap0)
378 || (\<0\> & !fsmcap1 & !fsmcap0)).
379 \</pre\>
380
381 Common examples:
382 0x0 = No capture.
383 0xA = Capture when fsmcap0 requests capture.
384 0xC = Capture when fsmcap1 requests capture.
385 0x6 = Capture on fsmcap0 EXOR fsmcap1.
386 0x8 = Capture on fsmcap0 & fsmcap1.
387 0xE = Capture on fsmcap0 | fsmcap1.
388 0xF = Always capture. */
389 #else /* Word 0 - Little Endian */
390 uint64_t cap_ctl : 4; /**< [ 3: 0](R/W) Minterms that will cause data to be captured. These minterms are the four inputs
391 to a four-to-one mux selected by PLA1 and zero. The output is thus calculated
392 from the equation:
393
394 \<pre\>
395 fsmcap0 = OCLA(0..2)_FSM(0)_STATE[state0][CAP].
396 fsmcap1 = OCLA(0..2)_FSM(1)_STATE[state1][CAP].
397 out = ( (\<3\> & fsmcap1 & fsmcap0)
398 || (\<2\> & fsmcap1 & !fsmcap0)
399 || (\<1\> & !fsmcap1 & fsmcap0)
400 || (\<0\> & !fsmcap1 & !fsmcap0)).
401 \</pre\>
402
403 Common examples:
404 0x0 = No capture.
405 0xA = Capture when fsmcap0 requests capture.
406 0xC = Capture when fsmcap1 requests capture.
407 0x6 = Capture on fsmcap0 EXOR fsmcap1.
408 0x8 = Capture on fsmcap0 & fsmcap1.
409 0xE = Capture on fsmcap0 | fsmcap1.
410 0xF = Always capture. */
411 uint64_t dis_stamp : 1; /**< [ 4: 4](R/W) Remove time stamps from data stream. */
412 uint64_t dup : 1; /**< [ 5: 5](R/W) Retain duplicates in the data stream. */
413 uint64_t reserved_6_63 : 58;
414 #endif /* Word 0 - End */
415 } cn83xx;
416 };
417 typedef union bdk_oclax_cdhx_ctl bdk_oclax_cdhx_ctl_t;
418
419 static inline uint64_t BDK_OCLAX_CDHX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_CDHX_CTL(unsigned long a,unsigned long b)420 static inline uint64_t BDK_OCLAX_CDHX_CTL(unsigned long a, unsigned long b)
421 {
422 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=1)))
423 return 0x87e0a8000600ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1);
424 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=1)))
425 return 0x87e0a8000600ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x1);
426 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=1)))
427 return 0x87e0a8000600ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x1);
428 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=1)))
429 return 0x87e0b0000600ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x1);
430 __bdk_csr_fatal("OCLAX_CDHX_CTL", 2, a, b, 0, 0);
431 }
432
433 #define typedef_BDK_OCLAX_CDHX_CTL(a,b) bdk_oclax_cdhx_ctl_t
434 #define bustype_BDK_OCLAX_CDHX_CTL(a,b) BDK_CSR_TYPE_RSL
435 #define basename_BDK_OCLAX_CDHX_CTL(a,b) "OCLAX_CDHX_CTL"
436 #define device_bar_BDK_OCLAX_CDHX_CTL(a,b) 0x0 /* PF_BAR0 */
437 #define busnum_BDK_OCLAX_CDHX_CTL(a,b) (a)
438 #define arguments_BDK_OCLAX_CDHX_CTL(a,b) (a),(b),-1,-1
439
440 /**
441 * Register (RSL) ocla#_cdh#_inject_state
442 *
443 * OCLA Capture Inject State Register
444 * This register allows various state inputs to be inserted into the captured stream
445 * data, to assist debugging of OCLA FSMs. Each input has two insertion positions
446 * (i.e. [MCD] and [ALT_MCD]), so that some of the normal non-inject capture stream data
447 * may still be observable.
448 */
449 union bdk_oclax_cdhx_inject_state
450 {
451 uint64_t u;
452 struct bdk_oclax_cdhx_inject_state_s
453 {
454 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
455 uint64_t reserved_32_63 : 32;
456 uint64_t alt_trig : 1; /**< [ 31: 31](R/W) When set, insert FSM trigger input into captured stream \<31\>. */
457 uint64_t alt_mcd : 3; /**< [ 30: 28](R/W) When set, insert multichip debug (MCD) 0..2 FSM inputs into captured stream \<30:28\>. */
458 uint64_t alt_match : 4; /**< [ 27: 24](R/W) When set, insert matcher FSM inputs into captured stream \<27:24\>. */
459 uint64_t alt_fsm1_state : 4; /**< [ 23: 20](R/W) When set, insert FSM 1 state input into captured stream \<23:20\>. */
460 uint64_t alt_fsm0_state : 4; /**< [ 19: 16](R/W) When set, insert FSM 0 state input into captured stream \<19:16\>. */
461 uint64_t trig : 1; /**< [ 15: 15](R/W) When set, insert FSM trigger input into captured stream \<15\>. */
462 uint64_t mcd : 3; /**< [ 14: 12](R/W) When set, insert multichip debug (MCD) 0..2 FSM inputs into captured stream \<14:12\>. */
463 uint64_t match : 4; /**< [ 11: 8](R/W) When set, insert matcher FSM inputs into captured stream \<11:8\>. */
464 uint64_t fsm1_state : 4; /**< [ 7: 4](R/W) When set, insert FSM 1 state input into captured stream \<7:4\>. */
465 uint64_t fsm0_state : 4; /**< [ 3: 0](R/W) When set, insert FSM 0 state input into captured stream \<3:0\>. */
466 #else /* Word 0 - Little Endian */
467 uint64_t fsm0_state : 4; /**< [ 3: 0](R/W) When set, insert FSM 0 state input into captured stream \<3:0\>. */
468 uint64_t fsm1_state : 4; /**< [ 7: 4](R/W) When set, insert FSM 1 state input into captured stream \<7:4\>. */
469 uint64_t match : 4; /**< [ 11: 8](R/W) When set, insert matcher FSM inputs into captured stream \<11:8\>. */
470 uint64_t mcd : 3; /**< [ 14: 12](R/W) When set, insert multichip debug (MCD) 0..2 FSM inputs into captured stream \<14:12\>. */
471 uint64_t trig : 1; /**< [ 15: 15](R/W) When set, insert FSM trigger input into captured stream \<15\>. */
472 uint64_t alt_fsm0_state : 4; /**< [ 19: 16](R/W) When set, insert FSM 0 state input into captured stream \<19:16\>. */
473 uint64_t alt_fsm1_state : 4; /**< [ 23: 20](R/W) When set, insert FSM 1 state input into captured stream \<23:20\>. */
474 uint64_t alt_match : 4; /**< [ 27: 24](R/W) When set, insert matcher FSM inputs into captured stream \<27:24\>. */
475 uint64_t alt_mcd : 3; /**< [ 30: 28](R/W) When set, insert multichip debug (MCD) 0..2 FSM inputs into captured stream \<30:28\>. */
476 uint64_t alt_trig : 1; /**< [ 31: 31](R/W) When set, insert FSM trigger input into captured stream \<31\>. */
477 uint64_t reserved_32_63 : 32;
478 #endif /* Word 0 - End */
479 } s;
480 /* struct bdk_oclax_cdhx_inject_state_s cn; */
481 };
482 typedef union bdk_oclax_cdhx_inject_state bdk_oclax_cdhx_inject_state_t;
483
484 static inline uint64_t BDK_OCLAX_CDHX_INJECT_STATE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_CDHX_INJECT_STATE(unsigned long a,unsigned long b)485 static inline uint64_t BDK_OCLAX_CDHX_INJECT_STATE(unsigned long a, unsigned long b)
486 {
487 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=1)))
488 return 0x87e0b0000610ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x1);
489 __bdk_csr_fatal("OCLAX_CDHX_INJECT_STATE", 2, a, b, 0, 0);
490 }
491
492 #define typedef_BDK_OCLAX_CDHX_INJECT_STATE(a,b) bdk_oclax_cdhx_inject_state_t
493 #define bustype_BDK_OCLAX_CDHX_INJECT_STATE(a,b) BDK_CSR_TYPE_RSL
494 #define basename_BDK_OCLAX_CDHX_INJECT_STATE(a,b) "OCLAX_CDHX_INJECT_STATE"
495 #define device_bar_BDK_OCLAX_CDHX_INJECT_STATE(a,b) 0x0 /* PF_BAR0 */
496 #define busnum_BDK_OCLAX_CDHX_INJECT_STATE(a,b) (a)
497 #define arguments_BDK_OCLAX_CDHX_INJECT_STATE(a,b) (a),(b),-1,-1
498
499 /**
500 * Register (RSL) ocla#_const
501 *
502 * OCLA Constants Registers
503 * Internal:
504 * FIXME add new NO_DDR bit \<16\> which is RO 0, indicating:
505 *
506 * No DDR supported.
507 * 0 = DDR dumping is supported, the OCLA()_STACK* registers exist and function.
508 * 1 = DDR dumping is not supported.
509 */
510 union bdk_oclax_const
511 {
512 uint64_t u;
513 struct bdk_oclax_const_s
514 {
515 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
516 uint64_t reserved_16_63 : 48;
517 uint64_t dat_size : 16; /**< [ 15: 0](RO) Size of data RAM in units of 36-bit entries. This value is subject to change between chip
518 passes, and software should thus use this value rather than a hard coded constant.
519 OCLA(0..1) size is 4096, OCLA(2) size is 8192. */
520 #else /* Word 0 - Little Endian */
521 uint64_t dat_size : 16; /**< [ 15: 0](RO) Size of data RAM in units of 36-bit entries. This value is subject to change between chip
522 passes, and software should thus use this value rather than a hard coded constant.
523 OCLA(0..1) size is 4096, OCLA(2) size is 8192. */
524 uint64_t reserved_16_63 : 48;
525 #endif /* Word 0 - End */
526 } s;
527 struct bdk_oclax_const_cn9
528 {
529 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
530 uint64_t reserved_16_63 : 48;
531 uint64_t dat_size : 16; /**< [ 15: 0](RO) Size of data RAM in units of 36-bit entries. This value is subject to change between chip
532 passes, and software should thus use this value rather than a hard coded constant.
533 OCLA(0..3) size is 4096, OCLA(4) size is 16384. */
534 #else /* Word 0 - Little Endian */
535 uint64_t dat_size : 16; /**< [ 15: 0](RO) Size of data RAM in units of 36-bit entries. This value is subject to change between chip
536 passes, and software should thus use this value rather than a hard coded constant.
537 OCLA(0..3) size is 4096, OCLA(4) size is 16384. */
538 uint64_t reserved_16_63 : 48;
539 #endif /* Word 0 - End */
540 } cn9;
541 /* struct bdk_oclax_const_s cn81xx; */
542 struct bdk_oclax_const_cn88xx
543 {
544 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
545 uint64_t reserved_16_63 : 48;
546 uint64_t dat_size : 16; /**< [ 15: 0](RO) Size of data RAM in units of 36-bit entries. This value is subject to change between chip
547 passes, and software should thus use this value rather than a hard coded constant.
548 OCLA(0..3) size is 4096, OCLA(4) size is 8192. */
549 #else /* Word 0 - Little Endian */
550 uint64_t dat_size : 16; /**< [ 15: 0](RO) Size of data RAM in units of 36-bit entries. This value is subject to change between chip
551 passes, and software should thus use this value rather than a hard coded constant.
552 OCLA(0..3) size is 4096, OCLA(4) size is 8192. */
553 uint64_t reserved_16_63 : 48;
554 #endif /* Word 0 - End */
555 } cn88xx;
556 /* struct bdk_oclax_const_s cn83xx; */
557 };
558 typedef union bdk_oclax_const bdk_oclax_const_t;
559
560 static inline uint64_t BDK_OCLAX_CONST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_CONST(unsigned long a)561 static inline uint64_t BDK_OCLAX_CONST(unsigned long a)
562 {
563 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
564 return 0x87e0a8000000ll + 0x1000000ll * ((a) & 0x1);
565 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
566 return 0x87e0a8000000ll + 0x1000000ll * ((a) & 0x3);
567 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
568 return 0x87e0a8000000ll + 0x1000000ll * ((a) & 0x7);
569 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
570 return 0x87e0b0000000ll + 0x1000000ll * ((a) & 0x7);
571 __bdk_csr_fatal("OCLAX_CONST", 1, a, 0, 0, 0);
572 }
573
574 #define typedef_BDK_OCLAX_CONST(a) bdk_oclax_const_t
575 #define bustype_BDK_OCLAX_CONST(a) BDK_CSR_TYPE_RSL
576 #define basename_BDK_OCLAX_CONST(a) "OCLAX_CONST"
577 #define device_bar_BDK_OCLAX_CONST(a) 0x0 /* PF_BAR0 */
578 #define busnum_BDK_OCLAX_CONST(a) (a)
579 #define arguments_BDK_OCLAX_CONST(a) (a),-1,-1,-1
580
581 /**
582 * Register (RSL) ocla#_dat#
583 *
584 * OCLA Data Registers
585 */
586 union bdk_oclax_datx
587 {
588 uint64_t u;
589 struct bdk_oclax_datx_s
590 {
591 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
592 uint64_t reserved_38_63 : 26;
593 uint64_t entry : 38; /**< [ 37: 0](RO/H) Captured entry. Data is in the format described by OCLA_CAP_DAT_S or OCLA_CAP_CTL_S. */
594 #else /* Word 0 - Little Endian */
595 uint64_t entry : 38; /**< [ 37: 0](RO/H) Captured entry. Data is in the format described by OCLA_CAP_DAT_S or OCLA_CAP_CTL_S. */
596 uint64_t reserved_38_63 : 26;
597 #endif /* Word 0 - End */
598 } s;
599 /* struct bdk_oclax_datx_s cn; */
600 };
601 typedef union bdk_oclax_datx bdk_oclax_datx_t;
602
603 static inline uint64_t BDK_OCLAX_DATX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_DATX(unsigned long a,unsigned long b)604 static inline uint64_t BDK_OCLAX_DATX(unsigned long a, unsigned long b)
605 {
606 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=8191)))
607 return 0x87e0a8400000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1fff);
608 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=8191)))
609 return 0x87e0a8400000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x1fff);
610 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=8191)))
611 return 0x87e0a8400000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x1fff);
612 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=16383)))
613 return 0x87e0b0400000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x3fff);
614 __bdk_csr_fatal("OCLAX_DATX", 2, a, b, 0, 0);
615 }
616
617 #define typedef_BDK_OCLAX_DATX(a,b) bdk_oclax_datx_t
618 #define bustype_BDK_OCLAX_DATX(a,b) BDK_CSR_TYPE_RSL
619 #define basename_BDK_OCLAX_DATX(a,b) "OCLAX_DATX"
620 #define device_bar_BDK_OCLAX_DATX(a,b) 0x0 /* PF_BAR0 */
621 #define busnum_BDK_OCLAX_DATX(a,b) (a)
622 #define arguments_BDK_OCLAX_DATX(a,b) (a),(b),-1,-1
623
624 /**
625 * Register (RSL) ocla#_dat_pop
626 *
627 * OCLA Data Pop Registers
628 */
629 union bdk_oclax_dat_pop
630 {
631 uint64_t u;
632 struct bdk_oclax_dat_pop_s
633 {
634 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
635 uint64_t valid : 1; /**< [ 63: 63](RC/H) Valid entry. Indicates the FIFO contains data, and equivalent to OCLA()_FIFO_DEPTH[DEPTH] != 0. */
636 uint64_t trig : 1; /**< [ 62: 62](RO/H) Internal trigger set. Equivalent to OCLA()_STATE_INT[TRIG]. */
637 uint64_t wmark : 1; /**< [ 61: 61](RO/H) Internal buffer watermark reached. Equivalent to OCLA()_STATE_INT[WMARK]. */
638 uint64_t reserved_38_60 : 23;
639 uint64_t entry : 38; /**< [ 37: 0](RC/H) Captured entry. If [VALID] is set, has read side effect of unloading data by decrementing
640 OCLA()_FIFO_DEPTH[DEPTH]. Data is in the format described by OCLA_CAP_DAT_S or
641 OCLA_CAP_CTL_S.
642
643 Note that unloading data will cause that data not to be sent to memory, therefore
644 OCLA()_DAT_POP should not be read when OCLA()_FIFO_LIMIT[DDR] != all-ones. */
645 #else /* Word 0 - Little Endian */
646 uint64_t entry : 38; /**< [ 37: 0](RC/H) Captured entry. If [VALID] is set, has read side effect of unloading data by decrementing
647 OCLA()_FIFO_DEPTH[DEPTH]. Data is in the format described by OCLA_CAP_DAT_S or
648 OCLA_CAP_CTL_S.
649
650 Note that unloading data will cause that data not to be sent to memory, therefore
651 OCLA()_DAT_POP should not be read when OCLA()_FIFO_LIMIT[DDR] != all-ones. */
652 uint64_t reserved_38_60 : 23;
653 uint64_t wmark : 1; /**< [ 61: 61](RO/H) Internal buffer watermark reached. Equivalent to OCLA()_STATE_INT[WMARK]. */
654 uint64_t trig : 1; /**< [ 62: 62](RO/H) Internal trigger set. Equivalent to OCLA()_STATE_INT[TRIG]. */
655 uint64_t valid : 1; /**< [ 63: 63](RC/H) Valid entry. Indicates the FIFO contains data, and equivalent to OCLA()_FIFO_DEPTH[DEPTH] != 0. */
656 #endif /* Word 0 - End */
657 } s;
658 /* struct bdk_oclax_dat_pop_s cn; */
659 };
660 typedef union bdk_oclax_dat_pop bdk_oclax_dat_pop_t;
661
662 static inline uint64_t BDK_OCLAX_DAT_POP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_DAT_POP(unsigned long a)663 static inline uint64_t BDK_OCLAX_DAT_POP(unsigned long a)
664 {
665 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
666 return 0x87e0a8000800ll + 0x1000000ll * ((a) & 0x1);
667 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
668 return 0x87e0a8000800ll + 0x1000000ll * ((a) & 0x3);
669 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
670 return 0x87e0a8000800ll + 0x1000000ll * ((a) & 0x7);
671 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
672 return 0x87e0b0000800ll + 0x1000000ll * ((a) & 0x7);
673 __bdk_csr_fatal("OCLAX_DAT_POP", 1, a, 0, 0, 0);
674 }
675
676 #define typedef_BDK_OCLAX_DAT_POP(a) bdk_oclax_dat_pop_t
677 #define bustype_BDK_OCLAX_DAT_POP(a) BDK_CSR_TYPE_RSL
678 #define basename_BDK_OCLAX_DAT_POP(a) "OCLAX_DAT_POP"
679 #define device_bar_BDK_OCLAX_DAT_POP(a) 0x0 /* PF_BAR0 */
680 #define busnum_BDK_OCLAX_DAT_POP(a) (a)
681 #define arguments_BDK_OCLAX_DAT_POP(a) (a),-1,-1,-1
682
683 /**
684 * Register (RSL) ocla#_eco
685 *
686 * INTERNAL: OCLA ECO Register
687 */
688 union bdk_oclax_eco
689 {
690 uint64_t u;
691 struct bdk_oclax_eco_s
692 {
693 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
694 uint64_t reserved_32_63 : 32;
695 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) Internal:
696 Reserved for ECO usage. */
697 #else /* Word 0 - Little Endian */
698 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) Internal:
699 Reserved for ECO usage. */
700 uint64_t reserved_32_63 : 32;
701 #endif /* Word 0 - End */
702 } s;
703 /* struct bdk_oclax_eco_s cn; */
704 };
705 typedef union bdk_oclax_eco bdk_oclax_eco_t;
706
707 static inline uint64_t BDK_OCLAX_ECO(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_ECO(unsigned long a)708 static inline uint64_t BDK_OCLAX_ECO(unsigned long a)
709 {
710 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
711 return 0x87e0a83200d0ll + 0x1000000ll * ((a) & 0x1);
712 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
713 return 0x87e0a83200d0ll + 0x1000000ll * ((a) & 0x3);
714 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && (a<=4))
715 return 0x87e0a83200d0ll + 0x1000000ll * ((a) & 0x7);
716 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
717 return 0x87e0b00000d0ll + 0x1000000ll * ((a) & 0x7);
718 __bdk_csr_fatal("OCLAX_ECO", 1, a, 0, 0, 0);
719 }
720
721 #define typedef_BDK_OCLAX_ECO(a) bdk_oclax_eco_t
722 #define bustype_BDK_OCLAX_ECO(a) BDK_CSR_TYPE_RSL
723 #define basename_BDK_OCLAX_ECO(a) "OCLAX_ECO"
724 #define device_bar_BDK_OCLAX_ECO(a) 0x0 /* PF_BAR0 */
725 #define busnum_BDK_OCLAX_ECO(a) (a)
726 #define arguments_BDK_OCLAX_ECO(a) (a),-1,-1,-1
727
728 /**
729 * Register (RSL) ocla#_fifo_depth
730 *
731 * OCLA Capture FIFO Depth Registers
732 */
733 union bdk_oclax_fifo_depth
734 {
735 uint64_t u;
736 struct bdk_oclax_fifo_depth_s
737 {
738 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
739 uint64_t reserved_16_63 : 48;
740 uint64_t depth : 16; /**< [ 15: 0](RO/H) Current capture FIFO depth in 36-bit words. */
741 #else /* Word 0 - Little Endian */
742 uint64_t depth : 16; /**< [ 15: 0](RO/H) Current capture FIFO depth in 36-bit words. */
743 uint64_t reserved_16_63 : 48;
744 #endif /* Word 0 - End */
745 } s;
746 /* struct bdk_oclax_fifo_depth_s cn; */
747 };
748 typedef union bdk_oclax_fifo_depth bdk_oclax_fifo_depth_t;
749
750 static inline uint64_t BDK_OCLAX_FIFO_DEPTH(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_FIFO_DEPTH(unsigned long a)751 static inline uint64_t BDK_OCLAX_FIFO_DEPTH(unsigned long a)
752 {
753 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
754 return 0x87e0a8000200ll + 0x1000000ll * ((a) & 0x1);
755 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
756 return 0x87e0a8000200ll + 0x1000000ll * ((a) & 0x3);
757 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
758 return 0x87e0a8000200ll + 0x1000000ll * ((a) & 0x7);
759 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
760 return 0x87e0b0000200ll + 0x1000000ll * ((a) & 0x7);
761 __bdk_csr_fatal("OCLAX_FIFO_DEPTH", 1, a, 0, 0, 0);
762 }
763
764 #define typedef_BDK_OCLAX_FIFO_DEPTH(a) bdk_oclax_fifo_depth_t
765 #define bustype_BDK_OCLAX_FIFO_DEPTH(a) BDK_CSR_TYPE_RSL
766 #define basename_BDK_OCLAX_FIFO_DEPTH(a) "OCLAX_FIFO_DEPTH"
767 #define device_bar_BDK_OCLAX_FIFO_DEPTH(a) 0x0 /* PF_BAR0 */
768 #define busnum_BDK_OCLAX_FIFO_DEPTH(a) (a)
769 #define arguments_BDK_OCLAX_FIFO_DEPTH(a) (a),-1,-1,-1
770
771 /**
772 * Register (RSL) ocla#_fifo_limit
773 *
774 * OCLA Capture FIFO Limit Registers
775 */
776 union bdk_oclax_fifo_limit
777 {
778 uint64_t u;
779 struct bdk_oclax_fifo_limit_s
780 {
781 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
782 uint64_t overfull : 16; /**< [ 63: 48](R/W) Stop level. When OCLA()_FIFO_DEPTH \> [OVERFULL], stop capturing and set
783 OCLA()_STATE_INT[OVERFULL]. This should be set to no more than
784 OCLA()_CONST[DAT_SIZE] minus 26 when using DDR capture to insure that overflow can be
785 detected. */
786 uint64_t ddr : 16; /**< [ 47: 32](R/W) DDR level. When OCLA()_FIFO_DEPTH \> [DDR], FIFO entries will be removed, packed into a
787 cache line, and overflowed to DDR/L2. All-ones disables overflow to DDR/L2. If nonzero
788 must be at least 52. */
789 uint64_t bp : 16; /**< [ 31: 16](R/W) Backpressure level. When OCLA()_FIFO_DEPTH \> [BP], OCLA will signal backpressure to
790 coprocessors. All-ones disables indicating backpressure. */
791 uint64_t wmark : 16; /**< [ 15: 0](R/W) Interrupt watermark level. When OCLA()_FIFO_DEPTH \> [WMARK], OCLA will set
792 OCLA()_STATE_INT[WMARK] interrupt. All-ones disables setting the interrupt. */
793 #else /* Word 0 - Little Endian */
794 uint64_t wmark : 16; /**< [ 15: 0](R/W) Interrupt watermark level. When OCLA()_FIFO_DEPTH \> [WMARK], OCLA will set
795 OCLA()_STATE_INT[WMARK] interrupt. All-ones disables setting the interrupt. */
796 uint64_t bp : 16; /**< [ 31: 16](R/W) Backpressure level. When OCLA()_FIFO_DEPTH \> [BP], OCLA will signal backpressure to
797 coprocessors. All-ones disables indicating backpressure. */
798 uint64_t ddr : 16; /**< [ 47: 32](R/W) DDR level. When OCLA()_FIFO_DEPTH \> [DDR], FIFO entries will be removed, packed into a
799 cache line, and overflowed to DDR/L2. All-ones disables overflow to DDR/L2. If nonzero
800 must be at least 52. */
801 uint64_t overfull : 16; /**< [ 63: 48](R/W) Stop level. When OCLA()_FIFO_DEPTH \> [OVERFULL], stop capturing and set
802 OCLA()_STATE_INT[OVERFULL]. This should be set to no more than
803 OCLA()_CONST[DAT_SIZE] minus 26 when using DDR capture to insure that overflow can be
804 detected. */
805 #endif /* Word 0 - End */
806 } s;
807 /* struct bdk_oclax_fifo_limit_s cn8; */
808 struct bdk_oclax_fifo_limit_cn9
809 {
810 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
811 uint64_t overfull : 16; /**< [ 63: 48](R/W) Stop level. When OCLA()_FIFO_DEPTH \> [OVERFULL], stop capturing and set
812 OCLA()_STATE_INT[OVERFULL]. This should be set to no more than
813 OCLA()_CONST[DAT_SIZE] minus 26 when using DDR capture to insure that overflow can be
814 detected. */
815 uint64_t ddr : 16; /**< [ 47: 32](R/W) DDR level. When OCLA()_FIFO_DEPTH \> [DDR], FIFO entries will be removed, packed into a
816 cache line, and overflowed to LLC/DRAM. All-ones disables overflow to DDR/L2. If nonzero
817 must be at least 52. */
818 uint64_t bp : 16; /**< [ 31: 16](R/W) Backpressure level. When OCLA()_FIFO_DEPTH \> [BP], OCLA will signal backpressure to
819 coprocessors. All-ones disables indicating backpressure. */
820 uint64_t wmark : 16; /**< [ 15: 0](R/W) Interrupt watermark level. When OCLA()_FIFO_DEPTH \> [WMARK], OCLA will set
821 OCLA()_STATE_INT[WMARK] interrupt. All-ones disables setting the interrupt. */
822 #else /* Word 0 - Little Endian */
823 uint64_t wmark : 16; /**< [ 15: 0](R/W) Interrupt watermark level. When OCLA()_FIFO_DEPTH \> [WMARK], OCLA will set
824 OCLA()_STATE_INT[WMARK] interrupt. All-ones disables setting the interrupt. */
825 uint64_t bp : 16; /**< [ 31: 16](R/W) Backpressure level. When OCLA()_FIFO_DEPTH \> [BP], OCLA will signal backpressure to
826 coprocessors. All-ones disables indicating backpressure. */
827 uint64_t ddr : 16; /**< [ 47: 32](R/W) DDR level. When OCLA()_FIFO_DEPTH \> [DDR], FIFO entries will be removed, packed into a
828 cache line, and overflowed to LLC/DRAM. All-ones disables overflow to DDR/L2. If nonzero
829 must be at least 52. */
830 uint64_t overfull : 16; /**< [ 63: 48](R/W) Stop level. When OCLA()_FIFO_DEPTH \> [OVERFULL], stop capturing and set
831 OCLA()_STATE_INT[OVERFULL]. This should be set to no more than
832 OCLA()_CONST[DAT_SIZE] minus 26 when using DDR capture to insure that overflow can be
833 detected. */
834 #endif /* Word 0 - End */
835 } cn9;
836 };
837 typedef union bdk_oclax_fifo_limit bdk_oclax_fifo_limit_t;
838
839 static inline uint64_t BDK_OCLAX_FIFO_LIMIT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_FIFO_LIMIT(unsigned long a)840 static inline uint64_t BDK_OCLAX_FIFO_LIMIT(unsigned long a)
841 {
842 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
843 return 0x87e0a8000240ll + 0x1000000ll * ((a) & 0x1);
844 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
845 return 0x87e0a8000240ll + 0x1000000ll * ((a) & 0x3);
846 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
847 return 0x87e0a8000240ll + 0x1000000ll * ((a) & 0x7);
848 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
849 return 0x87e0b0000240ll + 0x1000000ll * ((a) & 0x7);
850 __bdk_csr_fatal("OCLAX_FIFO_LIMIT", 1, a, 0, 0, 0);
851 }
852
853 #define typedef_BDK_OCLAX_FIFO_LIMIT(a) bdk_oclax_fifo_limit_t
854 #define bustype_BDK_OCLAX_FIFO_LIMIT(a) BDK_CSR_TYPE_RSL
855 #define basename_BDK_OCLAX_FIFO_LIMIT(a) "OCLAX_FIFO_LIMIT"
856 #define device_bar_BDK_OCLAX_FIFO_LIMIT(a) 0x0 /* PF_BAR0 */
857 #define busnum_BDK_OCLAX_FIFO_LIMIT(a) (a)
858 #define arguments_BDK_OCLAX_FIFO_LIMIT(a) (a),-1,-1,-1
859
860 /**
861 * Register (RSL) ocla#_fifo_tail
862 *
863 * OCLA Capture FIFO Tail Registers
864 */
865 union bdk_oclax_fifo_tail
866 {
867 uint64_t u;
868 struct bdk_oclax_fifo_tail_s
869 {
870 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
871 uint64_t reserved_16_63 : 48;
872 uint64_t tail : 16; /**< [ 15: 0](RO/H) Address last written into entry FIFO. */
873 #else /* Word 0 - Little Endian */
874 uint64_t tail : 16; /**< [ 15: 0](RO/H) Address last written into entry FIFO. */
875 uint64_t reserved_16_63 : 48;
876 #endif /* Word 0 - End */
877 } s;
878 /* struct bdk_oclax_fifo_tail_s cn; */
879 };
880 typedef union bdk_oclax_fifo_tail bdk_oclax_fifo_tail_t;
881
882 static inline uint64_t BDK_OCLAX_FIFO_TAIL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_FIFO_TAIL(unsigned long a)883 static inline uint64_t BDK_OCLAX_FIFO_TAIL(unsigned long a)
884 {
885 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
886 return 0x87e0a8000260ll + 0x1000000ll * ((a) & 0x1);
887 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
888 return 0x87e0a8000260ll + 0x1000000ll * ((a) & 0x3);
889 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
890 return 0x87e0a8000260ll + 0x1000000ll * ((a) & 0x7);
891 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
892 return 0x87e0b0000260ll + 0x1000000ll * ((a) & 0x7);
893 __bdk_csr_fatal("OCLAX_FIFO_TAIL", 1, a, 0, 0, 0);
894 }
895
896 #define typedef_BDK_OCLAX_FIFO_TAIL(a) bdk_oclax_fifo_tail_t
897 #define bustype_BDK_OCLAX_FIFO_TAIL(a) BDK_CSR_TYPE_RSL
898 #define basename_BDK_OCLAX_FIFO_TAIL(a) "OCLAX_FIFO_TAIL"
899 #define device_bar_BDK_OCLAX_FIFO_TAIL(a) 0x0 /* PF_BAR0 */
900 #define busnum_BDK_OCLAX_FIFO_TAIL(a) (a)
901 #define arguments_BDK_OCLAX_FIFO_TAIL(a) (a),-1,-1,-1
902
903 /**
904 * Register (RSL) ocla#_fifo_trig
905 *
906 * OCLA Capture FIFO Trigger Level Registers
907 */
908 union bdk_oclax_fifo_trig
909 {
910 uint64_t u;
911 struct bdk_oclax_fifo_trig_s
912 {
913 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
914 uint64_t reserved_32_63 : 32;
915 uint64_t limit : 16; /**< [ 31: 16](R/W) Post-trigger number of entries to collect before stopping collection. If zero, collection
916 will never stop, which may be desirable when overflowing to DDR/L2. Must be \<
917 OCLA()_CONST[DAT_SIZE] - 5. */
918 uint64_t cnt : 16; /**< [ 15: 0](R/W/H) Number of entries collected since trigger. Cleared when OCLA()_STATE_INT[TRIG] clear. */
919 #else /* Word 0 - Little Endian */
920 uint64_t cnt : 16; /**< [ 15: 0](R/W/H) Number of entries collected since trigger. Cleared when OCLA()_STATE_INT[TRIG] clear. */
921 uint64_t limit : 16; /**< [ 31: 16](R/W) Post-trigger number of entries to collect before stopping collection. If zero, collection
922 will never stop, which may be desirable when overflowing to DDR/L2. Must be \<
923 OCLA()_CONST[DAT_SIZE] - 5. */
924 uint64_t reserved_32_63 : 32;
925 #endif /* Word 0 - End */
926 } s;
927 /* struct bdk_oclax_fifo_trig_s cn8; */
928 struct bdk_oclax_fifo_trig_cn9
929 {
930 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
931 uint64_t reserved_32_63 : 32;
932 uint64_t limit : 16; /**< [ 31: 16](R/W) Post-trigger number of entries to collect before stopping collection. If zero, collection
933 will never stop, which may be desirable when overflowing to LLC/DRAM. Must be \<
934 OCLA()_CONST[DAT_SIZE] - 5. */
935 uint64_t cnt : 16; /**< [ 15: 0](R/W/H) Number of entries collected since trigger. Cleared when OCLA()_STATE_INT[TRIG] clear. */
936 #else /* Word 0 - Little Endian */
937 uint64_t cnt : 16; /**< [ 15: 0](R/W/H) Number of entries collected since trigger. Cleared when OCLA()_STATE_INT[TRIG] clear. */
938 uint64_t limit : 16; /**< [ 31: 16](R/W) Post-trigger number of entries to collect before stopping collection. If zero, collection
939 will never stop, which may be desirable when overflowing to LLC/DRAM. Must be \<
940 OCLA()_CONST[DAT_SIZE] - 5. */
941 uint64_t reserved_32_63 : 32;
942 #endif /* Word 0 - End */
943 } cn9;
944 };
945 typedef union bdk_oclax_fifo_trig bdk_oclax_fifo_trig_t;
946
947 static inline uint64_t BDK_OCLAX_FIFO_TRIG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_FIFO_TRIG(unsigned long a)948 static inline uint64_t BDK_OCLAX_FIFO_TRIG(unsigned long a)
949 {
950 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
951 return 0x87e0a80002a0ll + 0x1000000ll * ((a) & 0x1);
952 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
953 return 0x87e0a80002a0ll + 0x1000000ll * ((a) & 0x3);
954 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
955 return 0x87e0a80002a0ll + 0x1000000ll * ((a) & 0x7);
956 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
957 return 0x87e0b00002a0ll + 0x1000000ll * ((a) & 0x7);
958 __bdk_csr_fatal("OCLAX_FIFO_TRIG", 1, a, 0, 0, 0);
959 }
960
961 #define typedef_BDK_OCLAX_FIFO_TRIG(a) bdk_oclax_fifo_trig_t
962 #define bustype_BDK_OCLAX_FIFO_TRIG(a) BDK_CSR_TYPE_RSL
963 #define basename_BDK_OCLAX_FIFO_TRIG(a) "OCLAX_FIFO_TRIG"
964 #define device_bar_BDK_OCLAX_FIFO_TRIG(a) 0x0 /* PF_BAR0 */
965 #define busnum_BDK_OCLAX_FIFO_TRIG(a) (a)
966 #define arguments_BDK_OCLAX_FIFO_TRIG(a) (a),-1,-1,-1
967
968 /**
969 * Register (RSL) ocla#_fifo_wrap
970 *
971 * OCLA Capture FIFO Wrap Counter Registers
972 */
973 union bdk_oclax_fifo_wrap
974 {
975 uint64_t u;
976 struct bdk_oclax_fifo_wrap_s
977 {
978 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
979 uint64_t reserved_32_63 : 32;
980 uint64_t wraps : 32; /**< [ 31: 0](R/W/H) Number of times FIFO has wrapped since trigger.
981 Cleared when OCLA()_STATE_INT[TRIG] is clear.
982 This count has a one cycle lag observing when a trigger event occurs. */
983 #else /* Word 0 - Little Endian */
984 uint64_t wraps : 32; /**< [ 31: 0](R/W/H) Number of times FIFO has wrapped since trigger.
985 Cleared when OCLA()_STATE_INT[TRIG] is clear.
986 This count has a one cycle lag observing when a trigger event occurs. */
987 uint64_t reserved_32_63 : 32;
988 #endif /* Word 0 - End */
989 } s;
990 /* struct bdk_oclax_fifo_wrap_s cn; */
991 };
992 typedef union bdk_oclax_fifo_wrap bdk_oclax_fifo_wrap_t;
993
994 static inline uint64_t BDK_OCLAX_FIFO_WRAP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_FIFO_WRAP(unsigned long a)995 static inline uint64_t BDK_OCLAX_FIFO_WRAP(unsigned long a)
996 {
997 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
998 return 0x87e0a8000280ll + 0x1000000ll * ((a) & 0x1);
999 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
1000 return 0x87e0a8000280ll + 0x1000000ll * ((a) & 0x3);
1001 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
1002 return 0x87e0a8000280ll + 0x1000000ll * ((a) & 0x7);
1003 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
1004 return 0x87e0b0000280ll + 0x1000000ll * ((a) & 0x7);
1005 __bdk_csr_fatal("OCLAX_FIFO_WRAP", 1, a, 0, 0, 0);
1006 }
1007
1008 #define typedef_BDK_OCLAX_FIFO_WRAP(a) bdk_oclax_fifo_wrap_t
1009 #define bustype_BDK_OCLAX_FIFO_WRAP(a) BDK_CSR_TYPE_RSL
1010 #define basename_BDK_OCLAX_FIFO_WRAP(a) "OCLAX_FIFO_WRAP"
1011 #define device_bar_BDK_OCLAX_FIFO_WRAP(a) 0x0 /* PF_BAR0 */
1012 #define busnum_BDK_OCLAX_FIFO_WRAP(a) (a)
1013 #define arguments_BDK_OCLAX_FIFO_WRAP(a) (a),-1,-1,-1
1014
1015 /**
1016 * Register (RSL) ocla#_fsm#_and#_i#
1017 *
1018 * OCLA FSM PLA AND Tree Registers
1019 * Values for PLA-AND plane. AND(0..15) represents the 16 allowed AND terms. I(0..1) for I=0
1020 * indicates the term non-inverted, for I=1 indicates the term inverted. Any AND tree may be
1021 * disabled by setting the same bit in both _I(0) and _I(1), as '((1) & !(1))' is always false.
1022 */
1023 union bdk_oclax_fsmx_andx_ix
1024 {
1025 uint64_t u;
1026 struct bdk_oclax_fsmx_andx_ix_s
1027 {
1028 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1029 uint64_t reserved_16_63 : 48;
1030 uint64_t trig : 1; /**< [ 15: 15](R/W) AND plane control for trigger FSM input. */
1031 uint64_t mcd : 3; /**< [ 14: 12](R/W) AND plane control for multichip debug (MCD) 0..2 FSM inputs. */
1032 uint64_t match : 4; /**< [ 11: 8](R/W) AND plane control for matcher 0..3 FSM inputs. */
1033 uint64_t fsm1_state : 4; /**< [ 7: 4](R/W) AND plane control for FSM 1 last state input. */
1034 uint64_t fsm0_state : 4; /**< [ 3: 0](R/W) AND plane control for FSM 0 last state input. */
1035 #else /* Word 0 - Little Endian */
1036 uint64_t fsm0_state : 4; /**< [ 3: 0](R/W) AND plane control for FSM 0 last state input. */
1037 uint64_t fsm1_state : 4; /**< [ 7: 4](R/W) AND plane control for FSM 1 last state input. */
1038 uint64_t match : 4; /**< [ 11: 8](R/W) AND plane control for matcher 0..3 FSM inputs. */
1039 uint64_t mcd : 3; /**< [ 14: 12](R/W) AND plane control for multichip debug (MCD) 0..2 FSM inputs. */
1040 uint64_t trig : 1; /**< [ 15: 15](R/W) AND plane control for trigger FSM input. */
1041 uint64_t reserved_16_63 : 48;
1042 #endif /* Word 0 - End */
1043 } s;
1044 struct bdk_oclax_fsmx_andx_ix_cn88xxp1
1045 {
1046 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1047 uint64_t reserved_16_63 : 48;
1048 uint64_t trig : 1; /**< [ 15: 15](RAZ) Reserved. */
1049 uint64_t mcd : 3; /**< [ 14: 12](R/W) AND plane control for multichip debug (MCD) 0..2 FSM inputs. */
1050 uint64_t match : 4; /**< [ 11: 8](R/W) AND plane control for matcher 0..3 FSM inputs. */
1051 uint64_t fsm1_state : 4; /**< [ 7: 4](R/W) AND plane control for FSM 1 last state input. */
1052 uint64_t fsm0_state : 4; /**< [ 3: 0](R/W) AND plane control for FSM 0 last state input. */
1053 #else /* Word 0 - Little Endian */
1054 uint64_t fsm0_state : 4; /**< [ 3: 0](R/W) AND plane control for FSM 0 last state input. */
1055 uint64_t fsm1_state : 4; /**< [ 7: 4](R/W) AND plane control for FSM 1 last state input. */
1056 uint64_t match : 4; /**< [ 11: 8](R/W) AND plane control for matcher 0..3 FSM inputs. */
1057 uint64_t mcd : 3; /**< [ 14: 12](R/W) AND plane control for multichip debug (MCD) 0..2 FSM inputs. */
1058 uint64_t trig : 1; /**< [ 15: 15](RAZ) Reserved. */
1059 uint64_t reserved_16_63 : 48;
1060 #endif /* Word 0 - End */
1061 } cn88xxp1;
1062 /* struct bdk_oclax_fsmx_andx_ix_s cn9; */
1063 /* struct bdk_oclax_fsmx_andx_ix_s cn81xx; */
1064 /* struct bdk_oclax_fsmx_andx_ix_s cn83xx; */
1065 /* struct bdk_oclax_fsmx_andx_ix_s cn88xxp2; */
1066 };
1067 typedef union bdk_oclax_fsmx_andx_ix bdk_oclax_fsmx_andx_ix_t;
1068
1069 static inline uint64_t BDK_OCLAX_FSMX_ANDX_IX(unsigned long a, unsigned long b, unsigned long c, unsigned long d) __attribute__ ((pure, always_inline));
BDK_OCLAX_FSMX_ANDX_IX(unsigned long a,unsigned long b,unsigned long c,unsigned long d)1070 static inline uint64_t BDK_OCLAX_FSMX_ANDX_IX(unsigned long a, unsigned long b, unsigned long c, unsigned long d)
1071 {
1072 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=1) && (c<=15) && (d<=1)))
1073 return 0x87e0a8300000ll + 0x1000000ll * ((a) & 0x1) + 0x1000ll * ((b) & 0x1) + 0x10ll * ((c) & 0xf) + 8ll * ((d) & 0x1);
1074 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=1) && (c<=15) && (d<=1)))
1075 return 0x87e0a8300000ll + 0x1000000ll * ((a) & 0x3) + 0x1000ll * ((b) & 0x1) + 0x10ll * ((c) & 0xf) + 8ll * ((d) & 0x1);
1076 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=1) && (c<=15) && (d<=1)))
1077 return 0x87e0a8300000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x1) + 0x10ll * ((c) & 0xf) + 8ll * ((d) & 0x1);
1078 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=1) && (c<=15) && (d<=1)))
1079 return 0x87e0b0300000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x1) + 0x10ll * ((c) & 0xf) + 8ll * ((d) & 0x1);
1080 __bdk_csr_fatal("OCLAX_FSMX_ANDX_IX", 4, a, b, c, d);
1081 }
1082
1083 #define typedef_BDK_OCLAX_FSMX_ANDX_IX(a,b,c,d) bdk_oclax_fsmx_andx_ix_t
1084 #define bustype_BDK_OCLAX_FSMX_ANDX_IX(a,b,c,d) BDK_CSR_TYPE_RSL
1085 #define basename_BDK_OCLAX_FSMX_ANDX_IX(a,b,c,d) "OCLAX_FSMX_ANDX_IX"
1086 #define device_bar_BDK_OCLAX_FSMX_ANDX_IX(a,b,c,d) 0x0 /* PF_BAR0 */
1087 #define busnum_BDK_OCLAX_FSMX_ANDX_IX(a,b,c,d) (a)
1088 #define arguments_BDK_OCLAX_FSMX_ANDX_IX(a,b,c,d) (a),(b),(c),(d)
1089
1090 /**
1091 * Register (RSL) ocla#_fsm#_or#
1092 *
1093 * OCLA FSM PLA AND Tree Registers
1094 */
1095 union bdk_oclax_fsmx_orx
1096 {
1097 uint64_t u;
1098 struct bdk_oclax_fsmx_orx_s
1099 {
1100 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1101 uint64_t reserved_16_63 : 48;
1102 uint64_t or_state : 16; /**< [ 15: 0](R/W) Column to drive on PLA OR-plane. */
1103 #else /* Word 0 - Little Endian */
1104 uint64_t or_state : 16; /**< [ 15: 0](R/W) Column to drive on PLA OR-plane. */
1105 uint64_t reserved_16_63 : 48;
1106 #endif /* Word 0 - End */
1107 } s;
1108 /* struct bdk_oclax_fsmx_orx_s cn; */
1109 };
1110 typedef union bdk_oclax_fsmx_orx bdk_oclax_fsmx_orx_t;
1111
1112 static inline uint64_t BDK_OCLAX_FSMX_ORX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_OCLAX_FSMX_ORX(unsigned long a,unsigned long b,unsigned long c)1113 static inline uint64_t BDK_OCLAX_FSMX_ORX(unsigned long a, unsigned long b, unsigned long c)
1114 {
1115 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=1) && (c<=15)))
1116 return 0x87e0a8310000ll + 0x1000000ll * ((a) & 0x1) + 0x1000ll * ((b) & 0x1) + 8ll * ((c) & 0xf);
1117 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=1) && (c<=15)))
1118 return 0x87e0a8310000ll + 0x1000000ll * ((a) & 0x3) + 0x1000ll * ((b) & 0x1) + 8ll * ((c) & 0xf);
1119 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=1) && (c<=15)))
1120 return 0x87e0a8310000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x1) + 8ll * ((c) & 0xf);
1121 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=1) && (c<=15)))
1122 return 0x87e0b0310000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x1) + 8ll * ((c) & 0xf);
1123 __bdk_csr_fatal("OCLAX_FSMX_ORX", 3, a, b, c, 0);
1124 }
1125
1126 #define typedef_BDK_OCLAX_FSMX_ORX(a,b,c) bdk_oclax_fsmx_orx_t
1127 #define bustype_BDK_OCLAX_FSMX_ORX(a,b,c) BDK_CSR_TYPE_RSL
1128 #define basename_BDK_OCLAX_FSMX_ORX(a,b,c) "OCLAX_FSMX_ORX"
1129 #define device_bar_BDK_OCLAX_FSMX_ORX(a,b,c) 0x0 /* PF_BAR0 */
1130 #define busnum_BDK_OCLAX_FSMX_ORX(a,b,c) (a)
1131 #define arguments_BDK_OCLAX_FSMX_ORX(a,b,c) (a),(b),(c),-1
1132
1133 /**
1134 * Register (RSL) ocla#_fsm#_state#
1135 *
1136 * OCLA FSM State Registers
1137 * See the OCLA chapter text for more details on each of these actions.
1138 */
1139 union bdk_oclax_fsmx_statex
1140 {
1141 uint64_t u;
1142 struct bdk_oclax_fsmx_statex_s
1143 {
1144 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1145 uint64_t reserved_31_63 : 33;
1146 uint64_t sinfo_set : 1; /**< [ 30: 30](R/W) If a control packet is generated in this state (due to capture starting
1147 in the next cycle), set OCLA_CAP_CTL_S[SINFO]. */
1148 uint64_t set_int : 1; /**< [ 29: 29](R/W) In this state set interrupt. */
1149 uint64_t cap : 1; /**< [ 28: 28](R/W) In this state request capture this cycle. */
1150 uint64_t set_mcd : 3; /**< [ 27: 25](R/W) In this state set MCD. */
1151 uint64_t set_trig : 1; /**< [ 24: 24](R/W) In this state set internal trigger indication. */
1152 uint64_t reserved_20_23 : 4;
1153 uint64_t set_val : 4; /**< [ 19: 16](R/W) In this state store match value into matcher 0..3. */
1154 uint64_t reserved_12_15 : 4;
1155 uint64_t clr_cnt : 4; /**< [ 11: 8](R/W) In this state clear match counter. */
1156 uint64_t reserved_4_7 : 4;
1157 uint64_t inc_cnt : 4; /**< [ 3: 0](R/W) In this state increment match counter. */
1158 #else /* Word 0 - Little Endian */
1159 uint64_t inc_cnt : 4; /**< [ 3: 0](R/W) In this state increment match counter. */
1160 uint64_t reserved_4_7 : 4;
1161 uint64_t clr_cnt : 4; /**< [ 11: 8](R/W) In this state clear match counter. */
1162 uint64_t reserved_12_15 : 4;
1163 uint64_t set_val : 4; /**< [ 19: 16](R/W) In this state store match value into matcher 0..3. */
1164 uint64_t reserved_20_23 : 4;
1165 uint64_t set_trig : 1; /**< [ 24: 24](R/W) In this state set internal trigger indication. */
1166 uint64_t set_mcd : 3; /**< [ 27: 25](R/W) In this state set MCD. */
1167 uint64_t cap : 1; /**< [ 28: 28](R/W) In this state request capture this cycle. */
1168 uint64_t set_int : 1; /**< [ 29: 29](R/W) In this state set interrupt. */
1169 uint64_t sinfo_set : 1; /**< [ 30: 30](R/W) If a control packet is generated in this state (due to capture starting
1170 in the next cycle), set OCLA_CAP_CTL_S[SINFO]. */
1171 uint64_t reserved_31_63 : 33;
1172 #endif /* Word 0 - End */
1173 } s;
1174 /* struct bdk_oclax_fsmx_statex_s cn; */
1175 };
1176 typedef union bdk_oclax_fsmx_statex bdk_oclax_fsmx_statex_t;
1177
1178 static inline uint64_t BDK_OCLAX_FSMX_STATEX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_OCLAX_FSMX_STATEX(unsigned long a,unsigned long b,unsigned long c)1179 static inline uint64_t BDK_OCLAX_FSMX_STATEX(unsigned long a, unsigned long b, unsigned long c)
1180 {
1181 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=1) && (c<=15)))
1182 return 0x87e0a8320000ll + 0x1000000ll * ((a) & 0x1) + 0x1000ll * ((b) & 0x1) + 8ll * ((c) & 0xf);
1183 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=1) && (c<=15)))
1184 return 0x87e0a8320000ll + 0x1000000ll * ((a) & 0x3) + 0x1000ll * ((b) & 0x1) + 8ll * ((c) & 0xf);
1185 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=1) && (c<=15)))
1186 return 0x87e0a8320000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x1) + 8ll * ((c) & 0xf);
1187 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=1) && (c<=15)))
1188 return 0x87e0b0320000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x1) + 8ll * ((c) & 0xf);
1189 __bdk_csr_fatal("OCLAX_FSMX_STATEX", 3, a, b, c, 0);
1190 }
1191
1192 #define typedef_BDK_OCLAX_FSMX_STATEX(a,b,c) bdk_oclax_fsmx_statex_t
1193 #define bustype_BDK_OCLAX_FSMX_STATEX(a,b,c) BDK_CSR_TYPE_RSL
1194 #define basename_BDK_OCLAX_FSMX_STATEX(a,b,c) "OCLAX_FSMX_STATEX"
1195 #define device_bar_BDK_OCLAX_FSMX_STATEX(a,b,c) 0x0 /* PF_BAR0 */
1196 #define busnum_BDK_OCLAX_FSMX_STATEX(a,b,c) (a)
1197 #define arguments_BDK_OCLAX_FSMX_STATEX(a,b,c) (a),(b),(c),-1
1198
1199 /**
1200 * Register (RSL) ocla#_gen_ctl
1201 *
1202 * OCLA General Control Registers
1203 */
1204 union bdk_oclax_gen_ctl
1205 {
1206 uint64_t u;
1207 struct bdk_oclax_gen_ctl_s
1208 {
1209 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1210 uint64_t reserved_7_63 : 57;
1211 uint64_t mcdtrig : 3; /**< [ 6: 4](R/W) Enable MCD triggering. For each bit corresponding to the three MCDs:
1212 0 = MCD does not cause trigger.
1213 1 = When the corresponding MCD is received it will cause
1214 triggering and set OCLA()_STATE_SET[TRIG]. */
1215 uint64_t exten : 1; /**< [ 3: 3](R/W) Enable external triggering.
1216 0 = External triggering ignored.
1217 1 = When the external trigger pin selected with GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER
1218 is high it will cause
1219 triggering and set OCLA()_STATE_SET[TRIG]. The external device must de-assert the
1220 signal (it is not edge sensitive.) */
1221 uint64_t den : 1; /**< [ 2: 2](R/W) Enable data bus and counter clocking. When set, the OCLA inbound data bus may be used and
1222 counters may increment. When clear, the bus is always zero and internal flops may be clock
1223 gated off to save power. Must be set for normal operation. */
1224 uint64_t stt : 1; /**< [ 1: 1](R/W) Store to DDR directly, bypassing L2 cache. */
1225 uint64_t reserved_0 : 1;
1226 #else /* Word 0 - Little Endian */
1227 uint64_t reserved_0 : 1;
1228 uint64_t stt : 1; /**< [ 1: 1](R/W) Store to DDR directly, bypassing L2 cache. */
1229 uint64_t den : 1; /**< [ 2: 2](R/W) Enable data bus and counter clocking. When set, the OCLA inbound data bus may be used and
1230 counters may increment. When clear, the bus is always zero and internal flops may be clock
1231 gated off to save power. Must be set for normal operation. */
1232 uint64_t exten : 1; /**< [ 3: 3](R/W) Enable external triggering.
1233 0 = External triggering ignored.
1234 1 = When the external trigger pin selected with GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER
1235 is high it will cause
1236 triggering and set OCLA()_STATE_SET[TRIG]. The external device must de-assert the
1237 signal (it is not edge sensitive.) */
1238 uint64_t mcdtrig : 3; /**< [ 6: 4](R/W) Enable MCD triggering. For each bit corresponding to the three MCDs:
1239 0 = MCD does not cause trigger.
1240 1 = When the corresponding MCD is received it will cause
1241 triggering and set OCLA()_STATE_SET[TRIG]. */
1242 uint64_t reserved_7_63 : 57;
1243 #endif /* Word 0 - End */
1244 } s;
1245 struct bdk_oclax_gen_ctl_cn88xxp1
1246 {
1247 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1248 uint64_t reserved_7_63 : 57;
1249 uint64_t mcdtrig : 3; /**< [ 6: 4](RAZ) Reserved. */
1250 uint64_t exten : 1; /**< [ 3: 3](R/W) Enable external triggering.
1251 0 = External triggering ignored.
1252 1 = When the external trigger pin selected with GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER
1253 is high it will cause
1254 triggering and set OCLA()_STATE_SET[TRIG]. The external device must de-assert the
1255 signal (it is not edge sensitive.) */
1256 uint64_t den : 1; /**< [ 2: 2](R/W) Enable data bus and counter clocking. When set, the OCLA inbound data bus may be used and
1257 counters may increment. When clear, the bus is always zero and internal flops may be clock
1258 gated off to save power. Must be set for normal operation. */
1259 uint64_t stt : 1; /**< [ 1: 1](R/W) Store to DDR directly, bypassing L2 cache. */
1260 uint64_t reserved_0 : 1;
1261 #else /* Word 0 - Little Endian */
1262 uint64_t reserved_0 : 1;
1263 uint64_t stt : 1; /**< [ 1: 1](R/W) Store to DDR directly, bypassing L2 cache. */
1264 uint64_t den : 1; /**< [ 2: 2](R/W) Enable data bus and counter clocking. When set, the OCLA inbound data bus may be used and
1265 counters may increment. When clear, the bus is always zero and internal flops may be clock
1266 gated off to save power. Must be set for normal operation. */
1267 uint64_t exten : 1; /**< [ 3: 3](R/W) Enable external triggering.
1268 0 = External triggering ignored.
1269 1 = When the external trigger pin selected with GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER
1270 is high it will cause
1271 triggering and set OCLA()_STATE_SET[TRIG]. The external device must de-assert the
1272 signal (it is not edge sensitive.) */
1273 uint64_t mcdtrig : 3; /**< [ 6: 4](RAZ) Reserved. */
1274 uint64_t reserved_7_63 : 57;
1275 #endif /* Word 0 - End */
1276 } cn88xxp1;
1277 struct bdk_oclax_gen_ctl_cn9
1278 {
1279 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1280 uint64_t reserved_7_63 : 57;
1281 uint64_t mcdtrig : 3; /**< [ 6: 4](R/W) Enable MCD triggering. For each bit corresponding to the three MCDs:
1282 0 = MCD does not cause trigger.
1283 1 = When the corresponding MCD is received it will cause
1284 triggering and set OCLA()_STATE_SET[TRIG]. */
1285 uint64_t exten : 1; /**< [ 3: 3](R/W) Enable external triggering.
1286 0 = External triggering ignored.
1287 1 = When the external trigger pin selected with GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER
1288 is high it will cause
1289 triggering and set OCLA()_STATE_SET[TRIG]. The external device must de-assert the
1290 signal (it is not edge sensitive.) */
1291 uint64_t den : 1; /**< [ 2: 2](R/W) Enable data bus and counter clocking. When set, the OCLA inbound data bus may be used and
1292 counters may increment. When clear, the bus is always zero and internal flops may be clock
1293 gated off to save power. Must be set for normal operation. */
1294 uint64_t stt : 1; /**< [ 1: 1](R/W) Store to DRAM directly, bypassing LLC. */
1295 uint64_t reserved_0 : 1;
1296 #else /* Word 0 - Little Endian */
1297 uint64_t reserved_0 : 1;
1298 uint64_t stt : 1; /**< [ 1: 1](R/W) Store to DRAM directly, bypassing LLC. */
1299 uint64_t den : 1; /**< [ 2: 2](R/W) Enable data bus and counter clocking. When set, the OCLA inbound data bus may be used and
1300 counters may increment. When clear, the bus is always zero and internal flops may be clock
1301 gated off to save power. Must be set for normal operation. */
1302 uint64_t exten : 1; /**< [ 3: 3](R/W) Enable external triggering.
1303 0 = External triggering ignored.
1304 1 = When the external trigger pin selected with GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER
1305 is high it will cause
1306 triggering and set OCLA()_STATE_SET[TRIG]. The external device must de-assert the
1307 signal (it is not edge sensitive.) */
1308 uint64_t mcdtrig : 3; /**< [ 6: 4](R/W) Enable MCD triggering. For each bit corresponding to the three MCDs:
1309 0 = MCD does not cause trigger.
1310 1 = When the corresponding MCD is received it will cause
1311 triggering and set OCLA()_STATE_SET[TRIG]. */
1312 uint64_t reserved_7_63 : 57;
1313 #endif /* Word 0 - End */
1314 } cn9;
1315 /* struct bdk_oclax_gen_ctl_s cn81xx; */
1316 /* struct bdk_oclax_gen_ctl_s cn83xx; */
1317 /* struct bdk_oclax_gen_ctl_s cn88xxp2; */
1318 };
1319 typedef union bdk_oclax_gen_ctl bdk_oclax_gen_ctl_t;
1320
1321 static inline uint64_t BDK_OCLAX_GEN_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_GEN_CTL(unsigned long a)1322 static inline uint64_t BDK_OCLAX_GEN_CTL(unsigned long a)
1323 {
1324 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1325 return 0x87e0a8000060ll + 0x1000000ll * ((a) & 0x1);
1326 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
1327 return 0x87e0a8000060ll + 0x1000000ll * ((a) & 0x3);
1328 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
1329 return 0x87e0a8000060ll + 0x1000000ll * ((a) & 0x7);
1330 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
1331 return 0x87e0b0000060ll + 0x1000000ll * ((a) & 0x7);
1332 __bdk_csr_fatal("OCLAX_GEN_CTL", 1, a, 0, 0, 0);
1333 }
1334
1335 #define typedef_BDK_OCLAX_GEN_CTL(a) bdk_oclax_gen_ctl_t
1336 #define bustype_BDK_OCLAX_GEN_CTL(a) BDK_CSR_TYPE_RSL
1337 #define basename_BDK_OCLAX_GEN_CTL(a) "OCLAX_GEN_CTL"
1338 #define device_bar_BDK_OCLAX_GEN_CTL(a) 0x0 /* PF_BAR0 */
1339 #define busnum_BDK_OCLAX_GEN_CTL(a) (a)
1340 #define arguments_BDK_OCLAX_GEN_CTL(a) (a),-1,-1,-1
1341
1342 /**
1343 * Register (RSL) ocla#_mat#_count
1344 *
1345 * OCLA Matcher Count Registers
1346 */
1347 union bdk_oclax_matx_count
1348 {
1349 uint64_t u;
1350 struct bdk_oclax_matx_count_s
1351 {
1352 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1353 uint64_t reserved_32_63 : 32;
1354 uint64_t count : 32; /**< [ 31: 0](R/W/H) Current counter value. Note software must reset this to zero (or the appropriate count)
1355 before starting capture. */
1356 #else /* Word 0 - Little Endian */
1357 uint64_t count : 32; /**< [ 31: 0](R/W/H) Current counter value. Note software must reset this to zero (or the appropriate count)
1358 before starting capture. */
1359 uint64_t reserved_32_63 : 32;
1360 #endif /* Word 0 - End */
1361 } s;
1362 /* struct bdk_oclax_matx_count_s cn; */
1363 };
1364 typedef union bdk_oclax_matx_count bdk_oclax_matx_count_t;
1365
1366 static inline uint64_t BDK_OCLAX_MATX_COUNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_MATX_COUNT(unsigned long a,unsigned long b)1367 static inline uint64_t BDK_OCLAX_MATX_COUNT(unsigned long a, unsigned long b)
1368 {
1369 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1370 return 0x87e0a8230000ll + 0x1000000ll * ((a) & 0x1) + 0x1000ll * ((b) & 0x3);
1371 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=3)))
1372 return 0x87e0a8230000ll + 0x1000000ll * ((a) & 0x3) + 0x1000ll * ((b) & 0x3);
1373 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=3)))
1374 return 0x87e0a8230000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3);
1375 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=3)))
1376 return 0x87e0b0230000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3);
1377 __bdk_csr_fatal("OCLAX_MATX_COUNT", 2, a, b, 0, 0);
1378 }
1379
1380 #define typedef_BDK_OCLAX_MATX_COUNT(a,b) bdk_oclax_matx_count_t
1381 #define bustype_BDK_OCLAX_MATX_COUNT(a,b) BDK_CSR_TYPE_RSL
1382 #define basename_BDK_OCLAX_MATX_COUNT(a,b) "OCLAX_MATX_COUNT"
1383 #define device_bar_BDK_OCLAX_MATX_COUNT(a,b) 0x0 /* PF_BAR0 */
1384 #define busnum_BDK_OCLAX_MATX_COUNT(a,b) (a)
1385 #define arguments_BDK_OCLAX_MATX_COUNT(a,b) (a),(b),-1,-1
1386
1387 /**
1388 * Register (RSL) ocla#_mat#_ctl
1389 *
1390 * OCLA Matcher Control Registers
1391 */
1392 union bdk_oclax_matx_ctl
1393 {
1394 uint64_t u;
1395 struct bdk_oclax_matx_ctl_s
1396 {
1397 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1398 uint64_t reserved_8_63 : 56;
1399 uint64_t fsm_ctr : 1; /**< [ 7: 7](R/W) What output matcher provides to FSM:
1400 0 = FSM receives raw match signal, asserting only in those cycles with matches.
1401 1 = FSM receives OCLA()_MAT()_COUNT \>= OCLA()_MAT()_THRESH. */
1402 uint64_t inc_match : 1; /**< [ 6: 6](R/W) Increment OCLA()_MAT()_COUNT counter automatically on each match. */
1403 uint64_t shift : 6; /**< [ 5: 0](R/W) Right rotation amount to apply to data loaded into OCLA()_MAT()_VALUE()
1404 register when FSM requests a value load. */
1405 #else /* Word 0 - Little Endian */
1406 uint64_t shift : 6; /**< [ 5: 0](R/W) Right rotation amount to apply to data loaded into OCLA()_MAT()_VALUE()
1407 register when FSM requests a value load. */
1408 uint64_t inc_match : 1; /**< [ 6: 6](R/W) Increment OCLA()_MAT()_COUNT counter automatically on each match. */
1409 uint64_t fsm_ctr : 1; /**< [ 7: 7](R/W) What output matcher provides to FSM:
1410 0 = FSM receives raw match signal, asserting only in those cycles with matches.
1411 1 = FSM receives OCLA()_MAT()_COUNT \>= OCLA()_MAT()_THRESH. */
1412 uint64_t reserved_8_63 : 56;
1413 #endif /* Word 0 - End */
1414 } s;
1415 /* struct bdk_oclax_matx_ctl_s cn; */
1416 };
1417 typedef union bdk_oclax_matx_ctl bdk_oclax_matx_ctl_t;
1418
1419 static inline uint64_t BDK_OCLAX_MATX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_MATX_CTL(unsigned long a,unsigned long b)1420 static inline uint64_t BDK_OCLAX_MATX_CTL(unsigned long a, unsigned long b)
1421 {
1422 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1423 return 0x87e0a8200000ll + 0x1000000ll * ((a) & 0x1) + 0x1000ll * ((b) & 0x3);
1424 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=3)))
1425 return 0x87e0a8200000ll + 0x1000000ll * ((a) & 0x3) + 0x1000ll * ((b) & 0x3);
1426 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=3)))
1427 return 0x87e0a8200000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3);
1428 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=3)))
1429 return 0x87e0b0200000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3);
1430 __bdk_csr_fatal("OCLAX_MATX_CTL", 2, a, b, 0, 0);
1431 }
1432
1433 #define typedef_BDK_OCLAX_MATX_CTL(a,b) bdk_oclax_matx_ctl_t
1434 #define bustype_BDK_OCLAX_MATX_CTL(a,b) BDK_CSR_TYPE_RSL
1435 #define basename_BDK_OCLAX_MATX_CTL(a,b) "OCLAX_MATX_CTL"
1436 #define device_bar_BDK_OCLAX_MATX_CTL(a,b) 0x0 /* PF_BAR0 */
1437 #define busnum_BDK_OCLAX_MATX_CTL(a,b) (a)
1438 #define arguments_BDK_OCLAX_MATX_CTL(a,b) (a),(b),-1,-1
1439
1440 /**
1441 * Register (RSL) ocla#_mat#_mask#
1442 *
1443 * OCLA Matcher Compare Mask Registers
1444 */
1445 union bdk_oclax_matx_maskx
1446 {
1447 uint64_t u;
1448 struct bdk_oclax_matx_maskx_s
1449 {
1450 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1451 uint64_t reserved_36_63 : 28;
1452 uint64_t mask : 36; /**< [ 35: 0](R/W) Bitmask of which bits in OCLA()_MAT()_VALUE() are to be compared.
1453
1454 Each bit of OCLA()_MAT()_VALUE() and OCLA()_MAT()_MASK() are combined as
1455 follows:
1456
1457 _ If MASK = 1 and VALUE = 0, matches when corresponding bit of data = "0".
1458 _ If MASK = 1 and VALUE = 1, matches when corresponding bit of data = "1".
1459 _ If MASK = 0, matches regardless of corresponding bit of data. */
1460 #else /* Word 0 - Little Endian */
1461 uint64_t mask : 36; /**< [ 35: 0](R/W) Bitmask of which bits in OCLA()_MAT()_VALUE() are to be compared.
1462
1463 Each bit of OCLA()_MAT()_VALUE() and OCLA()_MAT()_MASK() are combined as
1464 follows:
1465
1466 _ If MASK = 1 and VALUE = 0, matches when corresponding bit of data = "0".
1467 _ If MASK = 1 and VALUE = 1, matches when corresponding bit of data = "1".
1468 _ If MASK = 0, matches regardless of corresponding bit of data. */
1469 uint64_t reserved_36_63 : 28;
1470 #endif /* Word 0 - End */
1471 } s;
1472 /* struct bdk_oclax_matx_maskx_s cn9; */
1473 /* struct bdk_oclax_matx_maskx_s cn81xx; */
1474 struct bdk_oclax_matx_maskx_cn88xx
1475 {
1476 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1477 uint64_t reserved_36_63 : 28;
1478 uint64_t mask : 36; /**< [ 35: 0](R/W) Bitmask of which bits in OCLA()_MAT()_VALUE() are to be compared.
1479
1480 Each bit of OCLA()_MAT()_VALUE() and OCLA()_MAT()_MASK() are combined as
1481 follows:
1482
1483 _ If MASK = 1 and VALUE = 0, matches when data = "0".
1484 _ If MASK = 1 and VALUE = 1, matches when data = "1".
1485 _ If MASK = 0 and VALUE = 0, matches any data.
1486 _ If MASK = 0 and VALUE = 1, reserved in pass 1, matches any data pass 2 and later. */
1487 #else /* Word 0 - Little Endian */
1488 uint64_t mask : 36; /**< [ 35: 0](R/W) Bitmask of which bits in OCLA()_MAT()_VALUE() are to be compared.
1489
1490 Each bit of OCLA()_MAT()_VALUE() and OCLA()_MAT()_MASK() are combined as
1491 follows:
1492
1493 _ If MASK = 1 and VALUE = 0, matches when data = "0".
1494 _ If MASK = 1 and VALUE = 1, matches when data = "1".
1495 _ If MASK = 0 and VALUE = 0, matches any data.
1496 _ If MASK = 0 and VALUE = 1, reserved in pass 1, matches any data pass 2 and later. */
1497 uint64_t reserved_36_63 : 28;
1498 #endif /* Word 0 - End */
1499 } cn88xx;
1500 /* struct bdk_oclax_matx_maskx_s cn83xx; */
1501 };
1502 typedef union bdk_oclax_matx_maskx bdk_oclax_matx_maskx_t;
1503
1504 static inline uint64_t BDK_OCLAX_MATX_MASKX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_OCLAX_MATX_MASKX(unsigned long a,unsigned long b,unsigned long c)1505 static inline uint64_t BDK_OCLAX_MATX_MASKX(unsigned long a, unsigned long b, unsigned long c)
1506 {
1507 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3) && (c<=1)))
1508 return 0x87e0a8220000ll + 0x1000000ll * ((a) & 0x1) + 0x1000ll * ((b) & 0x3) + 8ll * ((c) & 0x1);
1509 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=3) && (c<=1)))
1510 return 0x87e0a8220000ll + 0x1000000ll * ((a) & 0x3) + 0x1000ll * ((b) & 0x3) + 8ll * ((c) & 0x1);
1511 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=3) && (c<=1)))
1512 return 0x87e0a8220000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3) + 8ll * ((c) & 0x1);
1513 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=3) && (c<=1)))
1514 return 0x87e0b0220000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3) + 8ll * ((c) & 0x1);
1515 __bdk_csr_fatal("OCLAX_MATX_MASKX", 3, a, b, c, 0);
1516 }
1517
1518 #define typedef_BDK_OCLAX_MATX_MASKX(a,b,c) bdk_oclax_matx_maskx_t
1519 #define bustype_BDK_OCLAX_MATX_MASKX(a,b,c) BDK_CSR_TYPE_RSL
1520 #define basename_BDK_OCLAX_MATX_MASKX(a,b,c) "OCLAX_MATX_MASKX"
1521 #define device_bar_BDK_OCLAX_MATX_MASKX(a,b,c) 0x0 /* PF_BAR0 */
1522 #define busnum_BDK_OCLAX_MATX_MASKX(a,b,c) (a)
1523 #define arguments_BDK_OCLAX_MATX_MASKX(a,b,c) (a),(b),(c),-1
1524
1525 /**
1526 * Register (RSL) ocla#_mat#_thresh
1527 *
1528 * OCLA Matcher Count Threshold Registers
1529 */
1530 union bdk_oclax_matx_thresh
1531 {
1532 uint64_t u;
1533 struct bdk_oclax_matx_thresh_s
1534 {
1535 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1536 uint64_t reserved_32_63 : 32;
1537 uint64_t thresh : 32; /**< [ 31: 0](R/W) Counter threshold value. Compared against OCLA()_MAT()_COUNT to assert matcher
1538 output, and set OCLA()_STATE_INT[OVFL]. */
1539 #else /* Word 0 - Little Endian */
1540 uint64_t thresh : 32; /**< [ 31: 0](R/W) Counter threshold value. Compared against OCLA()_MAT()_COUNT to assert matcher
1541 output, and set OCLA()_STATE_INT[OVFL]. */
1542 uint64_t reserved_32_63 : 32;
1543 #endif /* Word 0 - End */
1544 } s;
1545 /* struct bdk_oclax_matx_thresh_s cn; */
1546 };
1547 typedef union bdk_oclax_matx_thresh bdk_oclax_matx_thresh_t;
1548
1549 static inline uint64_t BDK_OCLAX_MATX_THRESH(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_MATX_THRESH(unsigned long a,unsigned long b)1550 static inline uint64_t BDK_OCLAX_MATX_THRESH(unsigned long a, unsigned long b)
1551 {
1552 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1553 return 0x87e0a8240000ll + 0x1000000ll * ((a) & 0x1) + 0x1000ll * ((b) & 0x3);
1554 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=3)))
1555 return 0x87e0a8240000ll + 0x1000000ll * ((a) & 0x3) + 0x1000ll * ((b) & 0x3);
1556 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=3)))
1557 return 0x87e0a8240000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3);
1558 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=3)))
1559 return 0x87e0b0240000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3);
1560 __bdk_csr_fatal("OCLAX_MATX_THRESH", 2, a, b, 0, 0);
1561 }
1562
1563 #define typedef_BDK_OCLAX_MATX_THRESH(a,b) bdk_oclax_matx_thresh_t
1564 #define bustype_BDK_OCLAX_MATX_THRESH(a,b) BDK_CSR_TYPE_RSL
1565 #define basename_BDK_OCLAX_MATX_THRESH(a,b) "OCLAX_MATX_THRESH"
1566 #define device_bar_BDK_OCLAX_MATX_THRESH(a,b) 0x0 /* PF_BAR0 */
1567 #define busnum_BDK_OCLAX_MATX_THRESH(a,b) (a)
1568 #define arguments_BDK_OCLAX_MATX_THRESH(a,b) (a),(b),-1,-1
1569
1570 /**
1571 * Register (RSL) ocla#_mat#_value#
1572 *
1573 * OCLA Matcher Compare Value Registers
1574 */
1575 union bdk_oclax_matx_valuex
1576 {
1577 uint64_t u;
1578 struct bdk_oclax_matx_valuex_s
1579 {
1580 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1581 uint64_t reserved_36_63 : 28;
1582 uint64_t mask : 36; /**< [ 35: 0](R/W/H) Data value to compare against when corresponding bits of OCLA()_MAT()_MASK()
1583 are set. Value may be updated with OCLA()_FSM()_STATE()[SET_VAL]. */
1584 #else /* Word 0 - Little Endian */
1585 uint64_t mask : 36; /**< [ 35: 0](R/W/H) Data value to compare against when corresponding bits of OCLA()_MAT()_MASK()
1586 are set. Value may be updated with OCLA()_FSM()_STATE()[SET_VAL]. */
1587 uint64_t reserved_36_63 : 28;
1588 #endif /* Word 0 - End */
1589 } s;
1590 /* struct bdk_oclax_matx_valuex_s cn; */
1591 };
1592 typedef union bdk_oclax_matx_valuex bdk_oclax_matx_valuex_t;
1593
1594 static inline uint64_t BDK_OCLAX_MATX_VALUEX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_OCLAX_MATX_VALUEX(unsigned long a,unsigned long b,unsigned long c)1595 static inline uint64_t BDK_OCLAX_MATX_VALUEX(unsigned long a, unsigned long b, unsigned long c)
1596 {
1597 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3) && (c<=1)))
1598 return 0x87e0a8210000ll + 0x1000000ll * ((a) & 0x1) + 0x1000ll * ((b) & 0x3) + 8ll * ((c) & 0x1);
1599 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=3) && (c<=1)))
1600 return 0x87e0a8210000ll + 0x1000000ll * ((a) & 0x3) + 0x1000ll * ((b) & 0x3) + 8ll * ((c) & 0x1);
1601 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=3) && (c<=1)))
1602 return 0x87e0a8210000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3) + 8ll * ((c) & 0x1);
1603 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=3) && (c<=1)))
1604 return 0x87e0b0210000ll + 0x1000000ll * ((a) & 0x7) + 0x1000ll * ((b) & 0x3) + 8ll * ((c) & 0x1);
1605 __bdk_csr_fatal("OCLAX_MATX_VALUEX", 3, a, b, c, 0);
1606 }
1607
1608 #define typedef_BDK_OCLAX_MATX_VALUEX(a,b,c) bdk_oclax_matx_valuex_t
1609 #define bustype_BDK_OCLAX_MATX_VALUEX(a,b,c) BDK_CSR_TYPE_RSL
1610 #define basename_BDK_OCLAX_MATX_VALUEX(a,b,c) "OCLAX_MATX_VALUEX"
1611 #define device_bar_BDK_OCLAX_MATX_VALUEX(a,b,c) 0x0 /* PF_BAR0 */
1612 #define busnum_BDK_OCLAX_MATX_VALUEX(a,b,c) (a)
1613 #define arguments_BDK_OCLAX_MATX_VALUEX(a,b,c) (a),(b),(c),-1
1614
1615 /**
1616 * Register (RSL) ocla#_mparid
1617 *
1618 * OCLA Memory Partition ID Register
1619 */
1620 union bdk_oclax_mparid
1621 {
1622 uint64_t u;
1623 struct bdk_oclax_mparid_s
1624 {
1625 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1626 uint64_t reserved_8_63 : 56;
1627 uint64_t mparid : 8; /**< [ 7: 0](R/W) Memory partition ID. Only used for OCLAs inside clusters. */
1628 #else /* Word 0 - Little Endian */
1629 uint64_t mparid : 8; /**< [ 7: 0](R/W) Memory partition ID. Only used for OCLAs inside clusters. */
1630 uint64_t reserved_8_63 : 56;
1631 #endif /* Word 0 - End */
1632 } s;
1633 /* struct bdk_oclax_mparid_s cn; */
1634 };
1635 typedef union bdk_oclax_mparid bdk_oclax_mparid_t;
1636
1637 static inline uint64_t BDK_OCLAX_MPARID(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_MPARID(unsigned long a)1638 static inline uint64_t BDK_OCLAX_MPARID(unsigned long a)
1639 {
1640 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
1641 return 0x87e0b00000e0ll + 0x1000000ll * ((a) & 0x7);
1642 __bdk_csr_fatal("OCLAX_MPARID", 1, a, 0, 0, 0);
1643 }
1644
1645 #define typedef_BDK_OCLAX_MPARID(a) bdk_oclax_mparid_t
1646 #define bustype_BDK_OCLAX_MPARID(a) BDK_CSR_TYPE_RSL
1647 #define basename_BDK_OCLAX_MPARID(a) "OCLAX_MPARID"
1648 #define device_bar_BDK_OCLAX_MPARID(a) 0x0 /* PF_BAR0 */
1649 #define busnum_BDK_OCLAX_MPARID(a) (a)
1650 #define arguments_BDK_OCLAX_MPARID(a) (a),-1,-1,-1
1651
1652 /**
1653 * Register (RSL) ocla#_msix_pba#
1654 *
1655 * OCLA MSI-X Pending Bit Array Registers
1656 * This register is the MSI-X PBA table; the bit number is indexed by the OCLA_INT_VEC_E enumeration.
1657 */
1658 union bdk_oclax_msix_pbax
1659 {
1660 uint64_t u;
1661 struct bdk_oclax_msix_pbax_s
1662 {
1663 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1664 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated OCLA()_MSIX_VEC()_CTL, enumerated by OCLA_INT_VEC_E.
1665 Bits that have no associated OCLA_INT_VEC_E are 0. */
1666 #else /* Word 0 - Little Endian */
1667 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated OCLA()_MSIX_VEC()_CTL, enumerated by OCLA_INT_VEC_E.
1668 Bits that have no associated OCLA_INT_VEC_E are 0. */
1669 #endif /* Word 0 - End */
1670 } s;
1671 /* struct bdk_oclax_msix_pbax_s cn; */
1672 };
1673 typedef union bdk_oclax_msix_pbax bdk_oclax_msix_pbax_t;
1674
1675 static inline uint64_t BDK_OCLAX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_MSIX_PBAX(unsigned long a,unsigned long b)1676 static inline uint64_t BDK_OCLAX_MSIX_PBAX(unsigned long a, unsigned long b)
1677 {
1678 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
1679 return 0x87e0a8ff0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
1680 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b==0)))
1681 return 0x87e0a8ff0000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x0);
1682 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b==0)))
1683 return 0x87e0a8ff0000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x0);
1684 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b==0)))
1685 return 0x87e0b0ff0000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x0);
1686 __bdk_csr_fatal("OCLAX_MSIX_PBAX", 2, a, b, 0, 0);
1687 }
1688
1689 #define typedef_BDK_OCLAX_MSIX_PBAX(a,b) bdk_oclax_msix_pbax_t
1690 #define bustype_BDK_OCLAX_MSIX_PBAX(a,b) BDK_CSR_TYPE_RSL
1691 #define basename_BDK_OCLAX_MSIX_PBAX(a,b) "OCLAX_MSIX_PBAX"
1692 #define device_bar_BDK_OCLAX_MSIX_PBAX(a,b) 0x4 /* PF_BAR4 */
1693 #define busnum_BDK_OCLAX_MSIX_PBAX(a,b) (a)
1694 #define arguments_BDK_OCLAX_MSIX_PBAX(a,b) (a),(b),-1,-1
1695
1696 /**
1697 * Register (RSL) ocla#_msix_vec#_addr
1698 *
1699 * OCLA MSI-X Vector-Table Address Register
1700 * This register is the MSI-X vector table, indexed by the OCLA_INT_VEC_E enumeration.
1701 */
1702 union bdk_oclax_msix_vecx_addr
1703 {
1704 uint64_t u;
1705 struct bdk_oclax_msix_vecx_addr_s
1706 {
1707 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1708 uint64_t reserved_53_63 : 11;
1709 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1710 uint64_t reserved_1 : 1;
1711 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1712 0 = This vector may be read or written by either secure or nonsecure states.
1713 1 = This vector's OCLA()_MSIX_VEC()_ADDR, OCLA()_MSIX_VEC()_CTL, and
1714 corresponding bit of OCLA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1715 by the nonsecure world.
1716
1717 If PCCPF_OCLA()_VSEC_SCTL[MSIX_SEC] (for documentation, see
1718 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1719 was set. */
1720 #else /* Word 0 - Little Endian */
1721 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1722 0 = This vector may be read or written by either secure or nonsecure states.
1723 1 = This vector's OCLA()_MSIX_VEC()_ADDR, OCLA()_MSIX_VEC()_CTL, and
1724 corresponding bit of OCLA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1725 by the nonsecure world.
1726
1727 If PCCPF_OCLA()_VSEC_SCTL[MSIX_SEC] (for documentation, see
1728 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1729 was set. */
1730 uint64_t reserved_1 : 1;
1731 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1732 uint64_t reserved_53_63 : 11;
1733 #endif /* Word 0 - End */
1734 } s;
1735 struct bdk_oclax_msix_vecx_addr_cn8
1736 {
1737 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1738 uint64_t reserved_49_63 : 15;
1739 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1740 uint64_t reserved_1 : 1;
1741 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1742 0 = This vector may be read or written by either secure or nonsecure states.
1743 1 = This vector's OCLA()_MSIX_VEC()_ADDR, OCLA()_MSIX_VEC()_CTL, and
1744 corresponding bit of OCLA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1745 by the nonsecure world.
1746
1747 If PCCPF_OCLA()_VSEC_SCTL[MSIX_SEC] (for documentation, see
1748 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1749 was set. */
1750 #else /* Word 0 - Little Endian */
1751 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1752 0 = This vector may be read or written by either secure or nonsecure states.
1753 1 = This vector's OCLA()_MSIX_VEC()_ADDR, OCLA()_MSIX_VEC()_CTL, and
1754 corresponding bit of OCLA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1755 by the nonsecure world.
1756
1757 If PCCPF_OCLA()_VSEC_SCTL[MSIX_SEC] (for documentation, see
1758 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1759 was set. */
1760 uint64_t reserved_1 : 1;
1761 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1762 uint64_t reserved_49_63 : 15;
1763 #endif /* Word 0 - End */
1764 } cn8;
1765 /* struct bdk_oclax_msix_vecx_addr_s cn9; */
1766 };
1767 typedef union bdk_oclax_msix_vecx_addr bdk_oclax_msix_vecx_addr_t;
1768
1769 static inline uint64_t BDK_OCLAX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)1770 static inline uint64_t BDK_OCLAX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
1771 {
1772 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
1773 return 0x87e0a8f00000ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
1774 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b==0)))
1775 return 0x87e0a8f00000ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x0);
1776 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b==0)))
1777 return 0x87e0a8f00000ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x0);
1778 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b==0)))
1779 return 0x87e0b0f00000ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x0);
1780 __bdk_csr_fatal("OCLAX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
1781 }
1782
1783 #define typedef_BDK_OCLAX_MSIX_VECX_ADDR(a,b) bdk_oclax_msix_vecx_addr_t
1784 #define bustype_BDK_OCLAX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_RSL
1785 #define basename_BDK_OCLAX_MSIX_VECX_ADDR(a,b) "OCLAX_MSIX_VECX_ADDR"
1786 #define device_bar_BDK_OCLAX_MSIX_VECX_ADDR(a,b) 0x4 /* PF_BAR4 */
1787 #define busnum_BDK_OCLAX_MSIX_VECX_ADDR(a,b) (a)
1788 #define arguments_BDK_OCLAX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
1789
1790 /**
1791 * Register (RSL) ocla#_msix_vec#_ctl
1792 *
1793 * OCLA MSI-X Vector-Table Control and Data Register
1794 * This register is the MSI-X vector table, indexed by the OCLA_INT_VEC_E enumeration.
1795 */
1796 union bdk_oclax_msix_vecx_ctl
1797 {
1798 uint64_t u;
1799 struct bdk_oclax_msix_vecx_ctl_s
1800 {
1801 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1802 uint64_t reserved_33_63 : 31;
1803 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
1804 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
1805 #else /* Word 0 - Little Endian */
1806 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
1807 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
1808 uint64_t reserved_33_63 : 31;
1809 #endif /* Word 0 - End */
1810 } s;
1811 struct bdk_oclax_msix_vecx_ctl_cn8
1812 {
1813 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1814 uint64_t reserved_33_63 : 31;
1815 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
1816 uint64_t reserved_20_31 : 12;
1817 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
1818 #else /* Word 0 - Little Endian */
1819 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
1820 uint64_t reserved_20_31 : 12;
1821 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
1822 uint64_t reserved_33_63 : 31;
1823 #endif /* Word 0 - End */
1824 } cn8;
1825 /* struct bdk_oclax_msix_vecx_ctl_s cn9; */
1826 };
1827 typedef union bdk_oclax_msix_vecx_ctl bdk_oclax_msix_vecx_ctl_t;
1828
1829 static inline uint64_t BDK_OCLAX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_MSIX_VECX_CTL(unsigned long a,unsigned long b)1830 static inline uint64_t BDK_OCLAX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
1831 {
1832 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
1833 return 0x87e0a8f00008ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
1834 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b==0)))
1835 return 0x87e0a8f00008ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x0);
1836 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b==0)))
1837 return 0x87e0a8f00008ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x0);
1838 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b==0)))
1839 return 0x87e0b0f00008ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x0);
1840 __bdk_csr_fatal("OCLAX_MSIX_VECX_CTL", 2, a, b, 0, 0);
1841 }
1842
1843 #define typedef_BDK_OCLAX_MSIX_VECX_CTL(a,b) bdk_oclax_msix_vecx_ctl_t
1844 #define bustype_BDK_OCLAX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_RSL
1845 #define basename_BDK_OCLAX_MSIX_VECX_CTL(a,b) "OCLAX_MSIX_VECX_CTL"
1846 #define device_bar_BDK_OCLAX_MSIX_VECX_CTL(a,b) 0x4 /* PF_BAR4 */
1847 #define busnum_BDK_OCLAX_MSIX_VECX_CTL(a,b) (a)
1848 #define arguments_BDK_OCLAX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
1849
1850 /**
1851 * Register (RSL) ocla#_raw#
1852 *
1853 * OCLA Raw Input Registers
1854 */
1855 union bdk_oclax_rawx
1856 {
1857 uint64_t u;
1858 struct bdk_oclax_rawx_s
1859 {
1860 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1861 uint64_t reserved_36_63 : 28;
1862 uint64_t raw : 36; /**< [ 35: 0](RO/H) Raw value of debug bus input signals into OCLA. */
1863 #else /* Word 0 - Little Endian */
1864 uint64_t raw : 36; /**< [ 35: 0](RO/H) Raw value of debug bus input signals into OCLA. */
1865 uint64_t reserved_36_63 : 28;
1866 #endif /* Word 0 - End */
1867 } s;
1868 /* struct bdk_oclax_rawx_s cn; */
1869 };
1870 typedef union bdk_oclax_rawx bdk_oclax_rawx_t;
1871
1872 static inline uint64_t BDK_OCLAX_RAWX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_RAWX(unsigned long a,unsigned long b)1873 static inline uint64_t BDK_OCLAX_RAWX(unsigned long a, unsigned long b)
1874 {
1875 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=1)))
1876 return 0x87e0a8000100ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1);
1877 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=1)))
1878 return 0x87e0a8000100ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x1);
1879 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=1)))
1880 return 0x87e0a8000100ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x1);
1881 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=1)))
1882 return 0x87e0b0000100ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x1);
1883 __bdk_csr_fatal("OCLAX_RAWX", 2, a, b, 0, 0);
1884 }
1885
1886 #define typedef_BDK_OCLAX_RAWX(a,b) bdk_oclax_rawx_t
1887 #define bustype_BDK_OCLAX_RAWX(a,b) BDK_CSR_TYPE_RSL
1888 #define basename_BDK_OCLAX_RAWX(a,b) "OCLAX_RAWX"
1889 #define device_bar_BDK_OCLAX_RAWX(a,b) 0x0 /* PF_BAR0 */
1890 #define busnum_BDK_OCLAX_RAWX(a,b) (a)
1891 #define arguments_BDK_OCLAX_RAWX(a,b) (a),(b),-1,-1
1892
1893 /**
1894 * Register (RSL) ocla#_sft_rst
1895 *
1896 * OCLA Reset Registers
1897 */
1898 union bdk_oclax_sft_rst
1899 {
1900 uint64_t u;
1901 struct bdk_oclax_sft_rst_s
1902 {
1903 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1904 uint64_t reserved_1_63 : 63;
1905 uint64_t reset : 1; /**< [ 0: 0](R/W1) Reset. When written with one, reset OCLA excluding the RSL interface. Software
1906 must wait at least 1024 coprocessor-clocks after resetting before sending any
1907 other CSR read/write operations into OCLA. */
1908 #else /* Word 0 - Little Endian */
1909 uint64_t reset : 1; /**< [ 0: 0](R/W1) Reset. When written with one, reset OCLA excluding the RSL interface. Software
1910 must wait at least 1024 coprocessor-clocks after resetting before sending any
1911 other CSR read/write operations into OCLA. */
1912 uint64_t reserved_1_63 : 63;
1913 #endif /* Word 0 - End */
1914 } s;
1915 /* struct bdk_oclax_sft_rst_s cn; */
1916 };
1917 typedef union bdk_oclax_sft_rst bdk_oclax_sft_rst_t;
1918
1919 static inline uint64_t BDK_OCLAX_SFT_RST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_SFT_RST(unsigned long a)1920 static inline uint64_t BDK_OCLAX_SFT_RST(unsigned long a)
1921 {
1922 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1923 return 0x87e0a8000020ll + 0x1000000ll * ((a) & 0x1);
1924 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
1925 return 0x87e0a8000020ll + 0x1000000ll * ((a) & 0x3);
1926 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
1927 return 0x87e0a8000020ll + 0x1000000ll * ((a) & 0x7);
1928 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
1929 return 0x87e0b0000020ll + 0x1000000ll * ((a) & 0x7);
1930 __bdk_csr_fatal("OCLAX_SFT_RST", 1, a, 0, 0, 0);
1931 }
1932
1933 #define typedef_BDK_OCLAX_SFT_RST(a) bdk_oclax_sft_rst_t
1934 #define bustype_BDK_OCLAX_SFT_RST(a) BDK_CSR_TYPE_RSL
1935 #define basename_BDK_OCLAX_SFT_RST(a) "OCLAX_SFT_RST"
1936 #define device_bar_BDK_OCLAX_SFT_RST(a) 0x0 /* PF_BAR0 */
1937 #define busnum_BDK_OCLAX_SFT_RST(a) (a)
1938 #define arguments_BDK_OCLAX_SFT_RST(a) (a),-1,-1,-1
1939
1940 /**
1941 * Register (RSL) ocla#_stack_base
1942 *
1943 * OCLA Stack Base Registers
1944 */
1945 union bdk_oclax_stack_base
1946 {
1947 uint64_t u;
1948 struct bdk_oclax_stack_base_s
1949 {
1950 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1951 uint64_t reserved_53_63 : 11;
1952 uint64_t ptr : 46; /**< [ 52: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
1953 CCPI system.
1954 This may be an IOVA or physical address; see [PA]. */
1955 uint64_t reserved_2_6 : 5;
1956 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
1957 is in the secure world. */
1958 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
1959 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
1960
1961 Only used for OCLA(4) in the coprocessor-clock domain; for OCLA(0..3) in the core-clock
1962 domains this bit is ignored, addresses are always physical. */
1963 #else /* Word 0 - Little Endian */
1964 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
1965 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
1966
1967 Only used for OCLA(4) in the coprocessor-clock domain; for OCLA(0..3) in the core-clock
1968 domains this bit is ignored, addresses are always physical. */
1969 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
1970 is in the secure world. */
1971 uint64_t reserved_2_6 : 5;
1972 uint64_t ptr : 46; /**< [ 52: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
1973 CCPI system.
1974 This may be an IOVA or physical address; see [PA]. */
1975 uint64_t reserved_53_63 : 11;
1976 #endif /* Word 0 - End */
1977 } s;
1978 struct bdk_oclax_stack_base_cn9
1979 {
1980 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1981 uint64_t reserved_53_63 : 11;
1982 uint64_t ptr : 46; /**< [ 52: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
1983 CCPI system.
1984 This may be an IOVA or physical address; see [PA]. */
1985 uint64_t reserved_2_6 : 5;
1986 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
1987 is in the secure world. */
1988 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
1989 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
1990
1991 Only used for the OCLA in the coprocessor-clock domain; for OCLAs in the core-clock
1992 domains this bit is ignored, addresses are always physical. */
1993 #else /* Word 0 - Little Endian */
1994 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
1995 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
1996
1997 Only used for the OCLA in the coprocessor-clock domain; for OCLAs in the core-clock
1998 domains this bit is ignored, addresses are always physical. */
1999 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
2000 is in the secure world. */
2001 uint64_t reserved_2_6 : 5;
2002 uint64_t ptr : 46; /**< [ 52: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
2003 CCPI system.
2004 This may be an IOVA or physical address; see [PA]. */
2005 uint64_t reserved_53_63 : 11;
2006 #endif /* Word 0 - End */
2007 } cn9;
2008 struct bdk_oclax_stack_base_cn81xx
2009 {
2010 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2011 uint64_t reserved_49_63 : 15;
2012 uint64_t ptr : 42; /**< [ 48: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
2013 CCPI system.
2014 This may be an IOVA or physical address; see [PA]. */
2015 uint64_t reserved_2_6 : 5;
2016 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
2017 is in the secure world. */
2018 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
2019 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
2020
2021 Only used for OCLA(2) in the coprocessor-clock domain; for OCLA(0..1) in the core-clock
2022 domains this bit is ignored, addresses are always physical. */
2023 #else /* Word 0 - Little Endian */
2024 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
2025 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
2026
2027 Only used for OCLA(2) in the coprocessor-clock domain; for OCLA(0..1) in the core-clock
2028 domains this bit is ignored, addresses are always physical. */
2029 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
2030 is in the secure world. */
2031 uint64_t reserved_2_6 : 5;
2032 uint64_t ptr : 42; /**< [ 48: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
2033 CCPI system.
2034 This may be an IOVA or physical address; see [PA]. */
2035 uint64_t reserved_49_63 : 15;
2036 #endif /* Word 0 - End */
2037 } cn81xx;
2038 struct bdk_oclax_stack_base_cn88xx
2039 {
2040 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2041 uint64_t reserved_49_63 : 15;
2042 uint64_t ptr : 42; /**< [ 48: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
2043 CCPI system.
2044 This may be an IOVA or physical address; see [PA]. */
2045 uint64_t reserved_2_6 : 5;
2046 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
2047 is in the secure world. */
2048 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
2049 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
2050
2051 Only used for OCLA(4) in the coprocessor-clock domain; for OCLA(0..3) in the core-clock
2052 domains this bit is ignored, addresses are always physical. */
2053 #else /* Word 0 - Little Endian */
2054 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
2055 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
2056
2057 Only used for OCLA(4) in the coprocessor-clock domain; for OCLA(0..3) in the core-clock
2058 domains this bit is ignored, addresses are always physical. */
2059 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
2060 is in the secure world. */
2061 uint64_t reserved_2_6 : 5;
2062 uint64_t ptr : 42; /**< [ 48: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
2063 CCPI system.
2064 This may be an IOVA or physical address; see [PA]. */
2065 uint64_t reserved_49_63 : 15;
2066 #endif /* Word 0 - End */
2067 } cn88xx;
2068 struct bdk_oclax_stack_base_cn83xx
2069 {
2070 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2071 uint64_t reserved_49_63 : 15;
2072 uint64_t ptr : 42; /**< [ 48: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
2073 CCPI system.
2074 This may be an IOVA or physical address; see [PA]. */
2075 uint64_t reserved_2_6 : 5;
2076 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
2077 is in the secure world. */
2078 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
2079 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
2080
2081 Only used for the OCLA in the coprocessor-clock domain; for OCLAs in the core-clock
2082 domains this bit is ignored, addresses are always physical. */
2083 #else /* Word 0 - Little Endian */
2084 uint64_t pa : 1; /**< [ 0: 0](R/W) When set, [PTR] and all DMA addresses are physical addresses and will not be translated by
2085 the SMMU. When clear, is a virtual address which is subject to SMMU translation.
2086
2087 Only used for the OCLA in the coprocessor-clock domain; for OCLAs in the core-clock
2088 domains this bit is ignored, addresses are always physical. */
2089 uint64_t sec : 1; /**< [ 1: 1](SR/W) If set, and physical addressing is used as described under [PA], the physical address
2090 is in the secure world. */
2091 uint64_t reserved_2_6 : 5;
2092 uint64_t ptr : 42; /**< [ 48: 7](R/W) Memory address for base of overflow stack. This address must be on the local node in a
2093 CCPI system.
2094 This may be an IOVA or physical address; see [PA]. */
2095 uint64_t reserved_49_63 : 15;
2096 #endif /* Word 0 - End */
2097 } cn83xx;
2098 };
2099 typedef union bdk_oclax_stack_base bdk_oclax_stack_base_t;
2100
2101 static inline uint64_t BDK_OCLAX_STACK_BASE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STACK_BASE(unsigned long a)2102 static inline uint64_t BDK_OCLAX_STACK_BASE(unsigned long a)
2103 {
2104 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2105 return 0x87e0a8000400ll + 0x1000000ll * ((a) & 0x1);
2106 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2107 return 0x87e0a8000400ll + 0x1000000ll * ((a) & 0x3);
2108 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2109 return 0x87e0a8000400ll + 0x1000000ll * ((a) & 0x7);
2110 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2111 return 0x87e0b0000400ll + 0x1000000ll * ((a) & 0x7);
2112 __bdk_csr_fatal("OCLAX_STACK_BASE", 1, a, 0, 0, 0);
2113 }
2114
2115 #define typedef_BDK_OCLAX_STACK_BASE(a) bdk_oclax_stack_base_t
2116 #define bustype_BDK_OCLAX_STACK_BASE(a) BDK_CSR_TYPE_RSL
2117 #define basename_BDK_OCLAX_STACK_BASE(a) "OCLAX_STACK_BASE"
2118 #define device_bar_BDK_OCLAX_STACK_BASE(a) 0x0 /* PF_BAR0 */
2119 #define busnum_BDK_OCLAX_STACK_BASE(a) (a)
2120 #define arguments_BDK_OCLAX_STACK_BASE(a) (a),-1,-1,-1
2121
2122 /**
2123 * Register (RSL) ocla#_stack_cur
2124 *
2125 * OCLA Stack Current Registers
2126 */
2127 union bdk_oclax_stack_cur
2128 {
2129 uint64_t u;
2130 struct bdk_oclax_stack_cur_s
2131 {
2132 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2133 uint64_t reserved_53_63 : 11;
2134 uint64_t ptr : 46; /**< [ 52: 7](R/W/H) Next address to write for overflow stack. This address must be on the local node in a
2135 CCPI system. During initialization this must be between OCLA()_STACK_BASE and
2136 OCLA()_STACK_TOP.
2137 This may be an IOVA or physical address; see OCLA()_STACK_BASE[PA]. */
2138 uint64_t reserved_0_6 : 7;
2139 #else /* Word 0 - Little Endian */
2140 uint64_t reserved_0_6 : 7;
2141 uint64_t ptr : 46; /**< [ 52: 7](R/W/H) Next address to write for overflow stack. This address must be on the local node in a
2142 CCPI system. During initialization this must be between OCLA()_STACK_BASE and
2143 OCLA()_STACK_TOP.
2144 This may be an IOVA or physical address; see OCLA()_STACK_BASE[PA]. */
2145 uint64_t reserved_53_63 : 11;
2146 #endif /* Word 0 - End */
2147 } s;
2148 struct bdk_oclax_stack_cur_cn8
2149 {
2150 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2151 uint64_t reserved_49_63 : 15;
2152 uint64_t ptr : 42; /**< [ 48: 7](R/W/H) Next address to write for overflow stack. This address must be on the local node in a
2153 CCPI system. During initialization this must be between OCLA()_STACK_BASE and
2154 OCLA()_STACK_TOP.
2155 This may be an IOVA or physical address; see OCLA()_STACK_BASE[PA]. */
2156 uint64_t reserved_0_6 : 7;
2157 #else /* Word 0 - Little Endian */
2158 uint64_t reserved_0_6 : 7;
2159 uint64_t ptr : 42; /**< [ 48: 7](R/W/H) Next address to write for overflow stack. This address must be on the local node in a
2160 CCPI system. During initialization this must be between OCLA()_STACK_BASE and
2161 OCLA()_STACK_TOP.
2162 This may be an IOVA or physical address; see OCLA()_STACK_BASE[PA]. */
2163 uint64_t reserved_49_63 : 15;
2164 #endif /* Word 0 - End */
2165 } cn8;
2166 /* struct bdk_oclax_stack_cur_s cn9; */
2167 };
2168 typedef union bdk_oclax_stack_cur bdk_oclax_stack_cur_t;
2169
2170 static inline uint64_t BDK_OCLAX_STACK_CUR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STACK_CUR(unsigned long a)2171 static inline uint64_t BDK_OCLAX_STACK_CUR(unsigned long a)
2172 {
2173 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2174 return 0x87e0a8000480ll + 0x1000000ll * ((a) & 0x1);
2175 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2176 return 0x87e0a8000480ll + 0x1000000ll * ((a) & 0x3);
2177 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2178 return 0x87e0a8000480ll + 0x1000000ll * ((a) & 0x7);
2179 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2180 return 0x87e0b0000480ll + 0x1000000ll * ((a) & 0x7);
2181 __bdk_csr_fatal("OCLAX_STACK_CUR", 1, a, 0, 0, 0);
2182 }
2183
2184 #define typedef_BDK_OCLAX_STACK_CUR(a) bdk_oclax_stack_cur_t
2185 #define bustype_BDK_OCLAX_STACK_CUR(a) BDK_CSR_TYPE_RSL
2186 #define basename_BDK_OCLAX_STACK_CUR(a) "OCLAX_STACK_CUR"
2187 #define device_bar_BDK_OCLAX_STACK_CUR(a) 0x0 /* PF_BAR0 */
2188 #define busnum_BDK_OCLAX_STACK_CUR(a) (a)
2189 #define arguments_BDK_OCLAX_STACK_CUR(a) (a),-1,-1,-1
2190
2191 /**
2192 * Register (RSL) ocla#_stack_store_cnt
2193 *
2194 * OCLA Stack Stores Performance Counter Registers
2195 */
2196 union bdk_oclax_stack_store_cnt
2197 {
2198 uint64_t u;
2199 struct bdk_oclax_stack_store_cnt_s
2200 {
2201 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2202 uint64_t reserved_32_63 : 32;
2203 uint64_t stores : 32; /**< [ 31: 0](R/W/H) Number of cache line stores sent to memory subsystem. Not cleared by hardware. */
2204 #else /* Word 0 - Little Endian */
2205 uint64_t stores : 32; /**< [ 31: 0](R/W/H) Number of cache line stores sent to memory subsystem. Not cleared by hardware. */
2206 uint64_t reserved_32_63 : 32;
2207 #endif /* Word 0 - End */
2208 } s;
2209 /* struct bdk_oclax_stack_store_cnt_s cn; */
2210 };
2211 typedef union bdk_oclax_stack_store_cnt bdk_oclax_stack_store_cnt_t;
2212
2213 static inline uint64_t BDK_OCLAX_STACK_STORE_CNT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STACK_STORE_CNT(unsigned long a)2214 static inline uint64_t BDK_OCLAX_STACK_STORE_CNT(unsigned long a)
2215 {
2216 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2217 return 0x87e0a8000460ll + 0x1000000ll * ((a) & 0x1);
2218 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2219 return 0x87e0a8000460ll + 0x1000000ll * ((a) & 0x3);
2220 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2221 return 0x87e0a8000460ll + 0x1000000ll * ((a) & 0x7);
2222 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2223 return 0x87e0b0000460ll + 0x1000000ll * ((a) & 0x7);
2224 __bdk_csr_fatal("OCLAX_STACK_STORE_CNT", 1, a, 0, 0, 0);
2225 }
2226
2227 #define typedef_BDK_OCLAX_STACK_STORE_CNT(a) bdk_oclax_stack_store_cnt_t
2228 #define bustype_BDK_OCLAX_STACK_STORE_CNT(a) BDK_CSR_TYPE_RSL
2229 #define basename_BDK_OCLAX_STACK_STORE_CNT(a) "OCLAX_STACK_STORE_CNT"
2230 #define device_bar_BDK_OCLAX_STACK_STORE_CNT(a) 0x0 /* PF_BAR0 */
2231 #define busnum_BDK_OCLAX_STACK_STORE_CNT(a) (a)
2232 #define arguments_BDK_OCLAX_STACK_STORE_CNT(a) (a),-1,-1,-1
2233
2234 /**
2235 * Register (RSL) ocla#_stack_top
2236 *
2237 * OCLA Stack Top Address Registers
2238 */
2239 union bdk_oclax_stack_top
2240 {
2241 uint64_t u;
2242 struct bdk_oclax_stack_top_s
2243 {
2244 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2245 uint64_t reserved_53_63 : 11;
2246 uint64_t ptr : 46; /**< [ 52: 7](R/W) Memory address for top of overflow stack plus one. This address must be on the local node
2247 in a CCPI system.
2248 This may be an IOVA or physical address; see OCLA()_STACK_BASE[PA]. */
2249 uint64_t reserved_0_6 : 7;
2250 #else /* Word 0 - Little Endian */
2251 uint64_t reserved_0_6 : 7;
2252 uint64_t ptr : 46; /**< [ 52: 7](R/W) Memory address for top of overflow stack plus one. This address must be on the local node
2253 in a CCPI system.
2254 This may be an IOVA or physical address; see OCLA()_STACK_BASE[PA]. */
2255 uint64_t reserved_53_63 : 11;
2256 #endif /* Word 0 - End */
2257 } s;
2258 struct bdk_oclax_stack_top_cn8
2259 {
2260 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2261 uint64_t reserved_49_63 : 15;
2262 uint64_t ptr : 42; /**< [ 48: 7](R/W) Memory address for top of overflow stack plus one. This address must be on the local node
2263 in a CCPI system.
2264 This may be an IOVA or physical address; see OCLA()_STACK_BASE[PA]. */
2265 uint64_t reserved_0_6 : 7;
2266 #else /* Word 0 - Little Endian */
2267 uint64_t reserved_0_6 : 7;
2268 uint64_t ptr : 42; /**< [ 48: 7](R/W) Memory address for top of overflow stack plus one. This address must be on the local node
2269 in a CCPI system.
2270 This may be an IOVA or physical address; see OCLA()_STACK_BASE[PA]. */
2271 uint64_t reserved_49_63 : 15;
2272 #endif /* Word 0 - End */
2273 } cn8;
2274 /* struct bdk_oclax_stack_top_s cn9; */
2275 };
2276 typedef union bdk_oclax_stack_top bdk_oclax_stack_top_t;
2277
2278 static inline uint64_t BDK_OCLAX_STACK_TOP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STACK_TOP(unsigned long a)2279 static inline uint64_t BDK_OCLAX_STACK_TOP(unsigned long a)
2280 {
2281 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2282 return 0x87e0a8000420ll + 0x1000000ll * ((a) & 0x1);
2283 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2284 return 0x87e0a8000420ll + 0x1000000ll * ((a) & 0x3);
2285 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2286 return 0x87e0a8000420ll + 0x1000000ll * ((a) & 0x7);
2287 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2288 return 0x87e0b0000420ll + 0x1000000ll * ((a) & 0x7);
2289 __bdk_csr_fatal("OCLAX_STACK_TOP", 1, a, 0, 0, 0);
2290 }
2291
2292 #define typedef_BDK_OCLAX_STACK_TOP(a) bdk_oclax_stack_top_t
2293 #define bustype_BDK_OCLAX_STACK_TOP(a) BDK_CSR_TYPE_RSL
2294 #define basename_BDK_OCLAX_STACK_TOP(a) "OCLAX_STACK_TOP"
2295 #define device_bar_BDK_OCLAX_STACK_TOP(a) 0x0 /* PF_BAR0 */
2296 #define busnum_BDK_OCLAX_STACK_TOP(a) (a)
2297 #define arguments_BDK_OCLAX_STACK_TOP(a) (a),-1,-1,-1
2298
2299 /**
2300 * Register (RSL) ocla#_stack_wrap
2301 *
2302 * OCLA Stack Wrap Counter Registers
2303 */
2304 union bdk_oclax_stack_wrap
2305 {
2306 uint64_t u;
2307 struct bdk_oclax_stack_wrap_s
2308 {
2309 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2310 uint64_t reserved_32_63 : 32;
2311 uint64_t wraps : 32; /**< [ 31: 0](R/W/H) Number of times stack has been reset to OCLA()_STACK_BASE since trigger. Cleared when
2312 OCLA()_STATE_INT[TRIG] clear. */
2313 #else /* Word 0 - Little Endian */
2314 uint64_t wraps : 32; /**< [ 31: 0](R/W/H) Number of times stack has been reset to OCLA()_STACK_BASE since trigger. Cleared when
2315 OCLA()_STATE_INT[TRIG] clear. */
2316 uint64_t reserved_32_63 : 32;
2317 #endif /* Word 0 - End */
2318 } s;
2319 /* struct bdk_oclax_stack_wrap_s cn; */
2320 };
2321 typedef union bdk_oclax_stack_wrap bdk_oclax_stack_wrap_t;
2322
2323 static inline uint64_t BDK_OCLAX_STACK_WRAP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STACK_WRAP(unsigned long a)2324 static inline uint64_t BDK_OCLAX_STACK_WRAP(unsigned long a)
2325 {
2326 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2327 return 0x87e0a8000440ll + 0x1000000ll * ((a) & 0x1);
2328 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2329 return 0x87e0a8000440ll + 0x1000000ll * ((a) & 0x3);
2330 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2331 return 0x87e0a8000440ll + 0x1000000ll * ((a) & 0x7);
2332 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2333 return 0x87e0b0000440ll + 0x1000000ll * ((a) & 0x7);
2334 __bdk_csr_fatal("OCLAX_STACK_WRAP", 1, a, 0, 0, 0);
2335 }
2336
2337 #define typedef_BDK_OCLAX_STACK_WRAP(a) bdk_oclax_stack_wrap_t
2338 #define bustype_BDK_OCLAX_STACK_WRAP(a) BDK_CSR_TYPE_RSL
2339 #define basename_BDK_OCLAX_STACK_WRAP(a) "OCLAX_STACK_WRAP"
2340 #define device_bar_BDK_OCLAX_STACK_WRAP(a) 0x0 /* PF_BAR0 */
2341 #define busnum_BDK_OCLAX_STACK_WRAP(a) (a)
2342 #define arguments_BDK_OCLAX_STACK_WRAP(a) (a),-1,-1,-1
2343
2344 /**
2345 * Register (RSL) ocla#_stage#
2346 *
2347 * OCLA Input Staging Registers
2348 */
2349 union bdk_oclax_stagex
2350 {
2351 uint64_t u;
2352 struct bdk_oclax_stagex_s
2353 {
2354 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2355 uint64_t reserved_4_63 : 60;
2356 uint64_t dly : 4; /**< [ 3: 0](R/W) Cycles of delay staging to apply to corresponding input bit. */
2357 #else /* Word 0 - Little Endian */
2358 uint64_t dly : 4; /**< [ 3: 0](R/W) Cycles of delay staging to apply to corresponding input bit. */
2359 uint64_t reserved_4_63 : 60;
2360 #endif /* Word 0 - End */
2361 } s;
2362 struct bdk_oclax_stagex_cn8
2363 {
2364 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2365 uint64_t reserved_3_63 : 61;
2366 uint64_t dly : 3; /**< [ 2: 0](R/W) Cycles of delay staging to apply to corresponding input bit. */
2367 #else /* Word 0 - Little Endian */
2368 uint64_t dly : 3; /**< [ 2: 0](R/W) Cycles of delay staging to apply to corresponding input bit. */
2369 uint64_t reserved_3_63 : 61;
2370 #endif /* Word 0 - End */
2371 } cn8;
2372 /* struct bdk_oclax_stagex_s cn9; */
2373 };
2374 typedef union bdk_oclax_stagex bdk_oclax_stagex_t;
2375
2376 static inline uint64_t BDK_OCLAX_STAGEX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCLAX_STAGEX(unsigned long a,unsigned long b)2377 static inline uint64_t BDK_OCLAX_STAGEX(unsigned long a, unsigned long b)
2378 {
2379 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=71)))
2380 return 0x87e0a8100000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x7f);
2381 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=2) && (b<=71)))
2382 return 0x87e0a8100000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x7f);
2383 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=4) && (b<=71)))
2384 return 0x87e0a8100000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x7f);
2385 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=4) && (b<=71)))
2386 return 0x87e0b0100000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x7f);
2387 __bdk_csr_fatal("OCLAX_STAGEX", 2, a, b, 0, 0);
2388 }
2389
2390 #define typedef_BDK_OCLAX_STAGEX(a,b) bdk_oclax_stagex_t
2391 #define bustype_BDK_OCLAX_STAGEX(a,b) BDK_CSR_TYPE_RSL
2392 #define basename_BDK_OCLAX_STAGEX(a,b) "OCLAX_STAGEX"
2393 #define device_bar_BDK_OCLAX_STAGEX(a,b) 0x0 /* PF_BAR0 */
2394 #define busnum_BDK_OCLAX_STAGEX(a,b) (a)
2395 #define arguments_BDK_OCLAX_STAGEX(a,b) (a),(b),-1,-1
2396
2397 /**
2398 * Register (RSL) ocla#_state_ena_w1c
2399 *
2400 * OCLA State Interrupt Enable Clear Registers
2401 * This register clears interrupt enable bits.
2402 */
2403 union bdk_oclax_state_ena_w1c
2404 {
2405 uint64_t u;
2406 struct bdk_oclax_state_ena_w1c_s
2407 {
2408 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2409 uint64_t reserved_19_63 : 45;
2410 uint64_t ddrfull : 1; /**< [ 18: 18](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[DDRFULL]. */
2411 uint64_t wmark : 1; /**< [ 17: 17](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[WMARK]. */
2412 uint64_t overfull : 1; /**< [ 16: 16](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[OVERFULL]. */
2413 uint64_t trigfull : 1; /**< [ 15: 15](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[TRIGFULL]. */
2414 uint64_t captured : 1; /**< [ 14: 14](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[CAPTURED]. */
2415 uint64_t fsm1_int : 1; /**< [ 13: 13](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[FSM1_INT]. */
2416 uint64_t fsm0_int : 1; /**< [ 12: 12](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[FSM0_INT]. */
2417 uint64_t mcd : 3; /**< [ 11: 9](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[MCD]. */
2418 uint64_t trig : 1; /**< [ 8: 8](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[TRIG]. */
2419 uint64_t reserved_4_7 : 4;
2420 uint64_t ovfl : 4; /**< [ 3: 0](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[OVFL]. */
2421 #else /* Word 0 - Little Endian */
2422 uint64_t ovfl : 4; /**< [ 3: 0](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[OVFL]. */
2423 uint64_t reserved_4_7 : 4;
2424 uint64_t trig : 1; /**< [ 8: 8](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[TRIG]. */
2425 uint64_t mcd : 3; /**< [ 11: 9](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[MCD]. */
2426 uint64_t fsm0_int : 1; /**< [ 12: 12](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[FSM0_INT]. */
2427 uint64_t fsm1_int : 1; /**< [ 13: 13](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[FSM1_INT]. */
2428 uint64_t captured : 1; /**< [ 14: 14](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[CAPTURED]. */
2429 uint64_t trigfull : 1; /**< [ 15: 15](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[TRIGFULL]. */
2430 uint64_t overfull : 1; /**< [ 16: 16](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[OVERFULL]. */
2431 uint64_t wmark : 1; /**< [ 17: 17](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[WMARK]. */
2432 uint64_t ddrfull : 1; /**< [ 18: 18](R/W1C/H) Reads or clears OCLA()_STATE_ENA_W1S[DDRFULL]. */
2433 uint64_t reserved_19_63 : 45;
2434 #endif /* Word 0 - End */
2435 } s;
2436 /* struct bdk_oclax_state_ena_w1c_s cn; */
2437 };
2438 typedef union bdk_oclax_state_ena_w1c bdk_oclax_state_ena_w1c_t;
2439
2440 static inline uint64_t BDK_OCLAX_STATE_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STATE_ENA_W1C(unsigned long a)2441 static inline uint64_t BDK_OCLAX_STATE_ENA_W1C(unsigned long a)
2442 {
2443 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2444 return 0x87e0a80000b8ll + 0x1000000ll * ((a) & 0x1);
2445 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2446 return 0x87e0a80000b8ll + 0x1000000ll * ((a) & 0x3);
2447 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2448 return 0x87e0a80000b8ll + 0x1000000ll * ((a) & 0x7);
2449 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2450 return 0x87e0b00000b8ll + 0x1000000ll * ((a) & 0x7);
2451 __bdk_csr_fatal("OCLAX_STATE_ENA_W1C", 1, a, 0, 0, 0);
2452 }
2453
2454 #define typedef_BDK_OCLAX_STATE_ENA_W1C(a) bdk_oclax_state_ena_w1c_t
2455 #define bustype_BDK_OCLAX_STATE_ENA_W1C(a) BDK_CSR_TYPE_RSL
2456 #define basename_BDK_OCLAX_STATE_ENA_W1C(a) "OCLAX_STATE_ENA_W1C"
2457 #define device_bar_BDK_OCLAX_STATE_ENA_W1C(a) 0x0 /* PF_BAR0 */
2458 #define busnum_BDK_OCLAX_STATE_ENA_W1C(a) (a)
2459 #define arguments_BDK_OCLAX_STATE_ENA_W1C(a) (a),-1,-1,-1
2460
2461 /**
2462 * Register (RSL) ocla#_state_ena_w1s
2463 *
2464 * OCLA State Interrupt Enable Set Registers
2465 * This register sets interrupt enable bits.
2466 */
2467 union bdk_oclax_state_ena_w1s
2468 {
2469 uint64_t u;
2470 struct bdk_oclax_state_ena_w1s_s
2471 {
2472 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2473 uint64_t reserved_19_63 : 45;
2474 uint64_t ddrfull : 1; /**< [ 18: 18](R/W1S/H) Enables reporting of OCLA()_STATE_INT[DDRFULL]. */
2475 uint64_t wmark : 1; /**< [ 17: 17](R/W1S/H) Enables reporting of OCLA()_STATE_INT[WMARK]. */
2476 uint64_t overfull : 1; /**< [ 16: 16](R/W1S/H) Enables reporting of OCLA()_STATE_INT[OVERFULL]. */
2477 uint64_t trigfull : 1; /**< [ 15: 15](R/W1S/H) Enables reporting of OCLA()_STATE_INT[TRIGFULL]. */
2478 uint64_t captured : 1; /**< [ 14: 14](R/W1S/H) Enables reporting of OCLA()_STATE_INT[CAPTURED]. */
2479 uint64_t fsm1_int : 1; /**< [ 13: 13](R/W1S/H) Enables reporting of OCLA()_STATE_INT[FSM1_INT]. */
2480 uint64_t fsm0_int : 1; /**< [ 12: 12](R/W1S/H) Enables reporting of OCLA()_STATE_INT[FSM0_INT]. */
2481 uint64_t mcd : 3; /**< [ 11: 9](R/W1S/H) Enables reporting of OCLA()_STATE_INT[MCD]. */
2482 uint64_t trig : 1; /**< [ 8: 8](R/W1S/H) Enables reporting of OCLA()_STATE_INT[TRIG]. */
2483 uint64_t reserved_4_7 : 4;
2484 uint64_t ovfl : 4; /**< [ 3: 0](R/W1S/H) Enables reporting of OCLA()_STATE_INT[OVFL]. */
2485 #else /* Word 0 - Little Endian */
2486 uint64_t ovfl : 4; /**< [ 3: 0](R/W1S/H) Enables reporting of OCLA()_STATE_INT[OVFL]. */
2487 uint64_t reserved_4_7 : 4;
2488 uint64_t trig : 1; /**< [ 8: 8](R/W1S/H) Enables reporting of OCLA()_STATE_INT[TRIG]. */
2489 uint64_t mcd : 3; /**< [ 11: 9](R/W1S/H) Enables reporting of OCLA()_STATE_INT[MCD]. */
2490 uint64_t fsm0_int : 1; /**< [ 12: 12](R/W1S/H) Enables reporting of OCLA()_STATE_INT[FSM0_INT]. */
2491 uint64_t fsm1_int : 1; /**< [ 13: 13](R/W1S/H) Enables reporting of OCLA()_STATE_INT[FSM1_INT]. */
2492 uint64_t captured : 1; /**< [ 14: 14](R/W1S/H) Enables reporting of OCLA()_STATE_INT[CAPTURED]. */
2493 uint64_t trigfull : 1; /**< [ 15: 15](R/W1S/H) Enables reporting of OCLA()_STATE_INT[TRIGFULL]. */
2494 uint64_t overfull : 1; /**< [ 16: 16](R/W1S/H) Enables reporting of OCLA()_STATE_INT[OVERFULL]. */
2495 uint64_t wmark : 1; /**< [ 17: 17](R/W1S/H) Enables reporting of OCLA()_STATE_INT[WMARK]. */
2496 uint64_t ddrfull : 1; /**< [ 18: 18](R/W1S/H) Enables reporting of OCLA()_STATE_INT[DDRFULL]. */
2497 uint64_t reserved_19_63 : 45;
2498 #endif /* Word 0 - End */
2499 } s;
2500 /* struct bdk_oclax_state_ena_w1s_s cn; */
2501 };
2502 typedef union bdk_oclax_state_ena_w1s bdk_oclax_state_ena_w1s_t;
2503
2504 static inline uint64_t BDK_OCLAX_STATE_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STATE_ENA_W1S(unsigned long a)2505 static inline uint64_t BDK_OCLAX_STATE_ENA_W1S(unsigned long a)
2506 {
2507 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2508 return 0x87e0a80000b0ll + 0x1000000ll * ((a) & 0x1);
2509 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2510 return 0x87e0a80000b0ll + 0x1000000ll * ((a) & 0x3);
2511 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2512 return 0x87e0a80000b0ll + 0x1000000ll * ((a) & 0x7);
2513 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2514 return 0x87e0b00000b0ll + 0x1000000ll * ((a) & 0x7);
2515 __bdk_csr_fatal("OCLAX_STATE_ENA_W1S", 1, a, 0, 0, 0);
2516 }
2517
2518 #define typedef_BDK_OCLAX_STATE_ENA_W1S(a) bdk_oclax_state_ena_w1s_t
2519 #define bustype_BDK_OCLAX_STATE_ENA_W1S(a) BDK_CSR_TYPE_RSL
2520 #define basename_BDK_OCLAX_STATE_ENA_W1S(a) "OCLAX_STATE_ENA_W1S"
2521 #define device_bar_BDK_OCLAX_STATE_ENA_W1S(a) 0x0 /* PF_BAR0 */
2522 #define busnum_BDK_OCLAX_STATE_ENA_W1S(a) (a)
2523 #define arguments_BDK_OCLAX_STATE_ENA_W1S(a) (a),-1,-1,-1
2524
2525 /**
2526 * Register (RSL) ocla#_state_int
2527 *
2528 * OCLA State and Interrupt Registers
2529 */
2530 union bdk_oclax_state_int
2531 {
2532 uint64_t u;
2533 struct bdk_oclax_state_int_s
2534 {
2535 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2536 uint64_t fsm1_state : 4; /**< [ 63: 60](RO/H) FSM1 current state. */
2537 uint64_t fsm0_state : 4; /**< [ 59: 56](RO/H) FSM0 current state. */
2538 uint64_t reserved_36_55 : 20;
2539 uint64_t fsm1_rst : 1; /**< [ 35: 35](R/W1C) FSM1 hold in state zero. Writing one to OCLA()_STATE_SET[FSM1_RST] sets this bit and
2540 holds FSM1 in state zero, writing one to OCLA()_STATE_INT[FSM1_RST] removes the hold. */
2541 uint64_t fsm0_rst : 1; /**< [ 34: 34](R/W1C) FSM0 hold in state zero. Writing one to OCLA()_STATE_SET[FSM0_RST] sets this bit and
2542 holds FSM0 in state zero, writing one to OCLA()_STATE_INT[FSM0_RST] removes the hold. */
2543 uint64_t fsm1_ena : 1; /**< [ 33: 33](R/W1C/H) FSM1 sequencing enabled. */
2544 uint64_t fsm0_ena : 1; /**< [ 32: 32](R/W1C/H) FSM0 sequencing enabled. */
2545 uint64_t reserved_19_31 : 13;
2546 uint64_t ddrfull : 1; /**< [ 18: 18](R/W1C/H) DDR buffer wrapped. Asserted when OCLA()_STACK_CUR has wrapped and been re-initialized
2547 to OCLA()_STACK_BASE. */
2548 uint64_t wmark : 1; /**< [ 17: 17](R/W1C/H) Internal buffer watermark reached. Asserted when OCLA()_FIFO_DEPTH \>
2549 OCLA()_FIFO_LIMIT[WMARK]. */
2550 uint64_t overfull : 1; /**< [ 16: 16](R/W1C/H) Capture ended due to FIFO overflow. Asserted when OCLA()_FIFO_DEPTH \>
2551 OCLA()_FIFO_LIMIT[OVERFULL]. */
2552 uint64_t trigfull : 1; /**< [ 15: 15](R/W1C/H) Capture ended due to buffer full. Asserted when OCLA()_FIFO_TRIG[LIMIT] \>=
2553 OCLA()_FIFO_TRIG[CNT]. */
2554 uint64_t captured : 1; /**< [ 14: 14](R/W1C/H) Capture started. Asserted when the first capture is made. Informational only; often masked. */
2555 uint64_t fsm1_int : 1; /**< [ 13: 13](R/W1C/H) FSM1 interrupt requested. */
2556 uint64_t fsm0_int : 1; /**< [ 12: 12](R/W1C/H) FSM0 interrupt requested. */
2557 uint64_t mcd : 3; /**< [ 11: 9](R/W1C/H) Multichip debug (MCD0..2) set. Asserted on MCD received from another coprocessor or code,
2558 or FSM MCD request or W1S to OCLA()_STATE_SET[MCD]. */
2559 uint64_t trig : 1; /**< [ 8: 8](R/W1C/H) Internal trigger set. Asserted on FSM internal trigger request or W1S to OCLA()_STATE_SET[TRIG]. */
2560 uint64_t reserved_4_7 : 4;
2561 uint64_t ovfl : 4; /**< [ 3: 0](R/W1C/H) Match counter has overflowed. Asserted when OCLA()_MAT()_COUNT \>=
2562 OCLA()_MAT()_THRESH. Informational only; often masked. Writing 1 clears the
2563 counter, not just the interrupt. */
2564 #else /* Word 0 - Little Endian */
2565 uint64_t ovfl : 4; /**< [ 3: 0](R/W1C/H) Match counter has overflowed. Asserted when OCLA()_MAT()_COUNT \>=
2566 OCLA()_MAT()_THRESH. Informational only; often masked. Writing 1 clears the
2567 counter, not just the interrupt. */
2568 uint64_t reserved_4_7 : 4;
2569 uint64_t trig : 1; /**< [ 8: 8](R/W1C/H) Internal trigger set. Asserted on FSM internal trigger request or W1S to OCLA()_STATE_SET[TRIG]. */
2570 uint64_t mcd : 3; /**< [ 11: 9](R/W1C/H) Multichip debug (MCD0..2) set. Asserted on MCD received from another coprocessor or code,
2571 or FSM MCD request or W1S to OCLA()_STATE_SET[MCD]. */
2572 uint64_t fsm0_int : 1; /**< [ 12: 12](R/W1C/H) FSM0 interrupt requested. */
2573 uint64_t fsm1_int : 1; /**< [ 13: 13](R/W1C/H) FSM1 interrupt requested. */
2574 uint64_t captured : 1; /**< [ 14: 14](R/W1C/H) Capture started. Asserted when the first capture is made. Informational only; often masked. */
2575 uint64_t trigfull : 1; /**< [ 15: 15](R/W1C/H) Capture ended due to buffer full. Asserted when OCLA()_FIFO_TRIG[LIMIT] \>=
2576 OCLA()_FIFO_TRIG[CNT]. */
2577 uint64_t overfull : 1; /**< [ 16: 16](R/W1C/H) Capture ended due to FIFO overflow. Asserted when OCLA()_FIFO_DEPTH \>
2578 OCLA()_FIFO_LIMIT[OVERFULL]. */
2579 uint64_t wmark : 1; /**< [ 17: 17](R/W1C/H) Internal buffer watermark reached. Asserted when OCLA()_FIFO_DEPTH \>
2580 OCLA()_FIFO_LIMIT[WMARK]. */
2581 uint64_t ddrfull : 1; /**< [ 18: 18](R/W1C/H) DDR buffer wrapped. Asserted when OCLA()_STACK_CUR has wrapped and been re-initialized
2582 to OCLA()_STACK_BASE. */
2583 uint64_t reserved_19_31 : 13;
2584 uint64_t fsm0_ena : 1; /**< [ 32: 32](R/W1C/H) FSM0 sequencing enabled. */
2585 uint64_t fsm1_ena : 1; /**< [ 33: 33](R/W1C/H) FSM1 sequencing enabled. */
2586 uint64_t fsm0_rst : 1; /**< [ 34: 34](R/W1C) FSM0 hold in state zero. Writing one to OCLA()_STATE_SET[FSM0_RST] sets this bit and
2587 holds FSM0 in state zero, writing one to OCLA()_STATE_INT[FSM0_RST] removes the hold. */
2588 uint64_t fsm1_rst : 1; /**< [ 35: 35](R/W1C) FSM1 hold in state zero. Writing one to OCLA()_STATE_SET[FSM1_RST] sets this bit and
2589 holds FSM1 in state zero, writing one to OCLA()_STATE_INT[FSM1_RST] removes the hold. */
2590 uint64_t reserved_36_55 : 20;
2591 uint64_t fsm0_state : 4; /**< [ 59: 56](RO/H) FSM0 current state. */
2592 uint64_t fsm1_state : 4; /**< [ 63: 60](RO/H) FSM1 current state. */
2593 #endif /* Word 0 - End */
2594 } s;
2595 /* struct bdk_oclax_state_int_s cn; */
2596 };
2597 typedef union bdk_oclax_state_int bdk_oclax_state_int_t;
2598
2599 static inline uint64_t BDK_OCLAX_STATE_INT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STATE_INT(unsigned long a)2600 static inline uint64_t BDK_OCLAX_STATE_INT(unsigned long a)
2601 {
2602 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2603 return 0x87e0a8000080ll + 0x1000000ll * ((a) & 0x1);
2604 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2605 return 0x87e0a8000080ll + 0x1000000ll * ((a) & 0x3);
2606 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2607 return 0x87e0a8000080ll + 0x1000000ll * ((a) & 0x7);
2608 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2609 return 0x87e0b0000080ll + 0x1000000ll * ((a) & 0x7);
2610 __bdk_csr_fatal("OCLAX_STATE_INT", 1, a, 0, 0, 0);
2611 }
2612
2613 #define typedef_BDK_OCLAX_STATE_INT(a) bdk_oclax_state_int_t
2614 #define bustype_BDK_OCLAX_STATE_INT(a) BDK_CSR_TYPE_RSL
2615 #define basename_BDK_OCLAX_STATE_INT(a) "OCLAX_STATE_INT"
2616 #define device_bar_BDK_OCLAX_STATE_INT(a) 0x0 /* PF_BAR0 */
2617 #define busnum_BDK_OCLAX_STATE_INT(a) (a)
2618 #define arguments_BDK_OCLAX_STATE_INT(a) (a),-1,-1,-1
2619
2620 /**
2621 * Register (RSL) ocla#_state_set
2622 *
2623 * OCLA State Set Registers
2624 * This register reads identically to OCLA()_STATE_INT, but allows R/W1S instead of R/W1C access.
2625 */
2626 union bdk_oclax_state_set
2627 {
2628 uint64_t u;
2629 struct bdk_oclax_state_set_s
2630 {
2631 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2632 uint64_t fsm1_state : 4; /**< [ 63: 60](RO/H) See OCLA()_STATE_INT[FSM1_STATE]. */
2633 uint64_t fsm0_state : 4; /**< [ 59: 56](RO/H) See OCLA()_STATE_INT[FSM0_STATE]. */
2634 uint64_t reserved_36_55 : 20;
2635 uint64_t fsm1_rst : 1; /**< [ 35: 35](R/W1S) See OCLA()_STATE_INT[FSM1_RST]. */
2636 uint64_t fsm0_rst : 1; /**< [ 34: 34](R/W1S) See OCLA()_STATE_INT[FSM0_RST]. */
2637 uint64_t fsm1_ena : 1; /**< [ 33: 33](R/W1S/H) See OCLA()_STATE_INT[FSM1_ENA]. */
2638 uint64_t fsm0_ena : 1; /**< [ 32: 32](R/W1S/H) See OCLA()_STATE_INT[FSM0_ENA]. */
2639 uint64_t reserved_19_31 : 13;
2640 uint64_t ddrfull : 1; /**< [ 18: 18](R/W1S/H) See OCLA()_STATE_INT[DDRFULL]. */
2641 uint64_t wmark : 1; /**< [ 17: 17](R/W1S/H) See OCLA()_STATE_INT[WMARK]. */
2642 uint64_t overfull : 1; /**< [ 16: 16](R/W1S/H) See OCLA()_STATE_INT[OVERFULL]. */
2643 uint64_t trigfull : 1; /**< [ 15: 15](R/W1S/H) See OCLA()_STATE_INT[TRIGFULL]. */
2644 uint64_t captured : 1; /**< [ 14: 14](R/W1S/H) See OCLA()_STATE_INT[CAPTURED]. */
2645 uint64_t fsm1_int : 1; /**< [ 13: 13](R/W1S/H) See OCLA()_STATE_INT[FSM1_INT]. */
2646 uint64_t fsm0_int : 1; /**< [ 12: 12](R/W1S/H) See OCLA()_STATE_INT[FSM0_INT]. */
2647 uint64_t mcd : 3; /**< [ 11: 9](R/W1S/H) See OCLA()_STATE_INT[MCD]. */
2648 uint64_t trig : 1; /**< [ 8: 8](R/W1S/H) See OCLA()_STATE_INT[TRIG]. */
2649 uint64_t reserved_4_7 : 4;
2650 uint64_t ovfl : 4; /**< [ 3: 0](R/W1S/H) See OCLA()_STATE_INT[OVFL]. */
2651 #else /* Word 0 - Little Endian */
2652 uint64_t ovfl : 4; /**< [ 3: 0](R/W1S/H) See OCLA()_STATE_INT[OVFL]. */
2653 uint64_t reserved_4_7 : 4;
2654 uint64_t trig : 1; /**< [ 8: 8](R/W1S/H) See OCLA()_STATE_INT[TRIG]. */
2655 uint64_t mcd : 3; /**< [ 11: 9](R/W1S/H) See OCLA()_STATE_INT[MCD]. */
2656 uint64_t fsm0_int : 1; /**< [ 12: 12](R/W1S/H) See OCLA()_STATE_INT[FSM0_INT]. */
2657 uint64_t fsm1_int : 1; /**< [ 13: 13](R/W1S/H) See OCLA()_STATE_INT[FSM1_INT]. */
2658 uint64_t captured : 1; /**< [ 14: 14](R/W1S/H) See OCLA()_STATE_INT[CAPTURED]. */
2659 uint64_t trigfull : 1; /**< [ 15: 15](R/W1S/H) See OCLA()_STATE_INT[TRIGFULL]. */
2660 uint64_t overfull : 1; /**< [ 16: 16](R/W1S/H) See OCLA()_STATE_INT[OVERFULL]. */
2661 uint64_t wmark : 1; /**< [ 17: 17](R/W1S/H) See OCLA()_STATE_INT[WMARK]. */
2662 uint64_t ddrfull : 1; /**< [ 18: 18](R/W1S/H) See OCLA()_STATE_INT[DDRFULL]. */
2663 uint64_t reserved_19_31 : 13;
2664 uint64_t fsm0_ena : 1; /**< [ 32: 32](R/W1S/H) See OCLA()_STATE_INT[FSM0_ENA]. */
2665 uint64_t fsm1_ena : 1; /**< [ 33: 33](R/W1S/H) See OCLA()_STATE_INT[FSM1_ENA]. */
2666 uint64_t fsm0_rst : 1; /**< [ 34: 34](R/W1S) See OCLA()_STATE_INT[FSM0_RST]. */
2667 uint64_t fsm1_rst : 1; /**< [ 35: 35](R/W1S) See OCLA()_STATE_INT[FSM1_RST]. */
2668 uint64_t reserved_36_55 : 20;
2669 uint64_t fsm0_state : 4; /**< [ 59: 56](RO/H) See OCLA()_STATE_INT[FSM0_STATE]. */
2670 uint64_t fsm1_state : 4; /**< [ 63: 60](RO/H) See OCLA()_STATE_INT[FSM1_STATE]. */
2671 #endif /* Word 0 - End */
2672 } s;
2673 /* struct bdk_oclax_state_set_s cn; */
2674 };
2675 typedef union bdk_oclax_state_set bdk_oclax_state_set_t;
2676
2677 static inline uint64_t BDK_OCLAX_STATE_SET(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_STATE_SET(unsigned long a)2678 static inline uint64_t BDK_OCLAX_STATE_SET(unsigned long a)
2679 {
2680 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2681 return 0x87e0a80000a0ll + 0x1000000ll * ((a) & 0x1);
2682 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2683 return 0x87e0a80000a0ll + 0x1000000ll * ((a) & 0x3);
2684 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2685 return 0x87e0a80000a0ll + 0x1000000ll * ((a) & 0x7);
2686 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2687 return 0x87e0b00000a0ll + 0x1000000ll * ((a) & 0x7);
2688 __bdk_csr_fatal("OCLAX_STATE_SET", 1, a, 0, 0, 0);
2689 }
2690
2691 #define typedef_BDK_OCLAX_STATE_SET(a) bdk_oclax_state_set_t
2692 #define bustype_BDK_OCLAX_STATE_SET(a) BDK_CSR_TYPE_RSL
2693 #define basename_BDK_OCLAX_STATE_SET(a) "OCLAX_STATE_SET"
2694 #define device_bar_BDK_OCLAX_STATE_SET(a) 0x0 /* PF_BAR0 */
2695 #define busnum_BDK_OCLAX_STATE_SET(a) (a)
2696 #define arguments_BDK_OCLAX_STATE_SET(a) (a),-1,-1,-1
2697
2698 /**
2699 * Register (RSL) ocla#_time
2700 *
2701 * OCLA Current Time Registers
2702 */
2703 union bdk_oclax_time
2704 {
2705 uint64_t u;
2706 struct bdk_oclax_time_s
2707 {
2708 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2709 uint64_t cycle : 64; /**< [ 63: 0](R/W/H) Current time as free running counter. Loaded into captured control packets.
2710 Unconditionally clocked, independent of OCLA()_SFT_RST. */
2711 #else /* Word 0 - Little Endian */
2712 uint64_t cycle : 64; /**< [ 63: 0](R/W/H) Current time as free running counter. Loaded into captured control packets.
2713 Unconditionally clocked, independent of OCLA()_SFT_RST. */
2714 #endif /* Word 0 - End */
2715 } s;
2716 struct bdk_oclax_time_cn88xxp1
2717 {
2718 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2719 uint64_t reserved_32_63 : 32;
2720 uint64_t cycle : 32; /**< [ 31: 0](R/W/H) Current time as free running counter. Loaded into captured control packets.
2721 Unconditionally clocked, independent of OCLA()_SFT_RST. */
2722 #else /* Word 0 - Little Endian */
2723 uint64_t cycle : 32; /**< [ 31: 0](R/W/H) Current time as free running counter. Loaded into captured control packets.
2724 Unconditionally clocked, independent of OCLA()_SFT_RST. */
2725 uint64_t reserved_32_63 : 32;
2726 #endif /* Word 0 - End */
2727 } cn88xxp1;
2728 /* struct bdk_oclax_time_s cn9; */
2729 /* struct bdk_oclax_time_s cn81xx; */
2730 /* struct bdk_oclax_time_s cn83xx; */
2731 /* struct bdk_oclax_time_s cn88xxp2; */
2732 };
2733 typedef union bdk_oclax_time bdk_oclax_time_t;
2734
2735 static inline uint64_t BDK_OCLAX_TIME(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCLAX_TIME(unsigned long a)2736 static inline uint64_t BDK_OCLAX_TIME(unsigned long a)
2737 {
2738 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2739 return 0x87e0a80000c0ll + 0x1000000ll * ((a) & 0x1);
2740 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
2741 return 0x87e0a80000c0ll + 0x1000000ll * ((a) & 0x3);
2742 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=4))
2743 return 0x87e0a80000c0ll + 0x1000000ll * ((a) & 0x7);
2744 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=4))
2745 return 0x87e0b00000c0ll + 0x1000000ll * ((a) & 0x7);
2746 __bdk_csr_fatal("OCLAX_TIME", 1, a, 0, 0, 0);
2747 }
2748
2749 #define typedef_BDK_OCLAX_TIME(a) bdk_oclax_time_t
2750 #define bustype_BDK_OCLAX_TIME(a) BDK_CSR_TYPE_RSL
2751 #define basename_BDK_OCLAX_TIME(a) "OCLAX_TIME"
2752 #define device_bar_BDK_OCLAX_TIME(a) 0x0 /* PF_BAR0 */
2753 #define busnum_BDK_OCLAX_TIME(a) (a)
2754 #define arguments_BDK_OCLAX_TIME(a) (a),-1,-1,-1
2755
2756 #endif /* __BDK_CSRS_OCLA_H__ */
2757