1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <bootmode.h>
5 #include <console/console.h>
6 #include <cpu/intel/common/common.h>
7 #include <cpu/intel/cpu_ids.h>
8 #include <cpu/x86/msr.h>
9 #include <device/device.h>
10 #include <device/pci.h>
11 #include <drivers/wifi/generic/wifi.h>
12 #include <elog.h>
13 #include <fsp/fsp_debug_event.h>
14 #include <fsp/util.h>
15 #include <intelbasecode/ramtop.h>
16 #include <intelblocks/cpulib.h>
17 #include <intelblocks/cse.h>
18 #include <intelblocks/pcie_rp.h>
19 #include <option.h>
20 #include <soc/cpu.h>
21 #include <soc/gpio_soc_defs.h>
22 #include <soc/iomap.h>
23 #include <soc/msr.h>
24 #include <soc/pci_devs.h>
25 #include <soc/pcie.h>
26 #include <soc/romstage.h>
27 #include <soc/soc_chip.h>
28 #include <soc/soc_info.h>
29 #include <string.h>
30 #include <ux_locales.h>
31
32 #define FSP_CLK_NOTUSED 0xFF
33 #define FSP_CLK_LAN 0x70
34 #define FSP_CLK_FREE_RUNNING 0x80
35
pcie_rp_init(FSP_M_CONFIG * m_cfg,uint32_t en_mask,const struct pcie_rp_config * cfg,size_t cfg_count)36 static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
37 const struct pcie_rp_config *cfg, size_t cfg_count)
38 {
39 size_t i;
40 static unsigned int clk_req_mapping = 0;
41
42 for (i = 0; i < cfg_count; i++) {
43 if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) {
44 m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
45 continue;
46 }
47 if (!(en_mask & BIT(i)))
48 continue;
49 if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
50 continue;
51 if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) {
52 printk(BIOS_WARNING, "Missing root port clock structure definition\n");
53 continue;
54 }
55 if (clk_req_mapping & (1 << cfg[i].clk_req))
56 printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
57 , cfg[i].clk_req);
58 if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
59 m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
60 clk_req_mapping |= 1 << cfg[i].clk_req;
61 }
62 m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i;
63 }
64 }
65
fill_fspm_pcie_rp_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)66 static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg,
67 const struct soc_intel_meteorlake_config *config)
68 {
69 /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */
70 unsigned int i;
71 uint8_t max_clock = get_max_pcie_clock();
72
73 for (i = 0; i < max_clock; i++) {
74 if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
75 m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
76 else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
77 m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;
78 else
79 m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED;
80 m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
81 }
82
83 /* PCIE ports */
84 if (CONFIG(SOC_INTEL_METEORLAKE_U_H)) {
85 m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table());
86 m_cfg->PchPcieRpEnableMask = 0; /* Don't care about PCH PCIE RP Mask */
87 pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp,
88 get_max_pcie_port());
89 } else {
90 /*
91 * FIXME: Implement PCIe RP mask for `PchPcieRpEnableMask` and
92 * perform pcie_rp_init().
93 */
94 m_cfg->PcieRpEnableMask = 0; /* Don't care about SOC/IOE PCIE RP Mask */
95 }
96 }
97
fill_fspm_igd_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)98 static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
99 const struct soc_intel_meteorlake_config *config)
100 {
101 unsigned int i;
102 const struct ddi_port_upds {
103 uint8_t *ddc;
104 uint8_t *hpd;
105 } ddi_port_upds[] = {
106 [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd},
107 [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd},
108 [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd},
109 [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd},
110 [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd},
111 [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd},
112 [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd},
113 };
114 m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD);
115 if (m_cfg->InternalGfx) {
116 /* IGD is enabled, set IGD stolen size to 128MB. */
117 m_cfg->IgdDvmt50PreAlloc = IGD_SM_128MB;
118 /* DP port config */
119 m_cfg->DdiPortAConfig = config->ddi_port_A_config;
120 m_cfg->DdiPortBConfig = config->ddi_port_B_config;
121 for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) {
122 *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] &
123 DDI_ENABLE_DDC);
124 *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] &
125 DDI_ENABLE_HPD);
126 }
127 } else {
128 /* IGD is disabled, skip IGD init in FSP. */
129 m_cfg->IgdDvmt50PreAlloc = 0;
130 /* DP port config */
131 m_cfg->DdiPortAConfig = 0;
132 m_cfg->DdiPortBConfig = 0;
133 for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) {
134 *ddi_port_upds[i].ddc = 0;
135 *ddi_port_upds[i].hpd = 0;
136 }
137 }
138 }
139
fill_fspm_mrc_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)140 static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
141 const struct soc_intel_meteorlake_config *config)
142 {
143 unsigned int i;
144
145 m_cfg->SaGv = config->sagv;
146
147 if (m_cfg->SaGv) {
148 /*
149 * Set SaGv work points after reviewing the power and performance impact
150 * with SaGv set to 1 (Enabled) and various work points between 0-3 being
151 * enabled.
152 */
153 if (config->sagv_wp_bitmap)
154 m_cfg->SaGvWpMask = config->sagv_wp_bitmap;
155 else
156 m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3;
157
158 for (i = 0; i < HOB_MAX_SAGV_POINTS; i++) {
159 m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i];
160 m_cfg->SaGvGear[i] = config->sagv_gear[i];
161 }
162 }
163
164 m_cfg->RMT = config->rmt;
165 m_cfg->RMC = 0;
166 m_cfg->MarginLimitCheck = 0;
167 /* Enable MRC Fast Boot */
168 m_cfg->MrcFastBoot = 1;
169 m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size;
170 }
171
fill_fspm_cpu_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)172 static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
173 const struct soc_intel_meteorlake_config *config)
174 {
175 m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
176 /* CpuRatio Settings */
177 if (config->cpu_ratio_override)
178 m_cfg->CpuRatio = config->cpu_ratio_override;
179 else
180 /* Set CpuRatio to match existing MSR value */
181 m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
182
183 m_cfg->PrmrrSize = get_valid_prmrr_size();
184 m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
185 }
186
fill_tme_params(FSP_M_CONFIG * m_cfg)187 static void fill_tme_params(FSP_M_CONFIG *m_cfg)
188 {
189 m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
190 if (!m_cfg->TmeEnable)
191 return;
192 m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT) &&
193 CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP);
194 if (m_cfg->GenerateNewTmeKey) {
195 uint32_t ram_top = get_ramtop_addr();
196 if (!ram_top) {
197 printk(BIOS_WARNING, "Invalid exclusion range start address. "
198 "Full memory encryption is enabled.\n");
199 return;
200 }
201 m_cfg->TmeExcludeBase = (ram_top - 16*MiB);
202 m_cfg->TmeExcludeSize = 16*MiB;
203 }
204 }
205
fill_fspm_security_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)206 static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,
207 const struct soc_intel_meteorlake_config *config)
208 {
209 /* Disable BIOS Guard */
210 m_cfg->BiosGuard = 0;
211 fill_tme_params(m_cfg);
212 }
213
fill_fspm_uart_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)214 static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg,
215 const struct soc_intel_meteorlake_config *config)
216 {
217 if (CONFIG(DRIVERS_UART_8250IO))
218 m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
219 m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
220 m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
221 }
222
fill_fspm_ipu_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)223 static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg,
224 const struct soc_intel_meteorlake_config *config)
225 {
226 /* Image clock: disable all clocks for bypassing FSP pin mux */
227 memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
228 /* IPU */
229 m_cfg->SaIpuEnable = is_devfn_enabled(PCI_DEVFN_IPU);
230 }
231
fill_fspm_smbus_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)232 static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg,
233 const struct soc_intel_meteorlake_config *config)
234 {
235 m_cfg->SmbusEnable = is_devfn_enabled(PCI_DEVFN_SMBUS);
236 }
237
fill_fspm_vr_config_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)238 static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
239 const struct soc_intel_meteorlake_config *config)
240 {
241 /* FastVmode Settings for VR domains */
242 for (size_t domain = 0; domain < NUM_VR_DOMAINS; domain++) {
243 if (config->cep_enable[domain]) {
244 m_cfg->CepEnable[domain] = config->cep_enable[domain];
245 if (config->enable_fast_vmode[domain]) {
246 m_cfg->EnableFastVmode[domain] = config->enable_fast_vmode[domain];
247 m_cfg->IccLimit[domain] = config->fast_vmode_i_trip[domain];
248 }
249 }
250 if (config->ps_cur_1_threshold[domain])
251 m_cfg->Psi1Threshold[domain] = config->ps_cur_1_threshold[domain];
252 if (config->ps_cur_2_threshold[domain])
253 m_cfg->Psi2Threshold[domain] = config->ps_cur_2_threshold[domain];
254 if (config->ps_cur_3_threshold[domain])
255 m_cfg->Psi3Threshold[domain] = config->ps_cur_3_threshold[domain];
256 }
257 }
258
fill_fspm_misc_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)259 static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
260 const struct soc_intel_meteorlake_config *config)
261 {
262 /* Disable Lock PCU Thermal Management registers */
263 m_cfg->LockPTMregs = 0;
264
265 /* Skip CPU replacement check */
266 m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check;
267
268 /* Skip GPIO configuration from FSP */
269 m_cfg->GpioOverride = 0x1;
270
271 /* Skip MBP HOB */
272 m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB);
273
274 m_cfg->SkipExtGfxScan = config->skip_ext_gfx_scan;
275
276 /* Set PsysPmax if it is available in DT.
277 PsysPmax is in unit of 1/8 Watt */
278 if (config->psys_pmax_watts)
279 m_cfg->PsysPmax = config->psys_pmax_watts * 8;
280 }
281
fill_fspm_audio_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)282 static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
283 const struct soc_intel_meteorlake_config *config)
284 {
285 /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
286 m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA);
287 m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable;
288 m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
289 m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
290 m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
291 m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable;
292
293 for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++)
294 m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i];
295
296 memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
297 memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
298 memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
299 }
300
fill_fspm_cnvi_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)301 static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg,
302 const struct soc_intel_meteorlake_config *config)
303 {
304 /* CNVi DDR RFI Mitigation */
305 const struct device_path path[] = {
306 { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_CNVI_WIFI },
307 { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } };
308 const struct device *dev = find_dev_nested_path(pci_root_bus(), path,
309 ARRAY_SIZE(path));
310 if (is_dev_enabled(dev))
311 m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev);
312 }
313
fill_fspm_ish_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)314 static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg,
315 const struct soc_intel_meteorlake_config *config)
316 {
317 m_cfg->PchIshEnable = is_devfn_enabled(PCI_DEVFN_ISH);
318 }
319
fill_fspm_tcss_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)320 static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg,
321 const struct soc_intel_meteorlake_config *config)
322 {
323 int i, max_port;
324
325 /* Tcss USB */
326 m_cfg->TcssXhciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XHCI);
327 m_cfg->TcssXdciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XDCI);
328
329 /* TCSS DMA */
330 m_cfg->TcssDma0En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA0);
331 m_cfg->TcssDma1En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA1);
332
333 /* Enable TCSS port */
334 max_port = get_max_tcss_port();
335 m_cfg->UsbTcPortEnPreMem = 0;
336 for (i = 0; i < max_port; i++)
337 if (config->tcss_ports[i].enable)
338 m_cfg->UsbTcPortEnPreMem |= BIT(i);
339 }
340
fill_fspm_usb4_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)341 static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg,
342 const struct soc_intel_meteorlake_config *config)
343 {
344 m_cfg->TcssItbtPcie0En = is_devfn_enabled(PCI_DEVFN_TBT0);
345 m_cfg->TcssItbtPcie1En = is_devfn_enabled(PCI_DEVFN_TBT1);
346 m_cfg->TcssItbtPcie2En = is_devfn_enabled(PCI_DEVFN_TBT2);
347 m_cfg->TcssItbtPcie3En = is_devfn_enabled(PCI_DEVFN_TBT3);
348 }
349
fill_fspm_vtd_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)350 static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg,
351 const struct soc_intel_meteorlake_config *config)
352 {
353 m_cfg->VtdDisable = 0;
354 m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
355 m_cfg->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
356
357 /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
358 m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
359 }
360
fill_fspm_trace_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)361 static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
362 const struct soc_intel_meteorlake_config *config)
363 {
364 /* Set debug probe type */
365 m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_METEORLAKE_DEBUG_CONSENT;
366
367 /* CrashLog config */
368 if (CONFIG(SOC_INTEL_CRASHLOG)) {
369 m_cfg->CpuCrashLogEnable = 1;
370 }
371 }
372
fill_fspm_ibecc_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)373 static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg,
374 const struct soc_intel_meteorlake_config *config)
375 {
376 /* In-Band ECC configuration */
377 if (config->ibecc.enable) {
378 m_cfg->Ibecc = config->ibecc.enable;
379 m_cfg->IbeccParity = config->ibecc.parity_en;
380 m_cfg->IbeccOperationMode = config->ibecc.mode;
381 if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) {
382 FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionEnable,
383 config->ibecc.region_enable);
384 FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionBase,
385 config->ibecc.region_base);
386 FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionMask,
387 config->ibecc.region_mask);
388 }
389 }
390 }
391
fill_fsps_acoustic_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)392 static void fill_fsps_acoustic_params(FSP_M_CONFIG *m_cfg,
393 const struct soc_intel_meteorlake_config *config)
394 {
395 if (!config->enable_acoustic_noise_mitigation)
396 return;
397
398 m_cfg->AcousticNoiseMitigation = config->enable_acoustic_noise_mitigation;
399
400 for (int i = 0; i < NUM_VR_DOMAINS; i++) {
401 m_cfg->FastPkgCRampDisable[i] = config->disable_fast_pkgc_ramp[i];
402 m_cfg->SlowSlewRate[i] = config->slow_slew_rate_config[i];
403 }
404 }
405
soc_memory_init_params(FSP_M_CONFIG * m_cfg,const struct soc_intel_meteorlake_config * config)406 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
407 const struct soc_intel_meteorlake_config *config)
408 {
409 void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg,
410 const struct soc_intel_meteorlake_config *config) = {
411 fill_fspm_igd_params,
412 fill_fspm_mrc_params,
413 fill_fspm_cpu_params,
414 fill_fspm_security_params,
415 fill_fspm_uart_params,
416 fill_fspm_ipu_params,
417 fill_fspm_smbus_params,
418 fill_fspm_misc_params,
419 fill_fspm_audio_params,
420 fill_fspm_cnvi_params,
421 fill_fspm_pcie_rp_params,
422 fill_fspm_ish_params,
423 fill_fspm_tcss_params,
424 fill_fspm_usb4_params,
425 fill_fspm_vtd_params,
426 fill_fspm_trace_params,
427 fill_fspm_vr_config_params,
428 fill_fspm_ibecc_params,
429 fill_fsps_acoustic_params,
430 };
431
432 for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)
433 fill_fspm_params[i](m_cfg, config);
434 }
435
436 #define UX_MEMORY_TRAINING_DESC "memory_training_desc"
437
438 #define VGA_INIT_CONTROL_ENABLE BIT(0)
439 /* Tear down legacy VGA mode before exiting FSP-M. */
440 #define VGA_INIT_CONTROL_TEAR_DOWN BIT(1)
441
fill_fspm_sign_of_life(FSP_M_CONFIG * m_cfg,FSPM_ARCHx_UPD * arch_upd)442 static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
443 FSPM_ARCHx_UPD *arch_upd)
444 {
445 void *vbt;
446 size_t vbt_size;
447 uint32_t vga_init_control = 0;
448 uint8_t sol_type;
449
450 /* Memory training. */
451 if (!arch_upd->NvsBufferPtr) {
452 vga_init_control = VGA_INIT_CONTROL_ENABLE |
453 VGA_INIT_CONTROL_TEAR_DOWN;
454 sol_type = ELOG_FW_EARLY_SOL_MRC;
455 }
456
457 if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) {
458 vga_init_control = VGA_INIT_CONTROL_ENABLE;
459 sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC;
460 }
461
462 if (!vga_init_control)
463 return;
464
465 const char *text = ux_locales_get_text(UX_MEMORY_TRAINING_DESC);
466 /* No localized text found; fallback to built-in English. */
467 if (!text)
468 text = "Your device is finishing an update. "
469 "This may take 1-2 minutes.\n"
470 "Please do not turn off your device.";
471
472 vbt = cbfs_map("vbt.bin", &vbt_size);
473 if (!vbt) {
474 printk(BIOS_ERR, "Could not load vbt.bin\n");
475 return;
476 }
477
478 printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
479 elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type);
480
481 m_cfg->VgaInitControl = vga_init_control;
482 m_cfg->VbtPtr = (efi_uintn_t)vbt;
483 m_cfg->VbtSize = vbt_size;
484 m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
485 m_cfg->VgaMessage = (efi_uintn_t)text;
486 }
487
platform_fsp_memory_init_params_cb(FSPM_UPD * mupd,uint32_t version)488 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
489 {
490 const struct soc_intel_meteorlake_config *config;
491 FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
492 FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;
493
494 if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) {
495 if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) {
496 enum fsp_log_level log_level = fsp_map_console_log_level();
497 arch_upd->FspEventHandler = (efi_uintn_t)((FSP_EVENT_HANDLER *)
498 fsp_debug_event_handler);
499 /* Set Serial debug message level */
500 m_cfg->PcdSerialDebugLevel = log_level;
501 /* Set MRC debug level */
502 m_cfg->SerialDebugMrcLevel = log_level;
503 } else {
504 /* Disable Serial debug message */
505 m_cfg->PcdSerialDebugLevel = 0;
506 /* Disable MRC debug message */
507 m_cfg->SerialDebugMrcLevel = 0;
508 }
509 }
510 config = config_of_soc();
511
512 soc_memory_init_params(m_cfg, config);
513
514 if (CONFIG(SOC_INTEL_METEORLAKE_SIGN_OF_LIFE))
515 fill_fspm_sign_of_life(m_cfg, arch_upd);
516
517 mainboard_memory_init_params(mupd);
518 }
519
mainboard_memory_init_params(FSPM_UPD * memupd)520 __weak void mainboard_memory_init_params(FSPM_UPD *memupd)
521 {
522 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
523 }
524