1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <commonlib/bsd/gcd.h>
5 #include <console/console.h>
6 #include <delay.h>
7 #include <device/mmio.h>
8 #include <lib.h>
9 #include <soc/addressmap.h>
10 #include <soc/clock.h>
11 #include <soc/grf.h>
12 #include <soc/i2c.h>
13 #include <soc/soc.h>
14 #include <stdint.h>
15
16 struct pll_div {
17 u32 nr;
18 u32 nf;
19 u32 no;
20 };
21
22 struct rk3288_cru_reg {
23 u32 cru_apll_con[4];
24 u32 cru_dpll_con[4];
25 u32 cru_cpll_con[4];
26 u32 cru_gpll_con[4];
27 u32 cru_npll_con[4];
28 u32 cru_mode_con;
29 u32 reserved0[3];
30 u32 cru_clksel_con[43];
31 u32 reserved1[21];
32 u32 cru_clkgate_con[19];
33 u32 reserved2;
34 u32 cru_glb_srst_fst_value;
35 u32 cru_glb_srst_snd_value;
36 u32 cru_softrst_con[12];
37 u32 cru_misc_con;
38 u32 cru_glb_cnt_th;
39 u32 cru_glb_rst_con;
40 u32 reserved3;
41 u32 cru_glb_rst_st;
42 u32 reserved4;
43 u32 cru_sdmmc_con[2];
44 u32 cru_sdio0_con[2];
45 u32 cru_sdio1_con[2];
46 u32 cru_emmc_con[2];
47 };
48 check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c);
49
50 static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE;
51
52 #define PLL_DIVISORS(hz, _nr, _no) {\
53 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
54 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
55 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
56 "divisors on line " STRINGIFY(__LINE__))
57
58 /* Keep divisors as low as possible to reduce jitter and power usage. */
59 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
60 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
61
62 /* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
63 static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
64 static const struct pll_div apll_1416_cfg = PLL_DIVISORS(1416*MHz, 1, 1);
65 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2);
66 static const struct pll_div *apll_cfgs[] = {
67 [APLL_1800_MHZ] = &apll_1800_cfg,
68 [APLL_1416_MHZ] = &apll_1416_cfg,
69 [APLL_600_MHZ] = &apll_600_cfg,
70 };
71
72 /*******************PLL CON0 BITS***************************/
73 #define PLL_OD_MSK (0x0F)
74
75 #define PLL_NR_MSK (0x3F << 8)
76 #define PLL_NR_SHIFT (8)
77
78 /*******************PLL CON1 BITS***************************/
79 #define PLL_NF_MSK (0x1FFF)
80
81 /*******************PLL CON2 BITS***************************/
82 #define PLL_BWADJ_MSK (0x0FFF)
83
84 /*******************PLL CON3 BITS***************************/
85 #define PLL_RESET_MSK (1 << 5)
86 #define PLL_RESET (1 << 5)
87 #define PLL_RESET_RESUME (0 << 5)
88
89 /*******************CLKSEL0 BITS***************************/
90 /* core clk pll sel: amr or general */
91 #define CORE_SEL_PLL_MSK (1 << 15)
92 #define CORE_SEL_APLL (0 << 15)
93 #define CORE_SEL_GPLL (1 << 15)
94
95 /* a12 core clock div: clk_core = clk_src / (div_con + 1) */
96 #define A12_DIV_SHIFT (8)
97 #define A12_DIV_MSK (0x1F << 8)
98
99 /* mp core axi clock div: clk = clk_src / (div_con + 1) */
100 #define MP_DIV_SHIFT (4)
101 #define MP_DIV_MSK (0xF << 4)
102
103 /* m0 core axi clock div: clk = clk_src / (div_con + 1) */
104 #define M0_DIV_MSK (0xF)
105
106 /*******************CLKSEL1 BITS***************************/
107 /* pd bus clk pll sel: codec or general */
108 #define PD_BUS_SEL_PLL_MSK (1 << 15)
109 #define PD_BUS_SEL_CPLL (0 << 15)
110 #define PD_BUS_SEL_GPLL (1 << 15)
111
112 /* pd bus pclk div:
113 * pclk = pd_bus_aclk /(div + 1)
114 */
115 #define PD_BUS_PCLK_DIV_SHIFT (12)
116 #define PD_BUS_PCLK_DIV_MSK (0x7 << 12)
117
118 /* pd bus hclk div:
119 * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1
120 */
121 #define PD_BUS_HCLK_DIV_SHIFT (8)
122 #define PD_BUS_HCLK_DIV_MSK (0x3 << 8)
123
124 /* pd bus aclk div:
125 * pd_bus_aclk = pd_bus_src_clk /(div0 * div1)
126 */
127 #define PD_BUS_ACLK_DIV0_SHIFT (3)
128 #define PD_BUS_ACLK_DIV0_MASK (0x1f << 3)
129 #define PD_BUS_ACLK_DIV1_SHIFT (0)
130 #define PD_BUS_ACLK_DIV1_MASK (0x7 << 0)
131
132 /*******************CLKSEL10 BITS***************************/
133 /* peripheral bus clk pll sel: codec or general */
134 #define PERI_SEL_PLL_MSK (1 << 15)
135 #define PERI_SEL_CPLL (0 << 15)
136 #define PERI_SEL_GPLL (1 << 15)
137
138 /* peripheral bus pclk div:
139 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
140 */
141 #define PERI_PCLK_DIV_SHIFT (12)
142 #define PERI_PCLK_DIV_MSK (0x7 << 12)
143
144 /* peripheral bus hclk div:
145 * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1
146 */
147 #define PERI_HCLK_DIV_SHIFT (8)
148 #define PERI_HCLK_DIV_MSK (0x3 << 8)
149
150 /* peripheral bus aclk div:
151 * aclk_periph =
152 * periph_clk_src / (peri_aclk_div_con + 1)
153 */
154 #define PERI_ACLK_DIV_SHIFT (0x0)
155 #define PERI_ACLK_DIV_MSK (0x1F)
156
157 /*******************CLKSEL37 BITS***************************/
158 #define L2_DIV_MSK (0x7)
159
160 #define ATCLK_DIV_MSK (0x1F << 4)
161 #define ATCLK_DIV_SHIFT (4)
162
163 #define PCLK_DBG_DIV_MSK (0x1F << 9)
164 #define PCLK_DBG_DIV_SHIFT (9)
165
166 #define APLL_MODE_MSK (0x3)
167 #define APLL_MODE_SLOW (0)
168 #define APLL_MODE_NORM (1)
169
170 #define DPLL_MODE_MSK (0x3 << 4)
171 #define DPLL_MODE_SLOW (0 << 4)
172 #define DPLL_MODE_NORM (1 << 4)
173
174 #define CPLL_MODE_MSK (0x3 << 8)
175 #define CPLL_MODE_SLOW (0 << 8)
176 #define CPLL_MODE_NORM (1 << 8)
177
178 #define GPLL_MODE_MSK (0x3 << 12)
179 #define GPLL_MODE_SLOW (0 << 12)
180 #define GPLL_MODE_NORM (1 << 12)
181
182 #define NPLL_MODE_MSK (0x3 << 14)
183 #define NPLL_MODE_SLOW (0 << 14)
184 #define NPLL_MODE_NORM (1 << 14)
185
186 #define SOCSTS_DPLL_LOCK (1 << 5)
187 #define SOCSTS_APLL_LOCK (1 << 6)
188 #define SOCSTS_CPLL_LOCK (1 << 7)
189 #define SOCSTS_GPLL_LOCK (1 << 8)
190 #define SOCSTS_NPLL_LOCK (1 << 9)
191
192 #define VCO_MAX_KHZ (2200 * (MHz/KHz))
193 #define VCO_MIN_KHZ (440 * (MHz/KHz))
194 #define OUTPUT_MAX_KHZ (2200 * (MHz/KHz))
195 #define OUTPUT_MIN_KHZ 27500
196 #define FREF_MAX_KHZ (2200 * (MHz/KHz))
197 #define FREF_MIN_KHZ 269
198
rkclk_set_pll(u32 * pll_con,const struct pll_div * div)199 static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
200 {
201 /* All PLLs have same VCO and output frequency range restrictions. */
202 u32 vco_khz = OSC_HZ/KHz * div->nf / div->nr;
203 u32 output_khz = vco_khz / div->no;
204
205 printk(BIOS_DEBUG, "Configuring PLL at %p with NF = %d, NR = %d and "
206 "NO = %d (VCO = %uKHz, output = %uKHz)\n",
207 pll_con, div->nf, div->nr, div->no, vco_khz, output_khz);
208 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
209 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
210 (div->no == 1 || !(div->no % 2)));
211
212 /* enter rest */
213 write32(&pll_con[3], RK_SETBITS(PLL_RESET_MSK));
214
215 write32(&pll_con[0],
216 RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) |
217 RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1)));
218
219 write32(&pll_con[1], RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1)));
220
221 write32(&pll_con[2],
222 RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1)));
223
224 udelay(10);
225
226 /* return form rest */
227 write32(&pll_con[3], RK_CLRBITS(PLL_RESET_MSK));
228
229 return 0;
230 }
231
rkclk_init(void)232 void rkclk_init(void)
233 {
234 u32 aclk_div;
235 u32 hclk_div;
236 u32 pclk_div;
237
238 /* pll enter slow-mode */
239 write32(&cru_ptr->cru_mode_con,
240 RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) |
241 RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW));
242
243 /* init pll */
244 rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg);
245 rkclk_set_pll(&cru_ptr->cru_cpll_con[0], &cpll_init_cfg);
246
247 /* waiting for pll lock */
248 while (1) {
249 if ((read32(&rk3288_grf->soc_status[1])
250 & (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
251 == (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
252 break;
253 udelay(1);
254 }
255
256 /*
257 * pd_bus clock pll source selection and
258 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
259 */
260 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
261 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
262 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
263 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
264 PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2));
265
266 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
267 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
268 PD_BUS_ACLK_HZ && pclk_div <= 0x7);
269
270 write32(&cru_ptr->cru_clksel_con[1], RK_SETBITS(PD_BUS_SEL_GPLL) |
271 RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK,
272 pclk_div << PD_BUS_PCLK_DIV_SHIFT) |
273 RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK,
274 hclk_div << PD_BUS_HCLK_DIV_SHIFT) |
275 RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK,
276 aclk_div << PD_BUS_ACLK_DIV0_SHIFT) |
277 RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0));
278
279 /*
280 * peri clock pll source selection and
281 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
282 */
283 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
284 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
285
286 hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
287 assert((1 << hclk_div) * PERI_HCLK_HZ ==
288 PERI_ACLK_HZ && (hclk_div <= 0x2));
289
290 pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
291 assert((1 << pclk_div) * PERI_PCLK_HZ ==
292 PERI_ACLK_HZ && (pclk_div <= 0x3));
293
294 write32(&cru_ptr->cru_clksel_con[10], RK_SETBITS(PERI_SEL_GPLL) |
295 RK_CLRSETBITS(PERI_PCLK_DIV_MSK,
296 pclk_div << PERI_PCLK_DIV_SHIFT) |
297 RK_CLRSETBITS(PERI_HCLK_DIV_MSK,
298 hclk_div << PERI_HCLK_DIV_SHIFT) |
299 RK_CLRSETBITS(PERI_ACLK_DIV_MSK,
300 aclk_div << PERI_ACLK_DIV_SHIFT));
301
302 /* PLL enter normal-mode */
303 write32(&cru_ptr->cru_mode_con,
304 RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) |
305 RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM));
306 }
307
rkclk_configure_cpu(enum apll_frequencies apll_freq)308 void rkclk_configure_cpu(enum apll_frequencies apll_freq)
309 {
310 /* pll enter slow-mode */
311 write32(&cru_ptr->cru_mode_con,
312 RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW));
313
314 rkclk_set_pll(&cru_ptr->cru_apll_con[0], apll_cfgs[apll_freq]);
315
316 /* waiting for pll lock */
317 while (1) {
318 if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK)
319 break;
320 udelay(1);
321 }
322
323 /*
324 * core clock pll source selection and
325 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
326 * core clock select apll, apll clk = 1800MHz
327 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
328 */
329 write32(&cru_ptr->cru_clksel_con[0], RK_CLRBITS(CORE_SEL_PLL_MSK) |
330 RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) |
331 RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) |
332 RK_CLRSETBITS(M0_DIV_MSK, 1 << 0));
333
334 /*
335 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
336 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
337 */
338 write32(&cru_ptr->cru_clksel_con[37],
339 RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) |
340 RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) |
341 RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)));
342
343 /* PLL enter normal-mode */
344 write32(&cru_ptr->cru_mode_con,
345 RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM));
346 }
347
rkclk_configure_ddr(unsigned int hz)348 void rkclk_configure_ddr(unsigned int hz)
349 {
350 struct pll_div dpll_cfg;
351
352 switch (hz) {
353 case 300*MHz:
354 dpll_cfg = (struct pll_div){.nf = 50, .nr = 2, .no = 2};
355 break;
356 case 533*MHz: /* actually 533.3P MHz */
357 dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2};
358 break;
359 case 666*MHz: /* actually 666.6P MHz */
360 dpll_cfg = (struct pll_div){.nf = 500, .nr = 9, .no = 2};
361 break;
362 case 800*MHz:
363 dpll_cfg = (struct pll_div){.nf = 100, .nr = 3, .no = 1};
364 break;
365 default:
366 die("Unsupported SDRAM frequency, add to clock.c!");
367 }
368
369 /* pll enter slow-mode */
370 write32(&cru_ptr->cru_mode_con,
371 RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW));
372
373 rkclk_set_pll(&cru_ptr->cru_dpll_con[0], &dpll_cfg);
374
375 /* waiting for pll lock */
376 while (1) {
377 if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK)
378 break;
379 udelay(1);
380 }
381
382 /* PLL enter normal-mode */
383 write32(&cru_ptr->cru_mode_con,
384 RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM));
385 }
386
rkclk_ddr_reset(u32 ch,u32 ctl,u32 phy)387 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy)
388 {
389 u32 phy_ctl_srstn_shift = 4 + 5 * ch;
390 u32 ctl_psrstn_shift = 3 + 5 * ch;
391 u32 ctl_srstn_shift = 2 + 5 * ch;
392 u32 phy_psrstn_shift = 1 + 5 * ch;
393 u32 phy_srstn_shift = 5 * ch;
394
395 write32(&cru_ptr->cru_softrst_con[10],
396 RK_CLRSETBITS(1 << phy_ctl_srstn_shift,
397 phy << phy_ctl_srstn_shift) |
398 RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) |
399 RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) |
400 RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) |
401 RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift));
402 }
403
rkclk_ddr_phy_ctl_reset(u32 ch,u32 n)404 void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n)
405 {
406 u32 phy_ctl_srstn_shift = 4 + 5 * ch;
407
408 write32(&cru_ptr->cru_softrst_con[10],
409 RK_CLRSETBITS(1 << phy_ctl_srstn_shift,
410 n << phy_ctl_srstn_shift));
411 }
412
rkclk_configure_spi(unsigned int bus,unsigned int hz)413 void rkclk_configure_spi(unsigned int bus, unsigned int hz)
414 {
415 int src_clk_div = GPLL_HZ / hz;
416
417 assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == GPLL_HZ));
418
419 switch (bus) { /*select gpll as spi src clk, and set div*/
420 case 0:
421 write32(&cru_ptr->cru_clksel_con[25],
422 RK_CLRSETBITS(1 << 7 | 0x1f << 0,
423 1 << 7 | (src_clk_div - 1) << 0));
424 break;
425 case 1:
426 write32(&cru_ptr->cru_clksel_con[25],
427 RK_CLRSETBITS(1 << 15 | 0x1f << 8,
428 1 << 15 | (src_clk_div - 1) << 8));
429 break;
430 case 2:
431 write32(&cru_ptr->cru_clksel_con[39],
432 RK_CLRSETBITS(1 << 7 | 0x1f << 0,
433 1 << 7 | (src_clk_div - 1) << 0));
434 break;
435 default:
436 printk(BIOS_ERR, "do not support this spi bus\n");
437 }
438 }
439
rkclk_configure_i2s(unsigned int hz)440 void rkclk_configure_i2s(unsigned int hz)
441 {
442 int n, d;
443 int v;
444
445 /* i2s source clock: gpll
446 i2s0_outclk_sel: clk_i2s
447 i2s0_clk_sel: divider output from fraction
448 i2s0_pll_div_con: 0*/
449 write32(&cru_ptr->cru_clksel_con[4],
450 RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0,
451 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0));
452
453 /* set frac divider */
454 v = gcd(GPLL_HZ, hz);
455 n = (GPLL_HZ / v) & (0xffff);
456 d = (hz / v) & (0xffff);
457 assert(hz == GPLL_HZ / n * d);
458 write32(&cru_ptr->cru_clksel_con[8], d << 16 | n);
459 }
460
rkclk_configure_crypto(unsigned int hz)461 void rkclk_configure_crypto(unsigned int hz)
462 {
463 u32 div = PD_BUS_ACLK_HZ / hz;
464
465 assert((div - 1 <= 3) && (div * hz == PD_BUS_ACLK_HZ));
466 assert(hz <= 150*MHz); /* Suggested max in TRM. */
467 write32(&cru_ptr->cru_clksel_con[26],
468 RK_CLRSETBITS(0x3 << 6, (div - 1) << 6));
469 }
470
rkclk_configure_tsadc(unsigned int hz)471 void rkclk_configure_tsadc(unsigned int hz)
472 {
473 u32 div;
474 u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/
475
476 div = src_clk / hz;
477 assert((div - 1 <= 63) && (div * hz == 32 * KHz));
478 write32(&cru_ptr->cru_clksel_con[2],
479 RK_CLRSETBITS(0x3f << 0, (div - 1) << 0));
480 }
481
pll_para_config(u32 freq_hz,struct pll_div * div,u32 * ext_div)482 static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div)
483 {
484 u32 ref_khz = OSC_HZ / KHz, nr, nf = 0;
485 u32 fref_khz;
486 u32 diff_khz, best_diff_khz;
487 const u32 max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
488 u32 vco_khz;
489 u32 no = 1;
490 u32 freq_khz = freq_hz / KHz;
491
492 if (!freq_hz) {
493 printk(BIOS_ERR, "%s: the frequency can not be 0 Hz\n", __func__);
494 return -1;
495 }
496
497 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
498 if (ext_div) {
499 *ext_div = DIV_ROUND_UP(no, max_no);
500 no = DIV_ROUND_UP(no, *ext_div);
501 }
502
503 /* only even divisors (and 1) are supported */
504 if (no > 1)
505 no = DIV_ROUND_UP(no, 2) * 2;
506
507 vco_khz = freq_khz * no;
508 if (ext_div)
509 vco_khz *= *ext_div;
510
511 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
512 printk(BIOS_ERR, "%s: Cannot find out a supported VCO"
513 " for Frequency (%uHz).\n", __func__, freq_hz);
514 return -1;
515 }
516
517 div->no = no;
518
519 best_diff_khz = vco_khz;
520 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
521 fref_khz = ref_khz / nr;
522 if (fref_khz < FREF_MIN_KHZ)
523 break;
524 if (fref_khz > FREF_MAX_KHZ)
525 continue;
526
527 nf = vco_khz / fref_khz;
528 if (nf >= max_nf)
529 continue;
530 diff_khz = vco_khz - nf * fref_khz;
531 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
532 nf++;
533 diff_khz = fref_khz - diff_khz;
534 }
535
536 if (diff_khz >= best_diff_khz)
537 continue;
538
539 best_diff_khz = diff_khz;
540 div->nr = nr;
541 div->nf = nf;
542 }
543
544 if (best_diff_khz > 4 * (MHz/KHz)) {
545 printk(BIOS_ERR, "%s: Failed to match output frequency %u, "
546 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
547 best_diff_khz * KHz);
548 return -1;
549 }
550
551 return 0;
552 }
553
rkclk_configure_edp(void)554 void rkclk_configure_edp(void)
555 {
556 /* clk_edp_24M source: 24M */
557 write32(&cru_ptr->cru_clksel_con[28], RK_SETBITS(1 << 15));
558
559 /* rst edp */
560 write32(&cru_ptr->cru_softrst_con[6], RK_SETBITS(1 << 15));
561 udelay(1);
562 write32(&cru_ptr->cru_softrst_con[6], RK_CLRBITS(1 << 15));
563 }
564
rkclk_configure_hdmi(void)565 void rkclk_configure_hdmi(void)
566 {
567 /* enable pclk hdmi ctrl */
568 write32(&cru_ptr->cru_clkgate_con[16], RK_CLRBITS(1 << 9));
569
570 /* software reset hdmi */
571 write32(&cru_ptr->cru_softrst_con[7], RK_SETBITS(1 << 9));
572 udelay(1);
573 write32(&cru_ptr->cru_softrst_con[7], RK_CLRBITS(1 << 9));
574 }
575
rkclk_configure_vop_aclk(u32 vop_id,u32 aclk_hz)576 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
577 {
578 u32 div;
579
580 /* vop aclk source clk: cpll */
581 div = CPLL_HZ / aclk_hz;
582 assert((div - 1 <= 63) && (div * aclk_hz == CPLL_HZ));
583
584 switch (vop_id) {
585 case 0:
586 write32(&cru_ptr->cru_clksel_con[31],
587 RK_CLRSETBITS(3 << 6 | 0x1f << 0,
588 0 << 6 | (div - 1) << 0));
589 break;
590
591 case 1:
592 write32(&cru_ptr->cru_clksel_con[31],
593 RK_CLRSETBITS(3 << 14 | 0x1f << 8,
594 0 << 14 | (div - 1) << 8));
595 break;
596 }
597 }
598
rkclk_configure_vop_dclk(u32 vop_id,u32 dclk_hz)599 int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
600 {
601 struct pll_div npll_config = {0};
602 u32 lcdc_div;
603
604 if (pll_para_config(dclk_hz, &npll_config, &lcdc_div))
605 return -1;
606
607 /* npll enter slow-mode */
608 write32(&cru_ptr->cru_mode_con,
609 RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_SLOW));
610
611 rkclk_set_pll(&cru_ptr->cru_npll_con[0], &npll_config);
612
613 /* waiting for pll lock */
614 while (1) {
615 if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
616 break;
617 udelay(1);
618 }
619
620 /* npll enter normal-mode */
621 write32(&cru_ptr->cru_mode_con,
622 RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_NORM));
623
624 /* vop dclk source clk: npll,dclk_div: 1 */
625 switch (vop_id) {
626 case 0:
627 write32(&cru_ptr->cru_clksel_con[27],
628 RK_CLRSETBITS(0xff << 8 | 3 << 0,
629 (lcdc_div - 1) << 8 | 2 << 0));
630 break;
631
632 case 1:
633 write32(&cru_ptr->cru_clksel_con[29],
634 RK_CLRSETBITS(0xff << 8 | 3 << 6,
635 (lcdc_div - 1) << 8 | 2 << 6));
636 break;
637 }
638 return 0;
639 }
640
rkclk_was_watchdog_reset(void)641 int rkclk_was_watchdog_reset(void)
642 {
643 /* Bits 5 and 4 are "second" and "first" global watchdog reset. */
644 return read32(&cru_ptr->cru_glb_rst_st) & 0x30;
645 }
646
rkclk_i2c_clock_for_bus(unsigned int bus)647 unsigned int rkclk_i2c_clock_for_bus(unsigned int bus)
648 {
649 /*i2c0,i2c2 src clk from pd_bus_pclk
650 other i2c src clk from peri_pclk
651 */
652 switch (bus) {
653 case 0:
654 case 2:
655 return PD_BUS_PCLK_HZ;
656
657 case 1:
658 case 3:
659 case 4:
660 case 5:
661 return PERI_PCLK_HZ;
662
663 default:
664 return -1; /* Should never happen. */
665 }
666 }
667