1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef CPU_SAMSUNG_EXYNOS5250_CLK_H 4 #define CPU_SAMSUNG_EXYNOS5250_CLK_H 5 6 #include <soc/cpu.h> 7 #include <soc/dmc.h> 8 #include <soc/pinmux.h> 9 #include <stdint.h> 10 11 enum periph_id; 12 13 #define APLL 0 14 #define MPLL 1 15 #define EPLL 2 16 #define HPLL 3 17 #define VPLL 4 18 #define BPLL 5 19 20 enum pll_src_bit { 21 SRC_MPLL = 6, 22 SRC_EPLL, 23 SRC_VPLL, 24 }; 25 26 /* * 27 * This structure is to store the src bit, div bit and prediv bit 28 * positions of the peripheral clocks of the src and div registers 29 */ 30 struct clk_bit_info { 31 s8 src_bit; /* offset in register to clock source field */ 32 s8 n_src_bits; /* number of bits in 'src_bit' field */ 33 s8 div_bit; 34 s8 prediv_bit; 35 }; 36 37 unsigned long get_pll_clk(int pllreg); 38 unsigned long get_arm_clk(void); 39 unsigned long get_pwm_clk(void); 40 unsigned long get_uart_clk(int dev_index); 41 void set_mmc_clk(int dev_index, unsigned int div); 42 43 /** 44 * get the clk frequency of the required peripheral 45 * 46 * @param peripheral Peripheral id 47 * 48 * @return frequency of the peripheral clk 49 */ 50 unsigned long clock_get_periph_rate(enum periph_id peripheral); 51 52 #define MCT_HZ 24000000 53 54 /* 55 * Set mshci controller instances clock divider 56 * 57 * @param enum periph_id instance of the mshci controller 58 * 59 * Return 0 if ok else -1 60 */ 61 int clock_set_mshci(enum periph_id peripheral); 62 63 /* 64 * Sets the epll clockrate 65 * 66 * @param rate Required clock rate to the prescaler in Hz 67 * 68 * Return 0 if ok else -1 69 */ 70 int clock_epll_set_rate(unsigned long rate); 71 72 /* 73 * selects the clk source for I2S MCLK 74 */ 75 void clock_select_i2s_clk_source(void); 76 77 /* 78 * Set prescaler division based on input and output frequency 79 * for i2s audio clock 80 * 81 * @param src_frq Source frequency in Hz 82 * @param dst_frq Required MCLK frequency in Hz 83 * 84 * Return 0 if ok else -1 85 */ 86 int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); 87 88 struct exynos5_clock { 89 unsigned int apll_lock; /* base + 0 */ 90 unsigned char res1[0xfc]; 91 unsigned int apll_con0; 92 unsigned int apll_con1; 93 unsigned char res2[0xf8]; 94 unsigned int src_cpu; 95 unsigned char res3[0x1fc]; 96 unsigned int mux_stat_cpu; 97 unsigned char res4[0xfc]; 98 unsigned int div_cpu0; 99 unsigned int div_cpu1; 100 unsigned char res5[0xf8]; 101 unsigned int div_stat_cpu0; 102 unsigned int div_stat_cpu1; 103 unsigned char res6[0x1f8]; 104 unsigned int gate_sclk_cpu; 105 unsigned char res7[0x1fc]; 106 unsigned int clkout_cmu_cpu; 107 unsigned int clkout_cmu_cpu_div_stat; 108 unsigned char res8[0x5f8]; 109 110 unsigned int armclk_stopctrl; /* base + 0x1000 */ 111 unsigned int atclk_stopctrl; 112 unsigned char res9[0x8]; 113 unsigned int parityfail_status; 114 unsigned int parityfail_clear; 115 unsigned char res10[0x8]; 116 unsigned int pwr_ctrl; 117 unsigned int pwr_ctr2; 118 unsigned char res11[0xd8]; 119 unsigned int apll_con0_l8; 120 unsigned int apll_con0_l7; 121 unsigned int apll_con0_l6; 122 unsigned int apll_con0_l5; 123 unsigned int apll_con0_l4; 124 unsigned int apll_con0_l3; 125 unsigned int apll_con0_l2; 126 unsigned int apll_con0_l1; 127 unsigned int iem_control; 128 unsigned char res12[0xdc]; 129 unsigned int apll_con1_l8; 130 unsigned int apll_con1_l7; 131 unsigned int apll_con1_l6; 132 unsigned int apll_con1_l5; 133 unsigned int apll_con1_l4; 134 unsigned int apll_con1_l3; 135 unsigned int apll_con1_l2; 136 unsigned int apll_con1_l1; 137 unsigned char res13[0xe0]; 138 unsigned int div_iem_l8; 139 unsigned int div_iem_l7; 140 unsigned int div_iem_l6; 141 unsigned int div_iem_l5; 142 unsigned int div_iem_l4; 143 unsigned int div_iem_l3; 144 unsigned int div_iem_l2; 145 unsigned int div_iem_l1; 146 unsigned char res14[0x2ce0]; 147 148 unsigned int mpll_lock; /* base + 0x4000 */ 149 unsigned char res15[0xfc]; 150 unsigned int mpll_con0; 151 unsigned int mpll_con1; 152 unsigned char res16[0xf8]; 153 unsigned int src_core0; 154 unsigned int src_core1; 155 unsigned char res17[0xf8]; 156 unsigned int src_mask_core; 157 unsigned char res18[0x100]; 158 unsigned int mux_stat_core1; 159 unsigned char res19[0xf8]; 160 unsigned int div_core0; 161 unsigned int div_core1; 162 unsigned int div_sysrgt; 163 unsigned char res20[0xf4]; 164 unsigned int div_stat_core0; 165 unsigned int div_stat_core1; 166 unsigned int div_stat_sysrgt; 167 unsigned char res21[0x2f4]; 168 unsigned int gate_ip_core; 169 unsigned int gate_ip_sysrgt; 170 unsigned char res22[0xf8]; 171 unsigned int clkout_cmu_core; 172 unsigned int clkout_cmu_core_div_stat; 173 unsigned char res23[0x5f8]; 174 175 unsigned int dcgidx_map0; /* base + 0x5000 */ 176 unsigned int dcgidx_map1; 177 unsigned int dcgidx_map2; 178 unsigned char res24[0x14]; 179 unsigned int dcgperf_map0; 180 unsigned int dcgperf_map1; 181 unsigned char res25[0x18]; 182 unsigned int dvcidx_map; 183 unsigned char res26[0x1c]; 184 unsigned int freq_cpu; 185 unsigned int freq_dpm; 186 unsigned char res27[0x18]; 187 unsigned int dvsemclk_en; 188 unsigned int maxperf; 189 unsigned char res28[0x3478]; 190 191 unsigned int div_acp; /* base + 0x8500 */ 192 unsigned char res29[0xfc]; 193 unsigned int div_stat_acp; 194 unsigned char res30[0x1fc]; 195 unsigned int gate_ip_acp; 196 unsigned char res31a[0xfc]; 197 unsigned int div_syslft; 198 unsigned char res31b[0xc]; 199 unsigned int div_stat_syslft; 200 unsigned char res31c[0xc]; 201 unsigned int gate_bus_syslft; 202 unsigned char res31d[0xdc]; 203 unsigned int clkout_cmu_acp; 204 unsigned int clkout_cmu_acp_div_stat; 205 unsigned char res32[0x38f8]; 206 207 unsigned int div_isp0; /* base + 0xc300 */ 208 unsigned int div_isp1; 209 unsigned int div_isp2; 210 unsigned char res33[0xf4]; 211 212 unsigned int div_stat_isp0; /* base + 0xc400 */ 213 unsigned int div_stat_isp1; 214 unsigned int div_stat_isp2; 215 unsigned char res34[0x3f4]; 216 217 unsigned int gate_ip_isp0; /* base + 0xc800 */ 218 unsigned int gate_ip_isp1; 219 unsigned char res35[0xf8]; 220 unsigned int gate_sclk_isp; 221 unsigned char res36[0xc]; 222 unsigned int mcuisp_pwr_ctrl; 223 unsigned char res37[0xec]; 224 unsigned int clkout_cmu_isp; 225 unsigned int clkout_cmu_isp_div_stat; 226 unsigned char res38[0x3618]; 227 228 unsigned int cpll_lock; /* base + 0x10020 */ 229 unsigned char res39[0xc]; 230 unsigned int epll_lock; 231 unsigned char res40[0xc]; 232 unsigned int vpll_lock; 233 unsigned char res41a[0xc]; 234 unsigned int gpll_lock; 235 unsigned char res41b[0xcc]; 236 unsigned int cpll_con0; 237 unsigned int cpll_con1; 238 unsigned char res42[0x8]; 239 unsigned int epll_con0; 240 unsigned int epll_con1; 241 unsigned int epll_con2; 242 unsigned char res43[0x4]; 243 unsigned int vpll_con0; 244 unsigned int vpll_con1; 245 unsigned int vpll_con2; 246 unsigned char res44a[0x4]; 247 unsigned int gpll_con0; 248 unsigned int gpll_con1; 249 unsigned char res44b[0xb8]; 250 unsigned int src_top0; 251 unsigned int src_top1; 252 unsigned int src_top2; 253 unsigned int src_top3; 254 unsigned int src_gscl; 255 unsigned int src_disp0_0; 256 unsigned int src_disp0_1; 257 unsigned int src_disp1_0; 258 unsigned int src_disp1_1; 259 unsigned char res46[0xc]; 260 unsigned int src_mau; 261 unsigned int src_fsys; 262 unsigned char res47[0x8]; 263 unsigned int src_peric0; 264 unsigned int src_peric1; 265 unsigned char res48[0x18]; 266 unsigned int sclk_src_isp; 267 unsigned char res49[0x9c]; 268 unsigned int src_mask_top; 269 unsigned char res50[0xc]; 270 unsigned int src_mask_gscl; 271 unsigned int src_mask_disp0_0; 272 unsigned int src_mask_disp0_1; 273 unsigned int src_mask_disp1_0; 274 unsigned int src_mask_disp1_1; 275 unsigned int src_mask_maudio; 276 unsigned char res52[0x8]; 277 unsigned int src_mask_fsys; 278 unsigned char res53[0xc]; 279 unsigned int src_mask_peric0; 280 unsigned int src_mask_peric1; 281 unsigned char res54[0x18]; 282 unsigned int src_mask_isp; 283 unsigned char res55[0x9c]; 284 unsigned int mux_stat_top0; 285 unsigned int mux_stat_top1; 286 unsigned int mux_stat_top2; 287 unsigned int mux_stat_top3; 288 unsigned char res56[0xf0]; 289 unsigned int div_top0; 290 unsigned int div_top1; 291 unsigned char res57[0x8]; 292 unsigned int div_gscl; 293 unsigned int div_disp0_0; 294 unsigned int div_disp0_1; 295 unsigned int div_disp1_0; 296 unsigned int div_disp1_1; 297 unsigned char res59[0x8]; 298 unsigned int div_gen; 299 unsigned char res60[0x4]; 300 unsigned int div_mau; 301 unsigned int div_fsys0; 302 unsigned int div_fsys1; 303 unsigned int div_fsys2; 304 unsigned int div_fsys3; 305 unsigned int div_peric0; 306 unsigned int div_peric1; 307 unsigned int div_peric2; 308 unsigned int div_peric3; 309 unsigned int div_peric4; 310 unsigned int div_peric5; 311 unsigned char res61[0x10]; 312 unsigned int sclk_div_isp; 313 unsigned char res62[0xc]; 314 unsigned int div2_ratio0; 315 unsigned int div2_ratio1; 316 unsigned char res63[0x8]; 317 unsigned int div4_ratio; 318 unsigned char res64[0x6c]; 319 unsigned int div_stat_top0; 320 unsigned int div_stat_top1; 321 unsigned char res65[0x8]; 322 unsigned int div_stat_gscl; 323 unsigned int div_stat_disp0_0; 324 unsigned int div_stat_disp0_1; 325 unsigned int div_stat_disp1_0; 326 unsigned int div_stat_disp1_1; 327 unsigned char res67[0x8]; 328 unsigned int div_stat_gen; 329 unsigned char res68[0x4]; 330 unsigned int div_stat_maudio; 331 unsigned int div_stat_fsys0; 332 unsigned int div_stat_fsys1; 333 unsigned int div_stat_fsys2; 334 unsigned int div_stat_fsys3; 335 unsigned int div_stat_peric0; 336 unsigned int div_stat_peric1; 337 unsigned int div_stat_peric2; 338 unsigned int div_stat_peric3; 339 unsigned int div_stat_peric4; 340 unsigned int div_stat_peric5; 341 unsigned char res69[0x10]; 342 unsigned int sclk_div_stat_isp; 343 unsigned char res70[0xc]; 344 unsigned int div2_stat0; 345 unsigned int div2_stat1; 346 unsigned char res71[0x8]; 347 unsigned int div4_stat; 348 unsigned char res72[0x180]; 349 unsigned int gate_top_sclk_disp0; 350 unsigned int gate_top_sclk_disp1; 351 unsigned int gate_top_sclk_gen; 352 unsigned char res74[0xc]; 353 unsigned int gate_top_sclk_mau; 354 unsigned int gate_top_sclk_fsys; 355 unsigned char res75[0xc]; 356 unsigned int gate_top_sclk_peric; 357 unsigned char res76[0x1c]; 358 unsigned int gate_top_sclk_isp; 359 unsigned char res77[0xac]; 360 unsigned int gate_ip_gscl; 361 unsigned int gate_ip_disp0; 362 unsigned int gate_ip_disp1; 363 unsigned int gate_ip_mfc; 364 unsigned int gate_ip_g3d; 365 unsigned int gate_ip_gen; 366 unsigned char res79[0xc]; 367 unsigned int gate_ip_fsys; 368 unsigned char res80[0x4]; 369 unsigned int gate_ip_gps; 370 unsigned int gate_ip_peric; 371 unsigned char res81[0xc]; 372 unsigned int gate_ip_peris; 373 unsigned char res82[0x1c]; 374 unsigned int gate_block; 375 unsigned char res83[0x7c]; 376 unsigned int clkout_cmu_top; 377 unsigned int clkout_cmu_top_div_stat; 378 unsigned char res84[0x37f8]; 379 380 unsigned int src_lex; /* base + 0x14200 */ 381 unsigned char res85[0x1fc]; 382 unsigned int mux_stat_lex; 383 unsigned char res85b[0xfc]; 384 unsigned int div_lex; 385 unsigned char res86[0xfc]; 386 unsigned int div_stat_lex; 387 unsigned char res87[0x1fc]; 388 unsigned int gate_ip_lex; 389 unsigned char res88[0x1fc]; 390 unsigned int clkout_cmu_lex; 391 unsigned int clkout_cmu_lex_div_stat; 392 unsigned char res89[0x3af8]; 393 394 unsigned int div_r0x; /* base + 0x18500 */ 395 unsigned char res90[0xfc]; 396 unsigned int div_stat_r0x; 397 unsigned char res91[0x1fc]; 398 unsigned int gate_ip_r0x; 399 unsigned char res92[0x1fc]; 400 unsigned int clkout_cmu_r0x; 401 unsigned int clkout_cmu_r0x_div_stat; 402 unsigned char res94[0x3af8]; 403 404 unsigned int div_r1x; /* base + 0x1c500 */ 405 unsigned char res95[0xfc]; 406 unsigned int div_stat_r1x; 407 unsigned char res96[0x1fc]; 408 unsigned int gate_ip_r1x; 409 unsigned char res97[0x1fc]; 410 unsigned int clkout_cmu_r1x; 411 unsigned int clkout_cmu_r1x_div_stat; 412 unsigned char res98[0x3608]; 413 414 unsigned int bpll_lock; /* base + 0x20010 */ 415 unsigned char res99[0xfc]; 416 unsigned int bpll_con0; 417 unsigned int bpll_con1; 418 unsigned char res100[0xe8]; 419 unsigned int src_cdrex; 420 unsigned char res101[0x1fc]; 421 unsigned int mux_stat_cdrex; 422 unsigned char res102[0xfc]; 423 unsigned int div_cdrex; 424 unsigned int div_cdrex2; 425 unsigned char res103[0xf8]; 426 unsigned int div_stat_cdrex; 427 unsigned char res104[0x2fc]; 428 unsigned int gate_ip_cdrex; 429 unsigned char res105[0xc]; 430 unsigned int c2c_monitor; 431 unsigned int dmc_pwr_ctrl; 432 unsigned char res106[0x4]; 433 unsigned int drex2_pause; 434 unsigned char res107[0xe0]; 435 unsigned int clkout_cmu_cdrex; 436 unsigned int clkout_cmu_cdrex_div_stat; 437 unsigned char res108[0x8]; 438 unsigned int lpddr3phy_ctrl; 439 unsigned char res109a[0xc]; 440 unsigned int lpddr3phy_con3; 441 unsigned int pll_div2_sel; 442 unsigned char res109b[0xf5e4]; 443 }; 444 check_member(exynos5_clock, pll_div2_sel, 0x20a24); 445 446 static struct exynos5_clock * const exynos_clock = (void *)EXYNOS5_CLOCK_BASE; 447 448 struct exynos5_mct { 449 uint32_t mct_cfg; 450 uint8_t reserved0[0xfc]; 451 uint32_t g_cnt_l; 452 uint32_t g_cnt_u; 453 uint8_t reserved1[0x8]; 454 uint32_t g_cnt_wstat; 455 uint8_t reserved2[0xec]; 456 uint32_t g_comp0_l; 457 uint32_t g_comp0_u; 458 uint32_t g_comp0_addr_incr; 459 uint8_t reserved3[0x4]; 460 uint32_t g_comp1_l; 461 uint32_t g_comp1_u; 462 uint32_t g_comp1_addr_incr; 463 uint8_t reserved4[0x4]; 464 uint32_t g_comp2_l; 465 uint32_t g_comp2_u; 466 uint32_t g_comp2_addr_incr; 467 uint8_t reserved5[0x4]; 468 uint32_t g_comp3_l; 469 uint32_t g_comp3_u; 470 uint32_t g_comp3_addr_incr; 471 uint8_t reserved6[0x4]; 472 uint32_t g_tcon; 473 uint32_t g_int_cstat; 474 uint32_t g_int_enb; 475 uint32_t g_wstat; 476 uint8_t reserved7[0xb0]; 477 uint32_t l0_tcntb; 478 uint32_t l0_tcnto; 479 uint32_t l0_icntb; 480 uint32_t l0_icnto; 481 uint32_t l0_frcntb; 482 uint32_t l0_frcnto; 483 uint8_t reserved8[0x8]; 484 uint32_t l0_tcon; 485 uint8_t reserved9[0xc]; 486 uint32_t l0_int_cstat; 487 uint32_t l0_int_enb; 488 uint8_t reserved10[0x8]; 489 uint32_t l0_wstat; 490 uint8_t reserved11[0xbc]; 491 uint32_t l1_tcntb; 492 uint32_t l1_tcnto; 493 uint32_t l1_icntb; 494 uint32_t l1_icnto; 495 uint32_t l1_frcntb; 496 uint32_t l1_frcnto; 497 uint8_t reserved12[0x8]; 498 uint32_t l1_tcon; 499 uint8_t reserved13[0xc]; 500 uint32_t l1_int_cstat; 501 uint32_t l1_int_enb; 502 uint8_t reserved14[0x8]; 503 uint32_t l1_wstat; 504 }; 505 check_member(exynos5_mct, l1_wstat, 0x440); 506 507 static struct exynos5_mct * const exynos_mct = 508 (void *)EXYNOS5_MULTI_CORE_TIMER_BASE; 509 510 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ 511 #define EPLL_SRC_CLOCK 24000000 /*24 MHz Crystal Input */ 512 #define TIMEOUT_EPLL_LOCK 1000 513 514 #define AUDIO_0_RATIO_MASK 0x0f 515 #define AUDIO_1_RATIO_MASK 0x0f 516 517 #define CLK_SRC_PERIC1 0x254 518 #define AUDIO1_SEL_MASK 0xf 519 #define CLK_SRC_AUDIOCDCLK1 0x0 520 #define CLK_SRC_XXTI 0x1 521 #define CLK_SRC_SCLK_EPLL 0x7 522 523 /* CON0 bit-fields */ 524 #define EPLL_CON0_MDIV_MASK 0x1ff 525 #define EPLL_CON0_PDIV_MASK 0x3f 526 #define EPLL_CON0_SDIV_MASK 0x7 527 #define EPLL_CON0_LOCKED_SHIFT 29 528 #define EPLL_CON0_MDIV_SHIFT 16 529 #define EPLL_CON0_PDIV_SHIFT 8 530 #define EPLL_CON0_SDIV_SHIFT 0 531 #define EPLL_CON0_LOCK_DET_EN_SHIFT 28 532 #define EPLL_CON0_LOCK_DET_EN_MASK 1 533 534 /* structure for epll configuration used in audio clock configuration */ 535 struct st_epll_con_val { 536 unsigned int freq_out; /* frequency out */ 537 unsigned int en_lock_det; /* enable lock detect */ 538 unsigned int m_div; /* m divider value */ 539 unsigned int p_div; /* p divider value */ 540 unsigned int s_div; /* s divider value */ 541 unsigned int k_dsm; /* k value of delta signal modulator */ 542 }; 543 544 /** 545 * Low-level function to set the clock pre-ratio for a peripheral 546 * 547 * @param periph_id Peripheral ID of peripheral to change 548 * @param divisor New divisor for this peripheral's clock 549 */ 550 void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor); 551 552 /** 553 * Low-level function to set the clock ratio for a peripheral 554 * 555 * @param periph_id Peripheral ID of peripheral to change 556 * @param divisor New divisor for this peripheral's clock 557 */ 558 void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor); 559 560 /** 561 * Low-level function that selects the best clock scalars for a given rate and 562 * sets up the given peripheral's clock accordingly. 563 * 564 * @param periph_id Peripheral ID of peripheral to change 565 * @param rate Desired clock rate in Hz 566 * 567 * @return zero on success, negative on error 568 */ 569 int clock_set_rate(enum periph_id periph_id, unsigned int rate); 570 571 /* Clock gate unused IP */ 572 void clock_gate(void); 573 574 /* These are the ratio's for configuring ARM clock */ 575 struct arm_clk_ratios { 576 unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */ 577 578 unsigned int apll_mdiv; 579 unsigned int apll_pdiv; 580 unsigned int apll_sdiv; 581 582 unsigned int arm2_ratio; 583 unsigned int apll_ratio; 584 unsigned int pclk_dbg_ratio; 585 unsigned int atb_ratio; 586 unsigned int periph_ratio; 587 unsigned int acp_ratio; 588 unsigned int cpud_ratio; 589 unsigned int arm_ratio; 590 }; 591 592 /** 593 * Get the clock ratios for CPU configuration 594 * 595 * @return pointer to the clock ratios that we should use 596 */ 597 struct arm_clk_ratios *get_arm_clk_ratios(void); 598 599 /* 600 * Initialize clock for the device 601 */ 602 struct mem_timings; 603 void system_clock_init(struct mem_timings *mem, 604 struct arm_clk_ratios *arm_clk_ratio); 605 606 #endif 607