1 #ifndef __BDK_CSRS_USBDRD_H__
2 #define __BDK_CSRS_USBDRD_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium USBDRD.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration uctl_dma_read_cmd_e
57 *
58 * USB UCTL DMA Read Command Enumeration
59 * Enumerate NCB inbound command selections for DMA read operations.
60 */
61 #define BDK_UCTL_DMA_READ_CMD_E_LDI (0)
62 #define BDK_UCTL_DMA_READ_CMD_E_LDT (1)
63 #define BDK_UCTL_DMA_READ_CMD_E_LDY (2)
64
65 /**
66 * Enumeration uctl_dma_write_cmd_e
67 *
68 * USB UCTL DMA Write Command Enumeration
69 * Enumerate NCB inbound command selections for DMA write operations.
70 */
71 #define BDK_UCTL_DMA_WRITE_CMD_E_RSTP (1)
72 #define BDK_UCTL_DMA_WRITE_CMD_E_STP (0)
73
74 /**
75 * Enumeration uctl_endian_mode_e
76 *
77 * USB UCTL Endian-Mode Enumeration
78 * Enumerate endian mode selections.
79 */
80 #define BDK_UCTL_ENDIAN_MODE_E_BIG (1)
81 #define BDK_UCTL_ENDIAN_MODE_E_LITTLE (0)
82 #define BDK_UCTL_ENDIAN_MODE_E_RSVD2 (2)
83 #define BDK_UCTL_ENDIAN_MODE_E_RSVD3 (3)
84
85 /**
86 * Enumeration uctl_xm_bad_dma_type_e
87 *
88 * USB UCTL XM Bad DMA Type Enumeration
89 * Enumerate type of DMA error seen.
90 */
91 #define BDK_UCTL_XM_BAD_DMA_TYPE_E_ADDR_OOB (1)
92 #define BDK_UCTL_XM_BAD_DMA_TYPE_E_LEN_GT_16 (2)
93 #define BDK_UCTL_XM_BAD_DMA_TYPE_E_MULTIBEAT_BYTE (3)
94 #define BDK_UCTL_XM_BAD_DMA_TYPE_E_MULTIBEAT_HALFWORD (4)
95 #define BDK_UCTL_XM_BAD_DMA_TYPE_E_MULTIBEAT_QWORD (6)
96 #define BDK_UCTL_XM_BAD_DMA_TYPE_E_MULTIBEAT_WORD (5)
97 #define BDK_UCTL_XM_BAD_DMA_TYPE_E_NONE (0)
98
99 /**
100 * Enumeration usbdrd_bar_e
101 *
102 * USB Base Address Register Enumeration
103 * Enumerates the base address registers.
104 */
105 #define BDK_USBDRD_BAR_E_USBDRDX_PF_BAR0(a) (0x868000000000ll + 0x1000000000ll * (a))
106 #define BDK_USBDRD_BAR_E_USBDRDX_PF_BAR0_SIZE 0x200000ull
107 #define BDK_USBDRD_BAR_E_USBDRDX_PF_BAR4(a) (0x868000200000ll + 0x1000000000ll * (a))
108 #define BDK_USBDRD_BAR_E_USBDRDX_PF_BAR4_SIZE 0x100000ull
109
110 /**
111 * Enumeration usbdrd_int_vec_e
112 *
113 * USB MSI-X Vector Enumeration
114 * Enumerates the MSI-X interrupt vectors.
115 */
116 #define BDK_USBDRD_INT_VEC_E_UAHC_IMAN_IP (0)
117 #define BDK_USBDRD_INT_VEC_E_UAHC_USBSTS_HSE (2)
118 #define BDK_USBDRD_INT_VEC_E_UAHC_USBSTS_HSE_CLEAR (3)
119 #define BDK_USBDRD_INT_VEC_E_UCTL_INTSTAT (1)
120 #define BDK_USBDRD_INT_VEC_E_UCTL_RAS (4)
121
122 /**
123 * Enumeration usbdrd_uahc_dgcmd_cmdtype_e
124 *
125 * USB UAHC Device Generic Command Enumeration
126 * Commands for USBDRD()_UAHC_DGCMD[CMDTYPE].
127 * Any command encodings that are not present are considered Reserved.
128 *
129 * Internal:
130 * Synopsys DWC_usb3 Databook v3.10a, section 6.3.1.6.1 for details.
131 */
132 #define BDK_USBDRD_UAHC_DGCMD_CMDTYPE_E_ALL_FIFO_FLUSH (0xa)
133 #define BDK_USBDRD_UAHC_DGCMD_CMDTYPE_E_RUN_SOC_BUS_LOOPBACK_TEST (0x10)
134 #define BDK_USBDRD_UAHC_DGCMD_CMDTYPE_E_SELECTED_FIFO_FLUSH (9)
135 #define BDK_USBDRD_UAHC_DGCMD_CMDTYPE_E_SET_ENDPOINT_NRDY (0xc)
136 #define BDK_USBDRD_UAHC_DGCMD_CMDTYPE_E_SET_PERIODIC_PARAMETERS (2)
137 #define BDK_USBDRD_UAHC_DGCMD_CMDTYPE_E_SET_SCRATCHPAD_BUFFER_ARRAY_ADDR_H (5)
138 #define BDK_USBDRD_UAHC_DGCMD_CMDTYPE_E_SET_SCRATCHPAD_BUFFER_ARRAY_ADDR_L (4)
139 #define BDK_USBDRD_UAHC_DGCMD_CMDTYPE_E_TRANSMIT_DEVICE_NOTIFICATION (7)
140
141 /**
142 * Register (NCB) usbdrd#_bp_test0
143 *
144 * INTERNAL: USB Backpressure Test Register
145 */
146 union bdk_usbdrdx_bp_test0
147 {
148 uint64_t u;
149 struct bdk_usbdrdx_bp_test0_s
150 {
151 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
152 uint64_t enable : 4; /**< [ 63: 60](R/W) Enable test mode. For diagnostic use only.
153 Internal:
154 Once a bit is set, random backpressure is generated
155 at the corresponding point to allow for more frequent backpressure.
156 \<63\> = Limit the NCBI posted FIFO, backpressure doing posted requests to NCB GNT.
157 \<62\> = Limit the NCBI nonposted FIFO, backpressure doing nonposted requests to NCB GNT.
158 \<61\> = Limit the NCBI completion FIFO, backpressure doing completion requests to NCB GNT.
159 \<60\> = Limit the NCBI CSR completion FIFO, backpressure doing requests for CSR responses
160 to NCB GNT. */
161 uint64_t reserved_24_59 : 36;
162 uint64_t bp_cfg : 8; /**< [ 23: 16](R/W) Backpressure weight. For diagnostic use only.
163 Internal:
164 There are 2 backpressure configuration bits per enable, with the two bits
165 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
166 0x3=25% of the time.
167 \<23:22\> = Config 3.
168 \<21:20\> = Config 2.
169 \<19:18\> = Config 1.
170 \<17:16\> = Config 0. */
171 uint64_t reserved_12_15 : 4;
172 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
173 #else /* Word 0 - Little Endian */
174 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
175 uint64_t reserved_12_15 : 4;
176 uint64_t bp_cfg : 8; /**< [ 23: 16](R/W) Backpressure weight. For diagnostic use only.
177 Internal:
178 There are 2 backpressure configuration bits per enable, with the two bits
179 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
180 0x3=25% of the time.
181 \<23:22\> = Config 3.
182 \<21:20\> = Config 2.
183 \<19:18\> = Config 1.
184 \<17:16\> = Config 0. */
185 uint64_t reserved_24_59 : 36;
186 uint64_t enable : 4; /**< [ 63: 60](R/W) Enable test mode. For diagnostic use only.
187 Internal:
188 Once a bit is set, random backpressure is generated
189 at the corresponding point to allow for more frequent backpressure.
190 \<63\> = Limit the NCBI posted FIFO, backpressure doing posted requests to NCB GNT.
191 \<62\> = Limit the NCBI nonposted FIFO, backpressure doing nonposted requests to NCB GNT.
192 \<61\> = Limit the NCBI completion FIFO, backpressure doing completion requests to NCB GNT.
193 \<60\> = Limit the NCBI CSR completion FIFO, backpressure doing requests for CSR responses
194 to NCB GNT. */
195 #endif /* Word 0 - End */
196 } s;
197 /* struct bdk_usbdrdx_bp_test0_s cn; */
198 };
199 typedef union bdk_usbdrdx_bp_test0 bdk_usbdrdx_bp_test0_t;
200
201 static inline uint64_t BDK_USBDRDX_BP_TEST0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_BP_TEST0(unsigned long a)202 static inline uint64_t BDK_USBDRDX_BP_TEST0(unsigned long a)
203 {
204 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
205 return 0x868000100070ll + 0x1000000000ll * ((a) & 0x1);
206 __bdk_csr_fatal("USBDRDX_BP_TEST0", 1, a, 0, 0, 0);
207 }
208
209 #define typedef_BDK_USBDRDX_BP_TEST0(a) bdk_usbdrdx_bp_test0_t
210 #define bustype_BDK_USBDRDX_BP_TEST0(a) BDK_CSR_TYPE_NCB
211 #define basename_BDK_USBDRDX_BP_TEST0(a) "USBDRDX_BP_TEST0"
212 #define device_bar_BDK_USBDRDX_BP_TEST0(a) 0x0 /* PF_BAR0 */
213 #define busnum_BDK_USBDRDX_BP_TEST0(a) (a)
214 #define arguments_BDK_USBDRDX_BP_TEST0(a) (a),-1,-1,-1
215
216 /**
217 * Register (NCB) usbdrd#_const
218 *
219 * USB Constants Register
220 */
221 union bdk_usbdrdx_const
222 {
223 uint64_t u;
224 struct bdk_usbdrdx_const_s
225 {
226 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
227 uint64_t reserved_0_63 : 64;
228 #else /* Word 0 - Little Endian */
229 uint64_t reserved_0_63 : 64;
230 #endif /* Word 0 - End */
231 } s;
232 /* struct bdk_usbdrdx_const_s cn; */
233 };
234 typedef union bdk_usbdrdx_const bdk_usbdrdx_const_t;
235
236 static inline uint64_t BDK_USBDRDX_CONST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_CONST(unsigned long a)237 static inline uint64_t BDK_USBDRDX_CONST(unsigned long a)
238 {
239 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
240 return 0x868000100078ll + 0x1000000000ll * ((a) & 0x1);
241 __bdk_csr_fatal("USBDRDX_CONST", 1, a, 0, 0, 0);
242 }
243
244 #define typedef_BDK_USBDRDX_CONST(a) bdk_usbdrdx_const_t
245 #define bustype_BDK_USBDRDX_CONST(a) BDK_CSR_TYPE_NCB
246 #define basename_BDK_USBDRDX_CONST(a) "USBDRDX_CONST"
247 #define device_bar_BDK_USBDRDX_CONST(a) 0x0 /* PF_BAR0 */
248 #define busnum_BDK_USBDRDX_CONST(a) (a)
249 #define arguments_BDK_USBDRDX_CONST(a) (a),-1,-1,-1
250
251 /**
252 * Register (NCB) usbdrd#_msix_pba#
253 *
254 * USB MSI-X Pending Bit Array Registers
255 * This register is the MSI-X PBA table, the bit number is indexed by the USBDRD_INT_VEC_E
256 * enumeration.
257 */
258 union bdk_usbdrdx_msix_pbax
259 {
260 uint64_t u;
261 struct bdk_usbdrdx_msix_pbax_s
262 {
263 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
264 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated USBDRD()_MSIX_VEC()_CTL, enumerated by
265 USBDRD_INT_VEC_E.
266 Bits that have no associated USBDRD_INT_VEC_E are zero. */
267 #else /* Word 0 - Little Endian */
268 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated USBDRD()_MSIX_VEC()_CTL, enumerated by
269 USBDRD_INT_VEC_E.
270 Bits that have no associated USBDRD_INT_VEC_E are zero. */
271 #endif /* Word 0 - End */
272 } s;
273 /* struct bdk_usbdrdx_msix_pbax_s cn; */
274 };
275 typedef union bdk_usbdrdx_msix_pbax bdk_usbdrdx_msix_pbax_t;
276
277 static inline uint64_t BDK_USBDRDX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_MSIX_PBAX(unsigned long a,unsigned long b)278 static inline uint64_t BDK_USBDRDX_MSIX_PBAX(unsigned long a, unsigned long b)
279 {
280 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
281 return 0x8680002f0000ll + 0x1000000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
282 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
283 return 0x8680002f0000ll + 0x1000000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
284 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
285 return 0x8680002f0000ll + 0x1000000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
286 __bdk_csr_fatal("USBDRDX_MSIX_PBAX", 2, a, b, 0, 0);
287 }
288
289 #define typedef_BDK_USBDRDX_MSIX_PBAX(a,b) bdk_usbdrdx_msix_pbax_t
290 #define bustype_BDK_USBDRDX_MSIX_PBAX(a,b) BDK_CSR_TYPE_NCB
291 #define basename_BDK_USBDRDX_MSIX_PBAX(a,b) "USBDRDX_MSIX_PBAX"
292 #define device_bar_BDK_USBDRDX_MSIX_PBAX(a,b) 0x4 /* PF_BAR4 */
293 #define busnum_BDK_USBDRDX_MSIX_PBAX(a,b) (a)
294 #define arguments_BDK_USBDRDX_MSIX_PBAX(a,b) (a),(b),-1,-1
295
296 /**
297 * Register (NCB) usbdrd#_msix_vec#_addr
298 *
299 * USB MSI-X Vector Table Address Registers
300 * This register is the MSI-X vector table, indexed by the USBDRD_INT_VEC_E enumeration.
301 */
302 union bdk_usbdrdx_msix_vecx_addr
303 {
304 uint64_t u;
305 struct bdk_usbdrdx_msix_vecx_addr_s
306 {
307 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
308 uint64_t reserved_53_63 : 11;
309 uint64_t addr : 51; /**< [ 52: 2](R/W) Address to use for MSI-X delivery of this vector. */
310 uint64_t reserved_1 : 1;
311 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
312 0 = This vector may be read or written by either secure or nonsecure states.
313 1 = This vector's USBDRD()_MSIX_VEC()_ADDR, USBDRD()_MSIX_VEC()_CTL, and
314 corresponding
315 bit of USBDRD()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
316 by the nonsecure world.
317
318 If PCCPF_USBDRD()_VSEC_SCTL[MSIX_SEC] (for documentation, see
319 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
320 set, all vectors are secure and function as if [SECVEC] was set. */
321 #else /* Word 0 - Little Endian */
322 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
323 0 = This vector may be read or written by either secure or nonsecure states.
324 1 = This vector's USBDRD()_MSIX_VEC()_ADDR, USBDRD()_MSIX_VEC()_CTL, and
325 corresponding
326 bit of USBDRD()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
327 by the nonsecure world.
328
329 If PCCPF_USBDRD()_VSEC_SCTL[MSIX_SEC] (for documentation, see
330 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
331 set, all vectors are secure and function as if [SECVEC] was set. */
332 uint64_t reserved_1 : 1;
333 uint64_t addr : 51; /**< [ 52: 2](R/W) Address to use for MSI-X delivery of this vector. */
334 uint64_t reserved_53_63 : 11;
335 #endif /* Word 0 - End */
336 } s;
337 struct bdk_usbdrdx_msix_vecx_addr_cn8
338 {
339 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
340 uint64_t reserved_49_63 : 15;
341 uint64_t addr : 47; /**< [ 48: 2](R/W) Address to use for MSI-X delivery of this vector. */
342 uint64_t reserved_1 : 1;
343 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
344 0 = This vector may be read or written by either secure or nonsecure states.
345 1 = This vector's USBDRD()_MSIX_VEC()_ADDR, USBDRD()_MSIX_VEC()_CTL, and
346 corresponding
347 bit of USBDRD()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
348 by the nonsecure world.
349
350 If PCCPF_USBDRD()_VSEC_SCTL[MSIX_SEC] (for documentation, see
351 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
352 set, all vectors are secure and function as if [SECVEC] was set. */
353 #else /* Word 0 - Little Endian */
354 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
355 0 = This vector may be read or written by either secure or nonsecure states.
356 1 = This vector's USBDRD()_MSIX_VEC()_ADDR, USBDRD()_MSIX_VEC()_CTL, and
357 corresponding
358 bit of USBDRD()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
359 by the nonsecure world.
360
361 If PCCPF_USBDRD()_VSEC_SCTL[MSIX_SEC] (for documentation, see
362 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
363 set, all vectors are secure and function as if [SECVEC] was set. */
364 uint64_t reserved_1 : 1;
365 uint64_t addr : 47; /**< [ 48: 2](R/W) Address to use for MSI-X delivery of this vector. */
366 uint64_t reserved_49_63 : 15;
367 #endif /* Word 0 - End */
368 } cn8;
369 /* struct bdk_usbdrdx_msix_vecx_addr_s cn9; */
370 };
371 typedef union bdk_usbdrdx_msix_vecx_addr bdk_usbdrdx_msix_vecx_addr_t;
372
373 static inline uint64_t BDK_USBDRDX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)374 static inline uint64_t BDK_USBDRDX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
375 {
376 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
377 return 0x868000200000ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
378 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=3)))
379 return 0x868000200000ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
380 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=4)))
381 return 0x868000200000ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x7);
382 __bdk_csr_fatal("USBDRDX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
383 }
384
385 #define typedef_BDK_USBDRDX_MSIX_VECX_ADDR(a,b) bdk_usbdrdx_msix_vecx_addr_t
386 #define bustype_BDK_USBDRDX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_NCB
387 #define basename_BDK_USBDRDX_MSIX_VECX_ADDR(a,b) "USBDRDX_MSIX_VECX_ADDR"
388 #define device_bar_BDK_USBDRDX_MSIX_VECX_ADDR(a,b) 0x4 /* PF_BAR4 */
389 #define busnum_BDK_USBDRDX_MSIX_VECX_ADDR(a,b) (a)
390 #define arguments_BDK_USBDRDX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
391
392 /**
393 * Register (NCB) usbdrd#_msix_vec#_ctl
394 *
395 * USB MSI-X Vector Table Control and Data Registers
396 * This register is the MSI-X vector table, indexed by the USBDRD_INT_VEC_E enumeration.
397 */
398 union bdk_usbdrdx_msix_vecx_ctl
399 {
400 uint64_t u;
401 struct bdk_usbdrdx_msix_vecx_ctl_s
402 {
403 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
404 uint64_t reserved_33_63 : 31;
405 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
406 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
407 #else /* Word 0 - Little Endian */
408 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
409 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
410 uint64_t reserved_33_63 : 31;
411 #endif /* Word 0 - End */
412 } s;
413 struct bdk_usbdrdx_msix_vecx_ctl_cn8
414 {
415 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
416 uint64_t reserved_33_63 : 31;
417 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
418 uint64_t reserved_20_31 : 12;
419 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
420 #else /* Word 0 - Little Endian */
421 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
422 uint64_t reserved_20_31 : 12;
423 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
424 uint64_t reserved_33_63 : 31;
425 #endif /* Word 0 - End */
426 } cn8;
427 /* struct bdk_usbdrdx_msix_vecx_ctl_s cn9; */
428 };
429 typedef union bdk_usbdrdx_msix_vecx_ctl bdk_usbdrdx_msix_vecx_ctl_t;
430
431 static inline uint64_t BDK_USBDRDX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_MSIX_VECX_CTL(unsigned long a,unsigned long b)432 static inline uint64_t BDK_USBDRDX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
433 {
434 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
435 return 0x868000200008ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
436 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=3)))
437 return 0x868000200008ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x3);
438 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=4)))
439 return 0x868000200008ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x7);
440 __bdk_csr_fatal("USBDRDX_MSIX_VECX_CTL", 2, a, b, 0, 0);
441 }
442
443 #define typedef_BDK_USBDRDX_MSIX_VECX_CTL(a,b) bdk_usbdrdx_msix_vecx_ctl_t
444 #define bustype_BDK_USBDRDX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_NCB
445 #define basename_BDK_USBDRDX_MSIX_VECX_CTL(a,b) "USBDRDX_MSIX_VECX_CTL"
446 #define device_bar_BDK_USBDRDX_MSIX_VECX_CTL(a,b) 0x4 /* PF_BAR4 */
447 #define busnum_BDK_USBDRDX_MSIX_VECX_CTL(a,b) (a)
448 #define arguments_BDK_USBDRDX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
449
450 /**
451 * Register (NCB32b) usbdrd#_uahc_caplength
452 *
453 * USB XHCI Capability Length Register
454 * This register is used as an offset to add to register base to find the beginning of the
455 * operational register
456 * space. For information on this register, refer to the xHCI Specification, v1.1, section 5.3.1.
457 */
458 union bdk_usbdrdx_uahc_caplength
459 {
460 uint32_t u;
461 struct bdk_usbdrdx_uahc_caplength_s
462 {
463 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
464 uint32_t hciversion : 16; /**< [ 31: 16](RO) Host controller interface version number. */
465 uint32_t reserved_8_15 : 8;
466 uint32_t caplength : 8; /**< [ 7: 0](RO) Capability registers length. */
467 #else /* Word 0 - Little Endian */
468 uint32_t caplength : 8; /**< [ 7: 0](RO) Capability registers length. */
469 uint32_t reserved_8_15 : 8;
470 uint32_t hciversion : 16; /**< [ 31: 16](RO) Host controller interface version number. */
471 #endif /* Word 0 - End */
472 } s;
473 /* struct bdk_usbdrdx_uahc_caplength_s cn; */
474 };
475 typedef union bdk_usbdrdx_uahc_caplength bdk_usbdrdx_uahc_caplength_t;
476
477 static inline uint64_t BDK_USBDRDX_UAHC_CAPLENGTH(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_CAPLENGTH(unsigned long a)478 static inline uint64_t BDK_USBDRDX_UAHC_CAPLENGTH(unsigned long a)
479 {
480 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
481 return 0x868000000000ll + 0x1000000000ll * ((a) & 0x1);
482 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
483 return 0x868000000000ll + 0x1000000000ll * ((a) & 0x1);
484 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
485 return 0x868000000000ll + 0x1000000000ll * ((a) & 0x1);
486 __bdk_csr_fatal("USBDRDX_UAHC_CAPLENGTH", 1, a, 0, 0, 0);
487 }
488
489 #define typedef_BDK_USBDRDX_UAHC_CAPLENGTH(a) bdk_usbdrdx_uahc_caplength_t
490 #define bustype_BDK_USBDRDX_UAHC_CAPLENGTH(a) BDK_CSR_TYPE_NCB32b
491 #define basename_BDK_USBDRDX_UAHC_CAPLENGTH(a) "USBDRDX_UAHC_CAPLENGTH"
492 #define device_bar_BDK_USBDRDX_UAHC_CAPLENGTH(a) 0x0 /* PF_BAR0 */
493 #define busnum_BDK_USBDRDX_UAHC_CAPLENGTH(a) (a)
494 #define arguments_BDK_USBDRDX_UAHC_CAPLENGTH(a) (a),-1,-1,-1
495
496 /**
497 * Register (NCB32b) usbdrd#_uahc_config
498 *
499 * USB XHCI Configuration Register
500 * This register defines runtime xHC configuration parameters.
501 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.7.
502 *
503 * This register can be reset by NCB reset,
504 * or USBDRD()_UCTL_CTL[UAHC_RST],
505 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
506 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
507 */
508 union bdk_usbdrdx_uahc_config
509 {
510 uint32_t u;
511 struct bdk_usbdrdx_uahc_config_s
512 {
513 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
514 uint32_t reserved_8_31 : 24;
515 uint32_t maxslotsen : 8; /**< [ 7: 0](R/W) Maximum device slots enabled. */
516 #else /* Word 0 - Little Endian */
517 uint32_t maxslotsen : 8; /**< [ 7: 0](R/W) Maximum device slots enabled. */
518 uint32_t reserved_8_31 : 24;
519 #endif /* Word 0 - End */
520 } s;
521 /* struct bdk_usbdrdx_uahc_config_s cn; */
522 };
523 typedef union bdk_usbdrdx_uahc_config bdk_usbdrdx_uahc_config_t;
524
525 static inline uint64_t BDK_USBDRDX_UAHC_CONFIG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_CONFIG(unsigned long a)526 static inline uint64_t BDK_USBDRDX_UAHC_CONFIG(unsigned long a)
527 {
528 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
529 return 0x868000000058ll + 0x1000000000ll * ((a) & 0x1);
530 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
531 return 0x868000000058ll + 0x1000000000ll * ((a) & 0x1);
532 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
533 return 0x868000000058ll + 0x1000000000ll * ((a) & 0x1);
534 __bdk_csr_fatal("USBDRDX_UAHC_CONFIG", 1, a, 0, 0, 0);
535 }
536
537 #define typedef_BDK_USBDRDX_UAHC_CONFIG(a) bdk_usbdrdx_uahc_config_t
538 #define bustype_BDK_USBDRDX_UAHC_CONFIG(a) BDK_CSR_TYPE_NCB32b
539 #define basename_BDK_USBDRDX_UAHC_CONFIG(a) "USBDRDX_UAHC_CONFIG"
540 #define device_bar_BDK_USBDRDX_UAHC_CONFIG(a) 0x0 /* PF_BAR0 */
541 #define busnum_BDK_USBDRDX_UAHC_CONFIG(a) (a)
542 #define arguments_BDK_USBDRDX_UAHC_CONFIG(a) (a),-1,-1,-1
543
544 /**
545 * Register (NCB) usbdrd#_uahc_crcr
546 *
547 * USB XHCI Command Ring Control Register
548 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.5.
549 *
550 * This register can be reset by NCB reset,
551 * or USBDRD()_UCTL_CTL[UAHC_RST],
552 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
553 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
554 */
555 union bdk_usbdrdx_uahc_crcr
556 {
557 uint64_t u;
558 struct bdk_usbdrdx_uahc_crcr_s
559 {
560 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
561 uint64_t cmd_ring_ptr : 58; /**< [ 63: 6](WO) Command ring pointer. */
562 uint64_t reserved_4_5 : 2;
563 uint64_t crr : 1; /**< [ 3: 3](RO/H) Command ring running. */
564 uint64_t ca : 1; /**< [ 2: 2](WO) Command abort. */
565 uint64_t cs : 1; /**< [ 1: 1](WO) Command stop. */
566 uint64_t rcs : 1; /**< [ 0: 0](WO) Ring cycle state. */
567 #else /* Word 0 - Little Endian */
568 uint64_t rcs : 1; /**< [ 0: 0](WO) Ring cycle state. */
569 uint64_t cs : 1; /**< [ 1: 1](WO) Command stop. */
570 uint64_t ca : 1; /**< [ 2: 2](WO) Command abort. */
571 uint64_t crr : 1; /**< [ 3: 3](RO/H) Command ring running. */
572 uint64_t reserved_4_5 : 2;
573 uint64_t cmd_ring_ptr : 58; /**< [ 63: 6](WO) Command ring pointer. */
574 #endif /* Word 0 - End */
575 } s;
576 /* struct bdk_usbdrdx_uahc_crcr_s cn; */
577 };
578 typedef union bdk_usbdrdx_uahc_crcr bdk_usbdrdx_uahc_crcr_t;
579
580 static inline uint64_t BDK_USBDRDX_UAHC_CRCR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_CRCR(unsigned long a)581 static inline uint64_t BDK_USBDRDX_UAHC_CRCR(unsigned long a)
582 {
583 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
584 return 0x868000000038ll + 0x1000000000ll * ((a) & 0x1);
585 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
586 return 0x868000000038ll + 0x1000000000ll * ((a) & 0x1);
587 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
588 return 0x868000000038ll + 0x1000000000ll * ((a) & 0x1);
589 __bdk_csr_fatal("USBDRDX_UAHC_CRCR", 1, a, 0, 0, 0);
590 }
591
592 #define typedef_BDK_USBDRDX_UAHC_CRCR(a) bdk_usbdrdx_uahc_crcr_t
593 #define bustype_BDK_USBDRDX_UAHC_CRCR(a) BDK_CSR_TYPE_NCB
594 #define basename_BDK_USBDRDX_UAHC_CRCR(a) "USBDRDX_UAHC_CRCR"
595 #define device_bar_BDK_USBDRDX_UAHC_CRCR(a) 0x0 /* PF_BAR0 */
596 #define busnum_BDK_USBDRDX_UAHC_CRCR(a) (a)
597 #define arguments_BDK_USBDRDX_UAHC_CRCR(a) (a),-1,-1,-1
598
599 /**
600 * Register (NCB32b) usbdrd#_uahc_dalepena
601 *
602 * USB Device Active USB Endpoint Enable Register
603 * This register indicates whether a USB endpoint is active in a given configuration or
604 * interface.
605 *
606 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST] or
607 * USBDRD()_UAHC_GCTL[CORESOFTRESET] or
608 * USBDRD()_UAHC_USBCMD[HCRST] or USBDRD()_UAHC_USBCMD[LHCRST] or
609 * USBDRD()_UAHC_DCTL[CSFTRST].
610 *
611 * Internal:
612 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.7
613 */
614 union bdk_usbdrdx_uahc_dalepena
615 {
616 uint32_t u;
617 struct bdk_usbdrdx_uahc_dalepena_s
618 {
619 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
620 uint32_t usbactep : 32; /**< [ 31: 0](R/W) This field indicates if a USB endpoint is active in the current configuration
621 and interface. It applies to USB IN endpoints 0-15 and OUT endpoints 0-15,
622 with one bit for each of the 32 possible endpoints. Even numbers are for
623 USB OUT endpoints, and odd numbers are for USB IN endpoints, as
624 follows:
625
626 \<0\> = USB EP0-OUT.
627 \<1\> = USB EP0-IN.
628 \<2\> = USB EP1-OUT.
629 \<3\> = USB EP1-IN.
630
631 The entity programming this register must set bits 0 and 1 because they
632 enable control endpoints that map to physical endpoints (resources) after
633 USBReset.
634
635 Application software clears these bits for all endpoints (other than EP0-OUT
636 and EP0-IN) after detecting a USB reset. After receiving SetConfiguration
637 and SetInterface requests, the application must program endpoint registers
638 accordingly and set these bits.
639
640 Internal:
641 For more information, see 'Flexible Endpoint Mapping' on Synopsys DWC_usb3
642 Databook v2.80a, page 82. */
643 #else /* Word 0 - Little Endian */
644 uint32_t usbactep : 32; /**< [ 31: 0](R/W) This field indicates if a USB endpoint is active in the current configuration
645 and interface. It applies to USB IN endpoints 0-15 and OUT endpoints 0-15,
646 with one bit for each of the 32 possible endpoints. Even numbers are for
647 USB OUT endpoints, and odd numbers are for USB IN endpoints, as
648 follows:
649
650 \<0\> = USB EP0-OUT.
651 \<1\> = USB EP0-IN.
652 \<2\> = USB EP1-OUT.
653 \<3\> = USB EP1-IN.
654
655 The entity programming this register must set bits 0 and 1 because they
656 enable control endpoints that map to physical endpoints (resources) after
657 USBReset.
658
659 Application software clears these bits for all endpoints (other than EP0-OUT
660 and EP0-IN) after detecting a USB reset. After receiving SetConfiguration
661 and SetInterface requests, the application must program endpoint registers
662 accordingly and set these bits.
663
664 Internal:
665 For more information, see 'Flexible Endpoint Mapping' on Synopsys DWC_usb3
666 Databook v2.80a, page 82. */
667 #endif /* Word 0 - End */
668 } s;
669 /* struct bdk_usbdrdx_uahc_dalepena_s cn; */
670 };
671 typedef union bdk_usbdrdx_uahc_dalepena bdk_usbdrdx_uahc_dalepena_t;
672
673 static inline uint64_t BDK_USBDRDX_UAHC_DALEPENA(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DALEPENA(unsigned long a)674 static inline uint64_t BDK_USBDRDX_UAHC_DALEPENA(unsigned long a)
675 {
676 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
677 return 0x86800000c720ll + 0x1000000000ll * ((a) & 0x1);
678 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
679 return 0x86800000c720ll + 0x1000000000ll * ((a) & 0x1);
680 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
681 return 0x86800000c720ll + 0x1000000000ll * ((a) & 0x1);
682 __bdk_csr_fatal("USBDRDX_UAHC_DALEPENA", 1, a, 0, 0, 0);
683 }
684
685 #define typedef_BDK_USBDRDX_UAHC_DALEPENA(a) bdk_usbdrdx_uahc_dalepena_t
686 #define bustype_BDK_USBDRDX_UAHC_DALEPENA(a) BDK_CSR_TYPE_NCB32b
687 #define basename_BDK_USBDRDX_UAHC_DALEPENA(a) "USBDRDX_UAHC_DALEPENA"
688 #define device_bar_BDK_USBDRDX_UAHC_DALEPENA(a) 0x0 /* PF_BAR0 */
689 #define busnum_BDK_USBDRDX_UAHC_DALEPENA(a) (a)
690 #define arguments_BDK_USBDRDX_UAHC_DALEPENA(a) (a),-1,-1,-1
691
692 /**
693 * Register (NCB32b) usbdrd#_uahc_db#
694 *
695 * USB XHCI Doorbell Registers
696 * For information on this register, refer to the xHCI Specification, v1.1, section 5.6.
697 *
698 * This register can be reset by NCB reset,
699 * or USBDRD()_UCTL_CTL[UAHC_RST],
700 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
701 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
702 *
703 * Internal:
704 * xHCI spec, page 32: there are USBDRD()_UAHC_HCSPARAMS1[MAXSLOTS]+1 doorbell
705 * registers.
706 */
707 union bdk_usbdrdx_uahc_dbx
708 {
709 uint32_t u;
710 struct bdk_usbdrdx_uahc_dbx_s
711 {
712 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
713 uint32_t dbstreamid : 16; /**< [ 31: 16](WO) Doorbell stream ID. */
714 uint32_t reserved_8_15 : 8;
715 uint32_t dbtarget : 8; /**< [ 7: 0](WO) Doorbell target. */
716 #else /* Word 0 - Little Endian */
717 uint32_t dbtarget : 8; /**< [ 7: 0](WO) Doorbell target. */
718 uint32_t reserved_8_15 : 8;
719 uint32_t dbstreamid : 16; /**< [ 31: 16](WO) Doorbell stream ID. */
720 #endif /* Word 0 - End */
721 } s;
722 /* struct bdk_usbdrdx_uahc_dbx_s cn; */
723 };
724 typedef union bdk_usbdrdx_uahc_dbx bdk_usbdrdx_uahc_dbx_t;
725
726 static inline uint64_t BDK_USBDRDX_UAHC_DBX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DBX(unsigned long a,unsigned long b)727 static inline uint64_t BDK_USBDRDX_UAHC_DBX(unsigned long a, unsigned long b)
728 {
729 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=64)))
730 return 0x868000000480ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x7f);
731 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=64)))
732 return 0x868000000480ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x7f);
733 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=64)))
734 return 0x868000000480ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x7f);
735 __bdk_csr_fatal("USBDRDX_UAHC_DBX", 2, a, b, 0, 0);
736 }
737
738 #define typedef_BDK_USBDRDX_UAHC_DBX(a,b) bdk_usbdrdx_uahc_dbx_t
739 #define bustype_BDK_USBDRDX_UAHC_DBX(a,b) BDK_CSR_TYPE_NCB32b
740 #define basename_BDK_USBDRDX_UAHC_DBX(a,b) "USBDRDX_UAHC_DBX"
741 #define device_bar_BDK_USBDRDX_UAHC_DBX(a,b) 0x0 /* PF_BAR0 */
742 #define busnum_BDK_USBDRDX_UAHC_DBX(a,b) (a)
743 #define arguments_BDK_USBDRDX_UAHC_DBX(a,b) (a),(b),-1,-1
744
745 /**
746 * Register (NCB32b) usbdrd#_uahc_dboff
747 *
748 * USB XHCI Doorbell Array Offset Register
749 * This register defines the offset of the doorbell array base address from the base. For
750 * information on this register, refer to the xHCI Specification, v1.1, section 5.3.7.
751 */
752 union bdk_usbdrdx_uahc_dboff
753 {
754 uint32_t u;
755 struct bdk_usbdrdx_uahc_dboff_s
756 {
757 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
758 uint32_t dboff : 30; /**< [ 31: 2](RO) Doorbell array offset. */
759 uint32_t reserved_0_1 : 2;
760 #else /* Word 0 - Little Endian */
761 uint32_t reserved_0_1 : 2;
762 uint32_t dboff : 30; /**< [ 31: 2](RO) Doorbell array offset. */
763 #endif /* Word 0 - End */
764 } s;
765 /* struct bdk_usbdrdx_uahc_dboff_s cn; */
766 };
767 typedef union bdk_usbdrdx_uahc_dboff bdk_usbdrdx_uahc_dboff_t;
768
769 static inline uint64_t BDK_USBDRDX_UAHC_DBOFF(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DBOFF(unsigned long a)770 static inline uint64_t BDK_USBDRDX_UAHC_DBOFF(unsigned long a)
771 {
772 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
773 return 0x868000000014ll + 0x1000000000ll * ((a) & 0x1);
774 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
775 return 0x868000000014ll + 0x1000000000ll * ((a) & 0x1);
776 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
777 return 0x868000000014ll + 0x1000000000ll * ((a) & 0x1);
778 __bdk_csr_fatal("USBDRDX_UAHC_DBOFF", 1, a, 0, 0, 0);
779 }
780
781 #define typedef_BDK_USBDRDX_UAHC_DBOFF(a) bdk_usbdrdx_uahc_dboff_t
782 #define bustype_BDK_USBDRDX_UAHC_DBOFF(a) BDK_CSR_TYPE_NCB32b
783 #define basename_BDK_USBDRDX_UAHC_DBOFF(a) "USBDRDX_UAHC_DBOFF"
784 #define device_bar_BDK_USBDRDX_UAHC_DBOFF(a) 0x0 /* PF_BAR0 */
785 #define busnum_BDK_USBDRDX_UAHC_DBOFF(a) (a)
786 #define arguments_BDK_USBDRDX_UAHC_DBOFF(a) (a),-1,-1,-1
787
788 /**
789 * Register (NCB) usbdrd#_uahc_dcbaap
790 *
791 * USB XHCI Device Context Base-Address-Array Pointer Register
792 * The device context base address array pointer register identifies the base address of the
793 * device
794 * context base address array.
795 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.6.
796 *
797 * This register can be reset by NCB reset,
798 * or USBDRD()_UCTL_CTL[UAHC_RST],
799 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
800 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
801 */
802 union bdk_usbdrdx_uahc_dcbaap
803 {
804 uint64_t u;
805 struct bdk_usbdrdx_uahc_dcbaap_s
806 {
807 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
808 uint64_t dcbaap : 58; /**< [ 63: 6](R/W) Device context base address array pointer. */
809 uint64_t reserved_0_5 : 6;
810 #else /* Word 0 - Little Endian */
811 uint64_t reserved_0_5 : 6;
812 uint64_t dcbaap : 58; /**< [ 63: 6](R/W) Device context base address array pointer. */
813 #endif /* Word 0 - End */
814 } s;
815 /* struct bdk_usbdrdx_uahc_dcbaap_s cn; */
816 };
817 typedef union bdk_usbdrdx_uahc_dcbaap bdk_usbdrdx_uahc_dcbaap_t;
818
819 static inline uint64_t BDK_USBDRDX_UAHC_DCBAAP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DCBAAP(unsigned long a)820 static inline uint64_t BDK_USBDRDX_UAHC_DCBAAP(unsigned long a)
821 {
822 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
823 return 0x868000000050ll + 0x1000000000ll * ((a) & 0x1);
824 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
825 return 0x868000000050ll + 0x1000000000ll * ((a) & 0x1);
826 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
827 return 0x868000000050ll + 0x1000000000ll * ((a) & 0x1);
828 __bdk_csr_fatal("USBDRDX_UAHC_DCBAAP", 1, a, 0, 0, 0);
829 }
830
831 #define typedef_BDK_USBDRDX_UAHC_DCBAAP(a) bdk_usbdrdx_uahc_dcbaap_t
832 #define bustype_BDK_USBDRDX_UAHC_DCBAAP(a) BDK_CSR_TYPE_NCB
833 #define basename_BDK_USBDRDX_UAHC_DCBAAP(a) "USBDRDX_UAHC_DCBAAP"
834 #define device_bar_BDK_USBDRDX_UAHC_DCBAAP(a) 0x0 /* PF_BAR0 */
835 #define busnum_BDK_USBDRDX_UAHC_DCBAAP(a) (a)
836 #define arguments_BDK_USBDRDX_UAHC_DCBAAP(a) (a),-1,-1,-1
837
838 /**
839 * Register (NCB32b) usbdrd#_uahc_dcfg
840 *
841 * USB Device Configuration Register
842 * This register configures the core in device mode after power-on or after certain control
843 * commands or enumeration. Do not make changes to this register after initial programming.
844 *
845 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST].
846 *
847 * Internal:
848 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.1.1.
849 */
850 union bdk_usbdrdx_uahc_dcfg
851 {
852 uint32_t u;
853 struct bdk_usbdrdx_uahc_dcfg_s
854 {
855 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
856 uint32_t reserved_24_31 : 8;
857 uint32_t ignorestreampp : 1; /**< [ 23: 23](R/W) This bit only affects stream-capable bulk endpoints.
858 When this bit is set to 0x0 and the controller receives a data packet with the
859 packet pending (PP) bit set to 0 for OUT endpoints, or it receives an ACK
860 with the NumP field set to 0 and PP set to 0 for IN endpoints, the core
861 attempts to search for another stream (CStream) to initiate to the host.
862
863 However, there are two situations where this behavior is not optimal:
864
865 * When the host is setting PP=0 even though it has not finished the
866 stream, or.
867
868 * When the endpoint on the device is configured with one transfer
869 resource and therefore does not have any other streams to initiate to the
870 host.
871
872 When this bit is set to 0x1, the core ignores the packet pending bit for the
873 purposes of stream selection and does not search for another stream when
874 it receives DP(PP=0) or ACK(NumP=0, PP=0). This can enhance the
875 performance when the device system bus bandwidth is low */
876 uint32_t lpmcap : 1; /**< [ 22: 22](R/W) LPM capable.
877 The application uses this bit to control the controller's core LPM
878 capabilities. If the core operates as a non-LPM-capable device, it cannot
879 respond to LPM transactions.
880 0x0 = LPM capability is not enabled.
881 0x1 = LPM capability is enabled. */
882 uint32_t nump : 5; /**< [ 21: 17](R/W) Number of receive buffers.
883 This bit indicates the number of receive buffers to be reported in the ACK
884 TP.
885 The DWC_usb3 controller uses this field if USBDRD()_UAHC_GRXTHRCFG[USBRXPKTCNTSEL]
886 is set to 0x0. The application can program this value based on RxFIFO size,
887 buffer sizes programmed in descriptors, and system latency.
888 For an OUT endpoint, this field controls the number of receive buffers
889 reported in the NumP field of the ACK TP transmitted by the core.
890
891 Internal:
892 Note: This bit is used in host mode when Debug Capability is enabled. */
893 uint32_t intrnum : 5; /**< [ 16: 12](R/W) Interrupt number.
894 Indicates interrupt/EventQ number on which non-endpoint-specific device-related
895 interrupts (see DEVT) are generated. */
896 uint32_t reserved_10_11 : 2;
897 uint32_t devaddr : 7; /**< [ 9: 3](R/W) Device address.
898 The application must perform the following:
899 * Program this field after every SetAddress request.
900 * Reset this field to zero after USB reset. */
901 uint32_t devspd : 3; /**< [ 2: 0](R/W) Device speed.
902 Indicates the speed at which the application requires the core to connect, or
903 the maximum speed the application can support. However, the actual bus
904 speed is determined only after the chirp sequence is completed, and is
905 based on the speed of the USB host to which the core is connected.
906 0x0 = High-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz).
907 0x1 = Full-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz).
908 0x4 = SuperSpeed (USB 3.0 PHY clock is 125 MHz or 250 MHz). */
909 #else /* Word 0 - Little Endian */
910 uint32_t devspd : 3; /**< [ 2: 0](R/W) Device speed.
911 Indicates the speed at which the application requires the core to connect, or
912 the maximum speed the application can support. However, the actual bus
913 speed is determined only after the chirp sequence is completed, and is
914 based on the speed of the USB host to which the core is connected.
915 0x0 = High-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz).
916 0x1 = Full-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz).
917 0x4 = SuperSpeed (USB 3.0 PHY clock is 125 MHz or 250 MHz). */
918 uint32_t devaddr : 7; /**< [ 9: 3](R/W) Device address.
919 The application must perform the following:
920 * Program this field after every SetAddress request.
921 * Reset this field to zero after USB reset. */
922 uint32_t reserved_10_11 : 2;
923 uint32_t intrnum : 5; /**< [ 16: 12](R/W) Interrupt number.
924 Indicates interrupt/EventQ number on which non-endpoint-specific device-related
925 interrupts (see DEVT) are generated. */
926 uint32_t nump : 5; /**< [ 21: 17](R/W) Number of receive buffers.
927 This bit indicates the number of receive buffers to be reported in the ACK
928 TP.
929 The DWC_usb3 controller uses this field if USBDRD()_UAHC_GRXTHRCFG[USBRXPKTCNTSEL]
930 is set to 0x0. The application can program this value based on RxFIFO size,
931 buffer sizes programmed in descriptors, and system latency.
932 For an OUT endpoint, this field controls the number of receive buffers
933 reported in the NumP field of the ACK TP transmitted by the core.
934
935 Internal:
936 Note: This bit is used in host mode when Debug Capability is enabled. */
937 uint32_t lpmcap : 1; /**< [ 22: 22](R/W) LPM capable.
938 The application uses this bit to control the controller's core LPM
939 capabilities. If the core operates as a non-LPM-capable device, it cannot
940 respond to LPM transactions.
941 0x0 = LPM capability is not enabled.
942 0x1 = LPM capability is enabled. */
943 uint32_t ignorestreampp : 1; /**< [ 23: 23](R/W) This bit only affects stream-capable bulk endpoints.
944 When this bit is set to 0x0 and the controller receives a data packet with the
945 packet pending (PP) bit set to 0 for OUT endpoints, or it receives an ACK
946 with the NumP field set to 0 and PP set to 0 for IN endpoints, the core
947 attempts to search for another stream (CStream) to initiate to the host.
948
949 However, there are two situations where this behavior is not optimal:
950
951 * When the host is setting PP=0 even though it has not finished the
952 stream, or.
953
954 * When the endpoint on the device is configured with one transfer
955 resource and therefore does not have any other streams to initiate to the
956 host.
957
958 When this bit is set to 0x1, the core ignores the packet pending bit for the
959 purposes of stream selection and does not search for another stream when
960 it receives DP(PP=0) or ACK(NumP=0, PP=0). This can enhance the
961 performance when the device system bus bandwidth is low */
962 uint32_t reserved_24_31 : 8;
963 #endif /* Word 0 - End */
964 } s;
965 /* struct bdk_usbdrdx_uahc_dcfg_s cn; */
966 };
967 typedef union bdk_usbdrdx_uahc_dcfg bdk_usbdrdx_uahc_dcfg_t;
968
969 static inline uint64_t BDK_USBDRDX_UAHC_DCFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DCFG(unsigned long a)970 static inline uint64_t BDK_USBDRDX_UAHC_DCFG(unsigned long a)
971 {
972 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
973 return 0x86800000c700ll + 0x1000000000ll * ((a) & 0x1);
974 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
975 return 0x86800000c700ll + 0x1000000000ll * ((a) & 0x1);
976 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
977 return 0x86800000c700ll + 0x1000000000ll * ((a) & 0x1);
978 __bdk_csr_fatal("USBDRDX_UAHC_DCFG", 1, a, 0, 0, 0);
979 }
980
981 #define typedef_BDK_USBDRDX_UAHC_DCFG(a) bdk_usbdrdx_uahc_dcfg_t
982 #define bustype_BDK_USBDRDX_UAHC_DCFG(a) BDK_CSR_TYPE_NCB32b
983 #define basename_BDK_USBDRDX_UAHC_DCFG(a) "USBDRDX_UAHC_DCFG"
984 #define device_bar_BDK_USBDRDX_UAHC_DCFG(a) 0x0 /* PF_BAR0 */
985 #define busnum_BDK_USBDRDX_UAHC_DCFG(a) (a)
986 #define arguments_BDK_USBDRDX_UAHC_DCFG(a) (a),-1,-1,-1
987
988 /**
989 * Register (NCB32b) usbdrd#_uahc_dctl
990 *
991 * USB Device Control Register
992 * This register controls device mode.
993 *
994 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST].
995 *
996 * Internal:
997 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.1.2.
998 */
999 union bdk_usbdrdx_uahc_dctl
1000 {
1001 uint32_t u;
1002 struct bdk_usbdrdx_uahc_dctl_s
1003 {
1004 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1005 uint32_t rs : 1; /**< [ 31: 31](R/W) Run/Stop.
1006 The software writes 1 to this bit to start the device controller operation.
1007 To stop the device controller operation, the software must remove any active
1008 transfers and write 0 to this bit. When the controller is stopped, it sets the
1009 USBDRD()_UAHC_DSTS[DEVCTRLHLT] bit when the core is idle and the lower layer finishes
1010 the disconnect process.
1011
1012 The Run/Stop bit must be used in following cases as specified:
1013
1014 1. After power-on reset and CSR initialization, the software must write 1 to this bit
1015 to start the device controller. The controller does not signal connect to the host
1016 until this bit is set.
1017
1018 2. The software uses this bit to control the device controller to perform a soft
1019 disconnect. When the software writes 0 to this bit, the host does not see that
1020 the device is connected. The device controller stays in the disconnected state
1021 until the software writes 1 to this bit. The minimum duration of keeping this bit
1022 cleared is 30 ms in SuperSpeed and 10 ms in high-speed/full-speed/low-speed.
1023
1024 If the software attempts a connect after the soft disconnect or detects a
1025 disconnect event, it must set USBDRD()_UAHC_DCTL[ULSTCHNGREQ] to
1026 "Rx.Detect" before reasserting the Run/Stop bit.
1027
1028 Internal:
1029 3. When the USB or Link is in a lower power state and the Two Power Rails
1030 configuration is selected, software writes 0 to this bit to indicate that it is going
1031 to turn off the Core Power Rail. After the software turns on the Core Power Rail
1032 again and re-initializes the device controller, it must set this bit to start the
1033 device controller. For more details, see Low Power Operation on page 599. */
1034 uint32_t csftrst : 1; /**< [ 30: 30](R/W1S/H) Core soft reset.
1035 Resets the all clock domains as follows:
1036 * Clears the interrupts and all the CSRs except the following registers:
1037 GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUID, GUSB2PHYCFGn registers,
1038 GUSB3PIPECTLn registers, DCFG, DCTL, DEVTEN, DSTS.
1039
1040 * All module state machines (except the SoC Bus Slave Unit) are reset to the
1041 IDLE state, and all the TxFIFOs and the RxFIFO are flushed.
1042
1043 * Any transactions on the SoC bus Master are terminated as soon as possible,
1044 after gracefully completing the last data phase of a SoC bus transfer. Any
1045 transactions on the USB are terminated immediately.
1046
1047 The application can write this bit at any time to reset the core. This is a self-clearing
1048 bit; the core clears this bit after all necessary logic is reset in the core,
1049 which may take several clocks depending on the core's current state. Once this
1050 bit is cleared, the software must wait at least 3 PHY clocks before accessing the
1051 PHY domain (synchronization delay). Typically, software reset is used during
1052 software development and also when you dynamically change the PHY selection
1053 bits in the USB configuration registers listed above. When you change the PHY,
1054 the corresponding clock for the PHY is selected and used in the PHY domain.
1055 Once a new clock is selected, the PHY domain must be reset for proper
1056 operation. */
1057 uint32_t reserved_29 : 1;
1058 uint32_t hird_thres : 5; /**< [ 28: 24](R/W) HIRD threshold.
1059 The core asserts output signals utmi_l1_suspend_n and utmi_sleep_n on the basis of this
1060 signal:
1061
1062 * The core asserts utmi_l1_suspend_n to put the PHY into Deep Low-Power
1063 mode in L1 when both of the following are true:
1064 - HIRD value is greater than or equal to the value in HIRD_Thres[3:0]
1065 - HIRD_Thres[4] is set to 1'b1.
1066
1067 * The core asserts utmi_sleep_n on L1 when one of the following is true:
1068 - If the HIRD value is less than HIRD_Thres[3:0] or
1069 - HIRD_Thres[4] is set to 1'b0. */
1070 uint32_t appl1res : 1; /**< [ 23: 23](R/W) LPM response programmed by application.
1071 Handshake response to LPM token specified by device application. Response
1072 depends on USBDRD()_UAHC_DCFG[LPMCAP].
1073
1074 LPMCAP is 0x0 - The core always responds with timeout (that is, no
1075 response).
1076
1077 LPMCAP is 0x1 and this bit is 0:
1078 The core responds with an ACK upon a successful LPM transaction,
1079 which requires all of the following are satisfied:
1080
1081 * There are no PID/CRC5 errors in both the EXT token and the LPM token
1082 (if not true, inactivity results in a timeout ERROR).
1083
1084 * A valid bLinkState = 0001B (L1) is received in the LPM transaction (else
1085 STALL).
1086
1087 * No data is pending in the Transmit FIFO and OUT endpoints not in flow
1088 controlled state (else NYET).
1089
1090 LPMCAP is 0x1 and this bit is 1:
1091 The core responds with an ACK upon a successful LPM, independent
1092 of transmit FIFO status and OUT endpoint flow control state. The LPM
1093 transaction is successful if all of the following are satisfied:
1094
1095 * There are no PID/CRC5 errors in both the EXT token and the LPM token
1096 (else ERROR).
1097
1098 * A valid bLinkState = 0001B (L1) is received in the LPM transaction (else
1099 STALL). */
1100 uint32_t reserved_20_22 : 3;
1101 uint32_t keepconnect : 1; /**< [ 19: 19](WO) Always write 0.
1102 Internal:
1103 Writing this bit to 0x1 does nothing since we don't have hibernation feature. */
1104 uint32_t l1hibernationen : 1; /**< [ 18: 18](WO) Always write 0.
1105 Internal:
1106 Writing this bit to 0x1 does nothing since we don't have hibernation feature. */
1107 uint32_t crs : 1; /**< [ 17: 17](WO) Controller restore state.
1108 This command is similar to the USBDRD()_UAHC_USBCMD[CRS] bit in host mode and
1109 initiates the restore process. When software sets this bit to 1, the controller
1110 immediately sets USBDRD()_UAHC_DSTS[RSS] to 1. When the controller has finished
1111 the restore process, it sets USBDRD()_UAHC_DSTS[RSS] to 0.
1112 Note: When read, this field always returns 0. */
1113 uint32_t css : 1; /**< [ 16: 16](WO) Controller save state.
1114 This command is similar to the USBDRD()_UAHC_USBCMD[CSS] bit in host mode and
1115 initiates the restore process. When software sets this bit to 1, the controller
1116 immediately sets USBDRD()_UAHC_DSTS[SSS] to 1. When the controller has finished
1117 the save process, it sets USBDRD()_UAHC_DSTS[SSS] to 0.
1118 Note: When read, this field always returns 0. */
1119 uint32_t reserved_13_15 : 3;
1120 uint32_t initu2ena : 1; /**< [ 12: 12](R/W) Initiate U2 enable.
1121 0 = May not initiate U2 (default).
1122 1 = May initiate U2.
1123
1124 On USB reset, hardware clears this bit to 0. Software sets this bit after receiving
1125 SetFeature(U2_ENABLE), and clears this bit when ClearFeature(U2_ENABLE) is
1126 received.
1127
1128 If USBDRD()_UAHC_DCTL[ACCEPTU2ENA] is 0, the link immediately exits U2 state. */
1129 uint32_t acceptu2ena : 1; /**< [ 11: 11](R/W) Accept U2 enable.
1130 0 = Reject U2 except when Force_LinkPM_Accept bit is set (default).
1131 1 = Core accepts transition to U2 state if nothing is pending on the
1132 application side.
1133
1134 On USB reset, hardware clears this bit to 0. Software sets this bit after receiving
1135 a SetConfiguration command. */
1136 uint32_t initu1ena : 1; /**< [ 10: 10](R/W) Initiate U1 enable.
1137 0 = May not initiate U1 (default).
1138 1 = May initiate U1.
1139
1140 On USB reset, hardware clears this bit to 0. Software sets this bit after receiving
1141 SetFeature(U1_ENABLE), and clears this bit when ClearFeature(U1_ENABLE) is
1142 received.
1143
1144 If USBDRD()_UAHC_DCTL[ACCEPTU1ENA] is 0, the link immediately exits U1 state. */
1145 uint32_t acceptu1ena : 1; /**< [ 9: 9](R/W) Accept U1 enable.
1146 0 = Reject U1 except when Force_LinkPM_Accept bit is set (default)
1147 1 = Core accepts transition to U1 state if nothing is pending on the
1148 application side.
1149
1150 On USB reset, hardware clears this bit to 0. Software sets this bit after receiving
1151 a SetConfiguration command. */
1152 uint32_t ulstchngreq : 4; /**< [ 8: 5](WO) USB/link state change request.
1153 Software writes this field to issue a USB/link state change request. A change in
1154 this field indicates a new request to the core. If software wants to issue the same
1155 request back-to-back, it must write a 0 to this field between the two requests. The
1156 result of the state change request is reflected in USBDRD()_UAHC_DSTS[USBLNKST].
1157 These bits are self-cleared on the MAC Layer exiting suspended state.
1158
1159 If software is updating other fields of the USBDRD()_UAHC_DCTL register and not
1160 intending to force any link state change, then it must write a 0 to this field.
1161 SuperSpeed compliance mode is normally entered and controlled by the remote link
1162 partner. Refer to the USB3 specification. Alternatively, you can force the local link
1163 directly into Compliance mode, by resetting the SuperSpeed link with the
1164 USBDRD()_UAHC_DCTL[RS] bit set to zero. If you then write 0xA to the ULSTCHNGREQ
1165 field and 1 to USBDRD()_UAHC_DCTL[RS], the Link will go to compliance. Once you
1166 are in compliance, you may alternately write 0x0 and 0xA to this field to advance
1167 the compliance pattern.
1168
1169 In SS mode:
1170 0x0 = No action.
1171 0x4 = SS.Disabled.
1172 0x5 = Rx.Detect.
1173 0x6 = SS.Inactive.
1174 0x8 = Recovery.
1175 0xA = Compliance.
1176 Others = Reserved.
1177
1178 In HS/FS/LS mode:
1179
1180 0x8 = Remote wakeup request.
1181 The remote wakeup request should be issued 2us after the device goes into
1182 suspend state (USBDRD()_UAHC_DSTS[USBLNKST] is 0x3).
1183 Others = Reserved. */
1184 uint32_t tstctl : 4; /**< [ 4: 1](R/W) Test control.
1185 0x0 = Test mode disabled.
1186 0x1 = Test_J mode.
1187 0x2 = Test_K mode.
1188 0x3 = Test_SE0_NAK mode.
1189 0x4 = Test_Packet mode.
1190 0x5 = Test_Force_Enable.
1191 Others = Reserved. */
1192 uint32_t reserved_0 : 1;
1193 #else /* Word 0 - Little Endian */
1194 uint32_t reserved_0 : 1;
1195 uint32_t tstctl : 4; /**< [ 4: 1](R/W) Test control.
1196 0x0 = Test mode disabled.
1197 0x1 = Test_J mode.
1198 0x2 = Test_K mode.
1199 0x3 = Test_SE0_NAK mode.
1200 0x4 = Test_Packet mode.
1201 0x5 = Test_Force_Enable.
1202 Others = Reserved. */
1203 uint32_t ulstchngreq : 4; /**< [ 8: 5](WO) USB/link state change request.
1204 Software writes this field to issue a USB/link state change request. A change in
1205 this field indicates a new request to the core. If software wants to issue the same
1206 request back-to-back, it must write a 0 to this field between the two requests. The
1207 result of the state change request is reflected in USBDRD()_UAHC_DSTS[USBLNKST].
1208 These bits are self-cleared on the MAC Layer exiting suspended state.
1209
1210 If software is updating other fields of the USBDRD()_UAHC_DCTL register and not
1211 intending to force any link state change, then it must write a 0 to this field.
1212 SuperSpeed compliance mode is normally entered and controlled by the remote link
1213 partner. Refer to the USB3 specification. Alternatively, you can force the local link
1214 directly into Compliance mode, by resetting the SuperSpeed link with the
1215 USBDRD()_UAHC_DCTL[RS] bit set to zero. If you then write 0xA to the ULSTCHNGREQ
1216 field and 1 to USBDRD()_UAHC_DCTL[RS], the Link will go to compliance. Once you
1217 are in compliance, you may alternately write 0x0 and 0xA to this field to advance
1218 the compliance pattern.
1219
1220 In SS mode:
1221 0x0 = No action.
1222 0x4 = SS.Disabled.
1223 0x5 = Rx.Detect.
1224 0x6 = SS.Inactive.
1225 0x8 = Recovery.
1226 0xA = Compliance.
1227 Others = Reserved.
1228
1229 In HS/FS/LS mode:
1230
1231 0x8 = Remote wakeup request.
1232 The remote wakeup request should be issued 2us after the device goes into
1233 suspend state (USBDRD()_UAHC_DSTS[USBLNKST] is 0x3).
1234 Others = Reserved. */
1235 uint32_t acceptu1ena : 1; /**< [ 9: 9](R/W) Accept U1 enable.
1236 0 = Reject U1 except when Force_LinkPM_Accept bit is set (default)
1237 1 = Core accepts transition to U1 state if nothing is pending on the
1238 application side.
1239
1240 On USB reset, hardware clears this bit to 0. Software sets this bit after receiving
1241 a SetConfiguration command. */
1242 uint32_t initu1ena : 1; /**< [ 10: 10](R/W) Initiate U1 enable.
1243 0 = May not initiate U1 (default).
1244 1 = May initiate U1.
1245
1246 On USB reset, hardware clears this bit to 0. Software sets this bit after receiving
1247 SetFeature(U1_ENABLE), and clears this bit when ClearFeature(U1_ENABLE) is
1248 received.
1249
1250 If USBDRD()_UAHC_DCTL[ACCEPTU1ENA] is 0, the link immediately exits U1 state. */
1251 uint32_t acceptu2ena : 1; /**< [ 11: 11](R/W) Accept U2 enable.
1252 0 = Reject U2 except when Force_LinkPM_Accept bit is set (default).
1253 1 = Core accepts transition to U2 state if nothing is pending on the
1254 application side.
1255
1256 On USB reset, hardware clears this bit to 0. Software sets this bit after receiving
1257 a SetConfiguration command. */
1258 uint32_t initu2ena : 1; /**< [ 12: 12](R/W) Initiate U2 enable.
1259 0 = May not initiate U2 (default).
1260 1 = May initiate U2.
1261
1262 On USB reset, hardware clears this bit to 0. Software sets this bit after receiving
1263 SetFeature(U2_ENABLE), and clears this bit when ClearFeature(U2_ENABLE) is
1264 received.
1265
1266 If USBDRD()_UAHC_DCTL[ACCEPTU2ENA] is 0, the link immediately exits U2 state. */
1267 uint32_t reserved_13_15 : 3;
1268 uint32_t css : 1; /**< [ 16: 16](WO) Controller save state.
1269 This command is similar to the USBDRD()_UAHC_USBCMD[CSS] bit in host mode and
1270 initiates the restore process. When software sets this bit to 1, the controller
1271 immediately sets USBDRD()_UAHC_DSTS[SSS] to 1. When the controller has finished
1272 the save process, it sets USBDRD()_UAHC_DSTS[SSS] to 0.
1273 Note: When read, this field always returns 0. */
1274 uint32_t crs : 1; /**< [ 17: 17](WO) Controller restore state.
1275 This command is similar to the USBDRD()_UAHC_USBCMD[CRS] bit in host mode and
1276 initiates the restore process. When software sets this bit to 1, the controller
1277 immediately sets USBDRD()_UAHC_DSTS[RSS] to 1. When the controller has finished
1278 the restore process, it sets USBDRD()_UAHC_DSTS[RSS] to 0.
1279 Note: When read, this field always returns 0. */
1280 uint32_t l1hibernationen : 1; /**< [ 18: 18](WO) Always write 0.
1281 Internal:
1282 Writing this bit to 0x1 does nothing since we don't have hibernation feature. */
1283 uint32_t keepconnect : 1; /**< [ 19: 19](WO) Always write 0.
1284 Internal:
1285 Writing this bit to 0x1 does nothing since we don't have hibernation feature. */
1286 uint32_t reserved_20_22 : 3;
1287 uint32_t appl1res : 1; /**< [ 23: 23](R/W) LPM response programmed by application.
1288 Handshake response to LPM token specified by device application. Response
1289 depends on USBDRD()_UAHC_DCFG[LPMCAP].
1290
1291 LPMCAP is 0x0 - The core always responds with timeout (that is, no
1292 response).
1293
1294 LPMCAP is 0x1 and this bit is 0:
1295 The core responds with an ACK upon a successful LPM transaction,
1296 which requires all of the following are satisfied:
1297
1298 * There are no PID/CRC5 errors in both the EXT token and the LPM token
1299 (if not true, inactivity results in a timeout ERROR).
1300
1301 * A valid bLinkState = 0001B (L1) is received in the LPM transaction (else
1302 STALL).
1303
1304 * No data is pending in the Transmit FIFO and OUT endpoints not in flow
1305 controlled state (else NYET).
1306
1307 LPMCAP is 0x1 and this bit is 1:
1308 The core responds with an ACK upon a successful LPM, independent
1309 of transmit FIFO status and OUT endpoint flow control state. The LPM
1310 transaction is successful if all of the following are satisfied:
1311
1312 * There are no PID/CRC5 errors in both the EXT token and the LPM token
1313 (else ERROR).
1314
1315 * A valid bLinkState = 0001B (L1) is received in the LPM transaction (else
1316 STALL). */
1317 uint32_t hird_thres : 5; /**< [ 28: 24](R/W) HIRD threshold.
1318 The core asserts output signals utmi_l1_suspend_n and utmi_sleep_n on the basis of this
1319 signal:
1320
1321 * The core asserts utmi_l1_suspend_n to put the PHY into Deep Low-Power
1322 mode in L1 when both of the following are true:
1323 - HIRD value is greater than or equal to the value in HIRD_Thres[3:0]
1324 - HIRD_Thres[4] is set to 1'b1.
1325
1326 * The core asserts utmi_sleep_n on L1 when one of the following is true:
1327 - If the HIRD value is less than HIRD_Thres[3:0] or
1328 - HIRD_Thres[4] is set to 1'b0. */
1329 uint32_t reserved_29 : 1;
1330 uint32_t csftrst : 1; /**< [ 30: 30](R/W1S/H) Core soft reset.
1331 Resets the all clock domains as follows:
1332 * Clears the interrupts and all the CSRs except the following registers:
1333 GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUID, GUSB2PHYCFGn registers,
1334 GUSB3PIPECTLn registers, DCFG, DCTL, DEVTEN, DSTS.
1335
1336 * All module state machines (except the SoC Bus Slave Unit) are reset to the
1337 IDLE state, and all the TxFIFOs and the RxFIFO are flushed.
1338
1339 * Any transactions on the SoC bus Master are terminated as soon as possible,
1340 after gracefully completing the last data phase of a SoC bus transfer. Any
1341 transactions on the USB are terminated immediately.
1342
1343 The application can write this bit at any time to reset the core. This is a self-clearing
1344 bit; the core clears this bit after all necessary logic is reset in the core,
1345 which may take several clocks depending on the core's current state. Once this
1346 bit is cleared, the software must wait at least 3 PHY clocks before accessing the
1347 PHY domain (synchronization delay). Typically, software reset is used during
1348 software development and also when you dynamically change the PHY selection
1349 bits in the USB configuration registers listed above. When you change the PHY,
1350 the corresponding clock for the PHY is selected and used in the PHY domain.
1351 Once a new clock is selected, the PHY domain must be reset for proper
1352 operation. */
1353 uint32_t rs : 1; /**< [ 31: 31](R/W) Run/Stop.
1354 The software writes 1 to this bit to start the device controller operation.
1355 To stop the device controller operation, the software must remove any active
1356 transfers and write 0 to this bit. When the controller is stopped, it sets the
1357 USBDRD()_UAHC_DSTS[DEVCTRLHLT] bit when the core is idle and the lower layer finishes
1358 the disconnect process.
1359
1360 The Run/Stop bit must be used in following cases as specified:
1361
1362 1. After power-on reset and CSR initialization, the software must write 1 to this bit
1363 to start the device controller. The controller does not signal connect to the host
1364 until this bit is set.
1365
1366 2. The software uses this bit to control the device controller to perform a soft
1367 disconnect. When the software writes 0 to this bit, the host does not see that
1368 the device is connected. The device controller stays in the disconnected state
1369 until the software writes 1 to this bit. The minimum duration of keeping this bit
1370 cleared is 30 ms in SuperSpeed and 10 ms in high-speed/full-speed/low-speed.
1371
1372 If the software attempts a connect after the soft disconnect or detects a
1373 disconnect event, it must set USBDRD()_UAHC_DCTL[ULSTCHNGREQ] to
1374 "Rx.Detect" before reasserting the Run/Stop bit.
1375
1376 Internal:
1377 3. When the USB or Link is in a lower power state and the Two Power Rails
1378 configuration is selected, software writes 0 to this bit to indicate that it is going
1379 to turn off the Core Power Rail. After the software turns on the Core Power Rail
1380 again and re-initializes the device controller, it must set this bit to start the
1381 device controller. For more details, see Low Power Operation on page 599. */
1382 #endif /* Word 0 - End */
1383 } s;
1384 /* struct bdk_usbdrdx_uahc_dctl_s cn; */
1385 };
1386 typedef union bdk_usbdrdx_uahc_dctl bdk_usbdrdx_uahc_dctl_t;
1387
1388 static inline uint64_t BDK_USBDRDX_UAHC_DCTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DCTL(unsigned long a)1389 static inline uint64_t BDK_USBDRDX_UAHC_DCTL(unsigned long a)
1390 {
1391 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1392 return 0x86800000c704ll + 0x1000000000ll * ((a) & 0x1);
1393 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1394 return 0x86800000c704ll + 0x1000000000ll * ((a) & 0x1);
1395 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
1396 return 0x86800000c704ll + 0x1000000000ll * ((a) & 0x1);
1397 __bdk_csr_fatal("USBDRDX_UAHC_DCTL", 1, a, 0, 0, 0);
1398 }
1399
1400 #define typedef_BDK_USBDRDX_UAHC_DCTL(a) bdk_usbdrdx_uahc_dctl_t
1401 #define bustype_BDK_USBDRDX_UAHC_DCTL(a) BDK_CSR_TYPE_NCB32b
1402 #define basename_BDK_USBDRDX_UAHC_DCTL(a) "USBDRDX_UAHC_DCTL"
1403 #define device_bar_BDK_USBDRDX_UAHC_DCTL(a) 0x0 /* PF_BAR0 */
1404 #define busnum_BDK_USBDRDX_UAHC_DCTL(a) (a)
1405 #define arguments_BDK_USBDRDX_UAHC_DCTL(a) (a),-1,-1,-1
1406
1407 /**
1408 * Register (NCB32b) usbdrd#_uahc_depcmd#
1409 *
1410 * USB Device Physical Endpoint-n Command Register
1411 * This register enables software to issue physical endpoint-specific commands. This register
1412 * contains command, control, and status fields relevant to the current generic command,
1413 * while the USBDRD()_UAHC_DEPCMDPAR* registers provide command parameters and return
1414 * status information.
1415 *
1416 * Several fields (including CMDTYPE) are write-only, so their read values are undefined. After
1417 * power-on, prior to issuing the first endpoint command, the read value of this register is
1418 * undefined. In particular, [CMDACT] may be set after power-on. In this case, it is safe
1419 * to issue an endpoint command.
1420 *
1421 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST] or
1422 * USBDRD()_UAHC_GCTL[CORESOFTRESET] or
1423 * USBDRD()_UAHC_USBCMD[HCRST] or USBDRD()_UAHC_USBCMD[LHCRST] or
1424 * USBDRD()_UAHC_DCTL[CSFTRST].
1425 *
1426 * Internal:
1427 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.12
1428 */
1429 union bdk_usbdrdx_uahc_depcmdx
1430 {
1431 uint32_t u;
1432 struct bdk_usbdrdx_uahc_depcmdx_s
1433 {
1434 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1435 uint32_t commandparam : 16; /**< [ 31: 16](R/W) Command or event parameters.
1436 When this register is written:
1437
1438 Command parameters:
1439
1440 For start transfer command:
1441 _ - [31:16]: StreamID. The USB StreamID assigned to this transfer
1442
1443 For start transfer command applied to an isochronous endpoint:
1444 _ - [31:16]: StartMicroFramNum: Indicates the (micro)frame number to
1445 which the first TRB applies
1446
1447 For update transfer, end transfer, and start new configuration
1448 commands:
1449 _ - [22:16]: Transfer resource index (XferRscIdx). The hardware-assigned
1450 transfer resource index for the transfer, which was returned
1451 in response to the start transfer command. The application
1452 software-assigned transfer resource index for a start new
1453 configuration command.
1454
1455 When this register is read:
1456
1457 For XferNotReady, XferComplete, and stream events on bulk endpoints:
1458 _ - [31:16]: StreamID. Applies only to bulk endpoints that support streams. This
1459 indicates the StreamID of the transfer for which the event is
1460 generated
1461 For XferInProgress:
1462 _ - [31:16]: Isochronous microframe number (IsocMicroFrameNum): Indicates the
1463 microframe number of the beginning of the interval that generated
1464 the XferInProgress event (debug purposes only)
1465 For XferNotReady events on Isochronous Endpoints:
1466 _ - [31:16]: Isochronous microframe number (IsocMicroFrameNum). Indicates the
1467 microframe number during which the endpoint was not ready
1468
1469 Note: controller core represents USB bus time as a 14-bit value on the bus and also
1470 in the DSTS register (USBDRD()_UAHC_DSTS[SOFFN]), but as a 16-bit value in the
1471 XferNotReady event. Use the 16-bit value to interact with isochronous endpoints via
1472 the StartXfer command. The extra two bits that the controller core produces will be
1473 necessary for handling wrap-around conditions in the interaction between software
1474 and hardware.
1475
1476 For all EPCmdCmplt events
1477 _ - [27:24]: Command type. The command type that completed (Valid only in a DEPEVT
1478 event. Undefined when read from the
1479 USBDRD()_UAHC_DEPCMD()[COMMANDPARAM] field).
1480
1481 For EPCmdCmplt event in response to start transfer command:
1482 _ - [22:16]: Transfer resource index (XferRscIdx). The internal hardware transfer
1483 resource index assigned to this transfer. This index must be used in
1484 all update transfer and end transfer commands. */
1485 uint32_t cmdstatus : 4; /**< [ 15: 12](R/W) Command completion status.
1486 Additional information about the completion of this command is available in
1487 this field.
1488
1489 Within an XferNotReady event:
1490 _ [15]: Indicates the reason why the XferNotReady event is generated:
1491 _ [15] = 0: XferNotActive: Host initiated a transfer, but the requested transfer is not
1492 present in the hardware.
1493 _ [15] = 1: XferActive: Host initiated a transfer, the transfer is present, but no valid
1494 TRBs
1495 are available
1496 _ [14]: Not Used
1497 _ [13:12]: For control endpoints, indicates what stage was requested when the transfer was
1498 not ready:
1499 _ [13:12] = 0x1: Control data request
1500 _ [13:12] = 0x2: Control status request
1501
1502 Within an XferComplete or XferInProgress event:
1503 _ [15]: LST bit of the completed TRB (XferComplete only)
1504 _ [15]: MissedIsoc: Indicates the interval did not complete successfully (XferInProgress
1505 only)
1506 _ [14]: IOC bit of the TRB that completed.
1507 _ [13]: Indicates the TRB completed with a short packet reception or the last packet of an
1508 isochronous interval
1509 _ [12]: Reserved.
1510 If the host aborts the data stage of a control transfer, software may receive a
1511 XferComplete event with the EventStatus field equal to 0. This is a valid event
1512 that must be processed as a part of the control transfer programming model.
1513
1514 Within a stream event:
1515 _ [15:12] = 0x2: StreamNotFound: This stream event is issued when the stream-capable
1516 endpoint
1517 performed a search in its transfer resource cache, but could not find an active
1518 and ready stream.
1519 _ [15:12] = 0x1: StreamFound: This stream event is issued when the stream-capable endpoint
1520 found
1521 an active and ready stream in its transfer resource cache, and initiated traffic for
1522 that stream to the host. The ID of the selected Stream is in the EventParam field.
1523
1524 In response to a start transfer command:
1525 _ [15:12] = 0x2: Indicates expiry of the bus time reflected in the start transfer command.
1526 _ [15:12] = 0x1: Indicates there is no transfer resource available on the endpoint.
1527
1528 In response to a set transfer resource (DEPXFERCFG) command:
1529 _ [15:12] = 0x1: Indicates an error has occurred because software is requesting more
1530 transfer
1531 resources to be assigned than have been configured in the hardware.
1532
1533 In response to a end transfer command:
1534 _ [15:12] = 0x1: Indicates an invalid transfer resource was specified.
1535
1536 Internal:
1537 For abort handling, see also Synopsys DWC_usb3 Databook v2.80a, Section 8.4. */
1538 uint32_t hipri_forcerm : 1; /**< [ 11: 11](R/W) HighPriority: Only valid for start transfer command.
1539 ForceRM: Only valid for end transfer command. */
1540 uint32_t cmdact : 1; /**< [ 10: 10](R/W) Software sets this bit to 1 to enable the device endpoint controller to
1541 execute the generic command.
1542 The device controller sets this bit to 0 when [CMDSTATUS] is valid and
1543 the endpoint is ready to accept another command. This does not imply that
1544 all the effects of the previously-issued command have taken place. */
1545 uint32_t reserved_9 : 1;
1546 uint32_t cmdioc : 1; /**< [ 8: 8](R/W) Command interrupt on complete.
1547 When this bit is set, the device controller issues a generic endpoint
1548 command complete event after executing the command. Note that this
1549 interrupt is mapped to DEPCFG.IntrNum. When the DEPCFG command is
1550 executed, the command interrupt on completion goes to the interrupt
1551 pointed by the USBDRD()_UAHC_DCFG[INTRNUM] in the current command.
1552 Note: This field must not set to 1 if the USBDRD()_UAHC_DCTL[RS] field is 0. */
1553 uint32_t reserved_4_7 : 4;
1554 uint32_t cmdtyp : 4; /**< [ 3: 0](R/W) Command type.
1555 Specifies the type of command the software driver is requesting the core to
1556 perform.
1557 0x0 = Reserved.
1558 0x1 = Set endpoint configuration (64 or 96-bit parameter).
1559 0x2 = Set endpoint transfer resource configuration (32-bit parameter).
1560 0x3 = Get endpoint state (no parameter needed).
1561 0x4 = Set stall (no parameter needed).
1562 0x5 = Clear stall (see set stall, no parameter needed).
1563 0x6 = Start transfer (64-bit parameter).
1564 0x7 = Update transfer (no parameter needed).
1565 0x8 = End transfer (no parameter needed).
1566 0x9 = Start new configuration (no parameter needed). */
1567 #else /* Word 0 - Little Endian */
1568 uint32_t cmdtyp : 4; /**< [ 3: 0](R/W) Command type.
1569 Specifies the type of command the software driver is requesting the core to
1570 perform.
1571 0x0 = Reserved.
1572 0x1 = Set endpoint configuration (64 or 96-bit parameter).
1573 0x2 = Set endpoint transfer resource configuration (32-bit parameter).
1574 0x3 = Get endpoint state (no parameter needed).
1575 0x4 = Set stall (no parameter needed).
1576 0x5 = Clear stall (see set stall, no parameter needed).
1577 0x6 = Start transfer (64-bit parameter).
1578 0x7 = Update transfer (no parameter needed).
1579 0x8 = End transfer (no parameter needed).
1580 0x9 = Start new configuration (no parameter needed). */
1581 uint32_t reserved_4_7 : 4;
1582 uint32_t cmdioc : 1; /**< [ 8: 8](R/W) Command interrupt on complete.
1583 When this bit is set, the device controller issues a generic endpoint
1584 command complete event after executing the command. Note that this
1585 interrupt is mapped to DEPCFG.IntrNum. When the DEPCFG command is
1586 executed, the command interrupt on completion goes to the interrupt
1587 pointed by the USBDRD()_UAHC_DCFG[INTRNUM] in the current command.
1588 Note: This field must not set to 1 if the USBDRD()_UAHC_DCTL[RS] field is 0. */
1589 uint32_t reserved_9 : 1;
1590 uint32_t cmdact : 1; /**< [ 10: 10](R/W) Software sets this bit to 1 to enable the device endpoint controller to
1591 execute the generic command.
1592 The device controller sets this bit to 0 when [CMDSTATUS] is valid and
1593 the endpoint is ready to accept another command. This does not imply that
1594 all the effects of the previously-issued command have taken place. */
1595 uint32_t hipri_forcerm : 1; /**< [ 11: 11](R/W) HighPriority: Only valid for start transfer command.
1596 ForceRM: Only valid for end transfer command. */
1597 uint32_t cmdstatus : 4; /**< [ 15: 12](R/W) Command completion status.
1598 Additional information about the completion of this command is available in
1599 this field.
1600
1601 Within an XferNotReady event:
1602 _ [15]: Indicates the reason why the XferNotReady event is generated:
1603 _ [15] = 0: XferNotActive: Host initiated a transfer, but the requested transfer is not
1604 present in the hardware.
1605 _ [15] = 1: XferActive: Host initiated a transfer, the transfer is present, but no valid
1606 TRBs
1607 are available
1608 _ [14]: Not Used
1609 _ [13:12]: For control endpoints, indicates what stage was requested when the transfer was
1610 not ready:
1611 _ [13:12] = 0x1: Control data request
1612 _ [13:12] = 0x2: Control status request
1613
1614 Within an XferComplete or XferInProgress event:
1615 _ [15]: LST bit of the completed TRB (XferComplete only)
1616 _ [15]: MissedIsoc: Indicates the interval did not complete successfully (XferInProgress
1617 only)
1618 _ [14]: IOC bit of the TRB that completed.
1619 _ [13]: Indicates the TRB completed with a short packet reception or the last packet of an
1620 isochronous interval
1621 _ [12]: Reserved.
1622 If the host aborts the data stage of a control transfer, software may receive a
1623 XferComplete event with the EventStatus field equal to 0. This is a valid event
1624 that must be processed as a part of the control transfer programming model.
1625
1626 Within a stream event:
1627 _ [15:12] = 0x2: StreamNotFound: This stream event is issued when the stream-capable
1628 endpoint
1629 performed a search in its transfer resource cache, but could not find an active
1630 and ready stream.
1631 _ [15:12] = 0x1: StreamFound: This stream event is issued when the stream-capable endpoint
1632 found
1633 an active and ready stream in its transfer resource cache, and initiated traffic for
1634 that stream to the host. The ID of the selected Stream is in the EventParam field.
1635
1636 In response to a start transfer command:
1637 _ [15:12] = 0x2: Indicates expiry of the bus time reflected in the start transfer command.
1638 _ [15:12] = 0x1: Indicates there is no transfer resource available on the endpoint.
1639
1640 In response to a set transfer resource (DEPXFERCFG) command:
1641 _ [15:12] = 0x1: Indicates an error has occurred because software is requesting more
1642 transfer
1643 resources to be assigned than have been configured in the hardware.
1644
1645 In response to a end transfer command:
1646 _ [15:12] = 0x1: Indicates an invalid transfer resource was specified.
1647
1648 Internal:
1649 For abort handling, see also Synopsys DWC_usb3 Databook v2.80a, Section 8.4. */
1650 uint32_t commandparam : 16; /**< [ 31: 16](R/W) Command or event parameters.
1651 When this register is written:
1652
1653 Command parameters:
1654
1655 For start transfer command:
1656 _ - [31:16]: StreamID. The USB StreamID assigned to this transfer
1657
1658 For start transfer command applied to an isochronous endpoint:
1659 _ - [31:16]: StartMicroFramNum: Indicates the (micro)frame number to
1660 which the first TRB applies
1661
1662 For update transfer, end transfer, and start new configuration
1663 commands:
1664 _ - [22:16]: Transfer resource index (XferRscIdx). The hardware-assigned
1665 transfer resource index for the transfer, which was returned
1666 in response to the start transfer command. The application
1667 software-assigned transfer resource index for a start new
1668 configuration command.
1669
1670 When this register is read:
1671
1672 For XferNotReady, XferComplete, and stream events on bulk endpoints:
1673 _ - [31:16]: StreamID. Applies only to bulk endpoints that support streams. This
1674 indicates the StreamID of the transfer for which the event is
1675 generated
1676 For XferInProgress:
1677 _ - [31:16]: Isochronous microframe number (IsocMicroFrameNum): Indicates the
1678 microframe number of the beginning of the interval that generated
1679 the XferInProgress event (debug purposes only)
1680 For XferNotReady events on Isochronous Endpoints:
1681 _ - [31:16]: Isochronous microframe number (IsocMicroFrameNum). Indicates the
1682 microframe number during which the endpoint was not ready
1683
1684 Note: controller core represents USB bus time as a 14-bit value on the bus and also
1685 in the DSTS register (USBDRD()_UAHC_DSTS[SOFFN]), but as a 16-bit value in the
1686 XferNotReady event. Use the 16-bit value to interact with isochronous endpoints via
1687 the StartXfer command. The extra two bits that the controller core produces will be
1688 necessary for handling wrap-around conditions in the interaction between software
1689 and hardware.
1690
1691 For all EPCmdCmplt events
1692 _ - [27:24]: Command type. The command type that completed (Valid only in a DEPEVT
1693 event. Undefined when read from the
1694 USBDRD()_UAHC_DEPCMD()[COMMANDPARAM] field).
1695
1696 For EPCmdCmplt event in response to start transfer command:
1697 _ - [22:16]: Transfer resource index (XferRscIdx). The internal hardware transfer
1698 resource index assigned to this transfer. This index must be used in
1699 all update transfer and end transfer commands. */
1700 #endif /* Word 0 - End */
1701 } s;
1702 /* struct bdk_usbdrdx_uahc_depcmdx_s cn; */
1703 };
1704 typedef union bdk_usbdrdx_uahc_depcmdx bdk_usbdrdx_uahc_depcmdx_t;
1705
1706 static inline uint64_t BDK_USBDRDX_UAHC_DEPCMDX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DEPCMDX(unsigned long a,unsigned long b)1707 static inline uint64_t BDK_USBDRDX_UAHC_DEPCMDX(unsigned long a, unsigned long b)
1708 {
1709 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=15)))
1710 return 0x86800000c80cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1711 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=15)))
1712 return 0x86800000c80cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1713 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=15)))
1714 return 0x86800000c80cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1715 __bdk_csr_fatal("USBDRDX_UAHC_DEPCMDX", 2, a, b, 0, 0);
1716 }
1717
1718 #define typedef_BDK_USBDRDX_UAHC_DEPCMDX(a,b) bdk_usbdrdx_uahc_depcmdx_t
1719 #define bustype_BDK_USBDRDX_UAHC_DEPCMDX(a,b) BDK_CSR_TYPE_NCB32b
1720 #define basename_BDK_USBDRDX_UAHC_DEPCMDX(a,b) "USBDRDX_UAHC_DEPCMDX"
1721 #define device_bar_BDK_USBDRDX_UAHC_DEPCMDX(a,b) 0x0 /* PF_BAR0 */
1722 #define busnum_BDK_USBDRDX_UAHC_DEPCMDX(a,b) (a)
1723 #define arguments_BDK_USBDRDX_UAHC_DEPCMDX(a,b) (a),(b),-1,-1
1724
1725 /**
1726 * Register (NCB32b) usbdrd#_uahc_depcmdpar0_#
1727 *
1728 * USB Device Physical Endpoint-n Command Parameter 0 Register
1729 * This register indicates the physical endpoint command parameter 0. It must be programmed
1730 * before issuing the command.
1731 *
1732 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST] or
1733 * USBDRD()_UAHC_GCTL[CORESOFTRESET] or
1734 * USBDRD()_UAHC_USBCMD[HCRST] or USBDRD()_UAHC_USBCMD[LHCRST] or
1735 * USBDRD()_UAHC_DCTL[CSFTRST].
1736 *
1737 * Internal:
1738 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.11
1739 */
1740 union bdk_usbdrdx_uahc_depcmdpar0_x
1741 {
1742 uint32_t u;
1743 struct bdk_usbdrdx_uahc_depcmdpar0_x_s
1744 {
1745 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1746 uint32_t param0 : 32; /**< [ 31: 0](R/W) Physical endpoint command parameter 0 */
1747 #else /* Word 0 - Little Endian */
1748 uint32_t param0 : 32; /**< [ 31: 0](R/W) Physical endpoint command parameter 0 */
1749 #endif /* Word 0 - End */
1750 } s;
1751 /* struct bdk_usbdrdx_uahc_depcmdpar0_x_s cn; */
1752 };
1753 typedef union bdk_usbdrdx_uahc_depcmdpar0_x bdk_usbdrdx_uahc_depcmdpar0_x_t;
1754
1755 static inline uint64_t BDK_USBDRDX_UAHC_DEPCMDPAR0_X(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DEPCMDPAR0_X(unsigned long a,unsigned long b)1756 static inline uint64_t BDK_USBDRDX_UAHC_DEPCMDPAR0_X(unsigned long a, unsigned long b)
1757 {
1758 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=15)))
1759 return 0x86800000c808ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1760 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=15)))
1761 return 0x86800000c808ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1762 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=15)))
1763 return 0x86800000c808ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1764 __bdk_csr_fatal("USBDRDX_UAHC_DEPCMDPAR0_X", 2, a, b, 0, 0);
1765 }
1766
1767 #define typedef_BDK_USBDRDX_UAHC_DEPCMDPAR0_X(a,b) bdk_usbdrdx_uahc_depcmdpar0_x_t
1768 #define bustype_BDK_USBDRDX_UAHC_DEPCMDPAR0_X(a,b) BDK_CSR_TYPE_NCB32b
1769 #define basename_BDK_USBDRDX_UAHC_DEPCMDPAR0_X(a,b) "USBDRDX_UAHC_DEPCMDPAR0_X"
1770 #define device_bar_BDK_USBDRDX_UAHC_DEPCMDPAR0_X(a,b) 0x0 /* PF_BAR0 */
1771 #define busnum_BDK_USBDRDX_UAHC_DEPCMDPAR0_X(a,b) (a)
1772 #define arguments_BDK_USBDRDX_UAHC_DEPCMDPAR0_X(a,b) (a),(b),-1,-1
1773
1774 /**
1775 * Register (NCB32b) usbdrd#_uahc_depcmdpar1_#
1776 *
1777 * USB Device Physical Endpoint-n Command Parameter 1 Register
1778 * This register indicates the physical endpoint command parameter 1. It must be programmed
1779 * before issuing the command.
1780 *
1781 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST] or
1782 * USBDRD()_UAHC_GCTL[CORESOFTRESET] or
1783 * USBDRD()_UAHC_USBCMD[HCRST] or USBDRD()_UAHC_USBCMD[LHCRST] or
1784 * USBDRD()_UAHC_DCTL[CSFTRST].
1785 *
1786 * Internal:
1787 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.10
1788 */
1789 union bdk_usbdrdx_uahc_depcmdpar1_x
1790 {
1791 uint32_t u;
1792 struct bdk_usbdrdx_uahc_depcmdpar1_x_s
1793 {
1794 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1795 uint32_t param1 : 32; /**< [ 31: 0](R/W) Physical endpoint command parameter 1 */
1796 #else /* Word 0 - Little Endian */
1797 uint32_t param1 : 32; /**< [ 31: 0](R/W) Physical endpoint command parameter 1 */
1798 #endif /* Word 0 - End */
1799 } s;
1800 /* struct bdk_usbdrdx_uahc_depcmdpar1_x_s cn; */
1801 };
1802 typedef union bdk_usbdrdx_uahc_depcmdpar1_x bdk_usbdrdx_uahc_depcmdpar1_x_t;
1803
1804 static inline uint64_t BDK_USBDRDX_UAHC_DEPCMDPAR1_X(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DEPCMDPAR1_X(unsigned long a,unsigned long b)1805 static inline uint64_t BDK_USBDRDX_UAHC_DEPCMDPAR1_X(unsigned long a, unsigned long b)
1806 {
1807 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=15)))
1808 return 0x86800000c804ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1809 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=15)))
1810 return 0x86800000c804ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1811 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=15)))
1812 return 0x86800000c804ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1813 __bdk_csr_fatal("USBDRDX_UAHC_DEPCMDPAR1_X", 2, a, b, 0, 0);
1814 }
1815
1816 #define typedef_BDK_USBDRDX_UAHC_DEPCMDPAR1_X(a,b) bdk_usbdrdx_uahc_depcmdpar1_x_t
1817 #define bustype_BDK_USBDRDX_UAHC_DEPCMDPAR1_X(a,b) BDK_CSR_TYPE_NCB32b
1818 #define basename_BDK_USBDRDX_UAHC_DEPCMDPAR1_X(a,b) "USBDRDX_UAHC_DEPCMDPAR1_X"
1819 #define device_bar_BDK_USBDRDX_UAHC_DEPCMDPAR1_X(a,b) 0x0 /* PF_BAR0 */
1820 #define busnum_BDK_USBDRDX_UAHC_DEPCMDPAR1_X(a,b) (a)
1821 #define arguments_BDK_USBDRDX_UAHC_DEPCMDPAR1_X(a,b) (a),(b),-1,-1
1822
1823 /**
1824 * Register (NCB32b) usbdrd#_uahc_depcmdpar2_#
1825 *
1826 * USB Device Physical Endpoint-n Command Parameter 2 Register
1827 * This register indicates the physical endpoint command parameter 2. It must be programmed
1828 * before issuing the command.
1829 *
1830 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST] or
1831 * USBDRD()_UAHC_GCTL[CORESOFTRESET] or
1832 * USBDRD()_UAHC_USBCMD[HCRST] or USBDRD()_UAHC_USBCMD[LHCRST] or
1833 * USBDRD()_UAHC_DCTL[CSFTRST].
1834 *
1835 * Internal:
1836 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.9
1837 */
1838 union bdk_usbdrdx_uahc_depcmdpar2_x
1839 {
1840 uint32_t u;
1841 struct bdk_usbdrdx_uahc_depcmdpar2_x_s
1842 {
1843 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1844 uint32_t param2 : 32; /**< [ 31: 0](R/W) Physical endpoint command parameter 2 */
1845 #else /* Word 0 - Little Endian */
1846 uint32_t param2 : 32; /**< [ 31: 0](R/W) Physical endpoint command parameter 2 */
1847 #endif /* Word 0 - End */
1848 } s;
1849 /* struct bdk_usbdrdx_uahc_depcmdpar2_x_s cn; */
1850 };
1851 typedef union bdk_usbdrdx_uahc_depcmdpar2_x bdk_usbdrdx_uahc_depcmdpar2_x_t;
1852
1853 static inline uint64_t BDK_USBDRDX_UAHC_DEPCMDPAR2_X(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DEPCMDPAR2_X(unsigned long a,unsigned long b)1854 static inline uint64_t BDK_USBDRDX_UAHC_DEPCMDPAR2_X(unsigned long a, unsigned long b)
1855 {
1856 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=15)))
1857 return 0x86800000c800ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1858 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=15)))
1859 return 0x86800000c800ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1860 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=15)))
1861 return 0x86800000c800ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1862 __bdk_csr_fatal("USBDRDX_UAHC_DEPCMDPAR2_X", 2, a, b, 0, 0);
1863 }
1864
1865 #define typedef_BDK_USBDRDX_UAHC_DEPCMDPAR2_X(a,b) bdk_usbdrdx_uahc_depcmdpar2_x_t
1866 #define bustype_BDK_USBDRDX_UAHC_DEPCMDPAR2_X(a,b) BDK_CSR_TYPE_NCB32b
1867 #define basename_BDK_USBDRDX_UAHC_DEPCMDPAR2_X(a,b) "USBDRDX_UAHC_DEPCMDPAR2_X"
1868 #define device_bar_BDK_USBDRDX_UAHC_DEPCMDPAR2_X(a,b) 0x0 /* PF_BAR0 */
1869 #define busnum_BDK_USBDRDX_UAHC_DEPCMDPAR2_X(a,b) (a)
1870 #define arguments_BDK_USBDRDX_UAHC_DEPCMDPAR2_X(a,b) (a),(b),-1,-1
1871
1872 /**
1873 * Register (NCB32b) usbdrd#_uahc_dev_imod#
1874 *
1875 * USB Device Interrupt Moderation Register
1876 * This register controls the interrupt moderation feature that allows the device software to
1877 * throttle the interrupt rate.
1878 */
1879 union bdk_usbdrdx_uahc_dev_imodx
1880 {
1881 uint32_t u;
1882 struct bdk_usbdrdx_uahc_dev_imodx_s
1883 {
1884 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1885 uint32_t device_imodc : 16; /**< [ 31: 16](R/W) Interrupt moderation down counter. Loaded with the [DEVICE_IMODI] value,
1886 whenever the hardware interrupt(n) line is de-asserted from the asserted state,
1887 counts down to 0, and stops. */
1888 uint32_t device_imodi : 16; /**< [ 15: 0](R/W) Minimum inter-interrupt interval between events. The interval is
1889 specified in terms of 250 ns increments. */
1890 #else /* Word 0 - Little Endian */
1891 uint32_t device_imodi : 16; /**< [ 15: 0](R/W) Minimum inter-interrupt interval between events. The interval is
1892 specified in terms of 250 ns increments. */
1893 uint32_t device_imodc : 16; /**< [ 31: 16](R/W) Interrupt moderation down counter. Loaded with the [DEVICE_IMODI] value,
1894 whenever the hardware interrupt(n) line is de-asserted from the asserted state,
1895 counts down to 0, and stops. */
1896 #endif /* Word 0 - End */
1897 } s;
1898 /* struct bdk_usbdrdx_uahc_dev_imodx_s cn; */
1899 };
1900 typedef union bdk_usbdrdx_uahc_dev_imodx bdk_usbdrdx_uahc_dev_imodx_t;
1901
1902 static inline uint64_t BDK_USBDRDX_UAHC_DEV_IMODX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DEV_IMODX(unsigned long a,unsigned long b)1903 static inline uint64_t BDK_USBDRDX_UAHC_DEV_IMODX(unsigned long a, unsigned long b)
1904 {
1905 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=15)))
1906 return 0x86800000ca00ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0xf);
1907 __bdk_csr_fatal("USBDRDX_UAHC_DEV_IMODX", 2, a, b, 0, 0);
1908 }
1909
1910 #define typedef_BDK_USBDRDX_UAHC_DEV_IMODX(a,b) bdk_usbdrdx_uahc_dev_imodx_t
1911 #define bustype_BDK_USBDRDX_UAHC_DEV_IMODX(a,b) BDK_CSR_TYPE_NCB32b
1912 #define basename_BDK_USBDRDX_UAHC_DEV_IMODX(a,b) "USBDRDX_UAHC_DEV_IMODX"
1913 #define device_bar_BDK_USBDRDX_UAHC_DEV_IMODX(a,b) 0x0 /* PF_BAR0 */
1914 #define busnum_BDK_USBDRDX_UAHC_DEV_IMODX(a,b) (a)
1915 #define arguments_BDK_USBDRDX_UAHC_DEV_IMODX(a,b) (a),(b),-1,-1
1916
1917 /**
1918 * Register (NCB32b) usbdrd#_uahc_devten
1919 *
1920 * USB Device Event Enable Register
1921 * This register controls the generation of device-specific events.
1922 * If an enable bit is set to 0, the event will not be generated.
1923 *
1924 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST].
1925 *
1926 * Internal:
1927 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.3
1928 */
1929 union bdk_usbdrdx_uahc_devten
1930 {
1931 uint32_t u;
1932 struct bdk_usbdrdx_uahc_devten_s
1933 {
1934 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1935 uint32_t reserved_15_31 : 17;
1936 uint32_t l1wkupevten : 1; /**< [ 14: 14](R/W) L1 resume detected event enable. */
1937 uint32_t stopondisconnecten : 1; /**< [ 13: 13](RO/H) Vendor device test LMP received event. */
1938 uint32_t vndrdevtstrcveden : 1; /**< [ 12: 12](R/W) Vendor device test LMP received event. */
1939 uint32_t reserved_10_11 : 2;
1940 uint32_t errticerren : 1; /**< [ 9: 9](R/W) Erratic error event enable. */
1941 uint32_t l1suspen : 1; /**< [ 8: 8](R/W) Reserved. */
1942 uint32_t sofen : 1; /**< [ 7: 7](R/W) Start of (micro)frame enable.
1943 For debug purposes only; normally software must disable this event. */
1944 uint32_t u3l2l1suspen : 1; /**< [ 6: 6](R/W) U3/L2-L1 suspend event enable. */
1945 uint32_t hibernationreqevten : 1; /**< [ 5: 5](R/W) This bit enables/disables the generation of the hibernation request event.
1946 Internal:
1947 Writing this bit to 0x1 does nothing since we don't have hibernation feature. */
1948 uint32_t wkupevten : 1; /**< [ 4: 4](R/W) Resume/remote wakeup detected event enable. */
1949 uint32_t ulstcngen : 1; /**< [ 3: 3](R/W) USB/link state change event enable. */
1950 uint32_t connectdoneen : 1; /**< [ 2: 2](R/W) Connection done enable. */
1951 uint32_t usbrsten : 1; /**< [ 1: 1](R/W) USB reset enable. */
1952 uint32_t disconnevten : 1; /**< [ 0: 0](R/W) Disconnect detected event enable. */
1953 #else /* Word 0 - Little Endian */
1954 uint32_t disconnevten : 1; /**< [ 0: 0](R/W) Disconnect detected event enable. */
1955 uint32_t usbrsten : 1; /**< [ 1: 1](R/W) USB reset enable. */
1956 uint32_t connectdoneen : 1; /**< [ 2: 2](R/W) Connection done enable. */
1957 uint32_t ulstcngen : 1; /**< [ 3: 3](R/W) USB/link state change event enable. */
1958 uint32_t wkupevten : 1; /**< [ 4: 4](R/W) Resume/remote wakeup detected event enable. */
1959 uint32_t hibernationreqevten : 1; /**< [ 5: 5](R/W) This bit enables/disables the generation of the hibernation request event.
1960 Internal:
1961 Writing this bit to 0x1 does nothing since we don't have hibernation feature. */
1962 uint32_t u3l2l1suspen : 1; /**< [ 6: 6](R/W) U3/L2-L1 suspend event enable. */
1963 uint32_t sofen : 1; /**< [ 7: 7](R/W) Start of (micro)frame enable.
1964 For debug purposes only; normally software must disable this event. */
1965 uint32_t l1suspen : 1; /**< [ 8: 8](R/W) Reserved. */
1966 uint32_t errticerren : 1; /**< [ 9: 9](R/W) Erratic error event enable. */
1967 uint32_t reserved_10_11 : 2;
1968 uint32_t vndrdevtstrcveden : 1; /**< [ 12: 12](R/W) Vendor device test LMP received event. */
1969 uint32_t stopondisconnecten : 1; /**< [ 13: 13](RO/H) Vendor device test LMP received event. */
1970 uint32_t l1wkupevten : 1; /**< [ 14: 14](R/W) L1 resume detected event enable. */
1971 uint32_t reserved_15_31 : 17;
1972 #endif /* Word 0 - End */
1973 } s;
1974 struct bdk_usbdrdx_uahc_devten_cn8
1975 {
1976 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1977 uint32_t reserved_13_31 : 19;
1978 uint32_t vndrdevtstrcveden : 1; /**< [ 12: 12](R/W) Vendor device test LMP received event. */
1979 uint32_t reserved_10_11 : 2;
1980 uint32_t errticerren : 1; /**< [ 9: 9](R/W) Erratic error event enable. */
1981 uint32_t reserved_8 : 1;
1982 uint32_t sofen : 1; /**< [ 7: 7](R/W) Start of (micro)frame enable.
1983 For debug purposes only; normally software must disable this event. */
1984 uint32_t u3l2l1suspen : 1; /**< [ 6: 6](R/W) U3/L2-L1 suspend event enable. */
1985 uint32_t hibernationreqevten : 1; /**< [ 5: 5](R/W) This bit enables/disables the generation of the hibernation request event.
1986 Internal:
1987 Writing this bit to 0x1 does nothing since we don't have hibernation feature. */
1988 uint32_t wkupevten : 1; /**< [ 4: 4](R/W) Resume/remote wakeup detected event enable. */
1989 uint32_t ulstcngen : 1; /**< [ 3: 3](R/W) USB/link state change event enable. */
1990 uint32_t connectdoneen : 1; /**< [ 2: 2](R/W) Connection done enable. */
1991 uint32_t usbrsten : 1; /**< [ 1: 1](R/W) USB reset enable. */
1992 uint32_t disconnevten : 1; /**< [ 0: 0](R/W) Disconnect detected event enable. */
1993 #else /* Word 0 - Little Endian */
1994 uint32_t disconnevten : 1; /**< [ 0: 0](R/W) Disconnect detected event enable. */
1995 uint32_t usbrsten : 1; /**< [ 1: 1](R/W) USB reset enable. */
1996 uint32_t connectdoneen : 1; /**< [ 2: 2](R/W) Connection done enable. */
1997 uint32_t ulstcngen : 1; /**< [ 3: 3](R/W) USB/link state change event enable. */
1998 uint32_t wkupevten : 1; /**< [ 4: 4](R/W) Resume/remote wakeup detected event enable. */
1999 uint32_t hibernationreqevten : 1; /**< [ 5: 5](R/W) This bit enables/disables the generation of the hibernation request event.
2000 Internal:
2001 Writing this bit to 0x1 does nothing since we don't have hibernation feature. */
2002 uint32_t u3l2l1suspen : 1; /**< [ 6: 6](R/W) U3/L2-L1 suspend event enable. */
2003 uint32_t sofen : 1; /**< [ 7: 7](R/W) Start of (micro)frame enable.
2004 For debug purposes only; normally software must disable this event. */
2005 uint32_t reserved_8 : 1;
2006 uint32_t errticerren : 1; /**< [ 9: 9](R/W) Erratic error event enable. */
2007 uint32_t reserved_10_11 : 2;
2008 uint32_t vndrdevtstrcveden : 1; /**< [ 12: 12](R/W) Vendor device test LMP received event. */
2009 uint32_t reserved_13_31 : 19;
2010 #endif /* Word 0 - End */
2011 } cn8;
2012 /* struct bdk_usbdrdx_uahc_devten_s cn9; */
2013 };
2014 typedef union bdk_usbdrdx_uahc_devten bdk_usbdrdx_uahc_devten_t;
2015
2016 static inline uint64_t BDK_USBDRDX_UAHC_DEVTEN(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DEVTEN(unsigned long a)2017 static inline uint64_t BDK_USBDRDX_UAHC_DEVTEN(unsigned long a)
2018 {
2019 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2020 return 0x86800000c708ll + 0x1000000000ll * ((a) & 0x1);
2021 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
2022 return 0x86800000c708ll + 0x1000000000ll * ((a) & 0x1);
2023 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2024 return 0x86800000c708ll + 0x1000000000ll * ((a) & 0x1);
2025 __bdk_csr_fatal("USBDRDX_UAHC_DEVTEN", 1, a, 0, 0, 0);
2026 }
2027
2028 #define typedef_BDK_USBDRDX_UAHC_DEVTEN(a) bdk_usbdrdx_uahc_devten_t
2029 #define bustype_BDK_USBDRDX_UAHC_DEVTEN(a) BDK_CSR_TYPE_NCB32b
2030 #define basename_BDK_USBDRDX_UAHC_DEVTEN(a) "USBDRDX_UAHC_DEVTEN"
2031 #define device_bar_BDK_USBDRDX_UAHC_DEVTEN(a) 0x0 /* PF_BAR0 */
2032 #define busnum_BDK_USBDRDX_UAHC_DEVTEN(a) (a)
2033 #define arguments_BDK_USBDRDX_UAHC_DEVTEN(a) (a),-1,-1,-1
2034
2035 /**
2036 * Register (NCB32b) usbdrd#_uahc_dgcmd
2037 *
2038 * USB Device Generic Command Register
2039 * This register enables software to program the core using a single generic command interface to
2040 * send link management packets and notifications. This register contains command, control, and
2041 * status fields relevant to the current generic command, while the USBDRD()_UAHC_DGCMDPAR
2042 * register provides the command parameter.
2043 *
2044 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST] or
2045 * USBDRD()_UAHC_GCTL[CORESOFTRESET] or
2046 * USBDRD()_UAHC_USBCMD[HCRST] or USBDRD()_UAHC_USBCMD[LHCRST] or
2047 * USBDRD()_UAHC_DCTL[CSFTRST].
2048 *
2049 * Internal:
2050 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.6
2051 */
2052 union bdk_usbdrdx_uahc_dgcmd
2053 {
2054 uint32_t u;
2055 struct bdk_usbdrdx_uahc_dgcmd_s
2056 {
2057 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2058 uint32_t reserved_16_31 : 16;
2059 uint32_t cmdstatus : 1; /**< [ 15: 15](RO) Command status.
2060 0 = Indicates command success.
2061 1 = CmdErr - Indicates that the device controller encountered an error
2062 while processing the command. */
2063 uint32_t reserved_11_14 : 4;
2064 uint32_t cmdact : 1; /**< [ 10: 10](R/W1S/H) Command active.
2065 The software sets this bit to 1 to enable the device controller to execute the
2066 generic command.
2067 The device controller sets this bit to 0 after executing the command. */
2068 uint32_t reserved_9 : 1;
2069 uint32_t cmdioc : 1; /**< [ 8: 8](WO) Command interrupt on complete.
2070 When this bit is set, the device controller issues a generic command
2071 completion event after executing the command. Note that this interrupt is
2072 mapped to USBDRD()_UAHC_DCFG[INTRNUM].
2073 Note: This field must not set to 1 if the USBDRD()_UAHC_DCTL[RS] field is 0. */
2074 uint32_t cmdtyp : 8; /**< [ 7: 0](WO) Specifies the type of command the software driver is requesting the core to
2075 perform. See USBDRD_UAHC_DGCMD_CMDTYPE_E for encodings and usage. */
2076 #else /* Word 0 - Little Endian */
2077 uint32_t cmdtyp : 8; /**< [ 7: 0](WO) Specifies the type of command the software driver is requesting the core to
2078 perform. See USBDRD_UAHC_DGCMD_CMDTYPE_E for encodings and usage. */
2079 uint32_t cmdioc : 1; /**< [ 8: 8](WO) Command interrupt on complete.
2080 When this bit is set, the device controller issues a generic command
2081 completion event after executing the command. Note that this interrupt is
2082 mapped to USBDRD()_UAHC_DCFG[INTRNUM].
2083 Note: This field must not set to 1 if the USBDRD()_UAHC_DCTL[RS] field is 0. */
2084 uint32_t reserved_9 : 1;
2085 uint32_t cmdact : 1; /**< [ 10: 10](R/W1S/H) Command active.
2086 The software sets this bit to 1 to enable the device controller to execute the
2087 generic command.
2088 The device controller sets this bit to 0 after executing the command. */
2089 uint32_t reserved_11_14 : 4;
2090 uint32_t cmdstatus : 1; /**< [ 15: 15](RO) Command status.
2091 0 = Indicates command success.
2092 1 = CmdErr - Indicates that the device controller encountered an error
2093 while processing the command. */
2094 uint32_t reserved_16_31 : 16;
2095 #endif /* Word 0 - End */
2096 } s;
2097 /* struct bdk_usbdrdx_uahc_dgcmd_s cn; */
2098 };
2099 typedef union bdk_usbdrdx_uahc_dgcmd bdk_usbdrdx_uahc_dgcmd_t;
2100
2101 static inline uint64_t BDK_USBDRDX_UAHC_DGCMD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DGCMD(unsigned long a)2102 static inline uint64_t BDK_USBDRDX_UAHC_DGCMD(unsigned long a)
2103 {
2104 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2105 return 0x86800000c714ll + 0x1000000000ll * ((a) & 0x1);
2106 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
2107 return 0x86800000c714ll + 0x1000000000ll * ((a) & 0x1);
2108 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2109 return 0x86800000c714ll + 0x1000000000ll * ((a) & 0x1);
2110 __bdk_csr_fatal("USBDRDX_UAHC_DGCMD", 1, a, 0, 0, 0);
2111 }
2112
2113 #define typedef_BDK_USBDRDX_UAHC_DGCMD(a) bdk_usbdrdx_uahc_dgcmd_t
2114 #define bustype_BDK_USBDRDX_UAHC_DGCMD(a) BDK_CSR_TYPE_NCB32b
2115 #define basename_BDK_USBDRDX_UAHC_DGCMD(a) "USBDRDX_UAHC_DGCMD"
2116 #define device_bar_BDK_USBDRDX_UAHC_DGCMD(a) 0x0 /* PF_BAR0 */
2117 #define busnum_BDK_USBDRDX_UAHC_DGCMD(a) (a)
2118 #define arguments_BDK_USBDRDX_UAHC_DGCMD(a) (a),-1,-1,-1
2119
2120 /**
2121 * Register (NCB32b) usbdrd#_uahc_dgcmdpar
2122 *
2123 * USB Device Generic Command Parameter Register
2124 * This register indicates the device command parameter.
2125 * This must be programmed before or along with USBDRD()_UAHC_DGCMD.
2126 *
2127 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST] or
2128 * USBDRD()_UAHC_GCTL[CORESOFTRESET] or
2129 * USBDRD()_UAHC_USBCMD[HCRST] or USBDRD()_UAHC_USBCMD[LHCRST] or
2130 * USBDRD()_UAHC_DCTL[CSFTRST].
2131 *
2132 * Internal:
2133 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.5
2134 */
2135 union bdk_usbdrdx_uahc_dgcmdpar
2136 {
2137 uint32_t u;
2138 struct bdk_usbdrdx_uahc_dgcmdpar_s
2139 {
2140 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2141 uint32_t param : 32; /**< [ 31: 0](R/W) Device generic command parameter.
2142 Usage depends on which USBDRD()_UAHC_DGCMD[CMDTYPE] is used,
2143 see usage notes in USBDRD_UAHC_DGCMD_CMDTYPE_E descriptions. */
2144 #else /* Word 0 - Little Endian */
2145 uint32_t param : 32; /**< [ 31: 0](R/W) Device generic command parameter.
2146 Usage depends on which USBDRD()_UAHC_DGCMD[CMDTYPE] is used,
2147 see usage notes in USBDRD_UAHC_DGCMD_CMDTYPE_E descriptions. */
2148 #endif /* Word 0 - End */
2149 } s;
2150 /* struct bdk_usbdrdx_uahc_dgcmdpar_s cn; */
2151 };
2152 typedef union bdk_usbdrdx_uahc_dgcmdpar bdk_usbdrdx_uahc_dgcmdpar_t;
2153
2154 static inline uint64_t BDK_USBDRDX_UAHC_DGCMDPAR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DGCMDPAR(unsigned long a)2155 static inline uint64_t BDK_USBDRDX_UAHC_DGCMDPAR(unsigned long a)
2156 {
2157 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2158 return 0x86800000c710ll + 0x1000000000ll * ((a) & 0x1);
2159 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
2160 return 0x86800000c710ll + 0x1000000000ll * ((a) & 0x1);
2161 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2162 return 0x86800000c710ll + 0x1000000000ll * ((a) & 0x1);
2163 __bdk_csr_fatal("USBDRDX_UAHC_DGCMDPAR", 1, a, 0, 0, 0);
2164 }
2165
2166 #define typedef_BDK_USBDRDX_UAHC_DGCMDPAR(a) bdk_usbdrdx_uahc_dgcmdpar_t
2167 #define bustype_BDK_USBDRDX_UAHC_DGCMDPAR(a) BDK_CSR_TYPE_NCB32b
2168 #define basename_BDK_USBDRDX_UAHC_DGCMDPAR(a) "USBDRDX_UAHC_DGCMDPAR"
2169 #define device_bar_BDK_USBDRDX_UAHC_DGCMDPAR(a) 0x0 /* PF_BAR0 */
2170 #define busnum_BDK_USBDRDX_UAHC_DGCMDPAR(a) (a)
2171 #define arguments_BDK_USBDRDX_UAHC_DGCMDPAR(a) (a),-1,-1,-1
2172
2173 /**
2174 * Register (NCB32b) usbdrd#_uahc_dnctrl
2175 *
2176 * USB XHCI Device Notification Control Register
2177 * This register is used by software to enable or disable the reporting of the reception of
2178 * specific USB device
2179 * notification transaction packets.
2180 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.4.
2181 *
2182 * This register can be reset by NCB reset,
2183 * or USBDRD()_UCTL_CTL[UAHC_RST],
2184 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
2185 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
2186 */
2187 union bdk_usbdrdx_uahc_dnctrl
2188 {
2189 uint32_t u;
2190 struct bdk_usbdrdx_uahc_dnctrl_s
2191 {
2192 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2193 uint32_t reserved_16_31 : 16;
2194 uint32_t n : 16; /**< [ 15: 0](R/W) Notification enable. */
2195 #else /* Word 0 - Little Endian */
2196 uint32_t n : 16; /**< [ 15: 0](R/W) Notification enable. */
2197 uint32_t reserved_16_31 : 16;
2198 #endif /* Word 0 - End */
2199 } s;
2200 /* struct bdk_usbdrdx_uahc_dnctrl_s cn; */
2201 };
2202 typedef union bdk_usbdrdx_uahc_dnctrl bdk_usbdrdx_uahc_dnctrl_t;
2203
2204 static inline uint64_t BDK_USBDRDX_UAHC_DNCTRL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DNCTRL(unsigned long a)2205 static inline uint64_t BDK_USBDRDX_UAHC_DNCTRL(unsigned long a)
2206 {
2207 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2208 return 0x868000000034ll + 0x1000000000ll * ((a) & 0x1);
2209 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
2210 return 0x868000000034ll + 0x1000000000ll * ((a) & 0x1);
2211 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2212 return 0x868000000034ll + 0x1000000000ll * ((a) & 0x1);
2213 __bdk_csr_fatal("USBDRDX_UAHC_DNCTRL", 1, a, 0, 0, 0);
2214 }
2215
2216 #define typedef_BDK_USBDRDX_UAHC_DNCTRL(a) bdk_usbdrdx_uahc_dnctrl_t
2217 #define bustype_BDK_USBDRDX_UAHC_DNCTRL(a) BDK_CSR_TYPE_NCB32b
2218 #define basename_BDK_USBDRDX_UAHC_DNCTRL(a) "USBDRDX_UAHC_DNCTRL"
2219 #define device_bar_BDK_USBDRDX_UAHC_DNCTRL(a) 0x0 /* PF_BAR0 */
2220 #define busnum_BDK_USBDRDX_UAHC_DNCTRL(a) (a)
2221 #define arguments_BDK_USBDRDX_UAHC_DNCTRL(a) (a),-1,-1,-1
2222
2223 /**
2224 * Register (NCB32b) usbdrd#_uahc_dsts
2225 *
2226 * USB Device Status Register
2227 * This register indicates the status of the device controller with respect to USB-related
2228 * events.
2229 *
2230 * This register can be reset by IOI reset or USBDRD()_UCTL_CTL[UAHC_RST].
2231 *
2232 * Internal:
2233 * See Synopsys DWC_usb3 Databook v3.10a, section 6.3.4
2234 */
2235 union bdk_usbdrdx_uahc_dsts
2236 {
2237 uint32_t u;
2238 struct bdk_usbdrdx_uahc_dsts_s
2239 {
2240 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2241 uint32_t reserved_30_31 : 2;
2242 uint32_t dcnrd : 1; /**< [ 29: 29](RO/H) Device controller not ready.
2243 Will always read-as-zero.
2244
2245 Internal:
2246 Bit is only used with hibernation. */
2247 uint32_t sre : 1; /**< [ 28: 28](R/W1C/H) Save/restore error.
2248 This bit is currently not supported. */
2249 uint32_t reserved_26_27 : 2;
2250 uint32_t rss : 1; /**< [ 25: 25](RO) Restore state status.
2251 This bit is similar to the USBDRD()_UAHC_USBSTS[RSS] in host mode.
2252 When the controller has finished the restore process, it will complete the
2253 command by setting RSS to 0.
2254
2255 Will always read-as-zero.
2256
2257 Internal:
2258 Bit is only used with hibernation. */
2259 uint32_t sss : 1; /**< [ 24: 24](RO) Save state status.
2260 This bit is similar to the USBDRD()_UAHC_USBSTS[SSS] in host mode.
2261 When the controller has finished the save process, it will complete the
2262 command by setting SSS to 0.
2263
2264 Will always read-as-zero.
2265
2266 Internal:
2267 Bit is only used with hibernation. */
2268 uint32_t coreidle : 1; /**< [ 23: 23](RO/H) Core idle.
2269 The bit indicates that the core finished transferring all RxFIFO data to
2270 system memory, writing out all completed descriptors, and all event counts
2271 are zero.
2272
2273 Note: While testing for reset values, mask out the read value. This bit
2274 represents the changing state of the core and does not hold a static value. */
2275 uint32_t devctrlhlt : 1; /**< [ 22: 22](RO/H) Device controller halted.
2276 When 1, the core does not generate device events.
2277 - This bit is set to 0 when the USBDRD()_UAHC_DCTL[RS] register is set to 1.
2278 - The core sets this bit to 1 when, after software sets USBDRD()_UAHC_DCTL[RS] to 0,
2279 the core is
2280 idle and the lower layer finishes the disconnect process. */
2281 uint32_t usblnkst : 4; /**< [ 21: 18](RO/H) USB/link state.
2282 In SuperSpeed mode, uses LTSSM State:
2283 0x0 = U0.
2284 0x1 = U1.
2285 0x2 = U2.
2286 0x3 = U3.
2287 0x4 = SS_DIS.
2288 0x5 = RX_DET.
2289 0x6 = SS_INACT.
2290 0x7 = POLL.
2291 0x8 = RECOV.
2292 0x9 = HRESET.
2293 0xa = CMPLY.
2294 0xb = LPBK.
2295 0xf = Resume/Reset.
2296 others: Reserved.
2297
2298 In high-speed/full-speed/low-speed mode:
2299 0x0 = On state.
2300 0x2 = Sleep (L1) state.
2301 0x3 = Suspend (L2) state.
2302 0x4 = Disconnected state (Default state).
2303 0x5 = Early Suspend state.
2304 others: Reserved.
2305
2306 The link state resume/reset indicates that the core received a resume or USB
2307 reset request from the host while the link was in hibernation. Software must
2308 write 0x8 (recovery) to the USBDRD()_UAHC_DCTL[ULSTCHNGREQ] field to acknowledge
2309 the resume/reset request. */
2310 uint32_t rxfifoempty : 1; /**< [ 17: 17](RO/H) RxFIFO empty indication. */
2311 uint32_t soffn : 14; /**< [ 16: 3](RO/H) Frame/MicroFrame number of the received SOF.
2312
2313 When the core is operating at high-speed:
2314 \<16:6\> = Frame number.
2315 \<5:3\> = Microframe number.
2316
2317 When the core is operating at full-speed:
2318 \<16:14\> = Not used, software can ignore these three bits.
2319 \<13:3\> = Frame number. */
2320 uint32_t connectspd : 3; /**< [ 2: 0](RO/H) Connected speed.
2321 Indicates the speed at which the controller core has come up after speed
2322 detection through a chirp sequence.
2323 0x0 = High-speed (PHY clock is running at 60 MHz).
2324 0x1 = Full-speed (PHY clock is running at 60 MHz).
2325 0x2 = Low-speed (not supported).
2326 0x3 = Full-speed (PHY clock is running at 48 MHz).
2327 0x4 = SuperSpeed (PHY clock is running at 125 or 250 MHz). */
2328 #else /* Word 0 - Little Endian */
2329 uint32_t connectspd : 3; /**< [ 2: 0](RO/H) Connected speed.
2330 Indicates the speed at which the controller core has come up after speed
2331 detection through a chirp sequence.
2332 0x0 = High-speed (PHY clock is running at 60 MHz).
2333 0x1 = Full-speed (PHY clock is running at 60 MHz).
2334 0x2 = Low-speed (not supported).
2335 0x3 = Full-speed (PHY clock is running at 48 MHz).
2336 0x4 = SuperSpeed (PHY clock is running at 125 or 250 MHz). */
2337 uint32_t soffn : 14; /**< [ 16: 3](RO/H) Frame/MicroFrame number of the received SOF.
2338
2339 When the core is operating at high-speed:
2340 \<16:6\> = Frame number.
2341 \<5:3\> = Microframe number.
2342
2343 When the core is operating at full-speed:
2344 \<16:14\> = Not used, software can ignore these three bits.
2345 \<13:3\> = Frame number. */
2346 uint32_t rxfifoempty : 1; /**< [ 17: 17](RO/H) RxFIFO empty indication. */
2347 uint32_t usblnkst : 4; /**< [ 21: 18](RO/H) USB/link state.
2348 In SuperSpeed mode, uses LTSSM State:
2349 0x0 = U0.
2350 0x1 = U1.
2351 0x2 = U2.
2352 0x3 = U3.
2353 0x4 = SS_DIS.
2354 0x5 = RX_DET.
2355 0x6 = SS_INACT.
2356 0x7 = POLL.
2357 0x8 = RECOV.
2358 0x9 = HRESET.
2359 0xa = CMPLY.
2360 0xb = LPBK.
2361 0xf = Resume/Reset.
2362 others: Reserved.
2363
2364 In high-speed/full-speed/low-speed mode:
2365 0x0 = On state.
2366 0x2 = Sleep (L1) state.
2367 0x3 = Suspend (L2) state.
2368 0x4 = Disconnected state (Default state).
2369 0x5 = Early Suspend state.
2370 others: Reserved.
2371
2372 The link state resume/reset indicates that the core received a resume or USB
2373 reset request from the host while the link was in hibernation. Software must
2374 write 0x8 (recovery) to the USBDRD()_UAHC_DCTL[ULSTCHNGREQ] field to acknowledge
2375 the resume/reset request. */
2376 uint32_t devctrlhlt : 1; /**< [ 22: 22](RO/H) Device controller halted.
2377 When 1, the core does not generate device events.
2378 - This bit is set to 0 when the USBDRD()_UAHC_DCTL[RS] register is set to 1.
2379 - The core sets this bit to 1 when, after software sets USBDRD()_UAHC_DCTL[RS] to 0,
2380 the core is
2381 idle and the lower layer finishes the disconnect process. */
2382 uint32_t coreidle : 1; /**< [ 23: 23](RO/H) Core idle.
2383 The bit indicates that the core finished transferring all RxFIFO data to
2384 system memory, writing out all completed descriptors, and all event counts
2385 are zero.
2386
2387 Note: While testing for reset values, mask out the read value. This bit
2388 represents the changing state of the core and does not hold a static value. */
2389 uint32_t sss : 1; /**< [ 24: 24](RO) Save state status.
2390 This bit is similar to the USBDRD()_UAHC_USBSTS[SSS] in host mode.
2391 When the controller has finished the save process, it will complete the
2392 command by setting SSS to 0.
2393
2394 Will always read-as-zero.
2395
2396 Internal:
2397 Bit is only used with hibernation. */
2398 uint32_t rss : 1; /**< [ 25: 25](RO) Restore state status.
2399 This bit is similar to the USBDRD()_UAHC_USBSTS[RSS] in host mode.
2400 When the controller has finished the restore process, it will complete the
2401 command by setting RSS to 0.
2402
2403 Will always read-as-zero.
2404
2405 Internal:
2406 Bit is only used with hibernation. */
2407 uint32_t reserved_26_27 : 2;
2408 uint32_t sre : 1; /**< [ 28: 28](R/W1C/H) Save/restore error.
2409 This bit is currently not supported. */
2410 uint32_t dcnrd : 1; /**< [ 29: 29](RO/H) Device controller not ready.
2411 Will always read-as-zero.
2412
2413 Internal:
2414 Bit is only used with hibernation. */
2415 uint32_t reserved_30_31 : 2;
2416 #endif /* Word 0 - End */
2417 } s;
2418 /* struct bdk_usbdrdx_uahc_dsts_s cn; */
2419 };
2420 typedef union bdk_usbdrdx_uahc_dsts bdk_usbdrdx_uahc_dsts_t;
2421
2422 static inline uint64_t BDK_USBDRDX_UAHC_DSTS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_DSTS(unsigned long a)2423 static inline uint64_t BDK_USBDRDX_UAHC_DSTS(unsigned long a)
2424 {
2425 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2426 return 0x86800000c70cll + 0x1000000000ll * ((a) & 0x1);
2427 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
2428 return 0x86800000c70cll + 0x1000000000ll * ((a) & 0x1);
2429 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2430 return 0x86800000c70cll + 0x1000000000ll * ((a) & 0x1);
2431 __bdk_csr_fatal("USBDRDX_UAHC_DSTS", 1, a, 0, 0, 0);
2432 }
2433
2434 #define typedef_BDK_USBDRDX_UAHC_DSTS(a) bdk_usbdrdx_uahc_dsts_t
2435 #define bustype_BDK_USBDRDX_UAHC_DSTS(a) BDK_CSR_TYPE_NCB32b
2436 #define basename_BDK_USBDRDX_UAHC_DSTS(a) "USBDRDX_UAHC_DSTS"
2437 #define device_bar_BDK_USBDRDX_UAHC_DSTS(a) 0x0 /* PF_BAR0 */
2438 #define busnum_BDK_USBDRDX_UAHC_DSTS(a) (a)
2439 #define arguments_BDK_USBDRDX_UAHC_DSTS(a) (a),-1,-1,-1
2440
2441 /**
2442 * Register (NCB) usbdrd#_uahc_erdp#
2443 *
2444 * USB XHCI Event Ring Dequeue Pointer Register
2445 * For information on this register, refer to the xHCI Specification, v1.1, section 5.5.2.3.3.
2446 *
2447 * This register can be reset by NCB reset,
2448 * or USBDRD()_UCTL_CTL[UAHC_RST],
2449 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
2450 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
2451 */
2452 union bdk_usbdrdx_uahc_erdpx
2453 {
2454 uint64_t u;
2455 struct bdk_usbdrdx_uahc_erdpx_s
2456 {
2457 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2458 uint64_t erdp : 60; /**< [ 63: 4](R/W) Event ring dequeue pointer bits \<63:4\>. */
2459 uint64_t ehb : 1; /**< [ 3: 3](R/W1C/H) Event handler busy */
2460 uint64_t desi : 3; /**< [ 2: 0](R/W) Dequeue ERST segment index. */
2461 #else /* Word 0 - Little Endian */
2462 uint64_t desi : 3; /**< [ 2: 0](R/W) Dequeue ERST segment index. */
2463 uint64_t ehb : 1; /**< [ 3: 3](R/W1C/H) Event handler busy */
2464 uint64_t erdp : 60; /**< [ 63: 4](R/W) Event ring dequeue pointer bits \<63:4\>. */
2465 #endif /* Word 0 - End */
2466 } s;
2467 /* struct bdk_usbdrdx_uahc_erdpx_s cn; */
2468 };
2469 typedef union bdk_usbdrdx_uahc_erdpx bdk_usbdrdx_uahc_erdpx_t;
2470
2471 static inline uint64_t BDK_USBDRDX_UAHC_ERDPX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_ERDPX(unsigned long a,unsigned long b)2472 static inline uint64_t BDK_USBDRDX_UAHC_ERDPX(unsigned long a, unsigned long b)
2473 {
2474 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
2475 return 0x868000000478ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2476 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
2477 return 0x868000000478ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2478 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
2479 return 0x868000000478ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2480 __bdk_csr_fatal("USBDRDX_UAHC_ERDPX", 2, a, b, 0, 0);
2481 }
2482
2483 #define typedef_BDK_USBDRDX_UAHC_ERDPX(a,b) bdk_usbdrdx_uahc_erdpx_t
2484 #define bustype_BDK_USBDRDX_UAHC_ERDPX(a,b) BDK_CSR_TYPE_NCB
2485 #define basename_BDK_USBDRDX_UAHC_ERDPX(a,b) "USBDRDX_UAHC_ERDPX"
2486 #define device_bar_BDK_USBDRDX_UAHC_ERDPX(a,b) 0x0 /* PF_BAR0 */
2487 #define busnum_BDK_USBDRDX_UAHC_ERDPX(a,b) (a)
2488 #define arguments_BDK_USBDRDX_UAHC_ERDPX(a,b) (a),(b),-1,-1
2489
2490 /**
2491 * Register (NCB) usbdrd#_uahc_erstba#
2492 *
2493 * USB XHCI Event-Ring Segment-Table Base-Address Register
2494 * For information on this register, refer to the xHCI Specification, v1.1, section 5.5.2.3.2.
2495 *
2496 * This register can be reset by NCB reset,
2497 * or USBDRD()_UCTL_CTL[UAHC_RST],
2498 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
2499 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
2500 */
2501 union bdk_usbdrdx_uahc_erstbax
2502 {
2503 uint64_t u;
2504 struct bdk_usbdrdx_uahc_erstbax_s
2505 {
2506 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2507 uint64_t erstba : 58; /**< [ 63: 6](R/W) Event-ring segment-table base-address bits\<63:6\>. */
2508 uint64_t reserved_0_5 : 6;
2509 #else /* Word 0 - Little Endian */
2510 uint64_t reserved_0_5 : 6;
2511 uint64_t erstba : 58; /**< [ 63: 6](R/W) Event-ring segment-table base-address bits\<63:6\>. */
2512 #endif /* Word 0 - End */
2513 } s;
2514 /* struct bdk_usbdrdx_uahc_erstbax_s cn; */
2515 };
2516 typedef union bdk_usbdrdx_uahc_erstbax bdk_usbdrdx_uahc_erstbax_t;
2517
2518 static inline uint64_t BDK_USBDRDX_UAHC_ERSTBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_ERSTBAX(unsigned long a,unsigned long b)2519 static inline uint64_t BDK_USBDRDX_UAHC_ERSTBAX(unsigned long a, unsigned long b)
2520 {
2521 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
2522 return 0x868000000470ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2523 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
2524 return 0x868000000470ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2525 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
2526 return 0x868000000470ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2527 __bdk_csr_fatal("USBDRDX_UAHC_ERSTBAX", 2, a, b, 0, 0);
2528 }
2529
2530 #define typedef_BDK_USBDRDX_UAHC_ERSTBAX(a,b) bdk_usbdrdx_uahc_erstbax_t
2531 #define bustype_BDK_USBDRDX_UAHC_ERSTBAX(a,b) BDK_CSR_TYPE_NCB
2532 #define basename_BDK_USBDRDX_UAHC_ERSTBAX(a,b) "USBDRDX_UAHC_ERSTBAX"
2533 #define device_bar_BDK_USBDRDX_UAHC_ERSTBAX(a,b) 0x0 /* PF_BAR0 */
2534 #define busnum_BDK_USBDRDX_UAHC_ERSTBAX(a,b) (a)
2535 #define arguments_BDK_USBDRDX_UAHC_ERSTBAX(a,b) (a),(b),-1,-1
2536
2537 /**
2538 * Register (NCB32b) usbdrd#_uahc_erstsz#
2539 *
2540 * USB XHCI Event-Ring Segment-Table Size Register
2541 * For information on this register, refer to the xHCI Specification, v1.1, section 5.5.2.3.1.
2542 *
2543 * This register can be reset by NCB reset,
2544 * or USBDRD()_UCTL_CTL[UAHC_RST],
2545 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
2546 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
2547 */
2548 union bdk_usbdrdx_uahc_erstszx
2549 {
2550 uint32_t u;
2551 struct bdk_usbdrdx_uahc_erstszx_s
2552 {
2553 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2554 uint32_t reserved_16_31 : 16;
2555 uint32_t erstsz : 16; /**< [ 15: 0](R/W) Event-ring segment-table size. */
2556 #else /* Word 0 - Little Endian */
2557 uint32_t erstsz : 16; /**< [ 15: 0](R/W) Event-ring segment-table size. */
2558 uint32_t reserved_16_31 : 16;
2559 #endif /* Word 0 - End */
2560 } s;
2561 /* struct bdk_usbdrdx_uahc_erstszx_s cn; */
2562 };
2563 typedef union bdk_usbdrdx_uahc_erstszx bdk_usbdrdx_uahc_erstszx_t;
2564
2565 static inline uint64_t BDK_USBDRDX_UAHC_ERSTSZX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_ERSTSZX(unsigned long a,unsigned long b)2566 static inline uint64_t BDK_USBDRDX_UAHC_ERSTSZX(unsigned long a, unsigned long b)
2567 {
2568 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
2569 return 0x868000000468ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2570 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
2571 return 0x868000000468ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2572 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
2573 return 0x868000000468ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
2574 __bdk_csr_fatal("USBDRDX_UAHC_ERSTSZX", 2, a, b, 0, 0);
2575 }
2576
2577 #define typedef_BDK_USBDRDX_UAHC_ERSTSZX(a,b) bdk_usbdrdx_uahc_erstszx_t
2578 #define bustype_BDK_USBDRDX_UAHC_ERSTSZX(a,b) BDK_CSR_TYPE_NCB32b
2579 #define basename_BDK_USBDRDX_UAHC_ERSTSZX(a,b) "USBDRDX_UAHC_ERSTSZX"
2580 #define device_bar_BDK_USBDRDX_UAHC_ERSTSZX(a,b) 0x0 /* PF_BAR0 */
2581 #define busnum_BDK_USBDRDX_UAHC_ERSTSZX(a,b) (a)
2582 #define arguments_BDK_USBDRDX_UAHC_ERSTSZX(a,b) (a),(b),-1,-1
2583
2584 /**
2585 * Register (NCB) usbdrd#_uahc_gbuserraddr
2586 *
2587 * USB UAHC Bus-Error-Address Register
2588 * When the AXI master bus returns error response, the SoC bus error is generated. In the host
2589 * mode, the host_system_err port indicates this condition. In addition, it is also indicated in
2590 * USBDRD()_UAHC_USBSTS[HSE]. Due to the nature of AXI, it is possible that multiple AXI
2591 * transactions
2592 * are active at a time. The host controller does not keep track of the start address of all
2593 * outstanding transactions. Instead, it keeps track of the start address of the DMA transfer
2594 * associated with all active transactions. It is this address that is reported in
2595 * USBDRD()_UAHC_GBUSERRADDR when a bus error occurs. For example, if the host controller
2596 * initiates
2597 * a DMA
2598 * transfer to write 1k of packet data starting at buffer address 0xABCD0000, and this DMA is
2599 * broken up into multiple 256B bursts on the AXI, then if a bus error occurs on any of these
2600 * associated AXI transfers, USBDRD()_UAHC_GBUSERRADDR reflects the DMA start address of
2601 * 0xABCD0000
2602 * regardless of which AXI transaction received the error.
2603 *
2604 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
2605 *
2606 * Internal:
2607 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.13.
2608 */
2609 union bdk_usbdrdx_uahc_gbuserraddr
2610 {
2611 uint64_t u;
2612 struct bdk_usbdrdx_uahc_gbuserraddr_s
2613 {
2614 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2615 uint64_t busaddr : 64; /**< [ 63: 0](RO/H) Bus address. Contains the first bus address that encountered an SoC bus error. It is valid
2616 when the USBDRD()_UAHC_GSTS[BUSERRADDRVLD] = 1. It can only be cleared by resetting the
2617 core. */
2618 #else /* Word 0 - Little Endian */
2619 uint64_t busaddr : 64; /**< [ 63: 0](RO/H) Bus address. Contains the first bus address that encountered an SoC bus error. It is valid
2620 when the USBDRD()_UAHC_GSTS[BUSERRADDRVLD] = 1. It can only be cleared by resetting the
2621 core. */
2622 #endif /* Word 0 - End */
2623 } s;
2624 /* struct bdk_usbdrdx_uahc_gbuserraddr_s cn; */
2625 };
2626 typedef union bdk_usbdrdx_uahc_gbuserraddr bdk_usbdrdx_uahc_gbuserraddr_t;
2627
2628 static inline uint64_t BDK_USBDRDX_UAHC_GBUSERRADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GBUSERRADDR(unsigned long a)2629 static inline uint64_t BDK_USBDRDX_UAHC_GBUSERRADDR(unsigned long a)
2630 {
2631 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
2632 return 0x86800000c130ll + 0x1000000000ll * ((a) & 0x1);
2633 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
2634 return 0x86800000c130ll + 0x1000000000ll * ((a) & 0x1);
2635 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
2636 return 0x86800000c130ll + 0x1000000000ll * ((a) & 0x1);
2637 __bdk_csr_fatal("USBDRDX_UAHC_GBUSERRADDR", 1, a, 0, 0, 0);
2638 }
2639
2640 #define typedef_BDK_USBDRDX_UAHC_GBUSERRADDR(a) bdk_usbdrdx_uahc_gbuserraddr_t
2641 #define bustype_BDK_USBDRDX_UAHC_GBUSERRADDR(a) BDK_CSR_TYPE_NCB
2642 #define basename_BDK_USBDRDX_UAHC_GBUSERRADDR(a) "USBDRDX_UAHC_GBUSERRADDR"
2643 #define device_bar_BDK_USBDRDX_UAHC_GBUSERRADDR(a) 0x0 /* PF_BAR0 */
2644 #define busnum_BDK_USBDRDX_UAHC_GBUSERRADDR(a) (a)
2645 #define arguments_BDK_USBDRDX_UAHC_GBUSERRADDR(a) (a),-1,-1,-1
2646
2647 /**
2648 * Register (NCB32b) usbdrd#_uahc_gctl
2649 *
2650 * USB UAHC Control Register
2651 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
2652 * Internal:
2653 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.5.
2654 */
2655 union bdk_usbdrdx_uahc_gctl
2656 {
2657 uint32_t u;
2658 struct bdk_usbdrdx_uahc_gctl_s
2659 {
2660 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2661 uint32_t pwrdnscale : 13; /**< [ 31: 19](R/W) Power down scale. The USB3 suspend-clock input replaces pipe3_rx_pclk as a clock source to
2662 a small part of the USB3 core that operates when the SuperSpeed PHY is in its lowest power
2663 (P3) state, and therefore does not provide a clock. This field specifies how many suspend-
2664 clock periods fit into a 16 kHz clock period. When performing the division, round up the
2665 remainder.
2666
2667 For example, when using an 32-bit PHY and 25-MHz suspend clock, PWRDNSCALE = 25000 kHz/16
2668 kHz = 1563 (rounded up).
2669
2670 The minimum suspend-clock frequency is 32 KHz, and maximum suspend-clock frequency is 125
2671 MHz.
2672
2673 The LTSSM uses suspend clock for 12-ms and 100-ms timers during suspend mode. According to
2674 the USB 3.0 specification, the accuracy on these timers is 0% to +50%. 12 ms + 0~+50%
2675 accuracy = 18 ms (Range is 12 ms - 18 ms)
2676 100 ms + 0~+50% accuracy = 150 ms (Range is 100 ms - 150 ms).
2677
2678 The suspend clock accuracy requirement is:
2679 _ (12,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period should be between 12,000 and
2680 18,000
2681 _ (100,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period should be between 100,000 and
2682 150,000
2683
2684 For example, if your suspend_clk frequency varies from 7.5 MHz to 10.5 MHz, then the value
2685 needs to programmed is: power down scale = 10500/16 = 657 (rounded up; and fastest
2686 frequency used). */
2687 uint32_t masterfiltbypass : 1; /**< [ 18: 18](R/W) Master filter bypass. Not relevant for Cavium's configuration. */
2688 uint32_t bypssetaddr : 1; /**< [ 17: 17](R/W) Bypass SetAddress in device mode.
2689 Always set to 0.
2690
2691 Internal:
2692 When set, core uses the value in USBDRD()_UAHC_DCFG[DEVADDR] directly
2693 for comparing the device address tokens. In simulation, this can be used to avoid
2694 sending a SET_ADDRESS command. */
2695 uint32_t u2rstecn : 1; /**< [ 16: 16](R/W) If the SuperSpeed connection fails during POLL or LMP exchange, the device connects
2696 at non-SuperSpeed mode. If this bit is set, then the device attempts three more times to
2697 connect at SuperSpeed, even if it previously failed to operate in SuperSpeed mode.
2698 This bit is only applicable in device mode. */
2699 uint32_t frmscldwn : 2; /**< [ 15: 14](R/W) Frame scale down. Scales down device view of a SOF/USOF/ITP duration.
2700 For SuperSpeed/high-speed mode:
2701 0x0 = Interval is 125 us.
2702 0x1 = Interval is 62.5 us.
2703 0x2 = Interval is 31.25 us.
2704 0x3 = Interval is 15.625 us.
2705
2706 For full speed mode, the scale down value is multiplied by 8. */
2707 uint32_t prtcapdir : 2; /**< [ 13: 12](R/W) 0x1 = for Host configurations.
2708 0x2 = for Device configurations. */
2709 uint32_t coresoftreset : 1; /**< [ 11: 11](R/W) Core soft reset: 1 = soft reset to core, 0 = no soft reset.
2710 Clears the interrupts and all the USBDRD()_UAHC_* CSRs except the
2711 following registers: USBDRD()_UAHC_GCTL, USBDRD()_UAHC_GUCTL, USBDRD()_UAHC_GSTS,
2712 USBDRD()_UAHC_GRLSID, USBDRD()_UAHC_GGPIO, USBDRD()_UAHC_GUID,
2713 USBDRD()_UAHC_GUSB2PHYCFG(),
2714 USBDRD()_UAHC_GUSB3PIPECTL().
2715
2716 When you reset PHYs (using USBDRD()_UAHC_GUSB2PHYCFG() or
2717 USBDRD()_UAHC_GUSB3PIPECTL()), you must keep the core in reset state until PHY
2718 clocks are stable. This controls the bus, RAM, and MAC domain resets.
2719
2720 Internal:
2721 Refer to Reset Generation on Synopsys Databook page 250.
2722 Under soft reset, accesses to USBDRD()_UAHC_* CSRs other than USBDRD()_UAHC_GCTL may fail
2723 (timeout).
2724 This bit is for debug purposes only. Use USBDRD()_UAHC_USBCMD[HCRST] for soft reset. */
2725 uint32_t sofitpsync : 1; /**< [ 10: 10](R/W) Synchronize ITP to reference clock. In host mode, if this bit is set to:
2726 0 = The core keeps the UTMI/ULPI PHY on the first port in non-suspended state whenever
2727 there is a SuperSpeed port that is not in Rx.Detect, SS.Disable, and U3 state.
2728 1 = The core keeps the UTMI/ULPI PHY on the first port in non-suspended state whenever the
2729 other non-SuperSpeed ports are not in suspended state.
2730
2731 This feature is useful because it saves power by suspending UTMI/ULPI when SuperSpeed only
2732 is active and it helps resolve when the PHY does not transmit a host resume unless it is
2733 placed in suspend state.
2734 USBDRD()_UAHC_GUSB2PHYCFG()[SUSPHY] eventually decides to put the UTMI/ULPI PHY in to
2735 suspend
2736 state. In addition, when this bit is set to 1, the core generates ITP off of the REF_CLK-
2737 based counter. Otherwise, ITP and SOF are generated off of UTMI/ULPI_CLK[0] based counter.
2738
2739 To program the reference clock period inside the core, refer to
2740 USBDRD()_UAHC_GUCTL[REFCLKPER].
2741
2742 If you do not plan to ever use this feature or the
2743 USBDRD()_UAHC_GFLADJ[GFLADJ_REFCLK_LPM_SEL]
2744 feature, the minimum frequency for the ref_clk can be as low as 32 KHz. You can connect
2745 the
2746 SUSPEND_CLK (as low as 32 KHz) to REF_CLK.
2747
2748 If you plan to enable hardware-based LPM (PORTPMSC[HLE] = 1), this feature cannot be used.
2749 Turn off this feature by setting this bit to zero and use the
2750 USBDRD()_UAHC_GFLADJ[GFLADJ_REFCLK_LPM_SEL] feature.
2751
2752 If you set this bit to 1, the USBDRD()_UAHC_GUSB2PHYCFG()[U2_FREECLK_EXISTS] bit
2753 must be set to 0. */
2754 uint32_t u1u2timerscale : 1; /**< [ 9: 9](R/W) Disable U1/U2 timer scaledown. If set to 1, along with SCALEDOWN = 0x1, disables the scale
2755 down of U1/U2 inactive timer values.
2756 This is for simulation mode only. */
2757 uint32_t debugattach : 1; /**< [ 8: 8](R/W) Debug attach. When this bit is set:
2758 * SuperSpeed link proceeds directly to the polling-link state (USBDRD()_UAHC_DCTL[RS] = 1)
2759 without checking remote termination.
2760 * Link LFPS polling timeout is infinite.
2761 * Polling timeout during TS1 is infinite (in case link is waiting for TXEQ to finish). */
2762 uint32_t ramclksel : 2; /**< [ 7: 6](R/W) RAM clock select. Always keep set to 0x0. */
2763 uint32_t scaledown : 2; /**< [ 5: 4](R/W) Scale-down mode. When scale-down mode is enabled for simulation, the core uses scaled-down
2764 timing values, resulting in faster simulations. When scale-down mode is disabled, actual
2765 timing values are used. This is required for hardware operation.
2766
2767 High-speed/full-speed/low-speed modes:
2768 0x0 = Disables all scale-downs. Actual timing values are used.
2769 0x1 = Enables scale-down of all timing values. These include:
2770 * Speed enumeration.
2771 * HNP/SRP.
2772 * Suspend and resume.
2773
2774 0x2 = N/A
2775 0x3 = Enables bits \<0\> and \<1\> scale-down timing values.
2776
2777 SuperSpeed mode:
2778 0x0 = Disables all scale-downs. Actual timing values are used.
2779 0x1 = Enables scaled down SuperSpeed timing and repeat values including:
2780 * Number of TxEq training sequences reduce to eight.
2781 * LFPS polling burst time reduce to 100 ns.
2782 * LFPS warm reset receive reduce to 30 us.
2783
2784 Internal:
2785 Refer to the rtl_vip_scaledown_mapping.xls file under \<workspace\>/sim/SoC_sim
2786 directory for the complete list.
2787 0x2 = No TxEq training sequences are sent. Overrides bit\<4\>.
2788 0x3 = Enables bits\<0\> and \<1\> scale-down timing values. */
2789 uint32_t disscramble : 1; /**< [ 3: 3](R/W) Disable scrambling. Transmit request to link partner on next transition to recovery or polling. */
2790 uint32_t u2exit_lfps : 1; /**< [ 2: 2](R/W) LFPS U2 exit.
2791 0 = The link treats 248 ns LFPS as a valid U2 exit.
2792 1 = The link waits for 8 us of LFPS before it detects a valid U2 exit.
2793
2794 This bit is added to improve interoperability with a third party host controller. This
2795 host controller in U2 state while performing receiver detection generates an LFPS glitch
2796 of about 4s duration. This causes the device to exit from U2 state because the LFPS filter
2797 value is 248 ns. With the new functionality enabled, the device can stay in U2 while
2798 ignoring this glitch from the host controller. */
2799 uint32_t gblhibernationen : 1; /**< [ 1: 1](RO) This bit enables hibernation at the global level. */
2800 uint32_t dsblclkgtng : 1; /**< [ 0: 0](R/W) Disable clock gating. When set to 1 and the core is in low power mode, internal clock
2801 gating is disabled, which means the clocks are always running. This bit can be set to 1
2802 after power-up reset. */
2803 #else /* Word 0 - Little Endian */
2804 uint32_t dsblclkgtng : 1; /**< [ 0: 0](R/W) Disable clock gating. When set to 1 and the core is in low power mode, internal clock
2805 gating is disabled, which means the clocks are always running. This bit can be set to 1
2806 after power-up reset. */
2807 uint32_t gblhibernationen : 1; /**< [ 1: 1](RO) This bit enables hibernation at the global level. */
2808 uint32_t u2exit_lfps : 1; /**< [ 2: 2](R/W) LFPS U2 exit.
2809 0 = The link treats 248 ns LFPS as a valid U2 exit.
2810 1 = The link waits for 8 us of LFPS before it detects a valid U2 exit.
2811
2812 This bit is added to improve interoperability with a third party host controller. This
2813 host controller in U2 state while performing receiver detection generates an LFPS glitch
2814 of about 4s duration. This causes the device to exit from U2 state because the LFPS filter
2815 value is 248 ns. With the new functionality enabled, the device can stay in U2 while
2816 ignoring this glitch from the host controller. */
2817 uint32_t disscramble : 1; /**< [ 3: 3](R/W) Disable scrambling. Transmit request to link partner on next transition to recovery or polling. */
2818 uint32_t scaledown : 2; /**< [ 5: 4](R/W) Scale-down mode. When scale-down mode is enabled for simulation, the core uses scaled-down
2819 timing values, resulting in faster simulations. When scale-down mode is disabled, actual
2820 timing values are used. This is required for hardware operation.
2821
2822 High-speed/full-speed/low-speed modes:
2823 0x0 = Disables all scale-downs. Actual timing values are used.
2824 0x1 = Enables scale-down of all timing values. These include:
2825 * Speed enumeration.
2826 * HNP/SRP.
2827 * Suspend and resume.
2828
2829 0x2 = N/A
2830 0x3 = Enables bits \<0\> and \<1\> scale-down timing values.
2831
2832 SuperSpeed mode:
2833 0x0 = Disables all scale-downs. Actual timing values are used.
2834 0x1 = Enables scaled down SuperSpeed timing and repeat values including:
2835 * Number of TxEq training sequences reduce to eight.
2836 * LFPS polling burst time reduce to 100 ns.
2837 * LFPS warm reset receive reduce to 30 us.
2838
2839 Internal:
2840 Refer to the rtl_vip_scaledown_mapping.xls file under \<workspace\>/sim/SoC_sim
2841 directory for the complete list.
2842 0x2 = No TxEq training sequences are sent. Overrides bit\<4\>.
2843 0x3 = Enables bits\<0\> and \<1\> scale-down timing values. */
2844 uint32_t ramclksel : 2; /**< [ 7: 6](R/W) RAM clock select. Always keep set to 0x0. */
2845 uint32_t debugattach : 1; /**< [ 8: 8](R/W) Debug attach. When this bit is set:
2846 * SuperSpeed link proceeds directly to the polling-link state (USBDRD()_UAHC_DCTL[RS] = 1)
2847 without checking remote termination.
2848 * Link LFPS polling timeout is infinite.
2849 * Polling timeout during TS1 is infinite (in case link is waiting for TXEQ to finish). */
2850 uint32_t u1u2timerscale : 1; /**< [ 9: 9](R/W) Disable U1/U2 timer scaledown. If set to 1, along with SCALEDOWN = 0x1, disables the scale
2851 down of U1/U2 inactive timer values.
2852 This is for simulation mode only. */
2853 uint32_t sofitpsync : 1; /**< [ 10: 10](R/W) Synchronize ITP to reference clock. In host mode, if this bit is set to:
2854 0 = The core keeps the UTMI/ULPI PHY on the first port in non-suspended state whenever
2855 there is a SuperSpeed port that is not in Rx.Detect, SS.Disable, and U3 state.
2856 1 = The core keeps the UTMI/ULPI PHY on the first port in non-suspended state whenever the
2857 other non-SuperSpeed ports are not in suspended state.
2858
2859 This feature is useful because it saves power by suspending UTMI/ULPI when SuperSpeed only
2860 is active and it helps resolve when the PHY does not transmit a host resume unless it is
2861 placed in suspend state.
2862 USBDRD()_UAHC_GUSB2PHYCFG()[SUSPHY] eventually decides to put the UTMI/ULPI PHY in to
2863 suspend
2864 state. In addition, when this bit is set to 1, the core generates ITP off of the REF_CLK-
2865 based counter. Otherwise, ITP and SOF are generated off of UTMI/ULPI_CLK[0] based counter.
2866
2867 To program the reference clock period inside the core, refer to
2868 USBDRD()_UAHC_GUCTL[REFCLKPER].
2869
2870 If you do not plan to ever use this feature or the
2871 USBDRD()_UAHC_GFLADJ[GFLADJ_REFCLK_LPM_SEL]
2872 feature, the minimum frequency for the ref_clk can be as low as 32 KHz. You can connect
2873 the
2874 SUSPEND_CLK (as low as 32 KHz) to REF_CLK.
2875
2876 If you plan to enable hardware-based LPM (PORTPMSC[HLE] = 1), this feature cannot be used.
2877 Turn off this feature by setting this bit to zero and use the
2878 USBDRD()_UAHC_GFLADJ[GFLADJ_REFCLK_LPM_SEL] feature.
2879
2880 If you set this bit to 1, the USBDRD()_UAHC_GUSB2PHYCFG()[U2_FREECLK_EXISTS] bit
2881 must be set to 0. */
2882 uint32_t coresoftreset : 1; /**< [ 11: 11](R/W) Core soft reset: 1 = soft reset to core, 0 = no soft reset.
2883 Clears the interrupts and all the USBDRD()_UAHC_* CSRs except the
2884 following registers: USBDRD()_UAHC_GCTL, USBDRD()_UAHC_GUCTL, USBDRD()_UAHC_GSTS,
2885 USBDRD()_UAHC_GRLSID, USBDRD()_UAHC_GGPIO, USBDRD()_UAHC_GUID,
2886 USBDRD()_UAHC_GUSB2PHYCFG(),
2887 USBDRD()_UAHC_GUSB3PIPECTL().
2888
2889 When you reset PHYs (using USBDRD()_UAHC_GUSB2PHYCFG() or
2890 USBDRD()_UAHC_GUSB3PIPECTL()), you must keep the core in reset state until PHY
2891 clocks are stable. This controls the bus, RAM, and MAC domain resets.
2892
2893 Internal:
2894 Refer to Reset Generation on Synopsys Databook page 250.
2895 Under soft reset, accesses to USBDRD()_UAHC_* CSRs other than USBDRD()_UAHC_GCTL may fail
2896 (timeout).
2897 This bit is for debug purposes only. Use USBDRD()_UAHC_USBCMD[HCRST] for soft reset. */
2898 uint32_t prtcapdir : 2; /**< [ 13: 12](R/W) 0x1 = for Host configurations.
2899 0x2 = for Device configurations. */
2900 uint32_t frmscldwn : 2; /**< [ 15: 14](R/W) Frame scale down. Scales down device view of a SOF/USOF/ITP duration.
2901 For SuperSpeed/high-speed mode:
2902 0x0 = Interval is 125 us.
2903 0x1 = Interval is 62.5 us.
2904 0x2 = Interval is 31.25 us.
2905 0x3 = Interval is 15.625 us.
2906
2907 For full speed mode, the scale down value is multiplied by 8. */
2908 uint32_t u2rstecn : 1; /**< [ 16: 16](R/W) If the SuperSpeed connection fails during POLL or LMP exchange, the device connects
2909 at non-SuperSpeed mode. If this bit is set, then the device attempts three more times to
2910 connect at SuperSpeed, even if it previously failed to operate in SuperSpeed mode.
2911 This bit is only applicable in device mode. */
2912 uint32_t bypssetaddr : 1; /**< [ 17: 17](R/W) Bypass SetAddress in device mode.
2913 Always set to 0.
2914
2915 Internal:
2916 When set, core uses the value in USBDRD()_UAHC_DCFG[DEVADDR] directly
2917 for comparing the device address tokens. In simulation, this can be used to avoid
2918 sending a SET_ADDRESS command. */
2919 uint32_t masterfiltbypass : 1; /**< [ 18: 18](R/W) Master filter bypass. Not relevant for Cavium's configuration. */
2920 uint32_t pwrdnscale : 13; /**< [ 31: 19](R/W) Power down scale. The USB3 suspend-clock input replaces pipe3_rx_pclk as a clock source to
2921 a small part of the USB3 core that operates when the SuperSpeed PHY is in its lowest power
2922 (P3) state, and therefore does not provide a clock. This field specifies how many suspend-
2923 clock periods fit into a 16 kHz clock period. When performing the division, round up the
2924 remainder.
2925
2926 For example, when using an 32-bit PHY and 25-MHz suspend clock, PWRDNSCALE = 25000 kHz/16
2927 kHz = 1563 (rounded up).
2928
2929 The minimum suspend-clock frequency is 32 KHz, and maximum suspend-clock frequency is 125
2930 MHz.
2931
2932 The LTSSM uses suspend clock for 12-ms and 100-ms timers during suspend mode. According to
2933 the USB 3.0 specification, the accuracy on these timers is 0% to +50%. 12 ms + 0~+50%
2934 accuracy = 18 ms (Range is 12 ms - 18 ms)
2935 100 ms + 0~+50% accuracy = 150 ms (Range is 100 ms - 150 ms).
2936
2937 The suspend clock accuracy requirement is:
2938 _ (12,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period should be between 12,000 and
2939 18,000
2940 _ (100,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period should be between 100,000 and
2941 150,000
2942
2943 For example, if your suspend_clk frequency varies from 7.5 MHz to 10.5 MHz, then the value
2944 needs to programmed is: power down scale = 10500/16 = 657 (rounded up; and fastest
2945 frequency used). */
2946 #endif /* Word 0 - End */
2947 } s;
2948 struct bdk_usbdrdx_uahc_gctl_cn8
2949 {
2950 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2951 uint32_t pwrdnscale : 13; /**< [ 31: 19](R/W) Power down scale. The USB3 suspend-clock input replaces pipe3_rx_pclk as a clock source to
2952 a small part of the USB3 core that operates when the SuperSpeed PHY is in its lowest power
2953 (P3) state, and therefore does not provide a clock. This field specifies how many suspend-
2954 clock periods fit into a 16 kHz clock period. When performing the division, round up the
2955 remainder.
2956
2957 For example, when using an 32-bit PHY and 25-MHz suspend clock, PWRDNSCALE = 25000 kHz/16
2958 kHz = 1563 (rounded up).
2959
2960 The minimum suspend-clock frequency is 32 KHz, and maximum suspend-clock frequency is 125
2961 MHz.
2962
2963 The LTSSM uses suspend clock for 12-ms and 100-ms timers during suspend mode. According to
2964 the USB 3.0 specification, the accuracy on these timers is 0% to +50%. 12 ms + 0~+50%
2965 accuracy = 18 ms (Range is 12 ms - 18 ms)
2966 100 ms + 0~+50% accuracy = 150 ms (Range is 100 ms - 150 ms).
2967
2968 The suspend clock accuracy requirement is:
2969 _ (12,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period should be between 12,000 and
2970 18,000
2971 _ (100,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period should be between 100,000 and
2972 150,000
2973
2974 For example, if your suspend_clk frequency varies from 7.5 MHz to 10.5 MHz, then the value
2975 needs to programmed is: power down scale = 10500/16 = 657 (rounded up; and fastest
2976 frequency used). */
2977 uint32_t masterfiltbypass : 1; /**< [ 18: 18](R/W) Master filter bypass. Not relevant for Cavium's configuration. */
2978 uint32_t bypssetaddr : 1; /**< [ 17: 17](R/W) Bypass SetAddress in device mode.
2979 Always set to 0.
2980
2981 Internal:
2982 When set, core uses the value in USBDRD()_UAHC_DCFG[DEVADDR] directly
2983 for comparing the device address tokens. In simulation, this can be used to avoid
2984 sending a SET_ADDRESS command. */
2985 uint32_t u2rstecn : 1; /**< [ 16: 16](R/W) If the SuperSpeed connection fails during POLL or LMP exchange, the device connects
2986 at non-SuperSpeed mode. If this bit is set, then the device attempts three more times to
2987 connect at SuperSpeed, even if it previously failed to operate in SuperSpeed mode.
2988 This bit is only applicable in device mode. */
2989 uint32_t frmscldwn : 2; /**< [ 15: 14](R/W) Frame scale down. Scales down device view of a SOF/USOF/ITP duration.
2990 For SuperSpeed/high-speed mode:
2991 0x0 = Interval is 125 us.
2992 0x1 = Interval is 62.5 us.
2993 0x2 = Interval is 31.25 us.
2994 0x3 = Interval is 15.625 us.
2995
2996 For full speed mode, the scale down value is multiplied by 8. */
2997 uint32_t prtcapdir : 2; /**< [ 13: 12](R/W) 0x1 = for Host configurations.
2998 0x2 = for Device configurations. */
2999 uint32_t coresoftreset : 1; /**< [ 11: 11](R/W) Core soft reset: 1 = soft reset to core, 0 = no soft reset.
3000 Clears the interrupts and all the USBDRD()_UAHC_* CSRs except the
3001 following registers: USBDRD()_UAHC_GCTL, USBDRD()_UAHC_GUCTL, USBDRD()_UAHC_GSTS,
3002 USBDRD()_UAHC_GRLSID, USBDRD()_UAHC_GGPIO, USBDRD()_UAHC_GUID,
3003 USBDRD()_UAHC_GUSB2PHYCFG(),
3004 USBDRD()_UAHC_GUSB3PIPECTL().
3005
3006 When you reset PHYs (using USBDRD()_UAHC_GUSB2PHYCFG() or
3007 USBDRD()_UAHC_GUSB3PIPECTL()), you must keep the core in reset state until PHY
3008 clocks are stable. This controls the bus, RAM, and MAC domain resets.
3009
3010 Internal:
3011 Refer to Reset Generation on Synopsys Databook page 250.
3012 Under soft reset, accesses to USBDRD()_UAHC_* CSRs other than USBDRD()_UAHC_GCTL may fail
3013 (timeout).
3014 This bit is for debug purposes only. Use USBDRD()_UAHC_USBCMD[HCRST] for soft reset. */
3015 uint32_t sofitpsync : 1; /**< [ 10: 10](R/W) Synchronize ITP to reference clock. In host mode, if this bit is set to:
3016 0 = The core keeps the UTMI/ULPI PHY on the first port in non-suspended state whenever
3017 there is a SuperSpeed port that is not in Rx.Detect, SS.Disable, and U3 state.
3018 1 = The core keeps the UTMI/ULPI PHY on the first port in non-suspended state whenever the
3019 other non-SuperSpeed ports are not in suspended state.
3020
3021 This feature is useful because it saves power by suspending UTMI/ULPI when SuperSpeed only
3022 is active and it helps resolve when the PHY does not transmit a host resume unless it is
3023 placed in suspend state.
3024 USBDRD()_UAHC_GUSB2PHYCFG()[SUSPHY] eventually decides to put the UTMI/ULPI PHY in to
3025 suspend
3026 state. In addition, when this bit is set to 1, the core generates ITP off of the REF_CLK-
3027 based counter. Otherwise, ITP and SOF are generated off of UTMI/ULPI_CLK[0] based counter.
3028
3029 To program the reference clock period inside the core, refer to
3030 USBDRD()_UAHC_GUCTL[REFCLKPER].
3031
3032 If you do not plan to ever use this feature or the
3033 USBDRD()_UAHC_GFLADJ[GFLADJ_REFCLK_LPM_SEL]
3034 feature, the minimum frequency for the ref_clk can be as low as 32 KHz. You can connect
3035 the
3036 SUSPEND_CLK (as low as 32 KHz) to REF_CLK.
3037
3038 If you plan to enable hardware-based LPM (PORTPMSC[HLE] = 1), this feature cannot be used.
3039 Turn off this feature by setting this bit to zero and use the
3040 USBDRD()_UAHC_GFLADJ[GFLADJ_REFCLK_LPM_SEL] feature.
3041
3042 If you set this bit to 1, the USBDRD()_UAHC_GUSB2PHYCFG()[U2_FREECLK_EXISTS] bit
3043 must be set to 0. */
3044 uint32_t u1u2timerscale : 1; /**< [ 9: 9](R/W) Disable U1/U2 timer scaledown. If set to 1, along with SCALEDOWN = 0x1, disables the scale
3045 down of U1/U2 inactive timer values.
3046 This is for simulation mode only. */
3047 uint32_t debugattach : 1; /**< [ 8: 8](R/W) Debug attach. When this bit is set:
3048 * SuperSpeed link proceeds directly to the polling-link state (USBDRD()_UAHC_DCTL[RS] = 1)
3049 without checking remote termination.
3050 * Link LFPS polling timeout is infinite.
3051 * Polling timeout during TS1 is infinite (in case link is waiting for TXEQ to finish). */
3052 uint32_t ramclksel : 2; /**< [ 7: 6](R/W) RAM clock select. Always keep set to 0x0. */
3053 uint32_t scaledown : 2; /**< [ 5: 4](R/W) Scale-down mode. When scale-down mode is enabled for simulation, the core uses scaled-down
3054 timing values, resulting in faster simulations. When scale-down mode is disabled, actual
3055 timing values are used. This is required for hardware operation.
3056
3057 High-speed/full-speed/low-speed modes:
3058 0x0 = Disables all scale-downs. Actual timing values are used.
3059 0x1 = Enables scale-down of all timing values. These include:
3060 * Speed enumeration.
3061 * HNP/SRP.
3062 * Suspend and resume.
3063
3064 0x2 = N/A
3065 0x3 = Enables bits \<0\> and \<1\> scale-down timing values.
3066
3067 SuperSpeed mode:
3068 0x0 = Disables all scale-downs. Actual timing values are used.
3069 0x1 = Enables scaled down SuperSpeed timing and repeat values including:
3070 * Number of TxEq training sequences reduce to eight.
3071 * LFPS polling burst time reduce to 100 ns.
3072 * LFPS warm reset receive reduce to 30 us.
3073
3074 Internal:
3075 Refer to the rtl_vip_scaledown_mapping.xls file under \<workspace\>/sim/SoC_sim
3076 directory for the complete list.
3077 0x2 = No TxEq training sequences are sent. Overrides bit\<4\>.
3078 0x3 = Enables bits\<0\> and \<1\> scale-down timing values. */
3079 uint32_t disscramble : 1; /**< [ 3: 3](R/W) Disable scrambling. Transmit request to link partner on next transition to recovery or polling. */
3080 uint32_t u2exit_lfps : 1; /**< [ 2: 2](R/W) LFPS U2 exit.
3081 0 = The link treats 248 ns LFPS as a valid U2 exit.
3082 1 = The link waits for 8 us of LFPS before it detects a valid U2 exit.
3083
3084 This bit is added to improve interoperability with a third party host controller. This
3085 host controller in U2 state while performing receiver detection generates an LFPS glitch
3086 of about 4s duration. This causes the device to exit from U2 state because the LFPS filter
3087 value is 248 ns. With the new functionality enabled, the device can stay in U2 while
3088 ignoring this glitch from the host controller. */
3089 uint32_t reserved_1 : 1;
3090 uint32_t dsblclkgtng : 1; /**< [ 0: 0](R/W) Disable clock gating. When set to 1 and the core is in low power mode, internal clock
3091 gating is disabled, which means the clocks are always running. This bit can be set to 1
3092 after power-up reset. */
3093 #else /* Word 0 - Little Endian */
3094 uint32_t dsblclkgtng : 1; /**< [ 0: 0](R/W) Disable clock gating. When set to 1 and the core is in low power mode, internal clock
3095 gating is disabled, which means the clocks are always running. This bit can be set to 1
3096 after power-up reset. */
3097 uint32_t reserved_1 : 1;
3098 uint32_t u2exit_lfps : 1; /**< [ 2: 2](R/W) LFPS U2 exit.
3099 0 = The link treats 248 ns LFPS as a valid U2 exit.
3100 1 = The link waits for 8 us of LFPS before it detects a valid U2 exit.
3101
3102 This bit is added to improve interoperability with a third party host controller. This
3103 host controller in U2 state while performing receiver detection generates an LFPS glitch
3104 of about 4s duration. This causes the device to exit from U2 state because the LFPS filter
3105 value is 248 ns. With the new functionality enabled, the device can stay in U2 while
3106 ignoring this glitch from the host controller. */
3107 uint32_t disscramble : 1; /**< [ 3: 3](R/W) Disable scrambling. Transmit request to link partner on next transition to recovery or polling. */
3108 uint32_t scaledown : 2; /**< [ 5: 4](R/W) Scale-down mode. When scale-down mode is enabled for simulation, the core uses scaled-down
3109 timing values, resulting in faster simulations. When scale-down mode is disabled, actual
3110 timing values are used. This is required for hardware operation.
3111
3112 High-speed/full-speed/low-speed modes:
3113 0x0 = Disables all scale-downs. Actual timing values are used.
3114 0x1 = Enables scale-down of all timing values. These include:
3115 * Speed enumeration.
3116 * HNP/SRP.
3117 * Suspend and resume.
3118
3119 0x2 = N/A
3120 0x3 = Enables bits \<0\> and \<1\> scale-down timing values.
3121
3122 SuperSpeed mode:
3123 0x0 = Disables all scale-downs. Actual timing values are used.
3124 0x1 = Enables scaled down SuperSpeed timing and repeat values including:
3125 * Number of TxEq training sequences reduce to eight.
3126 * LFPS polling burst time reduce to 100 ns.
3127 * LFPS warm reset receive reduce to 30 us.
3128
3129 Internal:
3130 Refer to the rtl_vip_scaledown_mapping.xls file under \<workspace\>/sim/SoC_sim
3131 directory for the complete list.
3132 0x2 = No TxEq training sequences are sent. Overrides bit\<4\>.
3133 0x3 = Enables bits\<0\> and \<1\> scale-down timing values. */
3134 uint32_t ramclksel : 2; /**< [ 7: 6](R/W) RAM clock select. Always keep set to 0x0. */
3135 uint32_t debugattach : 1; /**< [ 8: 8](R/W) Debug attach. When this bit is set:
3136 * SuperSpeed link proceeds directly to the polling-link state (USBDRD()_UAHC_DCTL[RS] = 1)
3137 without checking remote termination.
3138 * Link LFPS polling timeout is infinite.
3139 * Polling timeout during TS1 is infinite (in case link is waiting for TXEQ to finish). */
3140 uint32_t u1u2timerscale : 1; /**< [ 9: 9](R/W) Disable U1/U2 timer scaledown. If set to 1, along with SCALEDOWN = 0x1, disables the scale
3141 down of U1/U2 inactive timer values.
3142 This is for simulation mode only. */
3143 uint32_t sofitpsync : 1; /**< [ 10: 10](R/W) Synchronize ITP to reference clock. In host mode, if this bit is set to:
3144 0 = The core keeps the UTMI/ULPI PHY on the first port in non-suspended state whenever
3145 there is a SuperSpeed port that is not in Rx.Detect, SS.Disable, and U3 state.
3146 1 = The core keeps the UTMI/ULPI PHY on the first port in non-suspended state whenever the
3147 other non-SuperSpeed ports are not in suspended state.
3148
3149 This feature is useful because it saves power by suspending UTMI/ULPI when SuperSpeed only
3150 is active and it helps resolve when the PHY does not transmit a host resume unless it is
3151 placed in suspend state.
3152 USBDRD()_UAHC_GUSB2PHYCFG()[SUSPHY] eventually decides to put the UTMI/ULPI PHY in to
3153 suspend
3154 state. In addition, when this bit is set to 1, the core generates ITP off of the REF_CLK-
3155 based counter. Otherwise, ITP and SOF are generated off of UTMI/ULPI_CLK[0] based counter.
3156
3157 To program the reference clock period inside the core, refer to
3158 USBDRD()_UAHC_GUCTL[REFCLKPER].
3159
3160 If you do not plan to ever use this feature or the
3161 USBDRD()_UAHC_GFLADJ[GFLADJ_REFCLK_LPM_SEL]
3162 feature, the minimum frequency for the ref_clk can be as low as 32 KHz. You can connect
3163 the
3164 SUSPEND_CLK (as low as 32 KHz) to REF_CLK.
3165
3166 If you plan to enable hardware-based LPM (PORTPMSC[HLE] = 1), this feature cannot be used.
3167 Turn off this feature by setting this bit to zero and use the
3168 USBDRD()_UAHC_GFLADJ[GFLADJ_REFCLK_LPM_SEL] feature.
3169
3170 If you set this bit to 1, the USBDRD()_UAHC_GUSB2PHYCFG()[U2_FREECLK_EXISTS] bit
3171 must be set to 0. */
3172 uint32_t coresoftreset : 1; /**< [ 11: 11](R/W) Core soft reset: 1 = soft reset to core, 0 = no soft reset.
3173 Clears the interrupts and all the USBDRD()_UAHC_* CSRs except the
3174 following registers: USBDRD()_UAHC_GCTL, USBDRD()_UAHC_GUCTL, USBDRD()_UAHC_GSTS,
3175 USBDRD()_UAHC_GRLSID, USBDRD()_UAHC_GGPIO, USBDRD()_UAHC_GUID,
3176 USBDRD()_UAHC_GUSB2PHYCFG(),
3177 USBDRD()_UAHC_GUSB3PIPECTL().
3178
3179 When you reset PHYs (using USBDRD()_UAHC_GUSB2PHYCFG() or
3180 USBDRD()_UAHC_GUSB3PIPECTL()), you must keep the core in reset state until PHY
3181 clocks are stable. This controls the bus, RAM, and MAC domain resets.
3182
3183 Internal:
3184 Refer to Reset Generation on Synopsys Databook page 250.
3185 Under soft reset, accesses to USBDRD()_UAHC_* CSRs other than USBDRD()_UAHC_GCTL may fail
3186 (timeout).
3187 This bit is for debug purposes only. Use USBDRD()_UAHC_USBCMD[HCRST] for soft reset. */
3188 uint32_t prtcapdir : 2; /**< [ 13: 12](R/W) 0x1 = for Host configurations.
3189 0x2 = for Device configurations. */
3190 uint32_t frmscldwn : 2; /**< [ 15: 14](R/W) Frame scale down. Scales down device view of a SOF/USOF/ITP duration.
3191 For SuperSpeed/high-speed mode:
3192 0x0 = Interval is 125 us.
3193 0x1 = Interval is 62.5 us.
3194 0x2 = Interval is 31.25 us.
3195 0x3 = Interval is 15.625 us.
3196
3197 For full speed mode, the scale down value is multiplied by 8. */
3198 uint32_t u2rstecn : 1; /**< [ 16: 16](R/W) If the SuperSpeed connection fails during POLL or LMP exchange, the device connects
3199 at non-SuperSpeed mode. If this bit is set, then the device attempts three more times to
3200 connect at SuperSpeed, even if it previously failed to operate in SuperSpeed mode.
3201 This bit is only applicable in device mode. */
3202 uint32_t bypssetaddr : 1; /**< [ 17: 17](R/W) Bypass SetAddress in device mode.
3203 Always set to 0.
3204
3205 Internal:
3206 When set, core uses the value in USBDRD()_UAHC_DCFG[DEVADDR] directly
3207 for comparing the device address tokens. In simulation, this can be used to avoid
3208 sending a SET_ADDRESS command. */
3209 uint32_t masterfiltbypass : 1; /**< [ 18: 18](R/W) Master filter bypass. Not relevant for Cavium's configuration. */
3210 uint32_t pwrdnscale : 13; /**< [ 31: 19](R/W) Power down scale. The USB3 suspend-clock input replaces pipe3_rx_pclk as a clock source to
3211 a small part of the USB3 core that operates when the SuperSpeed PHY is in its lowest power
3212 (P3) state, and therefore does not provide a clock. This field specifies how many suspend-
3213 clock periods fit into a 16 kHz clock period. When performing the division, round up the
3214 remainder.
3215
3216 For example, when using an 32-bit PHY and 25-MHz suspend clock, PWRDNSCALE = 25000 kHz/16
3217 kHz = 1563 (rounded up).
3218
3219 The minimum suspend-clock frequency is 32 KHz, and maximum suspend-clock frequency is 125
3220 MHz.
3221
3222 The LTSSM uses suspend clock for 12-ms and 100-ms timers during suspend mode. According to
3223 the USB 3.0 specification, the accuracy on these timers is 0% to +50%. 12 ms + 0~+50%
3224 accuracy = 18 ms (Range is 12 ms - 18 ms)
3225 100 ms + 0~+50% accuracy = 150 ms (Range is 100 ms - 150 ms).
3226
3227 The suspend clock accuracy requirement is:
3228 _ (12,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period should be between 12,000 and
3229 18,000
3230 _ (100,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period should be between 100,000 and
3231 150,000
3232
3233 For example, if your suspend_clk frequency varies from 7.5 MHz to 10.5 MHz, then the value
3234 needs to programmed is: power down scale = 10500/16 = 657 (rounded up; and fastest
3235 frequency used). */
3236 #endif /* Word 0 - End */
3237 } cn8;
3238 /* struct bdk_usbdrdx_uahc_gctl_s cn9; */
3239 };
3240 typedef union bdk_usbdrdx_uahc_gctl bdk_usbdrdx_uahc_gctl_t;
3241
3242 static inline uint64_t BDK_USBDRDX_UAHC_GCTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GCTL(unsigned long a)3243 static inline uint64_t BDK_USBDRDX_UAHC_GCTL(unsigned long a)
3244 {
3245 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3246 return 0x86800000c110ll + 0x1000000000ll * ((a) & 0x1);
3247 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3248 return 0x86800000c110ll + 0x1000000000ll * ((a) & 0x1);
3249 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3250 return 0x86800000c110ll + 0x1000000000ll * ((a) & 0x1);
3251 __bdk_csr_fatal("USBDRDX_UAHC_GCTL", 1, a, 0, 0, 0);
3252 }
3253
3254 #define typedef_BDK_USBDRDX_UAHC_GCTL(a) bdk_usbdrdx_uahc_gctl_t
3255 #define bustype_BDK_USBDRDX_UAHC_GCTL(a) BDK_CSR_TYPE_NCB32b
3256 #define basename_BDK_USBDRDX_UAHC_GCTL(a) "USBDRDX_UAHC_GCTL"
3257 #define device_bar_BDK_USBDRDX_UAHC_GCTL(a) 0x0 /* PF_BAR0 */
3258 #define busnum_BDK_USBDRDX_UAHC_GCTL(a) (a)
3259 #define arguments_BDK_USBDRDX_UAHC_GCTL(a) (a),-1,-1,-1
3260
3261 /**
3262 * Register (NCB32b) usbdrd#_uahc_gdbgbmu
3263 *
3264 * USB UAHC BMU Debug Register
3265 * See description in USBDRD()_UAHC_GDBGFIFOSPACE.
3266 *
3267 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3268 *
3269 * Internal:
3270 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.30
3271 */
3272 union bdk_usbdrdx_uahc_gdbgbmu
3273 {
3274 uint32_t u;
3275 struct bdk_usbdrdx_uahc_gdbgbmu_s
3276 {
3277 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3278 uint32_t bmu_bcu_dbg : 24; /**< [ 31: 8](RO/H) BMU_BCU debug information. */
3279 uint32_t bmu_dcu_dbg : 4; /**< [ 7: 4](RO/H) BMU_DCU debug information. */
3280 uint32_t bmu_ccu_dbg : 4; /**< [ 3: 0](RO/H) BMU_CCU debug information. */
3281 #else /* Word 0 - Little Endian */
3282 uint32_t bmu_ccu_dbg : 4; /**< [ 3: 0](RO/H) BMU_CCU debug information. */
3283 uint32_t bmu_dcu_dbg : 4; /**< [ 7: 4](RO/H) BMU_DCU debug information. */
3284 uint32_t bmu_bcu_dbg : 24; /**< [ 31: 8](RO/H) BMU_BCU debug information. */
3285 #endif /* Word 0 - End */
3286 } s;
3287 /* struct bdk_usbdrdx_uahc_gdbgbmu_s cn; */
3288 };
3289 typedef union bdk_usbdrdx_uahc_gdbgbmu bdk_usbdrdx_uahc_gdbgbmu_t;
3290
3291 static inline uint64_t BDK_USBDRDX_UAHC_GDBGBMU(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GDBGBMU(unsigned long a)3292 static inline uint64_t BDK_USBDRDX_UAHC_GDBGBMU(unsigned long a)
3293 {
3294 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3295 return 0x86800000c16cll + 0x1000000000ll * ((a) & 0x1);
3296 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3297 return 0x86800000c16cll + 0x1000000000ll * ((a) & 0x1);
3298 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3299 return 0x86800000c16cll + 0x1000000000ll * ((a) & 0x1);
3300 __bdk_csr_fatal("USBDRDX_UAHC_GDBGBMU", 1, a, 0, 0, 0);
3301 }
3302
3303 #define typedef_BDK_USBDRDX_UAHC_GDBGBMU(a) bdk_usbdrdx_uahc_gdbgbmu_t
3304 #define bustype_BDK_USBDRDX_UAHC_GDBGBMU(a) BDK_CSR_TYPE_NCB32b
3305 #define basename_BDK_USBDRDX_UAHC_GDBGBMU(a) "USBDRDX_UAHC_GDBGBMU"
3306 #define device_bar_BDK_USBDRDX_UAHC_GDBGBMU(a) 0x0 /* PF_BAR0 */
3307 #define busnum_BDK_USBDRDX_UAHC_GDBGBMU(a) (a)
3308 #define arguments_BDK_USBDRDX_UAHC_GDBGBMU(a) (a),-1,-1,-1
3309
3310 /**
3311 * Register (NCB) usbdrd#_uahc_gdbgepinfo
3312 *
3313 * USB UAHC Endpoint Information Debug Register
3314 * See description in USBDRD()_UAHC_GDBGFIFOSPACE.
3315 *
3316 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3317 */
3318 union bdk_usbdrdx_uahc_gdbgepinfo
3319 {
3320 uint64_t u;
3321 struct bdk_usbdrdx_uahc_gdbgepinfo_s
3322 {
3323 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3324 uint64_t endpt_dbg : 64; /**< [ 63: 0](RO/H) Endpoint debug information. */
3325 #else /* Word 0 - Little Endian */
3326 uint64_t endpt_dbg : 64; /**< [ 63: 0](RO/H) Endpoint debug information. */
3327 #endif /* Word 0 - End */
3328 } s;
3329 /* struct bdk_usbdrdx_uahc_gdbgepinfo_s cn; */
3330 };
3331 typedef union bdk_usbdrdx_uahc_gdbgepinfo bdk_usbdrdx_uahc_gdbgepinfo_t;
3332
3333 static inline uint64_t BDK_USBDRDX_UAHC_GDBGEPINFO(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GDBGEPINFO(unsigned long a)3334 static inline uint64_t BDK_USBDRDX_UAHC_GDBGEPINFO(unsigned long a)
3335 {
3336 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3337 return 0x86800000c178ll + 0x1000000000ll * ((a) & 0x1);
3338 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3339 return 0x86800000c178ll + 0x1000000000ll * ((a) & 0x1);
3340 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3341 return 0x86800000c178ll + 0x1000000000ll * ((a) & 0x1);
3342 __bdk_csr_fatal("USBDRDX_UAHC_GDBGEPINFO", 1, a, 0, 0, 0);
3343 }
3344
3345 #define typedef_BDK_USBDRDX_UAHC_GDBGEPINFO(a) bdk_usbdrdx_uahc_gdbgepinfo_t
3346 #define bustype_BDK_USBDRDX_UAHC_GDBGEPINFO(a) BDK_CSR_TYPE_NCB
3347 #define basename_BDK_USBDRDX_UAHC_GDBGEPINFO(a) "USBDRDX_UAHC_GDBGEPINFO"
3348 #define device_bar_BDK_USBDRDX_UAHC_GDBGEPINFO(a) 0x0 /* PF_BAR0 */
3349 #define busnum_BDK_USBDRDX_UAHC_GDBGEPINFO(a) (a)
3350 #define arguments_BDK_USBDRDX_UAHC_GDBGEPINFO(a) (a),-1,-1,-1
3351
3352 /**
3353 * Register (NCB32b) usbdrd#_uahc_gdbgfifospace
3354 *
3355 * USB UAHC Debug FIFO Space Available Register
3356 * This register is for debug purposes. It provides debug information on the internal status and
3357 * state machines. Global debug registers have design-specific information, and are used by state
3358 * machines. Global debug registers have design-specific information, and are used for debugging
3359 * purposes. These registers are not intended to be used by the customer. If any debug assistance
3360 * is needed for the silicon, contact customer support with a dump of these registers.
3361 *
3362 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3363 *
3364 * Internal:
3365 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.27
3366 * INTERNAL: Contact Synopsys directly.
3367 */
3368 union bdk_usbdrdx_uahc_gdbgfifospace
3369 {
3370 uint32_t u;
3371 struct bdk_usbdrdx_uahc_gdbgfifospace_s
3372 {
3373 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3374 uint32_t spaceavailable : 16; /**< [ 31: 16](RO/H) Space available in the selected FIFO. */
3375 uint32_t reserved_9_15 : 7;
3376 uint32_t select : 9; /**< [ 8: 0](R/W) FIFO/queue select/port-select.
3377 FIFO/queue select: \<7:5\> indicates the FIFO/queue type; \<4:0\> indicates the FIFO/queue
3378 number.
3379 For example, 0x21 refers to RxFIFO_1, and 0x5E refers to TxReqQ_30.
3380 0x1F-0x0: TxFIFO_31 to TxFIFO_0.
3381 0x3F-0x20: RxFIFO_31 to RxFIFO_0.
3382 0x5F-0x40: TxReqQ_31 to TxReqQ_0.
3383 0x7F-0x60: RxReqQ_31 to RxReqQ_0.
3384 0x9F-0x80: RxInfoQ_31 to RxInfoQ_0.
3385 0xA0: DescFetchQ.
3386 0xA1: EventQ.
3387 0xA2: ProtocolStatusQ.
3388
3389 Port-select: \<3:0\> selects the port-number when accessing USBDRD()_UAHC_GDBGLTSSM. */
3390 #else /* Word 0 - Little Endian */
3391 uint32_t select : 9; /**< [ 8: 0](R/W) FIFO/queue select/port-select.
3392 FIFO/queue select: \<7:5\> indicates the FIFO/queue type; \<4:0\> indicates the FIFO/queue
3393 number.
3394 For example, 0x21 refers to RxFIFO_1, and 0x5E refers to TxReqQ_30.
3395 0x1F-0x0: TxFIFO_31 to TxFIFO_0.
3396 0x3F-0x20: RxFIFO_31 to RxFIFO_0.
3397 0x5F-0x40: TxReqQ_31 to TxReqQ_0.
3398 0x7F-0x60: RxReqQ_31 to RxReqQ_0.
3399 0x9F-0x80: RxInfoQ_31 to RxInfoQ_0.
3400 0xA0: DescFetchQ.
3401 0xA1: EventQ.
3402 0xA2: ProtocolStatusQ.
3403
3404 Port-select: \<3:0\> selects the port-number when accessing USBDRD()_UAHC_GDBGLTSSM. */
3405 uint32_t reserved_9_15 : 7;
3406 uint32_t spaceavailable : 16; /**< [ 31: 16](RO/H) Space available in the selected FIFO. */
3407 #endif /* Word 0 - End */
3408 } s;
3409 /* struct bdk_usbdrdx_uahc_gdbgfifospace_s cn; */
3410 };
3411 typedef union bdk_usbdrdx_uahc_gdbgfifospace bdk_usbdrdx_uahc_gdbgfifospace_t;
3412
3413 static inline uint64_t BDK_USBDRDX_UAHC_GDBGFIFOSPACE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GDBGFIFOSPACE(unsigned long a)3414 static inline uint64_t BDK_USBDRDX_UAHC_GDBGFIFOSPACE(unsigned long a)
3415 {
3416 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3417 return 0x86800000c160ll + 0x1000000000ll * ((a) & 0x1);
3418 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3419 return 0x86800000c160ll + 0x1000000000ll * ((a) & 0x1);
3420 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3421 return 0x86800000c160ll + 0x1000000000ll * ((a) & 0x1);
3422 __bdk_csr_fatal("USBDRDX_UAHC_GDBGFIFOSPACE", 1, a, 0, 0, 0);
3423 }
3424
3425 #define typedef_BDK_USBDRDX_UAHC_GDBGFIFOSPACE(a) bdk_usbdrdx_uahc_gdbgfifospace_t
3426 #define bustype_BDK_USBDRDX_UAHC_GDBGFIFOSPACE(a) BDK_CSR_TYPE_NCB32b
3427 #define basename_BDK_USBDRDX_UAHC_GDBGFIFOSPACE(a) "USBDRDX_UAHC_GDBGFIFOSPACE"
3428 #define device_bar_BDK_USBDRDX_UAHC_GDBGFIFOSPACE(a) 0x0 /* PF_BAR0 */
3429 #define busnum_BDK_USBDRDX_UAHC_GDBGFIFOSPACE(a) (a)
3430 #define arguments_BDK_USBDRDX_UAHC_GDBGFIFOSPACE(a) (a),-1,-1,-1
3431
3432 /**
3433 * Register (NCB32b) usbdrd#_uahc_gdbglnmcc
3434 *
3435 * USB UAHC LNMCC Debug Register
3436 * See description in USBDRD()_UAHC_GDBGFIFOSPACE.
3437 *
3438 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3439 *
3440 * Internal:
3441 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.29
3442 */
3443 union bdk_usbdrdx_uahc_gdbglnmcc
3444 {
3445 uint32_t u;
3446 struct bdk_usbdrdx_uahc_gdbglnmcc_s
3447 {
3448 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3449 uint32_t reserved_9_31 : 23;
3450 uint32_t lnmcc_berc : 9; /**< [ 8: 0](RO/H) This field indicates the bit-error-rate information for the port selected in
3451 USBDRD()_UAHC_GDBGFIFOSPACE[SELECT] (port-select).
3452 This field is for debug purposes only. */
3453 #else /* Word 0 - Little Endian */
3454 uint32_t lnmcc_berc : 9; /**< [ 8: 0](RO/H) This field indicates the bit-error-rate information for the port selected in
3455 USBDRD()_UAHC_GDBGFIFOSPACE[SELECT] (port-select).
3456 This field is for debug purposes only. */
3457 uint32_t reserved_9_31 : 23;
3458 #endif /* Word 0 - End */
3459 } s;
3460 /* struct bdk_usbdrdx_uahc_gdbglnmcc_s cn; */
3461 };
3462 typedef union bdk_usbdrdx_uahc_gdbglnmcc bdk_usbdrdx_uahc_gdbglnmcc_t;
3463
3464 static inline uint64_t BDK_USBDRDX_UAHC_GDBGLNMCC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GDBGLNMCC(unsigned long a)3465 static inline uint64_t BDK_USBDRDX_UAHC_GDBGLNMCC(unsigned long a)
3466 {
3467 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3468 return 0x86800000c168ll + 0x1000000000ll * ((a) & 0x1);
3469 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3470 return 0x86800000c168ll + 0x1000000000ll * ((a) & 0x1);
3471 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3472 return 0x86800000c168ll + 0x1000000000ll * ((a) & 0x1);
3473 __bdk_csr_fatal("USBDRDX_UAHC_GDBGLNMCC", 1, a, 0, 0, 0);
3474 }
3475
3476 #define typedef_BDK_USBDRDX_UAHC_GDBGLNMCC(a) bdk_usbdrdx_uahc_gdbglnmcc_t
3477 #define bustype_BDK_USBDRDX_UAHC_GDBGLNMCC(a) BDK_CSR_TYPE_NCB32b
3478 #define basename_BDK_USBDRDX_UAHC_GDBGLNMCC(a) "USBDRDX_UAHC_GDBGLNMCC"
3479 #define device_bar_BDK_USBDRDX_UAHC_GDBGLNMCC(a) 0x0 /* PF_BAR0 */
3480 #define busnum_BDK_USBDRDX_UAHC_GDBGLNMCC(a) (a)
3481 #define arguments_BDK_USBDRDX_UAHC_GDBGLNMCC(a) (a),-1,-1,-1
3482
3483 /**
3484 * Register (NCB32b) usbdrd#_uahc_gdbglsp
3485 *
3486 * USB UAHC LSP Debug Register
3487 * See description in USBDRD()_UAHC_GDBGFIFOSPACE.
3488 *
3489 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3490 */
3491 union bdk_usbdrdx_uahc_gdbglsp
3492 {
3493 uint32_t u;
3494 struct bdk_usbdrdx_uahc_gdbglsp_s
3495 {
3496 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3497 uint32_t lsp_dbg : 32; /**< [ 31: 0](RO/H) LSP debug information. */
3498 #else /* Word 0 - Little Endian */
3499 uint32_t lsp_dbg : 32; /**< [ 31: 0](RO/H) LSP debug information. */
3500 #endif /* Word 0 - End */
3501 } s;
3502 /* struct bdk_usbdrdx_uahc_gdbglsp_s cn; */
3503 };
3504 typedef union bdk_usbdrdx_uahc_gdbglsp bdk_usbdrdx_uahc_gdbglsp_t;
3505
3506 static inline uint64_t BDK_USBDRDX_UAHC_GDBGLSP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GDBGLSP(unsigned long a)3507 static inline uint64_t BDK_USBDRDX_UAHC_GDBGLSP(unsigned long a)
3508 {
3509 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3510 return 0x86800000c174ll + 0x1000000000ll * ((a) & 0x1);
3511 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3512 return 0x86800000c174ll + 0x1000000000ll * ((a) & 0x1);
3513 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3514 return 0x86800000c174ll + 0x1000000000ll * ((a) & 0x1);
3515 __bdk_csr_fatal("USBDRDX_UAHC_GDBGLSP", 1, a, 0, 0, 0);
3516 }
3517
3518 #define typedef_BDK_USBDRDX_UAHC_GDBGLSP(a) bdk_usbdrdx_uahc_gdbglsp_t
3519 #define bustype_BDK_USBDRDX_UAHC_GDBGLSP(a) BDK_CSR_TYPE_NCB32b
3520 #define basename_BDK_USBDRDX_UAHC_GDBGLSP(a) "USBDRDX_UAHC_GDBGLSP"
3521 #define device_bar_BDK_USBDRDX_UAHC_GDBGLSP(a) 0x0 /* PF_BAR0 */
3522 #define busnum_BDK_USBDRDX_UAHC_GDBGLSP(a) (a)
3523 #define arguments_BDK_USBDRDX_UAHC_GDBGLSP(a) (a),-1,-1,-1
3524
3525 /**
3526 * Register (NCB32b) usbdrd#_uahc_gdbglspmux
3527 *
3528 * USB UAHC LSP Multiplexer Debug Register
3529 * See description in USBDRD()_UAHC_GDBGFIFOSPACE.
3530 *
3531 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3532 *
3533 * Internal:
3534 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.21
3535 * INTERNAL: This register is for Synopsys internal use only.
3536 */
3537 union bdk_usbdrdx_uahc_gdbglspmux
3538 {
3539 uint32_t u;
3540 struct bdk_usbdrdx_uahc_gdbglspmux_s
3541 {
3542 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3543 uint32_t reserved_24_31 : 8;
3544 uint32_t latraceportmuxselect : 8; /**< [ 23: 16](R/W) logic_analyzer_trace port multiplexer select. Only bits\<21:16\> are used. For details on
3545 how the mux controls the debug traces, refer to the Verilog file.
3546 A value of 0x3F drives 0s on the logic_analyzer_trace signal. If you plan to OR (instead
3547 using a mux) this signal with other trace signals in your system to generate a common
3548 trace signal, you can use this feature. */
3549 uint32_t endbc : 1; /**< [ 15: 15](R/W) Enable debugging of the debug capability LSP. Use HOSTSELECT to select the DbC LSP debug
3550 information presented in the GDBGLSP register.
3551
3552 Internal:
3553 Note this can only be used if DebugCapabaility was enabled at compile. */
3554 uint32_t reserved_14 : 1;
3555 uint32_t hostselect : 14; /**< [ 13: 0](R/W) Host select. Selects the LSP debug information presented in USBDRD()_UAHC_GDBGLSP. */
3556 #else /* Word 0 - Little Endian */
3557 uint32_t hostselect : 14; /**< [ 13: 0](R/W) Host select. Selects the LSP debug information presented in USBDRD()_UAHC_GDBGLSP. */
3558 uint32_t reserved_14 : 1;
3559 uint32_t endbc : 1; /**< [ 15: 15](R/W) Enable debugging of the debug capability LSP. Use HOSTSELECT to select the DbC LSP debug
3560 information presented in the GDBGLSP register.
3561
3562 Internal:
3563 Note this can only be used if DebugCapabaility was enabled at compile. */
3564 uint32_t latraceportmuxselect : 8; /**< [ 23: 16](R/W) logic_analyzer_trace port multiplexer select. Only bits\<21:16\> are used. For details on
3565 how the mux controls the debug traces, refer to the Verilog file.
3566 A value of 0x3F drives 0s on the logic_analyzer_trace signal. If you plan to OR (instead
3567 using a mux) this signal with other trace signals in your system to generate a common
3568 trace signal, you can use this feature. */
3569 uint32_t reserved_24_31 : 8;
3570 #endif /* Word 0 - End */
3571 } s;
3572 /* struct bdk_usbdrdx_uahc_gdbglspmux_s cn; */
3573 };
3574 typedef union bdk_usbdrdx_uahc_gdbglspmux bdk_usbdrdx_uahc_gdbglspmux_t;
3575
3576 static inline uint64_t BDK_USBDRDX_UAHC_GDBGLSPMUX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GDBGLSPMUX(unsigned long a)3577 static inline uint64_t BDK_USBDRDX_UAHC_GDBGLSPMUX(unsigned long a)
3578 {
3579 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3580 return 0x86800000c170ll + 0x1000000000ll * ((a) & 0x1);
3581 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3582 return 0x86800000c170ll + 0x1000000000ll * ((a) & 0x1);
3583 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3584 return 0x86800000c170ll + 0x1000000000ll * ((a) & 0x1);
3585 __bdk_csr_fatal("USBDRDX_UAHC_GDBGLSPMUX", 1, a, 0, 0, 0);
3586 }
3587
3588 #define typedef_BDK_USBDRDX_UAHC_GDBGLSPMUX(a) bdk_usbdrdx_uahc_gdbglspmux_t
3589 #define bustype_BDK_USBDRDX_UAHC_GDBGLSPMUX(a) BDK_CSR_TYPE_NCB32b
3590 #define basename_BDK_USBDRDX_UAHC_GDBGLSPMUX(a) "USBDRDX_UAHC_GDBGLSPMUX"
3591 #define device_bar_BDK_USBDRDX_UAHC_GDBGLSPMUX(a) 0x0 /* PF_BAR0 */
3592 #define busnum_BDK_USBDRDX_UAHC_GDBGLSPMUX(a) (a)
3593 #define arguments_BDK_USBDRDX_UAHC_GDBGLSPMUX(a) (a),-1,-1,-1
3594
3595 /**
3596 * Register (NCB32b) usbdrd#_uahc_gdbgltssm
3597 *
3598 * USB UAHC LTSSM Debug Register
3599 * In multiport host configuration, the port number is defined by
3600 * USBDRD()_UAHC_GDBGFIFOSPACE[SELECT]\<3:0\>. Value of this register may change immediately after
3601 * reset.
3602 * See description in USBDRD()_UAHC_GDBGFIFOSPACE.
3603 *
3604 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3605 *
3606 * Internal:
3607 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.28
3608 */
3609 union bdk_usbdrdx_uahc_gdbgltssm
3610 {
3611 uint32_t u;
3612 struct bdk_usbdrdx_uahc_gdbgltssm_s
3613 {
3614 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3615 uint32_t reserved_27_31 : 5;
3616 uint32_t ltdbtimeout : 1; /**< [ 26: 26](RO/H) LTDB timeout. */
3617 uint32_t ltdblinkstate : 4; /**< [ 25: 22](RO/H) LTDB link state. */
3618 uint32_t ltdbsubstate : 4; /**< [ 21: 18](RO/H) LTDB substate. */
3619 uint32_t debugpipestatus : 18; /**< [ 17: 0](RO/H) Debug PIPE status.
3620 _ \<17\> Elastic buffer mode.
3621 _ \<16\> TX elec idle.
3622 _ \<15\> RX polarity.
3623 _ \<14\> TX Detect RX/loopback.
3624 _ \<13:11\> LTSSM PHY command state.
3625 _ 0x0 = PHY_IDLE (PHY command state is in IDLE. No PHY request is pending.)
3626 _ 0x1 = PHY_DET (Request to start receiver detection).
3627 _ 0x2 = PHY_DET_3 (Wait for Phy_Status (receiver detection)).
3628 _ 0x3 = PHY_PWR_DLY (delay Pipe3_PowerDown P0 -\> P1/P2/P3 request).
3629 _ 0x4 = PHY_PWR_A (delay for internal logic).
3630 _ 0x5 = PHY_PWR_B (wait for Phy_Status(Power-state change request)).
3631
3632 _ \<10:9\> Power down.
3633 _ \<8\> RxEq train.
3634 _ \<7:6\> TX de-emphasis.
3635 _ \<5:3\> LTSSM clock state.
3636 _ 0x0 = CLK_NORM (PHY is in non-P3 state and PCLK is running).
3637 _ 0x1 = CLK_TO_P3 (P3 entry request to PHY).
3638 _ 0x2 = CLK_WAIT1 (wait for Phy_Status (P3 request)).
3639 _ 0x3 = CLK_P3 (PHY is in P3 and PCLK is not running).
3640 _ 0x4 = CLK_TO_P0 (P3 exit request to PHY).
3641 _ 0x5 = CLK_WAIT2 (Wait for Phy_Status (P3 exit request)).
3642
3643 _ \<2\> TX swing.
3644 _ \<1\> RX termination.
3645 _ \<0\> TX 1s/0s. */
3646 #else /* Word 0 - Little Endian */
3647 uint32_t debugpipestatus : 18; /**< [ 17: 0](RO/H) Debug PIPE status.
3648 _ \<17\> Elastic buffer mode.
3649 _ \<16\> TX elec idle.
3650 _ \<15\> RX polarity.
3651 _ \<14\> TX Detect RX/loopback.
3652 _ \<13:11\> LTSSM PHY command state.
3653 _ 0x0 = PHY_IDLE (PHY command state is in IDLE. No PHY request is pending.)
3654 _ 0x1 = PHY_DET (Request to start receiver detection).
3655 _ 0x2 = PHY_DET_3 (Wait for Phy_Status (receiver detection)).
3656 _ 0x3 = PHY_PWR_DLY (delay Pipe3_PowerDown P0 -\> P1/P2/P3 request).
3657 _ 0x4 = PHY_PWR_A (delay for internal logic).
3658 _ 0x5 = PHY_PWR_B (wait for Phy_Status(Power-state change request)).
3659
3660 _ \<10:9\> Power down.
3661 _ \<8\> RxEq train.
3662 _ \<7:6\> TX de-emphasis.
3663 _ \<5:3\> LTSSM clock state.
3664 _ 0x0 = CLK_NORM (PHY is in non-P3 state and PCLK is running).
3665 _ 0x1 = CLK_TO_P3 (P3 entry request to PHY).
3666 _ 0x2 = CLK_WAIT1 (wait for Phy_Status (P3 request)).
3667 _ 0x3 = CLK_P3 (PHY is in P3 and PCLK is not running).
3668 _ 0x4 = CLK_TO_P0 (P3 exit request to PHY).
3669 _ 0x5 = CLK_WAIT2 (Wait for Phy_Status (P3 exit request)).
3670
3671 _ \<2\> TX swing.
3672 _ \<1\> RX termination.
3673 _ \<0\> TX 1s/0s. */
3674 uint32_t ltdbsubstate : 4; /**< [ 21: 18](RO/H) LTDB substate. */
3675 uint32_t ltdblinkstate : 4; /**< [ 25: 22](RO/H) LTDB link state. */
3676 uint32_t ltdbtimeout : 1; /**< [ 26: 26](RO/H) LTDB timeout. */
3677 uint32_t reserved_27_31 : 5;
3678 #endif /* Word 0 - End */
3679 } s;
3680 /* struct bdk_usbdrdx_uahc_gdbgltssm_s cn; */
3681 };
3682 typedef union bdk_usbdrdx_uahc_gdbgltssm bdk_usbdrdx_uahc_gdbgltssm_t;
3683
3684 static inline uint64_t BDK_USBDRDX_UAHC_GDBGLTSSM(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GDBGLTSSM(unsigned long a)3685 static inline uint64_t BDK_USBDRDX_UAHC_GDBGLTSSM(unsigned long a)
3686 {
3687 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3688 return 0x86800000c164ll + 0x1000000000ll * ((a) & 0x1);
3689 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3690 return 0x86800000c164ll + 0x1000000000ll * ((a) & 0x1);
3691 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3692 return 0x86800000c164ll + 0x1000000000ll * ((a) & 0x1);
3693 __bdk_csr_fatal("USBDRDX_UAHC_GDBGLTSSM", 1, a, 0, 0, 0);
3694 }
3695
3696 #define typedef_BDK_USBDRDX_UAHC_GDBGLTSSM(a) bdk_usbdrdx_uahc_gdbgltssm_t
3697 #define bustype_BDK_USBDRDX_UAHC_GDBGLTSSM(a) BDK_CSR_TYPE_NCB32b
3698 #define basename_BDK_USBDRDX_UAHC_GDBGLTSSM(a) "USBDRDX_UAHC_GDBGLTSSM"
3699 #define device_bar_BDK_USBDRDX_UAHC_GDBGLTSSM(a) 0x0 /* PF_BAR0 */
3700 #define busnum_BDK_USBDRDX_UAHC_GDBGLTSSM(a) (a)
3701 #define arguments_BDK_USBDRDX_UAHC_GDBGLTSSM(a) (a),-1,-1,-1
3702
3703 /**
3704 * Register (NCB32b) usbdrd#_uahc_gdmahlratio
3705 *
3706 * USB UAHC DMA High/Low Ratio Register
3707 * This register specifies the relative priority of the SuperSpeed FIFOs with respect to the
3708 * high-speed/full-speed/low-speed FIFOs. The DMA arbiter prioritizes the high-speed/full-speed
3709 * /low-speed round-robin arbiter group every DMA high-low priority ratio grants as indicated in
3710 * the register separately for TX and RX.
3711 *
3712 * To illustrate, consider that all FIFOs are requesting access simultaneously, and the ratio is
3713 * 4. SuperSpeed gets priority for four packets, high-speed/full-speed/low-speed gets priority
3714 * for one packet, SuperSpeed gets priority for four packets, high-speed/full-speed/low-speed
3715 * gets priority for one packet, and so on.
3716 *
3717 * If FIFOs from both speed groups are not requesting access simultaneously then:
3718 * * If SuperSpeed got grants four out of the last four times, then high-speed/full-speed/
3719 * low-speed get the priority on any future request.
3720 * * If high-speed/full-speed/low-speed got the grant last time, SuperSpeed gets the priority on
3721 * the next request.
3722 *
3723 * If there is a valid request on either SuperSpeed or high-speed/full-speed/low-speed, a grant
3724 * is always awarded; there is no idle.
3725 *
3726 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3727 *
3728 * Internal:
3729 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.63
3730 */
3731 union bdk_usbdrdx_uahc_gdmahlratio
3732 {
3733 uint32_t u;
3734 struct bdk_usbdrdx_uahc_gdmahlratio_s
3735 {
3736 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3737 uint32_t reserved_13_31 : 19;
3738 uint32_t rx_ratio : 5; /**< [ 12: 8](R/W) Speed ratio for RX arbitration. */
3739 uint32_t reserved_5_7 : 3;
3740 uint32_t tx_ratio : 5; /**< [ 4: 0](R/W) Speed ratio for TX arbitration. */
3741 #else /* Word 0 - Little Endian */
3742 uint32_t tx_ratio : 5; /**< [ 4: 0](R/W) Speed ratio for TX arbitration. */
3743 uint32_t reserved_5_7 : 3;
3744 uint32_t rx_ratio : 5; /**< [ 12: 8](R/W) Speed ratio for RX arbitration. */
3745 uint32_t reserved_13_31 : 19;
3746 #endif /* Word 0 - End */
3747 } s;
3748 /* struct bdk_usbdrdx_uahc_gdmahlratio_s cn; */
3749 };
3750 typedef union bdk_usbdrdx_uahc_gdmahlratio bdk_usbdrdx_uahc_gdmahlratio_t;
3751
3752 static inline uint64_t BDK_USBDRDX_UAHC_GDMAHLRATIO(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GDMAHLRATIO(unsigned long a)3753 static inline uint64_t BDK_USBDRDX_UAHC_GDMAHLRATIO(unsigned long a)
3754 {
3755 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3756 return 0x86800000c624ll + 0x1000000000ll * ((a) & 0x1);
3757 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
3758 return 0x86800000c624ll + 0x1000000000ll * ((a) & 0x1);
3759 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
3760 return 0x86800000c624ll + 0x1000000000ll * ((a) & 0x1);
3761 __bdk_csr_fatal("USBDRDX_UAHC_GDMAHLRATIO", 1, a, 0, 0, 0);
3762 }
3763
3764 #define typedef_BDK_USBDRDX_UAHC_GDMAHLRATIO(a) bdk_usbdrdx_uahc_gdmahlratio_t
3765 #define bustype_BDK_USBDRDX_UAHC_GDMAHLRATIO(a) BDK_CSR_TYPE_NCB32b
3766 #define basename_BDK_USBDRDX_UAHC_GDMAHLRATIO(a) "USBDRDX_UAHC_GDMAHLRATIO"
3767 #define device_bar_BDK_USBDRDX_UAHC_GDMAHLRATIO(a) 0x0 /* PF_BAR0 */
3768 #define busnum_BDK_USBDRDX_UAHC_GDMAHLRATIO(a) (a)
3769 #define arguments_BDK_USBDRDX_UAHC_GDMAHLRATIO(a) (a),-1,-1,-1
3770
3771 /**
3772 * Register (NCB) usbdrd#_uahc_gevntadr#
3773 *
3774 * USB UAHC Global Event Buffer Address Register
3775 * This register holds the event buffer DMA address pointer. Software must initialize this
3776 * address once during power-on initialization. Software must not change the value of this
3777 * register after it is initialized.
3778 * Software must only use the GEVNTCOUNTn register for event processing. The lower n bits of the
3779 * address must be USBDRD()_UAHC_GEVNTSIZ()[EVNTSIZ]-aligned.
3780 *
3781 * This register can be reset by IOI reset,
3782 * or USBDRD()_UCTL_CTL[UAHC_RST],
3783 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
3784 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
3785 *
3786 * Internal:
3787 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.53.
3788 */
3789 union bdk_usbdrdx_uahc_gevntadrx
3790 {
3791 uint64_t u;
3792 struct bdk_usbdrdx_uahc_gevntadrx_s
3793 {
3794 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3795 uint64_t evntadr : 64; /**< [ 63: 0](R/W/H) Holds the start address of the external memory
3796 for the event buffer. During operation, hardware does not update
3797 this address. */
3798 #else /* Word 0 - Little Endian */
3799 uint64_t evntadr : 64; /**< [ 63: 0](R/W/H) Holds the start address of the external memory
3800 for the event buffer. During operation, hardware does not update
3801 this address. */
3802 #endif /* Word 0 - End */
3803 } s;
3804 /* struct bdk_usbdrdx_uahc_gevntadrx_s cn; */
3805 };
3806 typedef union bdk_usbdrdx_uahc_gevntadrx bdk_usbdrdx_uahc_gevntadrx_t;
3807
3808 static inline uint64_t BDK_USBDRDX_UAHC_GEVNTADRX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GEVNTADRX(unsigned long a,unsigned long b)3809 static inline uint64_t BDK_USBDRDX_UAHC_GEVNTADRX(unsigned long a, unsigned long b)
3810 {
3811 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
3812 return 0x86800000c400ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3813 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
3814 return 0x86800000c400ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3815 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
3816 return 0x86800000c400ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3817 __bdk_csr_fatal("USBDRDX_UAHC_GEVNTADRX", 2, a, b, 0, 0);
3818 }
3819
3820 #define typedef_BDK_USBDRDX_UAHC_GEVNTADRX(a,b) bdk_usbdrdx_uahc_gevntadrx_t
3821 #define bustype_BDK_USBDRDX_UAHC_GEVNTADRX(a,b) BDK_CSR_TYPE_NCB
3822 #define basename_BDK_USBDRDX_UAHC_GEVNTADRX(a,b) "USBDRDX_UAHC_GEVNTADRX"
3823 #define device_bar_BDK_USBDRDX_UAHC_GEVNTADRX(a,b) 0x0 /* PF_BAR0 */
3824 #define busnum_BDK_USBDRDX_UAHC_GEVNTADRX(a,b) (a)
3825 #define arguments_BDK_USBDRDX_UAHC_GEVNTADRX(a,b) (a),(b),-1,-1
3826
3827 /**
3828 * Register (NCB32b) usbdrd#_uahc_gevntcount#
3829 *
3830 * USB UAHC Global Event Buffer Count Register
3831 * This register holds the number of valid bytes in the event buffer. During initialization,
3832 * software must initialize the count by writing 0 to the event count field. Each time the
3833 * hardware writes a new event to the event buffer, it increments this count. Most events
3834 * are four bytes, but some events may span over multiple four byte entries. Whenever the
3835 * count is greater than zero, the hardware raises the corresponding interrupt
3836 * line (depending on the USBDRD()_UAHC_GEVNTSIZ()[EVNTINTMASK]). On an interrupt, software
3837 * processes one or more events out of the event buffer. Afterwards, software must write the
3838 * event count field with the number of bytes it processed.
3839 *
3840 * Clock crossing delays may result in the interrupt's continual assertion after software
3841 * acknowledges the last event. Therefore, when the interrupt line is asserted, software must
3842 * read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0.
3843 *
3844 * This register can be reset by IOI reset,
3845 * or USBDRD()_UCTL_CTL[UAHC_RST],
3846 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
3847 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
3848 *
3849 * Internal:
3850 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.57
3851 */
3852 union bdk_usbdrdx_uahc_gevntcountx
3853 {
3854 uint32_t u;
3855 struct bdk_usbdrdx_uahc_gevntcountx_s
3856 {
3857 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3858 uint32_t reserved_16_31 : 16;
3859 uint32_t evntcount : 16; /**< [ 15: 0](R/W/H) When read, returns the number of valid events in the event buffer (in bytes).
3860 When written, hardware decrements the count by the value written.
3861 The interrupt line remains high when count is not 0. */
3862 #else /* Word 0 - Little Endian */
3863 uint32_t evntcount : 16; /**< [ 15: 0](R/W/H) When read, returns the number of valid events in the event buffer (in bytes).
3864 When written, hardware decrements the count by the value written.
3865 The interrupt line remains high when count is not 0. */
3866 uint32_t reserved_16_31 : 16;
3867 #endif /* Word 0 - End */
3868 } s;
3869 /* struct bdk_usbdrdx_uahc_gevntcountx_s cn; */
3870 };
3871 typedef union bdk_usbdrdx_uahc_gevntcountx bdk_usbdrdx_uahc_gevntcountx_t;
3872
3873 static inline uint64_t BDK_USBDRDX_UAHC_GEVNTCOUNTX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GEVNTCOUNTX(unsigned long a,unsigned long b)3874 static inline uint64_t BDK_USBDRDX_UAHC_GEVNTCOUNTX(unsigned long a, unsigned long b)
3875 {
3876 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
3877 return 0x86800000c40cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3878 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
3879 return 0x86800000c40cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3880 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
3881 return 0x86800000c40cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3882 __bdk_csr_fatal("USBDRDX_UAHC_GEVNTCOUNTX", 2, a, b, 0, 0);
3883 }
3884
3885 #define typedef_BDK_USBDRDX_UAHC_GEVNTCOUNTX(a,b) bdk_usbdrdx_uahc_gevntcountx_t
3886 #define bustype_BDK_USBDRDX_UAHC_GEVNTCOUNTX(a,b) BDK_CSR_TYPE_NCB32b
3887 #define basename_BDK_USBDRDX_UAHC_GEVNTCOUNTX(a,b) "USBDRDX_UAHC_GEVNTCOUNTX"
3888 #define device_bar_BDK_USBDRDX_UAHC_GEVNTCOUNTX(a,b) 0x0 /* PF_BAR0 */
3889 #define busnum_BDK_USBDRDX_UAHC_GEVNTCOUNTX(a,b) (a)
3890 #define arguments_BDK_USBDRDX_UAHC_GEVNTCOUNTX(a,b) (a),(b),-1,-1
3891
3892 /**
3893 * Register (NCB32b) usbdrd#_uahc_gevntsiz#
3894 *
3895 * USB UAHC Global Event Buffer Size Register
3896 * This register holds the event buffer size and the event interrupt mask bit. During power-on
3897 * initialization, software must initialize the size with the number of bytes allocated for
3898 * the event buffer. The event interrupt mask will mask the interrupt, but events are still
3899 * queued. After configuration, software must preserve the event buffer size value when
3900 * changing the event interrupt mask.
3901 *
3902 * This register can be reset by IOI reset,
3903 * or USBDRD()_UCTL_CTL[UAHC_RST],
3904 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
3905 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
3906 *
3907 * Internal:
3908 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.56
3909 */
3910 union bdk_usbdrdx_uahc_gevntsizx
3911 {
3912 uint32_t u;
3913 struct bdk_usbdrdx_uahc_gevntsizx_s
3914 {
3915 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3916 uint32_t evntintmask : 1; /**< [ 31: 31](R/W) When set to 1, this prevents the interrupt from being generated.
3917 However, even when the mask is set, the events are queued. */
3918 uint32_t reserved_16_30 : 15;
3919 uint32_t evntsiz : 16; /**< [ 15: 0](R/W) Holds the size of the event buffer in bytes; must be a multiple of
3920 four. This is programmed by software once during initialization.
3921 The minimum size of the event buffer is 32 bytes. */
3922 #else /* Word 0 - Little Endian */
3923 uint32_t evntsiz : 16; /**< [ 15: 0](R/W) Holds the size of the event buffer in bytes; must be a multiple of
3924 four. This is programmed by software once during initialization.
3925 The minimum size of the event buffer is 32 bytes. */
3926 uint32_t reserved_16_30 : 15;
3927 uint32_t evntintmask : 1; /**< [ 31: 31](R/W) When set to 1, this prevents the interrupt from being generated.
3928 However, even when the mask is set, the events are queued. */
3929 #endif /* Word 0 - End */
3930 } s;
3931 /* struct bdk_usbdrdx_uahc_gevntsizx_s cn; */
3932 };
3933 typedef union bdk_usbdrdx_uahc_gevntsizx bdk_usbdrdx_uahc_gevntsizx_t;
3934
3935 static inline uint64_t BDK_USBDRDX_UAHC_GEVNTSIZX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GEVNTSIZX(unsigned long a,unsigned long b)3936 static inline uint64_t BDK_USBDRDX_UAHC_GEVNTSIZX(unsigned long a, unsigned long b)
3937 {
3938 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
3939 return 0x86800000c408ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3940 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
3941 return 0x86800000c408ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3942 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
3943 return 0x86800000c408ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
3944 __bdk_csr_fatal("USBDRDX_UAHC_GEVNTSIZX", 2, a, b, 0, 0);
3945 }
3946
3947 #define typedef_BDK_USBDRDX_UAHC_GEVNTSIZX(a,b) bdk_usbdrdx_uahc_gevntsizx_t
3948 #define bustype_BDK_USBDRDX_UAHC_GEVNTSIZX(a,b) BDK_CSR_TYPE_NCB32b
3949 #define basename_BDK_USBDRDX_UAHC_GEVNTSIZX(a,b) "USBDRDX_UAHC_GEVNTSIZX"
3950 #define device_bar_BDK_USBDRDX_UAHC_GEVNTSIZX(a,b) 0x0 /* PF_BAR0 */
3951 #define busnum_BDK_USBDRDX_UAHC_GEVNTSIZX(a,b) (a)
3952 #define arguments_BDK_USBDRDX_UAHC_GEVNTSIZX(a,b) (a),(b),-1,-1
3953
3954 /**
3955 * Register (NCB32b) usbdrd#_uahc_gfladj
3956 *
3957 * USB UAHC Global Frame Length Adjustment Register
3958 * This register provides options for the software to control the core behavior with respect to
3959 * SOF (start of frame) and ITP (isochronous timestamp packet) timers and frame timer
3960 * functionality. It provides the option to override the sideband signal fladj_30mhz_reg. In
3961 * addition, it enables running SOF or ITP frame timer counters completely off of the REF_CLK.
3962 * This facilitates hardware LPM in host mode with the SOF or ITP counters being run off of the
3963 * REF_CLK signal.
3964 *
3965 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
3966 *
3967 * Internal:
3968 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.64
3969 */
3970 union bdk_usbdrdx_uahc_gfladj
3971 {
3972 uint32_t u;
3973 struct bdk_usbdrdx_uahc_gfladj_s
3974 {
3975 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3976 uint32_t gfladj_refclk_240mhzdecr_pls1 : 1;/**< [ 31: 31](R/W) This field indicates that the decrement value that the controller applies for each REF_CLK
3977 must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each
3978 REF_CLK. Set this bit to 1 only if [GFLADJ_REFCLK_LPM_SEL] is set to 1 and the fractional
3979 component of 240/ref_frequency is greater than or equal to 0.5.
3980
3981 Example:
3982
3983 If the REF_CLK is 19.2 MHz then:
3984 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 52.
3985 * [GFLADJ_REFCLK_240MHZ_DECR] = (240/19.2) = 12.5.
3986 * [GFLADJ_REFCLK_240MHZDECR_PLS1] = 1.
3987
3988 If the REF_CLK is 24 MHz then:
3989 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 41.
3990 * [GFLADJ_REFCLK_240MHZ_DECR] = (240/24) = 10.
3991 * [GFLADJ_REFCLK_240MHZDECR_PLS1] = 0. */
3992 uint32_t gfladj_refclk_240mhz_decr : 7;/**< [ 30: 24](R/W) This field indicates the decrement value that the controller applies for each REF_CLK in
3993 order to derive a frame timer in terms of a 240-MHz clock. This field must be programmed
3994 to a nonzero value only if [GFLADJ_REFCLK_LPM_SEL] is set to 1.
3995
3996 The value is derived as follows:
3997 _ [GFLADJ_REFCLK_240MHZ_DECR] = 240/ref_clk_frequency
3998
3999 Examples:
4000
4001 If the REF_CLK is 24 MHz then:
4002 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 41.
4003 * [GFLADJ_REFCLK_240MHZ_DECR] = 240/24 = 10.
4004
4005 If the REF_CLK is 48 MHz then:
4006 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 20.
4007 * [GFLADJ_REFCLK_240MHZ_DECR] = 240/48 = 5.
4008
4009 If the REF_CLK is 17 MHz then:
4010 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 58.
4011 * [GFLADJ_REFCLK_240MHZ_DECR] = 240/17 = 14. */
4012 uint32_t gfladj_refclk_lpm_sel : 1; /**< [ 23: 23](R/W) This bit enables the functionality of running SOF/ITP counters on the REF_CLK.
4013 This bit must not be set to 1 if USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1. Similarly, if
4014 [GFLADJ_REFCLK_LPM_SEL] = 1, USBDRD()_UAHC_GCTL[SOFITPSYNC] must not be set to 1.
4015 When [GFLADJ_REFCLK_LPM_SEL] = 1 the overloading of the suspend control of the USB 2.0
4016 first
4017 port PHY (UTMI) with USB 3.0 port states is removed. Note that the REF_CLK frequencies
4018 supported in this mode are 16/17/19.2/20/24/39.7/40 MHz.
4019
4020 Internal:
4021 The utmi_clk[0] signal of the core must be connected to the FREECLK of the PHY.
4022 If you set this bit to 1, USBDRD()_UAHC_GUSB2PHYCFG()[U2_FREECLK_EXISTS] must be set to 0. */
4023 uint32_t reserved_22 : 1;
4024 uint32_t gfladj_refclk_fladj : 14; /**< [ 21: 8](R/W) This field indicates the frame length adjustment to be applied when SOF/ITP counter is
4025 running off of the REF_CLK. This register value is used to adjust:.
4026 * ITP interval when USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1
4027 * both SOF and ITP interval when [GFLADJ_REFCLK_LPM_SEL] = 1.
4028
4029 This field must be programmed to a nonzero value only if [GFLADJ_REFCLK_LPM_SEL] = 1 or
4030 USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1.
4031
4032 The value is derived as below:
4033
4034 _ FLADJ_REF_CLK_FLADJ = ((125000/ref_clk_period_integer) - (125000/ref_clk_period)) *
4035 ref_clk_period
4036
4037 where,
4038 * the ref_clk_period_integer is the integer value of the REF_CLK period got by truncating
4039 the decimal (fractional) value that is programmed in USBDRD()_UAHC_GUCTL[REFCLKPER].
4040 * the ref_clk_period is the REF_CLK period including the fractional value.
4041
4042 Examples:
4043
4044 If the REF_CLK is 24 MHz then:
4045 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 41.
4046 * GLADJ_REFCLK_FLADJ = ((125000/41) -
4047 (125000/41.6666)) * 41.6666 = 2032 (ignoring the fractional value).
4048
4049 If the REF_CLK is 48 MHz then:
4050 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 20.
4051 * GLADJ_REFCLK_FLADJ = ((125000/20) -
4052 (125000/20.8333)) * 20.8333 = 5208 (ignoring the fractional value). */
4053 uint32_t gfladj_30mhz_reg_sel : 1; /**< [ 7: 7](R/W) This field selects whether to use the input signal fladj_30mhz_reg or the [GFLADJ_30MHZ]
4054 to
4055 adjust the frame length for the SOF/ITP. When this bit is set to, 1, the controller uses
4056 [GFLADJ_30MHZ] value 0x0, the controller uses the input signal fladj_30mhz_reg value. */
4057 uint32_t reserved_6 : 1;
4058 uint32_t gfladj_30mhz : 6; /**< [ 5: 0](R/W) This field indicates the value that is used for frame length adjustment instead of
4059 considering from the sideband input signal fladj_30mhz_reg. This enables post-silicon
4060 frame length adjustment in case the input signal fladj_30mhz_reg is connected to a wrong
4061 value or is not valid. The controller uses this value if [GFLADJ_30MHZ_REG_SEL] = 1 and
4062 the
4063 SOF/ITP counters are running off of UTMI(ULPI) clock ([GFLADJ_REFCLK_LPM_SEL] = 0 and
4064 USBDRD()_UAHC_GCTL[SOFITPSYNC] is 1 or 0). For details on how to set this value, refer to
4065 section 5.2.4 Frame Length Adjustment Register (FLADJ) of the xHCI Specification. */
4066 #else /* Word 0 - Little Endian */
4067 uint32_t gfladj_30mhz : 6; /**< [ 5: 0](R/W) This field indicates the value that is used for frame length adjustment instead of
4068 considering from the sideband input signal fladj_30mhz_reg. This enables post-silicon
4069 frame length adjustment in case the input signal fladj_30mhz_reg is connected to a wrong
4070 value or is not valid. The controller uses this value if [GFLADJ_30MHZ_REG_SEL] = 1 and
4071 the
4072 SOF/ITP counters are running off of UTMI(ULPI) clock ([GFLADJ_REFCLK_LPM_SEL] = 0 and
4073 USBDRD()_UAHC_GCTL[SOFITPSYNC] is 1 or 0). For details on how to set this value, refer to
4074 section 5.2.4 Frame Length Adjustment Register (FLADJ) of the xHCI Specification. */
4075 uint32_t reserved_6 : 1;
4076 uint32_t gfladj_30mhz_reg_sel : 1; /**< [ 7: 7](R/W) This field selects whether to use the input signal fladj_30mhz_reg or the [GFLADJ_30MHZ]
4077 to
4078 adjust the frame length for the SOF/ITP. When this bit is set to, 1, the controller uses
4079 [GFLADJ_30MHZ] value 0x0, the controller uses the input signal fladj_30mhz_reg value. */
4080 uint32_t gfladj_refclk_fladj : 14; /**< [ 21: 8](R/W) This field indicates the frame length adjustment to be applied when SOF/ITP counter is
4081 running off of the REF_CLK. This register value is used to adjust:.
4082 * ITP interval when USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1
4083 * both SOF and ITP interval when [GFLADJ_REFCLK_LPM_SEL] = 1.
4084
4085 This field must be programmed to a nonzero value only if [GFLADJ_REFCLK_LPM_SEL] = 1 or
4086 USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1.
4087
4088 The value is derived as below:
4089
4090 _ FLADJ_REF_CLK_FLADJ = ((125000/ref_clk_period_integer) - (125000/ref_clk_period)) *
4091 ref_clk_period
4092
4093 where,
4094 * the ref_clk_period_integer is the integer value of the REF_CLK period got by truncating
4095 the decimal (fractional) value that is programmed in USBDRD()_UAHC_GUCTL[REFCLKPER].
4096 * the ref_clk_period is the REF_CLK period including the fractional value.
4097
4098 Examples:
4099
4100 If the REF_CLK is 24 MHz then:
4101 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 41.
4102 * GLADJ_REFCLK_FLADJ = ((125000/41) -
4103 (125000/41.6666)) * 41.6666 = 2032 (ignoring the fractional value).
4104
4105 If the REF_CLK is 48 MHz then:
4106 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 20.
4107 * GLADJ_REFCLK_FLADJ = ((125000/20) -
4108 (125000/20.8333)) * 20.8333 = 5208 (ignoring the fractional value). */
4109 uint32_t reserved_22 : 1;
4110 uint32_t gfladj_refclk_lpm_sel : 1; /**< [ 23: 23](R/W) This bit enables the functionality of running SOF/ITP counters on the REF_CLK.
4111 This bit must not be set to 1 if USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1. Similarly, if
4112 [GFLADJ_REFCLK_LPM_SEL] = 1, USBDRD()_UAHC_GCTL[SOFITPSYNC] must not be set to 1.
4113 When [GFLADJ_REFCLK_LPM_SEL] = 1 the overloading of the suspend control of the USB 2.0
4114 first
4115 port PHY (UTMI) with USB 3.0 port states is removed. Note that the REF_CLK frequencies
4116 supported in this mode are 16/17/19.2/20/24/39.7/40 MHz.
4117
4118 Internal:
4119 The utmi_clk[0] signal of the core must be connected to the FREECLK of the PHY.
4120 If you set this bit to 1, USBDRD()_UAHC_GUSB2PHYCFG()[U2_FREECLK_EXISTS] must be set to 0. */
4121 uint32_t gfladj_refclk_240mhz_decr : 7;/**< [ 30: 24](R/W) This field indicates the decrement value that the controller applies for each REF_CLK in
4122 order to derive a frame timer in terms of a 240-MHz clock. This field must be programmed
4123 to a nonzero value only if [GFLADJ_REFCLK_LPM_SEL] is set to 1.
4124
4125 The value is derived as follows:
4126 _ [GFLADJ_REFCLK_240MHZ_DECR] = 240/ref_clk_frequency
4127
4128 Examples:
4129
4130 If the REF_CLK is 24 MHz then:
4131 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 41.
4132 * [GFLADJ_REFCLK_240MHZ_DECR] = 240/24 = 10.
4133
4134 If the REF_CLK is 48 MHz then:
4135 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 20.
4136 * [GFLADJ_REFCLK_240MHZ_DECR] = 240/48 = 5.
4137
4138 If the REF_CLK is 17 MHz then:
4139 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 58.
4140 * [GFLADJ_REFCLK_240MHZ_DECR] = 240/17 = 14. */
4141 uint32_t gfladj_refclk_240mhzdecr_pls1 : 1;/**< [ 31: 31](R/W) This field indicates that the decrement value that the controller applies for each REF_CLK
4142 must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each
4143 REF_CLK. Set this bit to 1 only if [GFLADJ_REFCLK_LPM_SEL] is set to 1 and the fractional
4144 component of 240/ref_frequency is greater than or equal to 0.5.
4145
4146 Example:
4147
4148 If the REF_CLK is 19.2 MHz then:
4149 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 52.
4150 * [GFLADJ_REFCLK_240MHZ_DECR] = (240/19.2) = 12.5.
4151 * [GFLADJ_REFCLK_240MHZDECR_PLS1] = 1.
4152
4153 If the REF_CLK is 24 MHz then:
4154 * USBDRD()_UAHC_GUCTL[REFCLKPER] = 41.
4155 * [GFLADJ_REFCLK_240MHZ_DECR] = (240/24) = 10.
4156 * [GFLADJ_REFCLK_240MHZDECR_PLS1] = 0. */
4157 #endif /* Word 0 - End */
4158 } s;
4159 /* struct bdk_usbdrdx_uahc_gfladj_s cn; */
4160 };
4161 typedef union bdk_usbdrdx_uahc_gfladj bdk_usbdrdx_uahc_gfladj_t;
4162
4163 static inline uint64_t BDK_USBDRDX_UAHC_GFLADJ(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GFLADJ(unsigned long a)4164 static inline uint64_t BDK_USBDRDX_UAHC_GFLADJ(unsigned long a)
4165 {
4166 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4167 return 0x86800000c630ll + 0x1000000000ll * ((a) & 0x1);
4168 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4169 return 0x86800000c630ll + 0x1000000000ll * ((a) & 0x1);
4170 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4171 return 0x86800000c630ll + 0x1000000000ll * ((a) & 0x1);
4172 __bdk_csr_fatal("USBDRDX_UAHC_GFLADJ", 1, a, 0, 0, 0);
4173 }
4174
4175 #define typedef_BDK_USBDRDX_UAHC_GFLADJ(a) bdk_usbdrdx_uahc_gfladj_t
4176 #define bustype_BDK_USBDRDX_UAHC_GFLADJ(a) BDK_CSR_TYPE_NCB32b
4177 #define basename_BDK_USBDRDX_UAHC_GFLADJ(a) "USBDRDX_UAHC_GFLADJ"
4178 #define device_bar_BDK_USBDRDX_UAHC_GFLADJ(a) 0x0 /* PF_BAR0 */
4179 #define busnum_BDK_USBDRDX_UAHC_GFLADJ(a) (a)
4180 #define arguments_BDK_USBDRDX_UAHC_GFLADJ(a) (a),-1,-1,-1
4181
4182 /**
4183 * Register (NCB32b) usbdrd#_uahc_ggpio
4184 *
4185 * USB UAHC Core General-Purpose I/O Register
4186 * The application can use this register for general purpose input and output ports or for
4187 * debugging.
4188 *
4189 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
4190 *
4191 * Internal:
4192 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.10
4193 */
4194 union bdk_usbdrdx_uahc_ggpio
4195 {
4196 uint32_t u;
4197 struct bdk_usbdrdx_uahc_ggpio_s
4198 {
4199 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4200 uint32_t gpo : 16; /**< [ 31: 16](R/W) General purpose output. These outputs are not connected to anything. Can be used as scratch. */
4201 uint32_t gpi : 16; /**< [ 15: 0](RO) General purpose input. These inputs are tied 0x0. */
4202 #else /* Word 0 - Little Endian */
4203 uint32_t gpi : 16; /**< [ 15: 0](RO) General purpose input. These inputs are tied 0x0. */
4204 uint32_t gpo : 16; /**< [ 31: 16](R/W) General purpose output. These outputs are not connected to anything. Can be used as scratch. */
4205 #endif /* Word 0 - End */
4206 } s;
4207 /* struct bdk_usbdrdx_uahc_ggpio_s cn; */
4208 };
4209 typedef union bdk_usbdrdx_uahc_ggpio bdk_usbdrdx_uahc_ggpio_t;
4210
4211 static inline uint64_t BDK_USBDRDX_UAHC_GGPIO(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GGPIO(unsigned long a)4212 static inline uint64_t BDK_USBDRDX_UAHC_GGPIO(unsigned long a)
4213 {
4214 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4215 return 0x86800000c124ll + 0x1000000000ll * ((a) & 0x1);
4216 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4217 return 0x86800000c124ll + 0x1000000000ll * ((a) & 0x1);
4218 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4219 return 0x86800000c124ll + 0x1000000000ll * ((a) & 0x1);
4220 __bdk_csr_fatal("USBDRDX_UAHC_GGPIO", 1, a, 0, 0, 0);
4221 }
4222
4223 #define typedef_BDK_USBDRDX_UAHC_GGPIO(a) bdk_usbdrdx_uahc_ggpio_t
4224 #define bustype_BDK_USBDRDX_UAHC_GGPIO(a) BDK_CSR_TYPE_NCB32b
4225 #define basename_BDK_USBDRDX_UAHC_GGPIO(a) "USBDRDX_UAHC_GGPIO"
4226 #define device_bar_BDK_USBDRDX_UAHC_GGPIO(a) 0x0 /* PF_BAR0 */
4227 #define busnum_BDK_USBDRDX_UAHC_GGPIO(a) (a)
4228 #define arguments_BDK_USBDRDX_UAHC_GGPIO(a) (a),-1,-1,-1
4229
4230 /**
4231 * Register (NCB32b) usbdrd#_uahc_ghwparams0
4232 *
4233 * USB UAHC Hardware Parameters Register 0
4234 * This register contains the hardware configuration options selected at compile-time.
4235 * Internal:
4236 * Register field names refer to Synopsys DWC_USB3_* parameters of the same suffix.
4237 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.19
4238 */
4239 union bdk_usbdrdx_uahc_ghwparams0
4240 {
4241 uint32_t u;
4242 struct bdk_usbdrdx_uahc_ghwparams0_s
4243 {
4244 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4245 uint32_t awidth : 8; /**< [ 31: 24](RO) USB core bus-address width. */
4246 uint32_t sdwidth : 8; /**< [ 23: 16](RO) USB core bus slave-data width. */
4247 uint32_t mdwidth : 8; /**< [ 15: 8](RO) USB core bus master-data width. */
4248 uint32_t sbus_type : 2; /**< [ 7: 6](RO) USB core bus slave type: AXI. */
4249 uint32_t mbus_type : 3; /**< [ 5: 3](RO) USB core bus master type: AXI. */
4250 uint32_t mode : 3; /**< [ 2: 0](RO) Operation mode: 0x2: Dual-role device. */
4251 #else /* Word 0 - Little Endian */
4252 uint32_t mode : 3; /**< [ 2: 0](RO) Operation mode: 0x2: Dual-role device. */
4253 uint32_t mbus_type : 3; /**< [ 5: 3](RO) USB core bus master type: AXI. */
4254 uint32_t sbus_type : 2; /**< [ 7: 6](RO) USB core bus slave type: AXI. */
4255 uint32_t mdwidth : 8; /**< [ 15: 8](RO) USB core bus master-data width. */
4256 uint32_t sdwidth : 8; /**< [ 23: 16](RO) USB core bus slave-data width. */
4257 uint32_t awidth : 8; /**< [ 31: 24](RO) USB core bus-address width. */
4258 #endif /* Word 0 - End */
4259 } s;
4260 /* struct bdk_usbdrdx_uahc_ghwparams0_s cn; */
4261 };
4262 typedef union bdk_usbdrdx_uahc_ghwparams0 bdk_usbdrdx_uahc_ghwparams0_t;
4263
4264 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS0(unsigned long a)4265 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS0(unsigned long a)
4266 {
4267 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4268 return 0x86800000c140ll + 0x1000000000ll * ((a) & 0x1);
4269 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4270 return 0x86800000c140ll + 0x1000000000ll * ((a) & 0x1);
4271 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4272 return 0x86800000c140ll + 0x1000000000ll * ((a) & 0x1);
4273 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS0", 1, a, 0, 0, 0);
4274 }
4275
4276 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS0(a) bdk_usbdrdx_uahc_ghwparams0_t
4277 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS0(a) BDK_CSR_TYPE_NCB32b
4278 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS0(a) "USBDRDX_UAHC_GHWPARAMS0"
4279 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS0(a) 0x0 /* PF_BAR0 */
4280 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS0(a) (a)
4281 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS0(a) (a),-1,-1,-1
4282
4283 /**
4284 * Register (NCB32b) usbdrd#_uahc_ghwparams1
4285 *
4286 * USB UAHC Hardware Parameters Register 1
4287 * This register contains the hardware configuration options selected at compile-time.
4288 * Internal:
4289 * Register field names refer to Synopsys DWC_USB3_* parameters of the same suffix.
4290 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.20
4291 */
4292 union bdk_usbdrdx_uahc_ghwparams1
4293 {
4294 uint32_t u;
4295 struct bdk_usbdrdx_uahc_ghwparams1_s
4296 {
4297 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4298 uint32_t en_dbc : 1; /**< [ 31: 31](RAZ) Enable debug capability. */
4299 uint32_t rm_opt_features : 1; /**< [ 30: 30](RO) Remove optional features. */
4300 uint32_t sync_rst : 1; /**< [ 29: 29](RO) Synchronous reset coding. */
4301 uint32_t ram_bus_clks_sync : 1; /**< [ 28: 28](RO) RAM_CLK and BUS_CLK are synchronous.
4302 Internal:
4303 (appears to be orthogonal from the
4304 RAM_CLK_TO_BUS_CLK parameter) */
4305 uint32_t mac_ram_clks_sync : 1; /**< [ 27: 27](RO) MAC3_CLK and RAM_CLK are synchronous. */
4306 uint32_t mac_phy_clks_sync : 1; /**< [ 26: 26](RO) MAC3_CLK and PHY_CLK are synchronous. */
4307 uint32_t en_pwropt : 2; /**< [ 25: 24](RO) Power optimization mode:
4308 bit\<0\> = Clock-gating feature available.
4309 bit\<1\> = Hibernation feature available. */
4310 uint32_t spram_typ : 1; /**< [ 23: 23](RO) SRAM type: one-port RAMs. */
4311 uint32_t num_rams : 2; /**< [ 22: 21](RO) Number of RAMs. */
4312 uint32_t device_num_int : 6; /**< [ 20: 15](RO) Number of event buffers (and interrupts) in device-mode (unsupported). */
4313 uint32_t aspacewidth : 3; /**< [ 14: 12](RO) Native interface address-space port width. */
4314 uint32_t reqinfowidth : 3; /**< [ 11: 9](RO) Native interface request/response-info port width. */
4315 uint32_t datainfowidth : 3; /**< [ 8: 6](RO) Native interface data-info port width. */
4316 uint32_t burstwidth_m1 : 3; /**< [ 5: 3](RO) Width minus one of AXI length field. */
4317 uint32_t idwidth_m1 : 3; /**< [ 2: 0](RO) Width minus one of AXI ID field. */
4318 #else /* Word 0 - Little Endian */
4319 uint32_t idwidth_m1 : 3; /**< [ 2: 0](RO) Width minus one of AXI ID field. */
4320 uint32_t burstwidth_m1 : 3; /**< [ 5: 3](RO) Width minus one of AXI length field. */
4321 uint32_t datainfowidth : 3; /**< [ 8: 6](RO) Native interface data-info port width. */
4322 uint32_t reqinfowidth : 3; /**< [ 11: 9](RO) Native interface request/response-info port width. */
4323 uint32_t aspacewidth : 3; /**< [ 14: 12](RO) Native interface address-space port width. */
4324 uint32_t device_num_int : 6; /**< [ 20: 15](RO) Number of event buffers (and interrupts) in device-mode (unsupported). */
4325 uint32_t num_rams : 2; /**< [ 22: 21](RO) Number of RAMs. */
4326 uint32_t spram_typ : 1; /**< [ 23: 23](RO) SRAM type: one-port RAMs. */
4327 uint32_t en_pwropt : 2; /**< [ 25: 24](RO) Power optimization mode:
4328 bit\<0\> = Clock-gating feature available.
4329 bit\<1\> = Hibernation feature available. */
4330 uint32_t mac_phy_clks_sync : 1; /**< [ 26: 26](RO) MAC3_CLK and PHY_CLK are synchronous. */
4331 uint32_t mac_ram_clks_sync : 1; /**< [ 27: 27](RO) MAC3_CLK and RAM_CLK are synchronous. */
4332 uint32_t ram_bus_clks_sync : 1; /**< [ 28: 28](RO) RAM_CLK and BUS_CLK are synchronous.
4333 Internal:
4334 (appears to be orthogonal from the
4335 RAM_CLK_TO_BUS_CLK parameter) */
4336 uint32_t sync_rst : 1; /**< [ 29: 29](RO) Synchronous reset coding. */
4337 uint32_t rm_opt_features : 1; /**< [ 30: 30](RO) Remove optional features. */
4338 uint32_t en_dbc : 1; /**< [ 31: 31](RAZ) Enable debug capability. */
4339 #endif /* Word 0 - End */
4340 } s;
4341 /* struct bdk_usbdrdx_uahc_ghwparams1_s cn; */
4342 };
4343 typedef union bdk_usbdrdx_uahc_ghwparams1 bdk_usbdrdx_uahc_ghwparams1_t;
4344
4345 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS1(unsigned long a)4346 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS1(unsigned long a)
4347 {
4348 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4349 return 0x86800000c144ll + 0x1000000000ll * ((a) & 0x1);
4350 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4351 return 0x86800000c144ll + 0x1000000000ll * ((a) & 0x1);
4352 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4353 return 0x86800000c144ll + 0x1000000000ll * ((a) & 0x1);
4354 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS1", 1, a, 0, 0, 0);
4355 }
4356
4357 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS1(a) bdk_usbdrdx_uahc_ghwparams1_t
4358 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS1(a) BDK_CSR_TYPE_NCB32b
4359 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS1(a) "USBDRDX_UAHC_GHWPARAMS1"
4360 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS1(a) 0x0 /* PF_BAR0 */
4361 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS1(a) (a)
4362 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS1(a) (a),-1,-1,-1
4363
4364 /**
4365 * Register (NCB32b) usbdrd#_uahc_ghwparams2
4366 *
4367 * USB UAHC Core GHW Parameters Register 2
4368 * This register contains the hardware configuration options selected at compile-time.
4369 * Internal:
4370 * Register field names refer to Synopsys DWC_USB3_* parameters of the same suffix.
4371 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.21
4372 */
4373 union bdk_usbdrdx_uahc_ghwparams2
4374 {
4375 uint32_t u;
4376 struct bdk_usbdrdx_uahc_ghwparams2_s
4377 {
4378 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4379 uint32_t userid : 32; /**< [ 31: 0](RO) User ID. */
4380 #else /* Word 0 - Little Endian */
4381 uint32_t userid : 32; /**< [ 31: 0](RO) User ID. */
4382 #endif /* Word 0 - End */
4383 } s;
4384 /* struct bdk_usbdrdx_uahc_ghwparams2_s cn; */
4385 };
4386 typedef union bdk_usbdrdx_uahc_ghwparams2 bdk_usbdrdx_uahc_ghwparams2_t;
4387
4388 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS2(unsigned long a)4389 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS2(unsigned long a)
4390 {
4391 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4392 return 0x86800000c148ll + 0x1000000000ll * ((a) & 0x1);
4393 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4394 return 0x86800000c148ll + 0x1000000000ll * ((a) & 0x1);
4395 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4396 return 0x86800000c148ll + 0x1000000000ll * ((a) & 0x1);
4397 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS2", 1, a, 0, 0, 0);
4398 }
4399
4400 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS2(a) bdk_usbdrdx_uahc_ghwparams2_t
4401 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS2(a) BDK_CSR_TYPE_NCB32b
4402 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS2(a) "USBDRDX_UAHC_GHWPARAMS2"
4403 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS2(a) 0x0 /* PF_BAR0 */
4404 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS2(a) (a)
4405 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS2(a) (a),-1,-1,-1
4406
4407 /**
4408 * Register (NCB32b) usbdrd#_uahc_ghwparams3
4409 *
4410 * USB UAHC GHW Parameters Register 3
4411 * This register contains the hardware configuration options selected at compile-time.
4412 * Internal:
4413 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.22
4414 */
4415 union bdk_usbdrdx_uahc_ghwparams3
4416 {
4417 uint32_t u;
4418 struct bdk_usbdrdx_uahc_ghwparams3_s
4419 {
4420 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4421 uint32_t reserved_31 : 1;
4422 uint32_t cache_total_xfer_resources : 8;/**< [ 30: 23](RO) Maximum number of transfer resources in the core. */
4423 uint32_t num_in_eps : 5; /**< [ 22: 18](RO) Maximum number of device-mode IN endpoints active. */
4424 uint32_t num_eps : 6; /**< [ 17: 12](RO) Number of device-mode single-directional endpoints. */
4425 uint32_t ulpi_carkit : 1; /**< [ 11: 11](RO) ULPI carkit is not supported. */
4426 uint32_t vendor_ctl_interface : 1; /**< [ 10: 10](RO) UTMI+ PHY vendor control interface enabled. */
4427 uint32_t reserved_8_9 : 2;
4428 uint32_t hsphy_dwidth : 2; /**< [ 7: 6](RO) Data width of the UTMI+ PHY interface: 0x2 = 8-or-16 bits. */
4429 uint32_t fsphy_interface : 2; /**< [ 5: 4](RO) USB 1.1 full-speed serial transceiver interface. */
4430 uint32_t hsphy_interface : 2; /**< [ 3: 2](RO) High-speed PHY interface: 0x1 = UTMI+. */
4431 uint32_t ssphy_interface : 2; /**< [ 1: 0](RO) SuperSpeed PHY interface: 0x1 = PIPE3. */
4432 #else /* Word 0 - Little Endian */
4433 uint32_t ssphy_interface : 2; /**< [ 1: 0](RO) SuperSpeed PHY interface: 0x1 = PIPE3. */
4434 uint32_t hsphy_interface : 2; /**< [ 3: 2](RO) High-speed PHY interface: 0x1 = UTMI+. */
4435 uint32_t fsphy_interface : 2; /**< [ 5: 4](RO) USB 1.1 full-speed serial transceiver interface. */
4436 uint32_t hsphy_dwidth : 2; /**< [ 7: 6](RO) Data width of the UTMI+ PHY interface: 0x2 = 8-or-16 bits. */
4437 uint32_t reserved_8_9 : 2;
4438 uint32_t vendor_ctl_interface : 1; /**< [ 10: 10](RO) UTMI+ PHY vendor control interface enabled. */
4439 uint32_t ulpi_carkit : 1; /**< [ 11: 11](RO) ULPI carkit is not supported. */
4440 uint32_t num_eps : 6; /**< [ 17: 12](RO) Number of device-mode single-directional endpoints. */
4441 uint32_t num_in_eps : 5; /**< [ 22: 18](RO) Maximum number of device-mode IN endpoints active. */
4442 uint32_t cache_total_xfer_resources : 8;/**< [ 30: 23](RO) Maximum number of transfer resources in the core. */
4443 uint32_t reserved_31 : 1;
4444 #endif /* Word 0 - End */
4445 } s;
4446 /* struct bdk_usbdrdx_uahc_ghwparams3_s cn; */
4447 };
4448 typedef union bdk_usbdrdx_uahc_ghwparams3 bdk_usbdrdx_uahc_ghwparams3_t;
4449
4450 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS3(unsigned long a)4451 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS3(unsigned long a)
4452 {
4453 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4454 return 0x86800000c14cll + 0x1000000000ll * ((a) & 0x1);
4455 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4456 return 0x86800000c14cll + 0x1000000000ll * ((a) & 0x1);
4457 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4458 return 0x86800000c14cll + 0x1000000000ll * ((a) & 0x1);
4459 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS3", 1, a, 0, 0, 0);
4460 }
4461
4462 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS3(a) bdk_usbdrdx_uahc_ghwparams3_t
4463 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS3(a) BDK_CSR_TYPE_NCB32b
4464 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS3(a) "USBDRDX_UAHC_GHWPARAMS3"
4465 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS3(a) 0x0 /* PF_BAR0 */
4466 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS3(a) (a)
4467 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS3(a) (a),-1,-1,-1
4468
4469 /**
4470 * Register (NCB32b) usbdrd#_uahc_ghwparams4
4471 *
4472 * USB UAHC GHW Parameters Register 4
4473 * This register contains the hardware configuration options selected at compile-time.
4474 * Internal:
4475 * Register field names refer to Synopsys DWC_USB3_* parameters of the same suffix.
4476 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.23
4477 */
4478 union bdk_usbdrdx_uahc_ghwparams4
4479 {
4480 uint32_t u;
4481 struct bdk_usbdrdx_uahc_ghwparams4_s
4482 {
4483 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4484 uint32_t bmu_lsp_depth : 4; /**< [ 31: 28](RO) Depth of the BMU-LSP status buffer. */
4485 uint32_t bmu_ptl_depth_m1 : 4; /**< [ 27: 24](RO) Depth of the BMU-PTL source/sink buffers minus 1. */
4486 uint32_t en_isoc_supt : 1; /**< [ 23: 23](RO) Isochronous support enabled. */
4487 uint32_t reserved_22 : 1;
4488 uint32_t ext_buff_control : 1; /**< [ 21: 21](RO) Enables device external buffer control sideband controls. */
4489 uint32_t num_ss_usb_instances : 4; /**< [ 20: 17](RO) Number of SuperSpeed bus instances. */
4490 uint32_t hiber_scratchbufs : 4; /**< [ 16: 13](RO) Number of hibernation scratchpad buffers. */
4491 uint32_t reserved_6_12 : 7;
4492 uint32_t cache_trbs_per_transfer : 6;/**< [ 5: 0](RO) Number of TRBs per transfer that can be cached. */
4493 #else /* Word 0 - Little Endian */
4494 uint32_t cache_trbs_per_transfer : 6;/**< [ 5: 0](RO) Number of TRBs per transfer that can be cached. */
4495 uint32_t reserved_6_12 : 7;
4496 uint32_t hiber_scratchbufs : 4; /**< [ 16: 13](RO) Number of hibernation scratchpad buffers. */
4497 uint32_t num_ss_usb_instances : 4; /**< [ 20: 17](RO) Number of SuperSpeed bus instances. */
4498 uint32_t ext_buff_control : 1; /**< [ 21: 21](RO) Enables device external buffer control sideband controls. */
4499 uint32_t reserved_22 : 1;
4500 uint32_t en_isoc_supt : 1; /**< [ 23: 23](RO) Isochronous support enabled. */
4501 uint32_t bmu_ptl_depth_m1 : 4; /**< [ 27: 24](RO) Depth of the BMU-PTL source/sink buffers minus 1. */
4502 uint32_t bmu_lsp_depth : 4; /**< [ 31: 28](RO) Depth of the BMU-LSP status buffer. */
4503 #endif /* Word 0 - End */
4504 } s;
4505 /* struct bdk_usbdrdx_uahc_ghwparams4_s cn; */
4506 };
4507 typedef union bdk_usbdrdx_uahc_ghwparams4 bdk_usbdrdx_uahc_ghwparams4_t;
4508
4509 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS4(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS4(unsigned long a)4510 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS4(unsigned long a)
4511 {
4512 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4513 return 0x86800000c150ll + 0x1000000000ll * ((a) & 0x1);
4514 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4515 return 0x86800000c150ll + 0x1000000000ll * ((a) & 0x1);
4516 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4517 return 0x86800000c150ll + 0x1000000000ll * ((a) & 0x1);
4518 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS4", 1, a, 0, 0, 0);
4519 }
4520
4521 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS4(a) bdk_usbdrdx_uahc_ghwparams4_t
4522 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS4(a) BDK_CSR_TYPE_NCB32b
4523 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS4(a) "USBDRDX_UAHC_GHWPARAMS4"
4524 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS4(a) 0x0 /* PF_BAR0 */
4525 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS4(a) (a)
4526 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS4(a) (a),-1,-1,-1
4527
4528 /**
4529 * Register (NCB32b) usbdrd#_uahc_ghwparams5
4530 *
4531 * USB UAHC GHW Parameters Register 5
4532 * This register contains the hardware configuration options selected at compile-time.
4533 * Internal:
4534 * Register field names refer to Synopsys DWC_USB3_* parameters of the same suffix.
4535 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.24
4536 */
4537 union bdk_usbdrdx_uahc_ghwparams5
4538 {
4539 uint32_t u;
4540 struct bdk_usbdrdx_uahc_ghwparams5_s
4541 {
4542 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4543 uint32_t reserved_28_31 : 4;
4544 uint32_t dfq_fifo_depth : 6; /**< [ 27: 22](RO) Size of the BMU descriptor fetch-request queue. */
4545 uint32_t dwq_fifo_depth : 6; /**< [ 21: 16](RO) Size of the BMU descriptor write queue. */
4546 uint32_t txq_fifo_depth : 6; /**< [ 15: 10](RO) Size of the BMU TX request queue. */
4547 uint32_t rxq_fifo_depth : 6; /**< [ 9: 4](RO) Size of the BMU RX request queue. */
4548 uint32_t bmu_busgm_depth : 4; /**< [ 3: 0](RO) Depth of the BMU-BUSGM source/sink buffers. */
4549 #else /* Word 0 - Little Endian */
4550 uint32_t bmu_busgm_depth : 4; /**< [ 3: 0](RO) Depth of the BMU-BUSGM source/sink buffers. */
4551 uint32_t rxq_fifo_depth : 6; /**< [ 9: 4](RO) Size of the BMU RX request queue. */
4552 uint32_t txq_fifo_depth : 6; /**< [ 15: 10](RO) Size of the BMU TX request queue. */
4553 uint32_t dwq_fifo_depth : 6; /**< [ 21: 16](RO) Size of the BMU descriptor write queue. */
4554 uint32_t dfq_fifo_depth : 6; /**< [ 27: 22](RO) Size of the BMU descriptor fetch-request queue. */
4555 uint32_t reserved_28_31 : 4;
4556 #endif /* Word 0 - End */
4557 } s;
4558 /* struct bdk_usbdrdx_uahc_ghwparams5_s cn; */
4559 };
4560 typedef union bdk_usbdrdx_uahc_ghwparams5 bdk_usbdrdx_uahc_ghwparams5_t;
4561
4562 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS5(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS5(unsigned long a)4563 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS5(unsigned long a)
4564 {
4565 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4566 return 0x86800000c154ll + 0x1000000000ll * ((a) & 0x1);
4567 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4568 return 0x86800000c154ll + 0x1000000000ll * ((a) & 0x1);
4569 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4570 return 0x86800000c154ll + 0x1000000000ll * ((a) & 0x1);
4571 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS5", 1, a, 0, 0, 0);
4572 }
4573
4574 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS5(a) bdk_usbdrdx_uahc_ghwparams5_t
4575 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS5(a) BDK_CSR_TYPE_NCB32b
4576 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS5(a) "USBDRDX_UAHC_GHWPARAMS5"
4577 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS5(a) 0x0 /* PF_BAR0 */
4578 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS5(a) (a)
4579 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS5(a) (a),-1,-1,-1
4580
4581 /**
4582 * Register (NCB32b) usbdrd#_uahc_ghwparams6
4583 *
4584 * USB UAHC GHW Parameters Register 6
4585 * This register contains the hardware configuration options selected at compile-time.
4586 * Internal:
4587 * Register field names refer to Synopsys DWC_USB3_* parameters of the same suffix.
4588 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.25
4589 */
4590 union bdk_usbdrdx_uahc_ghwparams6
4591 {
4592 uint32_t u;
4593 struct bdk_usbdrdx_uahc_ghwparams6_s
4594 {
4595 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4596 uint32_t ram0_depth : 16; /**< [ 31: 16](RO) RAM0 depth. */
4597 uint32_t en_bus_filters : 1; /**< [ 15: 15](RO) VBus filters support. */
4598 uint32_t en_bc : 1; /**< [ 14: 14](RO) Enable battery charging support. */
4599 uint32_t en_otg_ss : 1; /**< [ 13: 13](RO) Enable OTG SuperSpeed support. */
4600 uint32_t en_adp : 1; /**< [ 12: 12](RO) Enable ADP support. */
4601 uint32_t hnp_support : 1; /**< [ 11: 11](RO) HNP support. */
4602 uint32_t srp_support : 1; /**< [ 10: 10](RO) SRP support. */
4603 uint32_t reserved_8_9 : 2;
4604 uint32_t en_fpga : 1; /**< [ 7: 7](RO) Enable FPGA implementation. */
4605 uint32_t en_dbg_ports : 1; /**< [ 6: 6](RO) Enable debug ports for FGPA. */
4606 uint32_t psq_fifo_depth : 6; /**< [ 5: 0](RO) Size of the BMU protocol status queue. */
4607 #else /* Word 0 - Little Endian */
4608 uint32_t psq_fifo_depth : 6; /**< [ 5: 0](RO) Size of the BMU protocol status queue. */
4609 uint32_t en_dbg_ports : 1; /**< [ 6: 6](RO) Enable debug ports for FGPA. */
4610 uint32_t en_fpga : 1; /**< [ 7: 7](RO) Enable FPGA implementation. */
4611 uint32_t reserved_8_9 : 2;
4612 uint32_t srp_support : 1; /**< [ 10: 10](RO) SRP support. */
4613 uint32_t hnp_support : 1; /**< [ 11: 11](RO) HNP support. */
4614 uint32_t en_adp : 1; /**< [ 12: 12](RO) Enable ADP support. */
4615 uint32_t en_otg_ss : 1; /**< [ 13: 13](RO) Enable OTG SuperSpeed support. */
4616 uint32_t en_bc : 1; /**< [ 14: 14](RO) Enable battery charging support. */
4617 uint32_t en_bus_filters : 1; /**< [ 15: 15](RO) VBus filters support. */
4618 uint32_t ram0_depth : 16; /**< [ 31: 16](RO) RAM0 depth. */
4619 #endif /* Word 0 - End */
4620 } s;
4621 /* struct bdk_usbdrdx_uahc_ghwparams6_s cn; */
4622 };
4623 typedef union bdk_usbdrdx_uahc_ghwparams6 bdk_usbdrdx_uahc_ghwparams6_t;
4624
4625 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS6(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS6(unsigned long a)4626 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS6(unsigned long a)
4627 {
4628 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4629 return 0x86800000c158ll + 0x1000000000ll * ((a) & 0x1);
4630 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4631 return 0x86800000c158ll + 0x1000000000ll * ((a) & 0x1);
4632 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4633 return 0x86800000c158ll + 0x1000000000ll * ((a) & 0x1);
4634 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS6", 1, a, 0, 0, 0);
4635 }
4636
4637 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS6(a) bdk_usbdrdx_uahc_ghwparams6_t
4638 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS6(a) BDK_CSR_TYPE_NCB32b
4639 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS6(a) "USBDRDX_UAHC_GHWPARAMS6"
4640 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS6(a) 0x0 /* PF_BAR0 */
4641 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS6(a) (a)
4642 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS6(a) (a),-1,-1,-1
4643
4644 /**
4645 * Register (NCB32b) usbdrd#_uahc_ghwparams7
4646 *
4647 * USB UAHC GHW Parameters Register 7
4648 * This register contains the hardware configuration options selected at compile-time.
4649 * Internal:
4650 * Register field names refer to Synopsys DWC_USB3_* parameters of the same suffix.
4651 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.26
4652 */
4653 union bdk_usbdrdx_uahc_ghwparams7
4654 {
4655 uint32_t u;
4656 struct bdk_usbdrdx_uahc_ghwparams7_s
4657 {
4658 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4659 uint32_t ram2_depth : 16; /**< [ 31: 16](RO) RAM2 depth. */
4660 uint32_t ram1_depth : 16; /**< [ 15: 0](RO) RAM1 depth. */
4661 #else /* Word 0 - Little Endian */
4662 uint32_t ram1_depth : 16; /**< [ 15: 0](RO) RAM1 depth. */
4663 uint32_t ram2_depth : 16; /**< [ 31: 16](RO) RAM2 depth. */
4664 #endif /* Word 0 - End */
4665 } s;
4666 /* struct bdk_usbdrdx_uahc_ghwparams7_s cn; */
4667 };
4668 typedef union bdk_usbdrdx_uahc_ghwparams7 bdk_usbdrdx_uahc_ghwparams7_t;
4669
4670 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS7(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS7(unsigned long a)4671 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS7(unsigned long a)
4672 {
4673 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4674 return 0x86800000c15cll + 0x1000000000ll * ((a) & 0x1);
4675 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4676 return 0x86800000c15cll + 0x1000000000ll * ((a) & 0x1);
4677 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4678 return 0x86800000c15cll + 0x1000000000ll * ((a) & 0x1);
4679 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS7", 1, a, 0, 0, 0);
4680 }
4681
4682 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS7(a) bdk_usbdrdx_uahc_ghwparams7_t
4683 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS7(a) BDK_CSR_TYPE_NCB32b
4684 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS7(a) "USBDRDX_UAHC_GHWPARAMS7"
4685 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS7(a) 0x0 /* PF_BAR0 */
4686 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS7(a) (a)
4687 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS7(a) (a),-1,-1,-1
4688
4689 /**
4690 * Register (NCB32b) usbdrd#_uahc_ghwparams8
4691 *
4692 * USB UAHC GHW Parameters Register 8
4693 * This register contains the hardware configuration options selected at compile-time.
4694 * Internal:
4695 * Register field names refer to Synopsys DWC_USB3_* parameters of the same suffix.
4696 * INTERNAL: See Synopsys DWC_usb3 Databook v2.20a, section 6.2.3.9.
4697 */
4698 union bdk_usbdrdx_uahc_ghwparams8
4699 {
4700 uint32_t u;
4701 struct bdk_usbdrdx_uahc_ghwparams8_s
4702 {
4703 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4704 uint32_t dcache_depth_info : 32; /**< [ 31: 0](RO) Dcache depth. */
4705 #else /* Word 0 - Little Endian */
4706 uint32_t dcache_depth_info : 32; /**< [ 31: 0](RO) Dcache depth. */
4707 #endif /* Word 0 - End */
4708 } s;
4709 /* struct bdk_usbdrdx_uahc_ghwparams8_s cn; */
4710 };
4711 typedef union bdk_usbdrdx_uahc_ghwparams8 bdk_usbdrdx_uahc_ghwparams8_t;
4712
4713 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS8(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GHWPARAMS8(unsigned long a)4714 static inline uint64_t BDK_USBDRDX_UAHC_GHWPARAMS8(unsigned long a)
4715 {
4716 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4717 return 0x86800000c600ll + 0x1000000000ll * ((a) & 0x1);
4718 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4719 return 0x86800000c600ll + 0x1000000000ll * ((a) & 0x1);
4720 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4721 return 0x86800000c600ll + 0x1000000000ll * ((a) & 0x1);
4722 __bdk_csr_fatal("USBDRDX_UAHC_GHWPARAMS8", 1, a, 0, 0, 0);
4723 }
4724
4725 #define typedef_BDK_USBDRDX_UAHC_GHWPARAMS8(a) bdk_usbdrdx_uahc_ghwparams8_t
4726 #define bustype_BDK_USBDRDX_UAHC_GHWPARAMS8(a) BDK_CSR_TYPE_NCB32b
4727 #define basename_BDK_USBDRDX_UAHC_GHWPARAMS8(a) "USBDRDX_UAHC_GHWPARAMS8"
4728 #define device_bar_BDK_USBDRDX_UAHC_GHWPARAMS8(a) 0x0 /* PF_BAR0 */
4729 #define busnum_BDK_USBDRDX_UAHC_GHWPARAMS8(a) (a)
4730 #define arguments_BDK_USBDRDX_UAHC_GHWPARAMS8(a) (a),-1,-1,-1
4731
4732 /**
4733 * Register (NCB32b) usbdrd#_uahc_gpmsts
4734 *
4735 * USB UAHC Global Power Management Status Register
4736 * This debug register gives information on which event caused the hibernation exit. These
4737 * registers are for debug purposes. They provide debug information on the internal status and
4738 * state machines. Global debug registers have design-specific information, and are used by for
4739 * debugging purposes. These registers are not intended to be used by the customer. If any debug
4740 * assistance is needed for the silicon, contact customer support with a dump of these registers.
4741 *
4742 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
4743 *
4744 * Internal:
4745 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.6
4746 * INTERNAL: Contact Synopsys directly.
4747 */
4748 union bdk_usbdrdx_uahc_gpmsts
4749 {
4750 uint32_t u;
4751 struct bdk_usbdrdx_uahc_gpmsts_s
4752 {
4753 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4754 uint32_t portsel : 4; /**< [ 31: 28](WO) This field selects the port number. Always 0x0. */
4755 uint32_t reserved_17_27 : 11;
4756 uint32_t u3wakeup : 5; /**< [ 16: 12](RO/H) This field gives the USB 3.0 port wakeup conditions.
4757 bit\<12\> = Overcurrent detected.
4758 bit\<13\> = Resume detected.
4759 bit\<14\> = Connect detected.
4760 bit\<15\> = Disconnect detected.
4761 bit\<16\> = Last connection state. */
4762 uint32_t reserved_10_11 : 2;
4763 uint32_t u2wakeup : 10; /**< [ 9: 0](RO/H) This field indicates the USB 2.0 port wakeup conditions.
4764 bit\<0\> = Overcurrent detected.
4765 bit\<1\> = Resume detected.
4766 bit\<2\> = Connect detected.
4767 bit\<3\> = Disconnect detected.
4768 bit\<4\> = Last connection state.
4769 bit\<5\> = ID change detected.
4770 bit\<6\> = SRP request detected.
4771 bit\<7\> = ULPI interrupt detected.
4772 bit\<8\> = USB reset detected.
4773 bit\<9\> = Resume detected changed. */
4774 #else /* Word 0 - Little Endian */
4775 uint32_t u2wakeup : 10; /**< [ 9: 0](RO/H) This field indicates the USB 2.0 port wakeup conditions.
4776 bit\<0\> = Overcurrent detected.
4777 bit\<1\> = Resume detected.
4778 bit\<2\> = Connect detected.
4779 bit\<3\> = Disconnect detected.
4780 bit\<4\> = Last connection state.
4781 bit\<5\> = ID change detected.
4782 bit\<6\> = SRP request detected.
4783 bit\<7\> = ULPI interrupt detected.
4784 bit\<8\> = USB reset detected.
4785 bit\<9\> = Resume detected changed. */
4786 uint32_t reserved_10_11 : 2;
4787 uint32_t u3wakeup : 5; /**< [ 16: 12](RO/H) This field gives the USB 3.0 port wakeup conditions.
4788 bit\<12\> = Overcurrent detected.
4789 bit\<13\> = Resume detected.
4790 bit\<14\> = Connect detected.
4791 bit\<15\> = Disconnect detected.
4792 bit\<16\> = Last connection state. */
4793 uint32_t reserved_17_27 : 11;
4794 uint32_t portsel : 4; /**< [ 31: 28](WO) This field selects the port number. Always 0x0. */
4795 #endif /* Word 0 - End */
4796 } s;
4797 /* struct bdk_usbdrdx_uahc_gpmsts_s cn; */
4798 };
4799 typedef union bdk_usbdrdx_uahc_gpmsts bdk_usbdrdx_uahc_gpmsts_t;
4800
4801 static inline uint64_t BDK_USBDRDX_UAHC_GPMSTS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GPMSTS(unsigned long a)4802 static inline uint64_t BDK_USBDRDX_UAHC_GPMSTS(unsigned long a)
4803 {
4804 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4805 return 0x86800000c114ll + 0x1000000000ll * ((a) & 0x1);
4806 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4807 return 0x86800000c114ll + 0x1000000000ll * ((a) & 0x1);
4808 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4809 return 0x86800000c114ll + 0x1000000000ll * ((a) & 0x1);
4810 __bdk_csr_fatal("USBDRDX_UAHC_GPMSTS", 1, a, 0, 0, 0);
4811 }
4812
4813 #define typedef_BDK_USBDRDX_UAHC_GPMSTS(a) bdk_usbdrdx_uahc_gpmsts_t
4814 #define bustype_BDK_USBDRDX_UAHC_GPMSTS(a) BDK_CSR_TYPE_NCB32b
4815 #define basename_BDK_USBDRDX_UAHC_GPMSTS(a) "USBDRDX_UAHC_GPMSTS"
4816 #define device_bar_BDK_USBDRDX_UAHC_GPMSTS(a) 0x0 /* PF_BAR0 */
4817 #define busnum_BDK_USBDRDX_UAHC_GPMSTS(a) (a)
4818 #define arguments_BDK_USBDRDX_UAHC_GPMSTS(a) (a),-1,-1,-1
4819
4820 /**
4821 * Register (NCB) usbdrd#_uahc_gprtbimap
4822 *
4823 * USB UAHC SuperSpeed Port-to-Bus Instance Mapping Register
4824 * This register specifies the SuperSpeed USB instance number to which each USB 3.0 port is
4825 * connected. By default, USB 3.0 ports are evenly distributed among all SuperSpeed USB
4826 * instances. Software can program this register to specify how USB 3.0 ports are connected to
4827 * SuperSpeed USB instances. The UAHC only implements one SuperSpeed bus-instance, so this
4828 * register should always be 0.
4829 *
4830 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
4831 *
4832 * Internal:
4833 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.16
4834 */
4835 union bdk_usbdrdx_uahc_gprtbimap
4836 {
4837 uint64_t u;
4838 struct bdk_usbdrdx_uahc_gprtbimap_s
4839 {
4840 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4841 uint64_t reserved_4_63 : 60;
4842 uint64_t binum1 : 4; /**< [ 3: 0](R/W) SuperSpeed USB instance number for port 1. */
4843 #else /* Word 0 - Little Endian */
4844 uint64_t binum1 : 4; /**< [ 3: 0](R/W) SuperSpeed USB instance number for port 1. */
4845 uint64_t reserved_4_63 : 60;
4846 #endif /* Word 0 - End */
4847 } s;
4848 /* struct bdk_usbdrdx_uahc_gprtbimap_s cn; */
4849 };
4850 typedef union bdk_usbdrdx_uahc_gprtbimap bdk_usbdrdx_uahc_gprtbimap_t;
4851
4852 static inline uint64_t BDK_USBDRDX_UAHC_GPRTBIMAP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GPRTBIMAP(unsigned long a)4853 static inline uint64_t BDK_USBDRDX_UAHC_GPRTBIMAP(unsigned long a)
4854 {
4855 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4856 return 0x86800000c138ll + 0x1000000000ll * ((a) & 0x1);
4857 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4858 return 0x86800000c138ll + 0x1000000000ll * ((a) & 0x1);
4859 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4860 return 0x86800000c138ll + 0x1000000000ll * ((a) & 0x1);
4861 __bdk_csr_fatal("USBDRDX_UAHC_GPRTBIMAP", 1, a, 0, 0, 0);
4862 }
4863
4864 #define typedef_BDK_USBDRDX_UAHC_GPRTBIMAP(a) bdk_usbdrdx_uahc_gprtbimap_t
4865 #define bustype_BDK_USBDRDX_UAHC_GPRTBIMAP(a) BDK_CSR_TYPE_NCB
4866 #define basename_BDK_USBDRDX_UAHC_GPRTBIMAP(a) "USBDRDX_UAHC_GPRTBIMAP"
4867 #define device_bar_BDK_USBDRDX_UAHC_GPRTBIMAP(a) 0x0 /* PF_BAR0 */
4868 #define busnum_BDK_USBDRDX_UAHC_GPRTBIMAP(a) (a)
4869 #define arguments_BDK_USBDRDX_UAHC_GPRTBIMAP(a) (a),-1,-1,-1
4870
4871 /**
4872 * Register (NCB) usbdrd#_uahc_gprtbimap_fs
4873 *
4874 * USB UAHC Full/Low-Speed Port-to-Bus Instance Mapping Register
4875 * This register specifies the full-speed/low-speed USB instance number to which each USB 1.1
4876 * port is connected. By default, USB 1.1 ports are evenly distributed among all full-speed/
4877 * low-speed USB instances. Software can program this register to specify how USB 1.1 ports are
4878 * connected to full-speed/low-speed USB instances. The UAHC only implements one full-speed/
4879 * low-speed bus-instance, so this register should always be 0x0.
4880 *
4881 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
4882 *
4883 * Internal:
4884 * See Synopsys DWC_usb3 Databook v2.20a, section 6.2.2.3.
4885 */
4886 union bdk_usbdrdx_uahc_gprtbimap_fs
4887 {
4888 uint64_t u;
4889 struct bdk_usbdrdx_uahc_gprtbimap_fs_s
4890 {
4891 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4892 uint64_t reserved_4_63 : 60;
4893 uint64_t binum1 : 4; /**< [ 3: 0](R/W) Full-speed USB instance number for port 1. */
4894 #else /* Word 0 - Little Endian */
4895 uint64_t binum1 : 4; /**< [ 3: 0](R/W) Full-speed USB instance number for port 1. */
4896 uint64_t reserved_4_63 : 60;
4897 #endif /* Word 0 - End */
4898 } s;
4899 /* struct bdk_usbdrdx_uahc_gprtbimap_fs_s cn; */
4900 };
4901 typedef union bdk_usbdrdx_uahc_gprtbimap_fs bdk_usbdrdx_uahc_gprtbimap_fs_t;
4902
4903 static inline uint64_t BDK_USBDRDX_UAHC_GPRTBIMAP_FS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GPRTBIMAP_FS(unsigned long a)4904 static inline uint64_t BDK_USBDRDX_UAHC_GPRTBIMAP_FS(unsigned long a)
4905 {
4906 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4907 return 0x86800000c188ll + 0x1000000000ll * ((a) & 0x1);
4908 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4909 return 0x86800000c188ll + 0x1000000000ll * ((a) & 0x1);
4910 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4911 return 0x86800000c188ll + 0x1000000000ll * ((a) & 0x1);
4912 __bdk_csr_fatal("USBDRDX_UAHC_GPRTBIMAP_FS", 1, a, 0, 0, 0);
4913 }
4914
4915 #define typedef_BDK_USBDRDX_UAHC_GPRTBIMAP_FS(a) bdk_usbdrdx_uahc_gprtbimap_fs_t
4916 #define bustype_BDK_USBDRDX_UAHC_GPRTBIMAP_FS(a) BDK_CSR_TYPE_NCB
4917 #define basename_BDK_USBDRDX_UAHC_GPRTBIMAP_FS(a) "USBDRDX_UAHC_GPRTBIMAP_FS"
4918 #define device_bar_BDK_USBDRDX_UAHC_GPRTBIMAP_FS(a) 0x0 /* PF_BAR0 */
4919 #define busnum_BDK_USBDRDX_UAHC_GPRTBIMAP_FS(a) (a)
4920 #define arguments_BDK_USBDRDX_UAHC_GPRTBIMAP_FS(a) (a),-1,-1,-1
4921
4922 /**
4923 * Register (NCB) usbdrd#_uahc_gprtbimap_hs
4924 *
4925 * USB UAHC High-Speed Port-to-Bus Instance Mapping Register
4926 * This register specifies the high-speed USB instance number to which each USB 2.0 port is
4927 * connected. By default, USB 2.0 ports are evenly distributed among all high-speed USB
4928 * instances. Software can program this register to specify how USB 2.0 ports are connected to
4929 * high-speed USB instances. The UAHC only implements one high-speed bus-instance, so this
4930 * register should always be 0.
4931 *
4932 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
4933 *
4934 * Internal:
4935 * See Synopsys DWC_usb3 Databook v2.20a, section 6.2.2.2.
4936 */
4937 union bdk_usbdrdx_uahc_gprtbimap_hs
4938 {
4939 uint64_t u;
4940 struct bdk_usbdrdx_uahc_gprtbimap_hs_s
4941 {
4942 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4943 uint64_t reserved_4_63 : 60;
4944 uint64_t binum1 : 4; /**< [ 3: 0](R/W) High-speed USB instance number for port 1. */
4945 #else /* Word 0 - Little Endian */
4946 uint64_t binum1 : 4; /**< [ 3: 0](R/W) High-speed USB instance number for port 1. */
4947 uint64_t reserved_4_63 : 60;
4948 #endif /* Word 0 - End */
4949 } s;
4950 /* struct bdk_usbdrdx_uahc_gprtbimap_hs_s cn; */
4951 };
4952 typedef union bdk_usbdrdx_uahc_gprtbimap_hs bdk_usbdrdx_uahc_gprtbimap_hs_t;
4953
4954 static inline uint64_t BDK_USBDRDX_UAHC_GPRTBIMAP_HS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GPRTBIMAP_HS(unsigned long a)4955 static inline uint64_t BDK_USBDRDX_UAHC_GPRTBIMAP_HS(unsigned long a)
4956 {
4957 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4958 return 0x86800000c180ll + 0x1000000000ll * ((a) & 0x1);
4959 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
4960 return 0x86800000c180ll + 0x1000000000ll * ((a) & 0x1);
4961 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
4962 return 0x86800000c180ll + 0x1000000000ll * ((a) & 0x1);
4963 __bdk_csr_fatal("USBDRDX_UAHC_GPRTBIMAP_HS", 1, a, 0, 0, 0);
4964 }
4965
4966 #define typedef_BDK_USBDRDX_UAHC_GPRTBIMAP_HS(a) bdk_usbdrdx_uahc_gprtbimap_hs_t
4967 #define bustype_BDK_USBDRDX_UAHC_GPRTBIMAP_HS(a) BDK_CSR_TYPE_NCB
4968 #define basename_BDK_USBDRDX_UAHC_GPRTBIMAP_HS(a) "USBDRDX_UAHC_GPRTBIMAP_HS"
4969 #define device_bar_BDK_USBDRDX_UAHC_GPRTBIMAP_HS(a) 0x0 /* PF_BAR0 */
4970 #define busnum_BDK_USBDRDX_UAHC_GPRTBIMAP_HS(a) (a)
4971 #define arguments_BDK_USBDRDX_UAHC_GPRTBIMAP_HS(a) (a),-1,-1,-1
4972
4973 /**
4974 * Register (NCB32b) usbdrd#_uahc_grlsid
4975 *
4976 * USB UAHC Release ID Register
4977 * This is a read-only register that contains the release number of the core.
4978 * Internal:
4979 * Original name: GSNPSID = Synopsys ID.
4980 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.9.
4981 */
4982 union bdk_usbdrdx_uahc_grlsid
4983 {
4984 uint32_t u;
4985 struct bdk_usbdrdx_uahc_grlsid_s
4986 {
4987 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4988 uint32_t releaseid : 32; /**< [ 31: 0](RO) Software can use this register to configure release-specific features in the driver.
4989 Internal:
4990 Synopsys ID
4991 * SynopsysID[31:16] indicates Core Identification Number. 0x5533 is ASCII for
4992 U3 (DWC_usb3).
4993 * SynopsysID[15:0] indicates the release number. Current Release is 2.50a. */
4994 #else /* Word 0 - Little Endian */
4995 uint32_t releaseid : 32; /**< [ 31: 0](RO) Software can use this register to configure release-specific features in the driver.
4996 Internal:
4997 Synopsys ID
4998 * SynopsysID[31:16] indicates Core Identification Number. 0x5533 is ASCII for
4999 U3 (DWC_usb3).
5000 * SynopsysID[15:0] indicates the release number. Current Release is 2.50a. */
5001 #endif /* Word 0 - End */
5002 } s;
5003 /* struct bdk_usbdrdx_uahc_grlsid_s cn8; */
5004 struct bdk_usbdrdx_uahc_grlsid_cn9
5005 {
5006 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5007 uint32_t releaseid : 32; /**< [ 31: 0](RO) Software can use this register to configure release-specific features in the driver.
5008 Internal:
5009 Synopsys ID
5010 * SynopsysID[31:16] indicates Core Identification Number. 0x5533 is ASCII for
5011 U3 (DWC_usb3).
5012 * SynopsysID[15:0] indicates the release number. Current Release is 3.10a. */
5013 #else /* Word 0 - Little Endian */
5014 uint32_t releaseid : 32; /**< [ 31: 0](RO) Software can use this register to configure release-specific features in the driver.
5015 Internal:
5016 Synopsys ID
5017 * SynopsysID[31:16] indicates Core Identification Number. 0x5533 is ASCII for
5018 U3 (DWC_usb3).
5019 * SynopsysID[15:0] indicates the release number. Current Release is 3.10a. */
5020 #endif /* Word 0 - End */
5021 } cn9;
5022 };
5023 typedef union bdk_usbdrdx_uahc_grlsid bdk_usbdrdx_uahc_grlsid_t;
5024
5025 static inline uint64_t BDK_USBDRDX_UAHC_GRLSID(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GRLSID(unsigned long a)5026 static inline uint64_t BDK_USBDRDX_UAHC_GRLSID(unsigned long a)
5027 {
5028 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5029 return 0x86800000c120ll + 0x1000000000ll * ((a) & 0x1);
5030 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5031 return 0x86800000c120ll + 0x1000000000ll * ((a) & 0x1);
5032 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
5033 return 0x86800000c120ll + 0x1000000000ll * ((a) & 0x1);
5034 __bdk_csr_fatal("USBDRDX_UAHC_GRLSID", 1, a, 0, 0, 0);
5035 }
5036
5037 #define typedef_BDK_USBDRDX_UAHC_GRLSID(a) bdk_usbdrdx_uahc_grlsid_t
5038 #define bustype_BDK_USBDRDX_UAHC_GRLSID(a) BDK_CSR_TYPE_NCB32b
5039 #define basename_BDK_USBDRDX_UAHC_GRLSID(a) "USBDRDX_UAHC_GRLSID"
5040 #define device_bar_BDK_USBDRDX_UAHC_GRLSID(a) 0x0 /* PF_BAR0 */
5041 #define busnum_BDK_USBDRDX_UAHC_GRLSID(a) (a)
5042 #define arguments_BDK_USBDRDX_UAHC_GRLSID(a) (a),-1,-1,-1
5043
5044 /**
5045 * Register (NCB32b) usbdrd#_uahc_grxfifoprihst
5046 *
5047 * USB UAHC RxFIFOs DMA Priority Register
5048 * This register specifies the relative DMA priority level among the host RxFIFOs (one per USB
5049 * bus instance) within the associated speed group (SuperSpeed or high-speed/full-speed/
5050 * low-speed). When multiple RxFIFOs compete for DMA service at a given time, the RXDMA arbiter
5051 * grants access on a packet-basis in the following manner:
5052 *
5053 * Among the FIFOs in the same speed group (SuperSpeed or high-speed/full-speed/low-speed):
5054 * * High-priority RxFIFOs are granted access using round-robin arbitration.
5055 * * Low-priority RxFIFOs are granted access using round-robin arbitration only after high-
5056 * priority
5057 * RxFIFOs have no further processing to do (i.e., either the RXQs are empty or the corresponding
5058 * RxFIFOs do not have the required data).
5059 *
5060 * The RX DMA arbiter prioritizes the SuperSpeed group or high-speed/full-speed/low-speed group
5061 * according to the ratio programmed in
5062 * USBDRD()_UAHC_GDMAHLRATIO.
5063 *
5064 * For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until
5065 * the entire packet is completed. The register size corresponds to the number of configured USB
5066 * bus instances; for example, in the default configuration, there are three USB bus instances (one
5067 * SuperSpeed, one high-speed, and one full-speed/low-speed).
5068 *
5069 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5070 *
5071 * Internal:
5072 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.60
5073 */
5074 union bdk_usbdrdx_uahc_grxfifoprihst
5075 {
5076 uint32_t u;
5077 struct bdk_usbdrdx_uahc_grxfifoprihst_s
5078 {
5079 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5080 uint32_t reserved_3_31 : 29;
5081 uint32_t rx_priority : 3; /**< [ 2: 0](R/W) Each register bit[n] controls the priority (1 = high, 0 = low) of RxFIFO[n] within a speed group. */
5082 #else /* Word 0 - Little Endian */
5083 uint32_t rx_priority : 3; /**< [ 2: 0](R/W) Each register bit[n] controls the priority (1 = high, 0 = low) of RxFIFO[n] within a speed group. */
5084 uint32_t reserved_3_31 : 29;
5085 #endif /* Word 0 - End */
5086 } s;
5087 /* struct bdk_usbdrdx_uahc_grxfifoprihst_s cn; */
5088 };
5089 typedef union bdk_usbdrdx_uahc_grxfifoprihst bdk_usbdrdx_uahc_grxfifoprihst_t;
5090
5091 static inline uint64_t BDK_USBDRDX_UAHC_GRXFIFOPRIHST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GRXFIFOPRIHST(unsigned long a)5092 static inline uint64_t BDK_USBDRDX_UAHC_GRXFIFOPRIHST(unsigned long a)
5093 {
5094 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5095 return 0x86800000c61cll + 0x1000000000ll * ((a) & 0x1);
5096 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5097 return 0x86800000c61cll + 0x1000000000ll * ((a) & 0x1);
5098 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
5099 return 0x86800000c61cll + 0x1000000000ll * ((a) & 0x1);
5100 __bdk_csr_fatal("USBDRDX_UAHC_GRXFIFOPRIHST", 1, a, 0, 0, 0);
5101 }
5102
5103 #define typedef_BDK_USBDRDX_UAHC_GRXFIFOPRIHST(a) bdk_usbdrdx_uahc_grxfifoprihst_t
5104 #define bustype_BDK_USBDRDX_UAHC_GRXFIFOPRIHST(a) BDK_CSR_TYPE_NCB32b
5105 #define basename_BDK_USBDRDX_UAHC_GRXFIFOPRIHST(a) "USBDRDX_UAHC_GRXFIFOPRIHST"
5106 #define device_bar_BDK_USBDRDX_UAHC_GRXFIFOPRIHST(a) 0x0 /* PF_BAR0 */
5107 #define busnum_BDK_USBDRDX_UAHC_GRXFIFOPRIHST(a) (a)
5108 #define arguments_BDK_USBDRDX_UAHC_GRXFIFOPRIHST(a) (a),-1,-1,-1
5109
5110 /**
5111 * Register (NCB32b) usbdrd#_uahc_grxfifosiz#
5112 *
5113 * USB UAHC RX FIFO Size Register
5114 * The application can program the internal RAM start address/depth of the each RxFIFO as shown
5115 * below. It is recommended that software use the default value. In Host mode, per-port registers
5116 * are implemented. One register per FIFO.
5117 *
5118 * Reset values = 0:{0x0000_0084} 1:{0x0084_0104} 2:{0x0188_0180}.
5119 *
5120 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5121 *
5122 * Internal:
5123 * See Synopsys DWC_usb3 Databook v2.20a, section 6.2.6.2.
5124 * INTERNAL: For more information, see the BMU section in Block Descriptions on Synopsys Databook
5125 * page 238.
5126 */
5127 union bdk_usbdrdx_uahc_grxfifosizx
5128 {
5129 uint32_t u;
5130 struct bdk_usbdrdx_uahc_grxfifosizx_s
5131 {
5132 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5133 uint32_t rxfstaddr : 16; /**< [ 31: 16](R/W) RxFIFOn RAM start address. This field contains the memory start address for RxFIFOn. The
5134 reset value is derived from configuration parameters. */
5135 uint32_t rxfdep : 16; /**< [ 15: 0](R/W) RxFIFOn depth. This value is in terms of RX RAM data width.
5136 minimum value = 0x20, maximum value = 0x4000.
5137
5138 Internal:
5139 For more information, see the Hardware Integration chapter of the Synopsys
5140 Databook.
5141 The reset value is derived from configuration parameters. */
5142 #else /* Word 0 - Little Endian */
5143 uint32_t rxfdep : 16; /**< [ 15: 0](R/W) RxFIFOn depth. This value is in terms of RX RAM data width.
5144 minimum value = 0x20, maximum value = 0x4000.
5145
5146 Internal:
5147 For more information, see the Hardware Integration chapter of the Synopsys
5148 Databook.
5149 The reset value is derived from configuration parameters. */
5150 uint32_t rxfstaddr : 16; /**< [ 31: 16](R/W) RxFIFOn RAM start address. This field contains the memory start address for RxFIFOn. The
5151 reset value is derived from configuration parameters. */
5152 #endif /* Word 0 - End */
5153 } s;
5154 /* struct bdk_usbdrdx_uahc_grxfifosizx_s cn; */
5155 };
5156 typedef union bdk_usbdrdx_uahc_grxfifosizx bdk_usbdrdx_uahc_grxfifosizx_t;
5157
5158 static inline uint64_t BDK_USBDRDX_UAHC_GRXFIFOSIZX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GRXFIFOSIZX(unsigned long a,unsigned long b)5159 static inline uint64_t BDK_USBDRDX_UAHC_GRXFIFOSIZX(unsigned long a, unsigned long b)
5160 {
5161 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=2)))
5162 return 0x86800000c380ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x3);
5163 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=2)))
5164 return 0x86800000c380ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x3);
5165 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=2)))
5166 return 0x86800000c380ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x3);
5167 __bdk_csr_fatal("USBDRDX_UAHC_GRXFIFOSIZX", 2, a, b, 0, 0);
5168 }
5169
5170 #define typedef_BDK_USBDRDX_UAHC_GRXFIFOSIZX(a,b) bdk_usbdrdx_uahc_grxfifosizx_t
5171 #define bustype_BDK_USBDRDX_UAHC_GRXFIFOSIZX(a,b) BDK_CSR_TYPE_NCB32b
5172 #define basename_BDK_USBDRDX_UAHC_GRXFIFOSIZX(a,b) "USBDRDX_UAHC_GRXFIFOSIZX"
5173 #define device_bar_BDK_USBDRDX_UAHC_GRXFIFOSIZX(a,b) 0x0 /* PF_BAR0 */
5174 #define busnum_BDK_USBDRDX_UAHC_GRXFIFOSIZX(a,b) (a)
5175 #define arguments_BDK_USBDRDX_UAHC_GRXFIFOSIZX(a,b) (a),(b),-1,-1
5176
5177 /**
5178 * Register (NCB32b) usbdrd#_uahc_grxthrcfg
5179 *
5180 * USB UAHC RX Threshold Control Register
5181 * In a normal case, an RX burst starts as soon as 1-packet space is available. This works well
5182 * as long as the system bus is faster than the USB3.0 bus (a 1024-bytes packet takes ~2.2 us on
5183 * the USB bus in SuperSpeed mode). If the system bus latency is larger than 2.2 us to access a
5184 * 1024-byte packet, then starting a burst on 1-packet condition leads to an early abort of the
5185 * burst causing unnecessary performance reduction. This register allows the configuration of
5186 * threshold and burst size control. This feature is enabled by USBRXPKTCNTSEL.
5187 *
5188 * Receive Path:
5189 * * The RX threshold is controlled by USBRXPKTCNT and the RX burst size is controlled by
5190 * USBMAXRXBURSTSIZE.
5191 * * Selecting optimal RxFIFO size, RX threshold, and RX burst size avoids RX burst aborts due
5192 * to overrun if the system bus is slower than USB. Once in a while overrun is OK, and there is
5193 * no functional issue.
5194 * * Some devices do not support terminating ACK retry. With these devices, host cannot set ACK=0
5195 * and Retry=0 and do retry later and you have to retry immediately. For such devices, minimize
5196 * retry due to underrun. Setting threshold and burst size guarantees this.
5197 * A larger RX threshold affects the performance since the scheduler is idle during this time.
5198 *
5199 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5200 *
5201 * Internal:
5202 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.4.
5203 */
5204 union bdk_usbdrdx_uahc_grxthrcfg
5205 {
5206 uint32_t u;
5207 struct bdk_usbdrdx_uahc_grxthrcfg_s
5208 {
5209 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5210 uint32_t reserved_30_31 : 2;
5211 uint32_t usbrxpktcntsel : 1; /**< [ 29: 29](R/W) USB receive-packet-count enable. Enables/disables the USB reception multipacket
5212 thresholding:
5213 0 = the core can only start reception on the USB when the RxFIFO has space for at least
5214 one packet.
5215 1 = the core can only start reception on the USB when the RxFIFO has space for at least
5216 USBRXPKTCNT amount of packets.
5217 This mode is only used for SuperSpeed.
5218
5219 In device mode, setting this bit to 1 also enables the functionality of reporting
5220 NUMP in the ACK TP based on the RxFIFO space instead of reporting a fixed NUMP derived
5221 from USBDRD()_UAHC_DCFG[NUMP]. */
5222 uint32_t reserved_28 : 1;
5223 uint32_t usbrxpktcnt : 4; /**< [ 27: 24](R/W) USB receive-packet count. In host-mode, specifies space (in number of packets) that must
5224 be available in the RxFIFO before the core can start the corresponding USB RX transaction
5225 (burst).
5226
5227 This field is only valid when [USBRXPKTCNTSEL] = 1. The valid values are from 0x1 to 0xF.
5228 This field must be \<= [USBMAXRXBURSTSIZE]. */
5229 uint32_t usbmaxrxburstsize : 5; /**< [ 23: 19](R/W) USB maximum receive-burst size. Specifies the maximum bulk IN burst the core
5230 should do. When the system bus is slower than the USB, RxFIFO can overrun during a long
5231 burst.
5232
5233 Program a smaller value to this field to limit the RX burst size that the core can do. It
5234 only applies to SuperSpeed Bulk, Isochronous, and Interrupt IN endpoints.
5235 This field is only valid when [USBRXPKTCNTSEL] = 1. The valid values are from 0x1 to 0x10. */
5236 uint32_t reserved_0_18 : 19;
5237 #else /* Word 0 - Little Endian */
5238 uint32_t reserved_0_18 : 19;
5239 uint32_t usbmaxrxburstsize : 5; /**< [ 23: 19](R/W) USB maximum receive-burst size. Specifies the maximum bulk IN burst the core
5240 should do. When the system bus is slower than the USB, RxFIFO can overrun during a long
5241 burst.
5242
5243 Program a smaller value to this field to limit the RX burst size that the core can do. It
5244 only applies to SuperSpeed Bulk, Isochronous, and Interrupt IN endpoints.
5245 This field is only valid when [USBRXPKTCNTSEL] = 1. The valid values are from 0x1 to 0x10. */
5246 uint32_t usbrxpktcnt : 4; /**< [ 27: 24](R/W) USB receive-packet count. In host-mode, specifies space (in number of packets) that must
5247 be available in the RxFIFO before the core can start the corresponding USB RX transaction
5248 (burst).
5249
5250 This field is only valid when [USBRXPKTCNTSEL] = 1. The valid values are from 0x1 to 0xF.
5251 This field must be \<= [USBMAXRXBURSTSIZE]. */
5252 uint32_t reserved_28 : 1;
5253 uint32_t usbrxpktcntsel : 1; /**< [ 29: 29](R/W) USB receive-packet-count enable. Enables/disables the USB reception multipacket
5254 thresholding:
5255 0 = the core can only start reception on the USB when the RxFIFO has space for at least
5256 one packet.
5257 1 = the core can only start reception on the USB when the RxFIFO has space for at least
5258 USBRXPKTCNT amount of packets.
5259 This mode is only used for SuperSpeed.
5260
5261 In device mode, setting this bit to 1 also enables the functionality of reporting
5262 NUMP in the ACK TP based on the RxFIFO space instead of reporting a fixed NUMP derived
5263 from USBDRD()_UAHC_DCFG[NUMP]. */
5264 uint32_t reserved_30_31 : 2;
5265 #endif /* Word 0 - End */
5266 } s;
5267 struct bdk_usbdrdx_uahc_grxthrcfg_cn
5268 {
5269 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5270 uint32_t reserved_30_31 : 2;
5271 uint32_t usbrxpktcntsel : 1; /**< [ 29: 29](R/W) USB receive-packet-count enable. Enables/disables the USB reception multipacket
5272 thresholding:
5273 0 = the core can only start reception on the USB when the RxFIFO has space for at least
5274 one packet.
5275 1 = the core can only start reception on the USB when the RxFIFO has space for at least
5276 USBRXPKTCNT amount of packets.
5277 This mode is only used for SuperSpeed.
5278
5279 In device mode, setting this bit to 1 also enables the functionality of reporting
5280 NUMP in the ACK TP based on the RxFIFO space instead of reporting a fixed NUMP derived
5281 from USBDRD()_UAHC_DCFG[NUMP]. */
5282 uint32_t reserved_28 : 1;
5283 uint32_t usbrxpktcnt : 4; /**< [ 27: 24](R/W) USB receive-packet count. In host-mode, specifies space (in number of packets) that must
5284 be available in the RxFIFO before the core can start the corresponding USB RX transaction
5285 (burst).
5286
5287 This field is only valid when [USBRXPKTCNTSEL] = 1. The valid values are from 0x1 to 0xF.
5288 This field must be \<= [USBMAXRXBURSTSIZE]. */
5289 uint32_t usbmaxrxburstsize : 5; /**< [ 23: 19](R/W) USB maximum receive-burst size. Specifies the maximum bulk IN burst the core
5290 should do. When the system bus is slower than the USB, RxFIFO can overrun during a long
5291 burst.
5292
5293 Program a smaller value to this field to limit the RX burst size that the core can do. It
5294 only applies to SuperSpeed Bulk, Isochronous, and Interrupt IN endpoints.
5295 This field is only valid when [USBRXPKTCNTSEL] = 1. The valid values are from 0x1 to 0x10. */
5296 uint32_t reserved_16_18 : 3;
5297 uint32_t reserved_15 : 1;
5298 uint32_t reserved_11_14 : 4;
5299 uint32_t reserved_0_10 : 11;
5300 #else /* Word 0 - Little Endian */
5301 uint32_t reserved_0_10 : 11;
5302 uint32_t reserved_11_14 : 4;
5303 uint32_t reserved_15 : 1;
5304 uint32_t reserved_16_18 : 3;
5305 uint32_t usbmaxrxburstsize : 5; /**< [ 23: 19](R/W) USB maximum receive-burst size. Specifies the maximum bulk IN burst the core
5306 should do. When the system bus is slower than the USB, RxFIFO can overrun during a long
5307 burst.
5308
5309 Program a smaller value to this field to limit the RX burst size that the core can do. It
5310 only applies to SuperSpeed Bulk, Isochronous, and Interrupt IN endpoints.
5311 This field is only valid when [USBRXPKTCNTSEL] = 1. The valid values are from 0x1 to 0x10. */
5312 uint32_t usbrxpktcnt : 4; /**< [ 27: 24](R/W) USB receive-packet count. In host-mode, specifies space (in number of packets) that must
5313 be available in the RxFIFO before the core can start the corresponding USB RX transaction
5314 (burst).
5315
5316 This field is only valid when [USBRXPKTCNTSEL] = 1. The valid values are from 0x1 to 0xF.
5317 This field must be \<= [USBMAXRXBURSTSIZE]. */
5318 uint32_t reserved_28 : 1;
5319 uint32_t usbrxpktcntsel : 1; /**< [ 29: 29](R/W) USB receive-packet-count enable. Enables/disables the USB reception multipacket
5320 thresholding:
5321 0 = the core can only start reception on the USB when the RxFIFO has space for at least
5322 one packet.
5323 1 = the core can only start reception on the USB when the RxFIFO has space for at least
5324 USBRXPKTCNT amount of packets.
5325 This mode is only used for SuperSpeed.
5326
5327 In device mode, setting this bit to 1 also enables the functionality of reporting
5328 NUMP in the ACK TP based on the RxFIFO space instead of reporting a fixed NUMP derived
5329 from USBDRD()_UAHC_DCFG[NUMP]. */
5330 uint32_t reserved_30_31 : 2;
5331 #endif /* Word 0 - End */
5332 } cn;
5333 };
5334 typedef union bdk_usbdrdx_uahc_grxthrcfg bdk_usbdrdx_uahc_grxthrcfg_t;
5335
5336 static inline uint64_t BDK_USBDRDX_UAHC_GRXTHRCFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GRXTHRCFG(unsigned long a)5337 static inline uint64_t BDK_USBDRDX_UAHC_GRXTHRCFG(unsigned long a)
5338 {
5339 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5340 return 0x86800000c10cll + 0x1000000000ll * ((a) & 0x1);
5341 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5342 return 0x86800000c10cll + 0x1000000000ll * ((a) & 0x1);
5343 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
5344 return 0x86800000c10cll + 0x1000000000ll * ((a) & 0x1);
5345 __bdk_csr_fatal("USBDRDX_UAHC_GRXTHRCFG", 1, a, 0, 0, 0);
5346 }
5347
5348 #define typedef_BDK_USBDRDX_UAHC_GRXTHRCFG(a) bdk_usbdrdx_uahc_grxthrcfg_t
5349 #define bustype_BDK_USBDRDX_UAHC_GRXTHRCFG(a) BDK_CSR_TYPE_NCB32b
5350 #define basename_BDK_USBDRDX_UAHC_GRXTHRCFG(a) "USBDRDX_UAHC_GRXTHRCFG"
5351 #define device_bar_BDK_USBDRDX_UAHC_GRXTHRCFG(a) 0x0 /* PF_BAR0 */
5352 #define busnum_BDK_USBDRDX_UAHC_GRXTHRCFG(a) (a)
5353 #define arguments_BDK_USBDRDX_UAHC_GRXTHRCFG(a) (a),-1,-1,-1
5354
5355 /**
5356 * Register (NCB32b) usbdrd#_uahc_gsbuscfg0
5357 *
5358 * USB UAHC Bus Configuration Register 0
5359 * This register can be used to configure the core after power-on or a change in mode of
5360 * operation. This register mainly contains AXI system-related configuration parameters. Do not
5361 * change this register after the initial programming. The application must program this register
5362 * before starting any transactions on AXI. When [INCRBRSTENA] is enabled, it has the highest
5363 * priority over other burst lengths. The core always performs the largest burst when enabled.
5364 *
5365 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5366 *
5367 * Internal:
5368 * The AXI cache signals are not connected in Cavium's hookup, so the *REQINFO fields
5369 * can be ignored.
5370 * INTERNAL: See Synopsys DWC_usb3 Databook v3.10a, section 6.2.1
5371 */
5372 union bdk_usbdrdx_uahc_gsbuscfg0
5373 {
5374 uint32_t u;
5375 struct bdk_usbdrdx_uahc_gsbuscfg0_s
5376 {
5377 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5378 uint32_t datrdreqinfo : 4; /**< [ 31: 28](R/W) AXI-cache for data-read operations. Always set to 0x0. */
5379 uint32_t desrdreqinfo : 4; /**< [ 27: 24](R/W) AXI-cache for descriptor-read operations. Always set to 0x0. */
5380 uint32_t datwrreqinfo : 4; /**< [ 23: 20](R/W) AXI-cache for data-write operations. Always set to 0x0. */
5381 uint32_t deswrreqinfo : 4; /**< [ 19: 16](R/W) AXI-cache for descriptor-write operations. Always set to 0x0. */
5382 uint32_t reserved_12_15 : 4;
5383 uint32_t datbigend : 1; /**< [ 11: 11](R/W) Data access is big-endian. Keep this set to 0 (little-endian) and use the
5384 USBDRD()_UCTL_SHIM_CFG[DMA_ENDIAN_MODE] setting instead.
5385
5386 For diagnostic use only, drivers should be written assuming little-endian. */
5387 uint32_t descbigend : 1; /**< [ 10: 10](R/W) Descriptor access is big-endian. Keep this set to 0 (little-endian) and use the
5388 USBDRD()_UCTL_SHIM_CFG[DMA_ENDIAN_MODE] setting instead.
5389
5390 For diagnostic use only, drivers should be written assuming little-endian. */
5391 uint32_t reserved_8_9 : 2;
5392 uint32_t incr256brstena : 1; /**< [ 7: 7](R/W) INCR256 burst-type enable. Always set to 0. */
5393 uint32_t incr128brstena : 1; /**< [ 6: 6](R/W) INCR128 burst-type enable. Always set to 0. */
5394 uint32_t incr64brstena : 1; /**< [ 5: 5](R/W) INCR64 burst-type enable. Always set to 0. */
5395 uint32_t incr32brstena : 1; /**< [ 4: 4](R/W) INCR32 burst-type enable. Always set to 0. */
5396 uint32_t incr16brstena : 1; /**< [ 3: 3](R/W) INCR16 burst-type enable. Allows the AXI master to generate INCR 16-beat bursts. */
5397 uint32_t incr8brstena : 1; /**< [ 2: 2](R/W) INCR8 burst-type enable. Allows the AXI master to generate INCR eight-beat bursts. */
5398 uint32_t incr4brstena : 1; /**< [ 1: 1](R/W) INCR4 burst-type enable. Allows the AXI master to generate INCR four-beat bursts. */
5399 uint32_t incrbrstena : 1; /**< [ 0: 0](R/W) Undefined-length INCR burst-type enable.
5400 This bit determines the set of burst lengths to be utilized by the master interface. It
5401 works in conjunction with the GSBUSCFG0[7:1] enables (INCR*BRSTENA).
5402
5403 If disabled, the AXI master will use only the burst lengths
5404 1, 4, 8, 16 (assuming the INCR*BRSTENA are set to their reset values).
5405
5406 If enabled, the AXI master uses any length less than or equal to the largest-enabled burst
5407 length based on the INCR*BRSTENA fields. */
5408 #else /* Word 0 - Little Endian */
5409 uint32_t incrbrstena : 1; /**< [ 0: 0](R/W) Undefined-length INCR burst-type enable.
5410 This bit determines the set of burst lengths to be utilized by the master interface. It
5411 works in conjunction with the GSBUSCFG0[7:1] enables (INCR*BRSTENA).
5412
5413 If disabled, the AXI master will use only the burst lengths
5414 1, 4, 8, 16 (assuming the INCR*BRSTENA are set to their reset values).
5415
5416 If enabled, the AXI master uses any length less than or equal to the largest-enabled burst
5417 length based on the INCR*BRSTENA fields. */
5418 uint32_t incr4brstena : 1; /**< [ 1: 1](R/W) INCR4 burst-type enable. Allows the AXI master to generate INCR four-beat bursts. */
5419 uint32_t incr8brstena : 1; /**< [ 2: 2](R/W) INCR8 burst-type enable. Allows the AXI master to generate INCR eight-beat bursts. */
5420 uint32_t incr16brstena : 1; /**< [ 3: 3](R/W) INCR16 burst-type enable. Allows the AXI master to generate INCR 16-beat bursts. */
5421 uint32_t incr32brstena : 1; /**< [ 4: 4](R/W) INCR32 burst-type enable. Always set to 0. */
5422 uint32_t incr64brstena : 1; /**< [ 5: 5](R/W) INCR64 burst-type enable. Always set to 0. */
5423 uint32_t incr128brstena : 1; /**< [ 6: 6](R/W) INCR128 burst-type enable. Always set to 0. */
5424 uint32_t incr256brstena : 1; /**< [ 7: 7](R/W) INCR256 burst-type enable. Always set to 0. */
5425 uint32_t reserved_8_9 : 2;
5426 uint32_t descbigend : 1; /**< [ 10: 10](R/W) Descriptor access is big-endian. Keep this set to 0 (little-endian) and use the
5427 USBDRD()_UCTL_SHIM_CFG[DMA_ENDIAN_MODE] setting instead.
5428
5429 For diagnostic use only, drivers should be written assuming little-endian. */
5430 uint32_t datbigend : 1; /**< [ 11: 11](R/W) Data access is big-endian. Keep this set to 0 (little-endian) and use the
5431 USBDRD()_UCTL_SHIM_CFG[DMA_ENDIAN_MODE] setting instead.
5432
5433 For diagnostic use only, drivers should be written assuming little-endian. */
5434 uint32_t reserved_12_15 : 4;
5435 uint32_t deswrreqinfo : 4; /**< [ 19: 16](R/W) AXI-cache for descriptor-write operations. Always set to 0x0. */
5436 uint32_t datwrreqinfo : 4; /**< [ 23: 20](R/W) AXI-cache for data-write operations. Always set to 0x0. */
5437 uint32_t desrdreqinfo : 4; /**< [ 27: 24](R/W) AXI-cache for descriptor-read operations. Always set to 0x0. */
5438 uint32_t datrdreqinfo : 4; /**< [ 31: 28](R/W) AXI-cache for data-read operations. Always set to 0x0. */
5439 #endif /* Word 0 - End */
5440 } s;
5441 /* struct bdk_usbdrdx_uahc_gsbuscfg0_s cn8; */
5442 struct bdk_usbdrdx_uahc_gsbuscfg0_cn9
5443 {
5444 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5445 uint32_t datrdreqinfo : 4; /**< [ 31: 28](R/W) AXI-cache for data-read operations. Always set to 0x0. */
5446 uint32_t desrdreqinfo : 4; /**< [ 27: 24](R/W) AXI-cache for descriptor-read operations. Always set to 0x0. */
5447 uint32_t datwrreqinfo : 4; /**< [ 23: 20](R/W) AXI-cache for data-write operations. Always set to 0x0. */
5448 uint32_t deswrreqinfo : 4; /**< [ 19: 16](R/W) AXI-cache for descriptor-write operations. Always set to 0x0. */
5449 uint32_t reserved_12_15 : 4;
5450 uint32_t datbigend : 1; /**< [ 11: 11](R/W) Data access is big-endian. Keep this set to 0 (little-endian) and use the
5451 USBDRD()_UCTL_SHIM_CFG[DMA_ENDIAN_MODE] setting instead.
5452
5453 For diagnostic use only, drivers should be written assuming little-endian. */
5454 uint32_t descbigend : 1; /**< [ 10: 10](R/W) Descriptor access is big-endian. Keep this set to 0 (little-endian) and use the
5455 USBDRD()_UCTL_SHIM_CFG[DMA_ENDIAN_MODE] setting instead.
5456
5457 For diagnostic use only, drivers should be written assuming little-endian. */
5458 uint32_t reserved_8_9 : 2;
5459 uint32_t incr256brstena : 1; /**< [ 7: 7](R/W) INCR256 burst-type enable. Always set to 0. */
5460 uint32_t incr128brstena : 1; /**< [ 6: 6](R/W) INCR128 burst-type enable. Always set to 0. */
5461 uint32_t incr64brstena : 1; /**< [ 5: 5](R/W) INCR64 burst-type enable. Always set to 0. */
5462 uint32_t incr32brstena : 1; /**< [ 4: 4](R/W) INCR32 burst-type enable. Always set to 0. */
5463 uint32_t incr16brstena : 1; /**< [ 3: 3](R/W) INCR16 burst-type enable. Always set to 0. */
5464 uint32_t incr8brstena : 1; /**< [ 2: 2](R/W) INCR8 burst-type enable. Allows the AXI master to generate INCR eight-beat bursts. */
5465 uint32_t incr4brstena : 1; /**< [ 1: 1](R/W) INCR4 burst-type enable. Allows the AXI master to generate INCR four-beat bursts. */
5466 uint32_t incrbrstena : 1; /**< [ 0: 0](R/W) Undefined-length INCR burst-type enable.
5467 This bit determines the set of burst lengths to be utilized by the master interface. It
5468 works in conjunction with the GSBUSCFG0[7:1] enables (INCR*BRSTENA).
5469
5470 If disabled, the AXI master will use only the burst lengths
5471 1, 4, 8, 16 (assuming the INCR*BRSTENA are set to their reset values).
5472
5473 If enabled, the AXI master uses any length less than or equal to the largest-enabled burst
5474 length based on the INCR*BRSTENA fields. */
5475 #else /* Word 0 - Little Endian */
5476 uint32_t incrbrstena : 1; /**< [ 0: 0](R/W) Undefined-length INCR burst-type enable.
5477 This bit determines the set of burst lengths to be utilized by the master interface. It
5478 works in conjunction with the GSBUSCFG0[7:1] enables (INCR*BRSTENA).
5479
5480 If disabled, the AXI master will use only the burst lengths
5481 1, 4, 8, 16 (assuming the INCR*BRSTENA are set to their reset values).
5482
5483 If enabled, the AXI master uses any length less than or equal to the largest-enabled burst
5484 length based on the INCR*BRSTENA fields. */
5485 uint32_t incr4brstena : 1; /**< [ 1: 1](R/W) INCR4 burst-type enable. Allows the AXI master to generate INCR four-beat bursts. */
5486 uint32_t incr8brstena : 1; /**< [ 2: 2](R/W) INCR8 burst-type enable. Allows the AXI master to generate INCR eight-beat bursts. */
5487 uint32_t incr16brstena : 1; /**< [ 3: 3](R/W) INCR16 burst-type enable. Always set to 0. */
5488 uint32_t incr32brstena : 1; /**< [ 4: 4](R/W) INCR32 burst-type enable. Always set to 0. */
5489 uint32_t incr64brstena : 1; /**< [ 5: 5](R/W) INCR64 burst-type enable. Always set to 0. */
5490 uint32_t incr128brstena : 1; /**< [ 6: 6](R/W) INCR128 burst-type enable. Always set to 0. */
5491 uint32_t incr256brstena : 1; /**< [ 7: 7](R/W) INCR256 burst-type enable. Always set to 0. */
5492 uint32_t reserved_8_9 : 2;
5493 uint32_t descbigend : 1; /**< [ 10: 10](R/W) Descriptor access is big-endian. Keep this set to 0 (little-endian) and use the
5494 USBDRD()_UCTL_SHIM_CFG[DMA_ENDIAN_MODE] setting instead.
5495
5496 For diagnostic use only, drivers should be written assuming little-endian. */
5497 uint32_t datbigend : 1; /**< [ 11: 11](R/W) Data access is big-endian. Keep this set to 0 (little-endian) and use the
5498 USBDRD()_UCTL_SHIM_CFG[DMA_ENDIAN_MODE] setting instead.
5499
5500 For diagnostic use only, drivers should be written assuming little-endian. */
5501 uint32_t reserved_12_15 : 4;
5502 uint32_t deswrreqinfo : 4; /**< [ 19: 16](R/W) AXI-cache for descriptor-write operations. Always set to 0x0. */
5503 uint32_t datwrreqinfo : 4; /**< [ 23: 20](R/W) AXI-cache for data-write operations. Always set to 0x0. */
5504 uint32_t desrdreqinfo : 4; /**< [ 27: 24](R/W) AXI-cache for descriptor-read operations. Always set to 0x0. */
5505 uint32_t datrdreqinfo : 4; /**< [ 31: 28](R/W) AXI-cache for data-read operations. Always set to 0x0. */
5506 #endif /* Word 0 - End */
5507 } cn9;
5508 };
5509 typedef union bdk_usbdrdx_uahc_gsbuscfg0 bdk_usbdrdx_uahc_gsbuscfg0_t;
5510
5511 static inline uint64_t BDK_USBDRDX_UAHC_GSBUSCFG0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GSBUSCFG0(unsigned long a)5512 static inline uint64_t BDK_USBDRDX_UAHC_GSBUSCFG0(unsigned long a)
5513 {
5514 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5515 return 0x86800000c100ll + 0x1000000000ll * ((a) & 0x1);
5516 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5517 return 0x86800000c100ll + 0x1000000000ll * ((a) & 0x1);
5518 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
5519 return 0x86800000c100ll + 0x1000000000ll * ((a) & 0x1);
5520 __bdk_csr_fatal("USBDRDX_UAHC_GSBUSCFG0", 1, a, 0, 0, 0);
5521 }
5522
5523 #define typedef_BDK_USBDRDX_UAHC_GSBUSCFG0(a) bdk_usbdrdx_uahc_gsbuscfg0_t
5524 #define bustype_BDK_USBDRDX_UAHC_GSBUSCFG0(a) BDK_CSR_TYPE_NCB32b
5525 #define basename_BDK_USBDRDX_UAHC_GSBUSCFG0(a) "USBDRDX_UAHC_GSBUSCFG0"
5526 #define device_bar_BDK_USBDRDX_UAHC_GSBUSCFG0(a) 0x0 /* PF_BAR0 */
5527 #define busnum_BDK_USBDRDX_UAHC_GSBUSCFG0(a) (a)
5528 #define arguments_BDK_USBDRDX_UAHC_GSBUSCFG0(a) (a),-1,-1,-1
5529
5530 /**
5531 * Register (NCB32b) usbdrd#_uahc_gsbuscfg1
5532 *
5533 * USB UAHC Bus Configuration Register 1
5534 * This register can be used to configure the core after power-on or a change in mode of
5535 * operation. This register mainly contains AXI system-related configuration parameters. Do not
5536 * change this register after the initial programming. The application must program this register
5537 * before starting any transactions on AXI.
5538 *
5539 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5540 *
5541 * Internal:
5542 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.2.
5543 */
5544 union bdk_usbdrdx_uahc_gsbuscfg1
5545 {
5546 uint32_t u;
5547 struct bdk_usbdrdx_uahc_gsbuscfg1_s
5548 {
5549 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5550 uint32_t reserved_13_31 : 19;
5551 uint32_t en1kpage : 1; /**< [ 12: 12](R/W) 1K page-boundary enable.
5552 0 = Break transfers at the 4K page boundary (default).
5553 1 = Break transfers at the 1K page boundary. */
5554 uint32_t pipetranslimit : 4; /**< [ 11: 8](R/W) AXI pipelined transfers burst-request limit. Controls the number of outstanding pipelined
5555 transfers requests the AXI master will push to the AXI slave. Once the AXI master reaches
5556 this limit, it does not make more requests on the AXI ARADDR and AWADDR buses until the
5557 associated data phases complete. This field is encoded as follows:
5558 0x0 = 1 request. 0x8 = 9 requests.
5559 0x1 = 2 requests. 0x9 = 10 requests.
5560 0x2 = 3 requests. 0xA = 11 requests.
5561 0x3 = 4 requests. 0xB = 12 requests.
5562 0x4 = 5 requests. 0xC = 13 requests.
5563 0x5 = 6 requests. 0xD = 14 requests.
5564 0x6 = 7 requests. 0xE = 15 requests.
5565 0x7 = 8 requests. 0xF = 16 requests. */
5566 uint32_t reserved_0_7 : 8;
5567 #else /* Word 0 - Little Endian */
5568 uint32_t reserved_0_7 : 8;
5569 uint32_t pipetranslimit : 4; /**< [ 11: 8](R/W) AXI pipelined transfers burst-request limit. Controls the number of outstanding pipelined
5570 transfers requests the AXI master will push to the AXI slave. Once the AXI master reaches
5571 this limit, it does not make more requests on the AXI ARADDR and AWADDR buses until the
5572 associated data phases complete. This field is encoded as follows:
5573 0x0 = 1 request. 0x8 = 9 requests.
5574 0x1 = 2 requests. 0x9 = 10 requests.
5575 0x2 = 3 requests. 0xA = 11 requests.
5576 0x3 = 4 requests. 0xB = 12 requests.
5577 0x4 = 5 requests. 0xC = 13 requests.
5578 0x5 = 6 requests. 0xD = 14 requests.
5579 0x6 = 7 requests. 0xE = 15 requests.
5580 0x7 = 8 requests. 0xF = 16 requests. */
5581 uint32_t en1kpage : 1; /**< [ 12: 12](R/W) 1K page-boundary enable.
5582 0 = Break transfers at the 4K page boundary (default).
5583 1 = Break transfers at the 1K page boundary. */
5584 uint32_t reserved_13_31 : 19;
5585 #endif /* Word 0 - End */
5586 } s;
5587 /* struct bdk_usbdrdx_uahc_gsbuscfg1_s cn; */
5588 };
5589 typedef union bdk_usbdrdx_uahc_gsbuscfg1 bdk_usbdrdx_uahc_gsbuscfg1_t;
5590
5591 static inline uint64_t BDK_USBDRDX_UAHC_GSBUSCFG1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GSBUSCFG1(unsigned long a)5592 static inline uint64_t BDK_USBDRDX_UAHC_GSBUSCFG1(unsigned long a)
5593 {
5594 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5595 return 0x86800000c104ll + 0x1000000000ll * ((a) & 0x1);
5596 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5597 return 0x86800000c104ll + 0x1000000000ll * ((a) & 0x1);
5598 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
5599 return 0x86800000c104ll + 0x1000000000ll * ((a) & 0x1);
5600 __bdk_csr_fatal("USBDRDX_UAHC_GSBUSCFG1", 1, a, 0, 0, 0);
5601 }
5602
5603 #define typedef_BDK_USBDRDX_UAHC_GSBUSCFG1(a) bdk_usbdrdx_uahc_gsbuscfg1_t
5604 #define bustype_BDK_USBDRDX_UAHC_GSBUSCFG1(a) BDK_CSR_TYPE_NCB32b
5605 #define basename_BDK_USBDRDX_UAHC_GSBUSCFG1(a) "USBDRDX_UAHC_GSBUSCFG1"
5606 #define device_bar_BDK_USBDRDX_UAHC_GSBUSCFG1(a) 0x0 /* PF_BAR0 */
5607 #define busnum_BDK_USBDRDX_UAHC_GSBUSCFG1(a) (a)
5608 #define arguments_BDK_USBDRDX_UAHC_GSBUSCFG1(a) (a),-1,-1,-1
5609
5610 /**
5611 * Register (NCB32b) usbdrd#_uahc_gsts
5612 *
5613 * USB UAHC Core Status Register
5614 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5615 * Internal:
5616 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.7
5617 */
5618 union bdk_usbdrdx_uahc_gsts
5619 {
5620 uint32_t u;
5621 struct bdk_usbdrdx_uahc_gsts_s
5622 {
5623 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5624 uint32_t cbelt : 12; /**< [ 31: 20](RO/H) Current BELT value. In host mode, indicates the minimum value of all received device BELT
5625 values and the BELT value that is set by the set latency tolerance value command. */
5626 uint32_t reserved_8_19 : 12;
5627 uint32_t host_ip : 1; /**< [ 7: 7](RO/H) Host interrupt pending. Indicates that there is a pending interrupt pertaining to xHC in
5628 the host-event queue. */
5629 uint32_t device_ip : 1; /**< [ 6: 6](RO/H) Device interrupt pending. Indicates that there is a pending interrupt pertaining to
5630 peripheral (device) operation in the Device event queue. */
5631 uint32_t csrtimeout : 1; /**< [ 5: 5](R/W1C/H) CSR timeout. When set to 1, indicates that software performed a write or read operation to
5632 a core register that could not be completed within 0xFFFF controller-clock cycles. */
5633 uint32_t buserraddrvld : 1; /**< [ 4: 4](R/W1C/H) Bus-error address valid. Indicates that USBDRD()_UAHC_GBUSERRADDR is valid and reports the
5634 first bus address that encounters a bus error. */
5635 uint32_t reserved_2_3 : 2;
5636 uint32_t curmod : 2; /**< [ 1: 0](RO/H) Current mode of operation. 0x0 for device, 0x1 for host. */
5637 #else /* Word 0 - Little Endian */
5638 uint32_t curmod : 2; /**< [ 1: 0](RO/H) Current mode of operation. 0x0 for device, 0x1 for host. */
5639 uint32_t reserved_2_3 : 2;
5640 uint32_t buserraddrvld : 1; /**< [ 4: 4](R/W1C/H) Bus-error address valid. Indicates that USBDRD()_UAHC_GBUSERRADDR is valid and reports the
5641 first bus address that encounters a bus error. */
5642 uint32_t csrtimeout : 1; /**< [ 5: 5](R/W1C/H) CSR timeout. When set to 1, indicates that software performed a write or read operation to
5643 a core register that could not be completed within 0xFFFF controller-clock cycles. */
5644 uint32_t device_ip : 1; /**< [ 6: 6](RO/H) Device interrupt pending. Indicates that there is a pending interrupt pertaining to
5645 peripheral (device) operation in the Device event queue. */
5646 uint32_t host_ip : 1; /**< [ 7: 7](RO/H) Host interrupt pending. Indicates that there is a pending interrupt pertaining to xHC in
5647 the host-event queue. */
5648 uint32_t reserved_8_19 : 12;
5649 uint32_t cbelt : 12; /**< [ 31: 20](RO/H) Current BELT value. In host mode, indicates the minimum value of all received device BELT
5650 values and the BELT value that is set by the set latency tolerance value command. */
5651 #endif /* Word 0 - End */
5652 } s;
5653 /* struct bdk_usbdrdx_uahc_gsts_s cn; */
5654 };
5655 typedef union bdk_usbdrdx_uahc_gsts bdk_usbdrdx_uahc_gsts_t;
5656
5657 static inline uint64_t BDK_USBDRDX_UAHC_GSTS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GSTS(unsigned long a)5658 static inline uint64_t BDK_USBDRDX_UAHC_GSTS(unsigned long a)
5659 {
5660 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5661 return 0x86800000c118ll + 0x1000000000ll * ((a) & 0x1);
5662 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5663 return 0x86800000c118ll + 0x1000000000ll * ((a) & 0x1);
5664 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
5665 return 0x86800000c118ll + 0x1000000000ll * ((a) & 0x1);
5666 __bdk_csr_fatal("USBDRDX_UAHC_GSTS", 1, a, 0, 0, 0);
5667 }
5668
5669 #define typedef_BDK_USBDRDX_UAHC_GSTS(a) bdk_usbdrdx_uahc_gsts_t
5670 #define bustype_BDK_USBDRDX_UAHC_GSTS(a) BDK_CSR_TYPE_NCB32b
5671 #define basename_BDK_USBDRDX_UAHC_GSTS(a) "USBDRDX_UAHC_GSTS"
5672 #define device_bar_BDK_USBDRDX_UAHC_GSTS(a) 0x0 /* PF_BAR0 */
5673 #define busnum_BDK_USBDRDX_UAHC_GSTS(a) (a)
5674 #define arguments_BDK_USBDRDX_UAHC_GSTS(a) (a),-1,-1,-1
5675
5676 /**
5677 * Register (NCB32b) usbdrd#_uahc_gtxfifopridev
5678 *
5679 * USB UAHC TxFIFOs DMA Priority Register
5680 * This register specifies the relative DMA priority level among the host TxFIFOs (one per USB
5681 * bus instance) within the associated speed group (SuperSpeed or high-speed/full-speed/
5682 * low-speed). When multiple TxFIFOs compete for DMA service at a given time, the TXDMA arbiter
5683 * grants access on a packet-basis in the following manner:
5684 *
5685 * Among the FIFOs in the same speed group (SuperSpeed or high-speed/full-speed/low-speed):
5686 *
5687 * * High-priority TxFIFOs are granted access using round-robin arbitration.
5688 * * Low-priority TxFIFOs are granted access using round-robin arbitration only after high-
5689 * priority
5690 * TxFIFOs have no further processing to do (i.e., either the TXQs are empty or the corresponding
5691 * TxFIFOs do not have the required data).
5692 *
5693 * The TX DMA arbiter prioritizes the SuperSpeed group or high-speed/full-speed/low-speed group
5694 * according to the ratio programmed in
5695 * USBDRD()_UAHC_GDMAHLRATIO.
5696 *
5697 * For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until
5698 * the entire packet is completed. The register size corresponds to the number of configured USB
5699 * bus instances; for example, in the default configuration, there are three USB bus instances (one
5700 * SuperSpeed, one high-speed, and one full-speed/low-speed).
5701 *
5702 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5703 *
5704 * Internal:
5705 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.59
5706 */
5707 union bdk_usbdrdx_uahc_gtxfifopridev
5708 {
5709 uint32_t u;
5710 struct bdk_usbdrdx_uahc_gtxfifopridev_s
5711 {
5712 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5713 uint32_t reserved_3_31 : 29;
5714 uint32_t tx_priority : 3; /**< [ 2: 0](R/W) Each register bit n controls the priority (1 = high, 0 = low) of TxFIFO\<n\> within a speed
5715 group. */
5716 #else /* Word 0 - Little Endian */
5717 uint32_t tx_priority : 3; /**< [ 2: 0](R/W) Each register bit n controls the priority (1 = high, 0 = low) of TxFIFO\<n\> within a speed
5718 group. */
5719 uint32_t reserved_3_31 : 29;
5720 #endif /* Word 0 - End */
5721 } s;
5722 /* struct bdk_usbdrdx_uahc_gtxfifopridev_s cn; */
5723 };
5724 typedef union bdk_usbdrdx_uahc_gtxfifopridev bdk_usbdrdx_uahc_gtxfifopridev_t;
5725
5726 static inline uint64_t BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(unsigned long a)5727 static inline uint64_t BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(unsigned long a)
5728 {
5729 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5730 return 0x86800000c610ll + 0x1000000000ll * ((a) & 0x1);
5731 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5732 return 0x86800000c610ll + 0x1000000000ll * ((a) & 0x1);
5733 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
5734 return 0x86800000c610ll + 0x1000000000ll * ((a) & 0x1);
5735 __bdk_csr_fatal("USBDRDX_UAHC_GTXFIFOPRIDEV", 1, a, 0, 0, 0);
5736 }
5737
5738 #define typedef_BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(a) bdk_usbdrdx_uahc_gtxfifopridev_t
5739 #define bustype_BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(a) BDK_CSR_TYPE_NCB32b
5740 #define basename_BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(a) "USBDRDX_UAHC_GTXFIFOPRIDEV"
5741 #define device_bar_BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(a) 0x0 /* PF_BAR0 */
5742 #define busnum_BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(a) (a)
5743 #define arguments_BDK_USBDRDX_UAHC_GTXFIFOPRIDEV(a) (a),-1,-1,-1
5744
5745 /**
5746 * Register (NCB32b) usbdrd#_uahc_gtxfifoprihst
5747 *
5748 * USB UAHC Global Host TxFIFO DMA Priority Register
5749 * This register specifies the relative DMA priority level among the Host TxFIFOs (one per USB
5750 * bus instance) within the associated speed group (SuperSpeed or HighSpeed/FullSpeed/LowSpeed).
5751 * When multiple TxFIFOs compete for DMA service at a given time, the TXDMA arbiter grants access
5752 * on a packet-basis in the following manner:
5753 *
5754 * 1. Among the FIFOs in the same speed group (SuperSpeed or high-speed/full-speed/low-speed):
5755 *
5756 * _ a. High-priority TxFIFOs are granted access using round-robin arbitration
5757 *
5758 * _ b. Low-priority TxFIFOs are granted access using round-robin arbitration only after the
5759 * high priority TxFIFOs have no further processing to do (i.e., either the TXQs are empty
5760 * or the corresponding TxFIFOs are full).
5761 * or the corresponding TxFIFOs are full).
5762 *
5763 * 2. The TX DMA arbiter prioritizes the SuperSpeed group or high-speed/full-speed/low-speed
5764 * group according to the ratio programmed in USBDRD()_UAHC_GDMAHLRATIO.
5765 *
5766 * For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until
5767 * the entire packet is completed.
5768 * The register size corresponds to the number of configured USB bus instances; for example, in
5769 * the default configuration, there are three USB bus instances (one SuperSpeed, one
5770 * high-speed, and one full-speed/low-speed).
5771 *
5772 * This register can be reset by IOI reset or with USBDRD()_UCTL_CTL[UAHC_RST],
5773 * or USBDRD()_UAHC_GCTL[CORESOFTRESET].
5774 *
5775 * Internal:
5776 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.60
5777 */
5778 union bdk_usbdrdx_uahc_gtxfifoprihst
5779 {
5780 uint32_t u;
5781 struct bdk_usbdrdx_uahc_gtxfifoprihst_s
5782 {
5783 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5784 uint32_t reserved_3_31 : 29;
5785 uint32_t tx_priority : 3; /**< [ 2: 0](R/W) Each register bit n controls the priority (1 = high, 0 = low) of TxFIFO\<n\> within a speed
5786 group. */
5787 #else /* Word 0 - Little Endian */
5788 uint32_t tx_priority : 3; /**< [ 2: 0](R/W) Each register bit n controls the priority (1 = high, 0 = low) of TxFIFO\<n\> within a speed
5789 group. */
5790 uint32_t reserved_3_31 : 29;
5791 #endif /* Word 0 - End */
5792 } s;
5793 /* struct bdk_usbdrdx_uahc_gtxfifoprihst_s cn; */
5794 };
5795 typedef union bdk_usbdrdx_uahc_gtxfifoprihst bdk_usbdrdx_uahc_gtxfifoprihst_t;
5796
5797 static inline uint64_t BDK_USBDRDX_UAHC_GTXFIFOPRIHST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GTXFIFOPRIHST(unsigned long a)5798 static inline uint64_t BDK_USBDRDX_UAHC_GTXFIFOPRIHST(unsigned long a)
5799 {
5800 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5801 return 0x86800000c618ll + 0x1000000000ll * ((a) & 0x1);
5802 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
5803 return 0x86800000c618ll + 0x1000000000ll * ((a) & 0x1);
5804 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
5805 return 0x86800000c618ll + 0x1000000000ll * ((a) & 0x1);
5806 __bdk_csr_fatal("USBDRDX_UAHC_GTXFIFOPRIHST", 1, a, 0, 0, 0);
5807 }
5808
5809 #define typedef_BDK_USBDRDX_UAHC_GTXFIFOPRIHST(a) bdk_usbdrdx_uahc_gtxfifoprihst_t
5810 #define bustype_BDK_USBDRDX_UAHC_GTXFIFOPRIHST(a) BDK_CSR_TYPE_NCB32b
5811 #define basename_BDK_USBDRDX_UAHC_GTXFIFOPRIHST(a) "USBDRDX_UAHC_GTXFIFOPRIHST"
5812 #define device_bar_BDK_USBDRDX_UAHC_GTXFIFOPRIHST(a) 0x0 /* PF_BAR0 */
5813 #define busnum_BDK_USBDRDX_UAHC_GTXFIFOPRIHST(a) (a)
5814 #define arguments_BDK_USBDRDX_UAHC_GTXFIFOPRIHST(a) (a),-1,-1,-1
5815
5816 /**
5817 * Register (NCB32b) usbdrd#_uahc_gtxfifosiz#
5818 *
5819 * USB UAHC TX FIFO Size Registers
5820 * This register holds the internal RAM start address/depth of each TxFIFO implemented. Unless
5821 * packet size/buffer size for each endpoint is different and application-specific, it is
5822 * recommended that the software use the default value. One register per FIFO. One register per
5823 * FIFO.
5824 *
5825 * Reset values = 0:{0x0000_0082} 1:{0x0082_0103} 2:{0x0185_0205}.
5826 *
5827 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5828 *
5829 * Internal:
5830 * See Synopsys DWC_usb3 Databook v2.20a, section 6.2.6.1.
5831 * INTERNAL: For more information, refer to the BMU section in Block Descriptions on Synopsys
5832 * Databook page 238.
5833 */
5834 union bdk_usbdrdx_uahc_gtxfifosizx
5835 {
5836 uint32_t u;
5837 struct bdk_usbdrdx_uahc_gtxfifosizx_s
5838 {
5839 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5840 uint32_t txfstaddr : 16; /**< [ 31: 16](R/W) Transmit FIFOn RAM start address. Contains the memory start address for TxFIFOn. The reset
5841 is value derived from configuration parameters. */
5842 uint32_t txfdep : 16; /**< [ 15: 0](R/W) TxFIFOn depth. This value is in terms of TX RAM data width.
5843 minimum value = 0x20, maximum value = 0x8000.
5844
5845 Internal:
5846 For more information, see the Hardware Integration chapter of the Synopsys
5847 Databook.
5848 The reset value derived from configuration parameters. */
5849 #else /* Word 0 - Little Endian */
5850 uint32_t txfdep : 16; /**< [ 15: 0](R/W) TxFIFOn depth. This value is in terms of TX RAM data width.
5851 minimum value = 0x20, maximum value = 0x8000.
5852
5853 Internal:
5854 For more information, see the Hardware Integration chapter of the Synopsys
5855 Databook.
5856 The reset value derived from configuration parameters. */
5857 uint32_t txfstaddr : 16; /**< [ 31: 16](R/W) Transmit FIFOn RAM start address. Contains the memory start address for TxFIFOn. The reset
5858 is value derived from configuration parameters. */
5859 #endif /* Word 0 - End */
5860 } s;
5861 /* struct bdk_usbdrdx_uahc_gtxfifosizx_s cn; */
5862 };
5863 typedef union bdk_usbdrdx_uahc_gtxfifosizx bdk_usbdrdx_uahc_gtxfifosizx_t;
5864
5865 static inline uint64_t BDK_USBDRDX_UAHC_GTXFIFOSIZX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GTXFIFOSIZX(unsigned long a,unsigned long b)5866 static inline uint64_t BDK_USBDRDX_UAHC_GTXFIFOSIZX(unsigned long a, unsigned long b)
5867 {
5868 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
5869 return 0x86800000c300ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x3);
5870 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=3)))
5871 return 0x86800000c300ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x3);
5872 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=3)))
5873 return 0x86800000c300ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x3);
5874 __bdk_csr_fatal("USBDRDX_UAHC_GTXFIFOSIZX", 2, a, b, 0, 0);
5875 }
5876
5877 #define typedef_BDK_USBDRDX_UAHC_GTXFIFOSIZX(a,b) bdk_usbdrdx_uahc_gtxfifosizx_t
5878 #define bustype_BDK_USBDRDX_UAHC_GTXFIFOSIZX(a,b) BDK_CSR_TYPE_NCB32b
5879 #define basename_BDK_USBDRDX_UAHC_GTXFIFOSIZX(a,b) "USBDRDX_UAHC_GTXFIFOSIZX"
5880 #define device_bar_BDK_USBDRDX_UAHC_GTXFIFOSIZX(a,b) 0x0 /* PF_BAR0 */
5881 #define busnum_BDK_USBDRDX_UAHC_GTXFIFOSIZX(a,b) (a)
5882 #define arguments_BDK_USBDRDX_UAHC_GTXFIFOSIZX(a,b) (a),(b),-1,-1
5883
5884 /**
5885 * Register (NCB32b) usbdrd#_uahc_gtxthrcfg
5886 *
5887 * USB UAHC TX Threshold Control Register
5888 * In a normal case, a TX burst starts as soon as one packet is prefetched. This works well as
5889 * long as the system bus is faster than the USB3.0 bus (a 1024-bytes packet takes ~2.2 us on the
5890 * USB bus in SuperSpeed mode). If the system bus latency is larger than 2.2 us to access a
5891 * 1024-byte packet, then starting a burst on 1-packet condition leads to an early abort of the
5892 * burst causing unnecessary performance reduction. This register allows the configuration of
5893 * threshold and burst size control. This feature is enabled by [USBTXPKTCNTSEL].
5894 *
5895 * Transmit path:
5896 * * The TX threshold is controlled by [USBTXPKTCNT], and the TX burst size is controlled by
5897 * [USBMAXTXBURSTSIZE].
5898 * * Selecting optimal TxFIFO size, TX threshold, and TX burst size avoids TX burst aborts due
5899 * to an underrun if the system bus is slower than USB. Once in a while an underrun is OK, and
5900 * there is no functional issue.
5901 * * A larger threshold affects the performance, since the scheduler is idle during this time.
5902 *
5903 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
5904 *
5905 * Internal:
5906 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.3
5907 */
5908 union bdk_usbdrdx_uahc_gtxthrcfg
5909 {
5910 uint32_t u;
5911 struct bdk_usbdrdx_uahc_gtxthrcfg_s
5912 {
5913 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5914 uint32_t reserved_30_31 : 2;
5915 uint32_t usbtxpktcntsel : 1; /**< [ 29: 29](R/W) USB transmit packet-count enable. Enables/disables the USB transmission multipacket
5916 thresholding:
5917 0 = USB transmission multipacket thresholding is disabled, the core can only start
5918 transmission on the USB after the entire packet has been fetched into the corresponding
5919 TxFIFO.
5920 1 = USB transmission multipacket thresholding is enabled. The core can only start
5921 transmission on the USB after USBTXPKTCNT amount of packets for the USB transaction
5922 (burst) are already in the corresponding TxFIFO.
5923 This mode is only used for SuperSpeed. */
5924 uint32_t reserved_28 : 1;
5925 uint32_t usbtxpktcnt : 4; /**< [ 27: 24](R/W) USB transmit-packet count. Specifies the number of packets that must be in the TxFIFO
5926 before the core can start transmission for the corresponding USB transaction (burst). This
5927 field is only valid when [USBTXPKTCNTSEL] = 1. Valid values are from 0x1 to 0xF.
5928 This field must be \<= [USBMAXTXBURSTSIZE]. */
5929 uint32_t usbmaxtxburstsize : 8; /**< [ 23: 16](R/W) USB maximum TX burst size. When [USBTXPKTCNTSEL] = 1, this field specifies the
5930 maximum bulk OUT burst the core should do. When the system bus is slower than
5931 the USB, TxFIFO can underrun during a long burst. Program a smaller value to
5932 this field to limit the TX burst size that the core can do. It only applies to
5933 SuperSpeed bulk, isochronous, and interrupt OUT endpoints in the host
5934 mode. Valid values are from 0x1 to 0x10. */
5935 uint32_t reserved_0_15 : 16;
5936 #else /* Word 0 - Little Endian */
5937 uint32_t reserved_0_15 : 16;
5938 uint32_t usbmaxtxburstsize : 8; /**< [ 23: 16](R/W) USB maximum TX burst size. When [USBTXPKTCNTSEL] = 1, this field specifies the
5939 maximum bulk OUT burst the core should do. When the system bus is slower than
5940 the USB, TxFIFO can underrun during a long burst. Program a smaller value to
5941 this field to limit the TX burst size that the core can do. It only applies to
5942 SuperSpeed bulk, isochronous, and interrupt OUT endpoints in the host
5943 mode. Valid values are from 0x1 to 0x10. */
5944 uint32_t usbtxpktcnt : 4; /**< [ 27: 24](R/W) USB transmit-packet count. Specifies the number of packets that must be in the TxFIFO
5945 before the core can start transmission for the corresponding USB transaction (burst). This
5946 field is only valid when [USBTXPKTCNTSEL] = 1. Valid values are from 0x1 to 0xF.
5947 This field must be \<= [USBMAXTXBURSTSIZE]. */
5948 uint32_t reserved_28 : 1;
5949 uint32_t usbtxpktcntsel : 1; /**< [ 29: 29](R/W) USB transmit packet-count enable. Enables/disables the USB transmission multipacket
5950 thresholding:
5951 0 = USB transmission multipacket thresholding is disabled, the core can only start
5952 transmission on the USB after the entire packet has been fetched into the corresponding
5953 TxFIFO.
5954 1 = USB transmission multipacket thresholding is enabled. The core can only start
5955 transmission on the USB after USBTXPKTCNT amount of packets for the USB transaction
5956 (burst) are already in the corresponding TxFIFO.
5957 This mode is only used for SuperSpeed. */
5958 uint32_t reserved_30_31 : 2;
5959 #endif /* Word 0 - End */
5960 } s;
5961 struct bdk_usbdrdx_uahc_gtxthrcfg_cn
5962 {
5963 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5964 uint32_t reserved_30_31 : 2;
5965 uint32_t usbtxpktcntsel : 1; /**< [ 29: 29](R/W) USB transmit packet-count enable. Enables/disables the USB transmission multipacket
5966 thresholding:
5967 0 = USB transmission multipacket thresholding is disabled, the core can only start
5968 transmission on the USB after the entire packet has been fetched into the corresponding
5969 TxFIFO.
5970 1 = USB transmission multipacket thresholding is enabled. The core can only start
5971 transmission on the USB after USBTXPKTCNT amount of packets for the USB transaction
5972 (burst) are already in the corresponding TxFIFO.
5973 This mode is only used for SuperSpeed. */
5974 uint32_t reserved_28 : 1;
5975 uint32_t usbtxpktcnt : 4; /**< [ 27: 24](R/W) USB transmit-packet count. Specifies the number of packets that must be in the TxFIFO
5976 before the core can start transmission for the corresponding USB transaction (burst). This
5977 field is only valid when [USBTXPKTCNTSEL] = 1. Valid values are from 0x1 to 0xF.
5978 This field must be \<= [USBMAXTXBURSTSIZE]. */
5979 uint32_t usbmaxtxburstsize : 8; /**< [ 23: 16](R/W) USB maximum TX burst size. When [USBTXPKTCNTSEL] = 1, this field specifies the
5980 maximum bulk OUT burst the core should do. When the system bus is slower than
5981 the USB, TxFIFO can underrun during a long burst. Program a smaller value to
5982 this field to limit the TX burst size that the core can do. It only applies to
5983 SuperSpeed bulk, isochronous, and interrupt OUT endpoints in the host
5984 mode. Valid values are from 0x1 to 0x10. */
5985 uint32_t reserved_14_15 : 2;
5986 uint32_t reserved_10_13 : 4;
5987 uint32_t reserved_0_9 : 10;
5988 #else /* Word 0 - Little Endian */
5989 uint32_t reserved_0_9 : 10;
5990 uint32_t reserved_10_13 : 4;
5991 uint32_t reserved_14_15 : 2;
5992 uint32_t usbmaxtxburstsize : 8; /**< [ 23: 16](R/W) USB maximum TX burst size. When [USBTXPKTCNTSEL] = 1, this field specifies the
5993 maximum bulk OUT burst the core should do. When the system bus is slower than
5994 the USB, TxFIFO can underrun during a long burst. Program a smaller value to
5995 this field to limit the TX burst size that the core can do. It only applies to
5996 SuperSpeed bulk, isochronous, and interrupt OUT endpoints in the host
5997 mode. Valid values are from 0x1 to 0x10. */
5998 uint32_t usbtxpktcnt : 4; /**< [ 27: 24](R/W) USB transmit-packet count. Specifies the number of packets that must be in the TxFIFO
5999 before the core can start transmission for the corresponding USB transaction (burst). This
6000 field is only valid when [USBTXPKTCNTSEL] = 1. Valid values are from 0x1 to 0xF.
6001 This field must be \<= [USBMAXTXBURSTSIZE]. */
6002 uint32_t reserved_28 : 1;
6003 uint32_t usbtxpktcntsel : 1; /**< [ 29: 29](R/W) USB transmit packet-count enable. Enables/disables the USB transmission multipacket
6004 thresholding:
6005 0 = USB transmission multipacket thresholding is disabled, the core can only start
6006 transmission on the USB after the entire packet has been fetched into the corresponding
6007 TxFIFO.
6008 1 = USB transmission multipacket thresholding is enabled. The core can only start
6009 transmission on the USB after USBTXPKTCNT amount of packets for the USB transaction
6010 (burst) are already in the corresponding TxFIFO.
6011 This mode is only used for SuperSpeed. */
6012 uint32_t reserved_30_31 : 2;
6013 #endif /* Word 0 - End */
6014 } cn;
6015 };
6016 typedef union bdk_usbdrdx_uahc_gtxthrcfg bdk_usbdrdx_uahc_gtxthrcfg_t;
6017
6018 static inline uint64_t BDK_USBDRDX_UAHC_GTXTHRCFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GTXTHRCFG(unsigned long a)6019 static inline uint64_t BDK_USBDRDX_UAHC_GTXTHRCFG(unsigned long a)
6020 {
6021 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6022 return 0x86800000c108ll + 0x1000000000ll * ((a) & 0x1);
6023 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
6024 return 0x86800000c108ll + 0x1000000000ll * ((a) & 0x1);
6025 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6026 return 0x86800000c108ll + 0x1000000000ll * ((a) & 0x1);
6027 __bdk_csr_fatal("USBDRDX_UAHC_GTXTHRCFG", 1, a, 0, 0, 0);
6028 }
6029
6030 #define typedef_BDK_USBDRDX_UAHC_GTXTHRCFG(a) bdk_usbdrdx_uahc_gtxthrcfg_t
6031 #define bustype_BDK_USBDRDX_UAHC_GTXTHRCFG(a) BDK_CSR_TYPE_NCB32b
6032 #define basename_BDK_USBDRDX_UAHC_GTXTHRCFG(a) "USBDRDX_UAHC_GTXTHRCFG"
6033 #define device_bar_BDK_USBDRDX_UAHC_GTXTHRCFG(a) 0x0 /* PF_BAR0 */
6034 #define busnum_BDK_USBDRDX_UAHC_GTXTHRCFG(a) (a)
6035 #define arguments_BDK_USBDRDX_UAHC_GTXTHRCFG(a) (a),-1,-1,-1
6036
6037 /**
6038 * Register (NCB32b) usbdrd#_uahc_guctl
6039 *
6040 * USB UAHC Core User-Control Register
6041 * This register provides a few options for the software to control the core behavior in the host
6042 * mode. Most of the options are used to improve host interoperability with different devices.
6043 *
6044 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
6045 *
6046 * Internal:
6047 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.12
6048 */
6049 union bdk_usbdrdx_uahc_guctl
6050 {
6051 uint32_t u;
6052 struct bdk_usbdrdx_uahc_guctl_s
6053 {
6054 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6055 uint32_t refclkper : 10; /**< [ 31: 22](R/W) Reference-clock period. Indicates (in terms of ns) the period of REF_CLK. The default
6056 value is set to 0x8
6057 (8 ns/125 MHz). This field must be updated during power on initialization if
6058 USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1 or USBDRD()_UAHC_GFLADJ [GFLADJ_REFCLK_LPM_SEL] = 1.
6059 The
6060 programmable maximum value 62 ns, and the minimum value is 8 ns. You use a reference clock
6061 with a period that is a integer multiple, so that ITP can meet the jitter margin of 32 ns.
6062 The allowable REF_CLK frequencies whose period is not integer multiples are
6063 16/17/19.2/24/39.7 MHz.
6064
6065 This field should not be set to 0x0 at any time. If you do not plan to use this feature,
6066 then you need to set this field to 0x8, the default value. */
6067 uint32_t noextrdl : 1; /**< [ 21: 21](R/W) No extra delay between SOF and the first packet.
6068 Some high-speed devices misbehave when the host sends a packet immediately after an SOF.
6069 However, adding an extra delay between an SOF and the first packet can reduce the USB data
6070 rate and performance.
6071
6072 This bit is used to control whether the host should wait for 2 us before it sends the
6073 first packet after a SOF, or not. You can set this bit to 1 to improve the performance if
6074 those problematic devices are not a concern in your host environment.
6075 0 = host waits for 2 us after an SOF before it sends the first USB packet.
6076 1 = host does not wait after an SOF before it sends the first USB packet. */
6077 uint32_t psqextrressp : 3; /**< [ 20: 18](R/W) PSQ extra reserved space. This is a debug feature, and is not intended for normal usage.
6078 This parameter specifies how much additional space in the PSQ (protocol-status queue) must
6079 be reserved before the U3PTL initiates a new USB transaction and burst beats. */
6080 uint32_t sprsctrltransen : 1; /**< [ 17: 17](R/W) Sparse control transaction enable. Some devices are slow in responding to control
6081 transfers. Scheduling multiple transactions in one microframe/frame can cause these
6082 devices to misbehave. If this bit is set to 1, the host controller schedules transactions
6083 for a control transfer in different microframes/frames. */
6084 uint32_t resbwhseps : 1; /**< [ 16: 16](R/W) Reserving 85% bandwidth for high-speed periodic EPs. By default, host controller reserves
6085 80% of the bandwidth for periodic EPs. If this bit is set, the bandwidth is relaxed to 85%
6086 to accommodate two high-speed, high-bandwidth ISOC EPs.
6087
6088 USB 2.0 required 80% bandwidth allocated for ISOC traffic. If two high bandwidth ISOC
6089 devices (HD webcams) are connected, and if each requires 1024-bytes * 3 packets per
6090 microframe, then the bandwidth required is around 82%. If this bit is set to 1, it is
6091 possible to connect two webcams of 1024 bytes * 3 payload per microframe each. Otherwise,
6092 you may have to reduce the resolution of the webcams. */
6093 uint32_t cmdevaddr : 1; /**< [ 15: 15](R/W) Compliance mode for device address. When set to 1, slot ID can have different value than
6094 device address if max_slot_enabled \< 128.
6095 0 = Device address is equal to slot ID.
6096 1 = Increment device address on each address device command.
6097
6098 The xHCI compliance requires this bit to be set to 1. The 0 mode is for debug purpose
6099 only. This allows you to easily identify a device connected to a port in the Lecroy or
6100 Eliisys trace during hardware debug.
6101
6102 This bit is used in host mode only. */
6103 uint32_t usbdrdstinautoretryen : 1; /**< [ 14: 14](R/W) Host IN auto-retry enable. When set, this field enables the auto-retry feature. For IN
6104 transfers (non-isochronous) that encounter data packets with CRC errors or internal
6105 overrun scenarios, the auto-retry feature causes the host core to reply to the device with
6106 a non-terminating retry ACK (i.e. an ACK transaction packet with Retry = 1 and NumP != 0).
6107 If the auto-retry feature is disabled (default), the core responds with a terminating
6108 retry ACK (i.e. an ACK transaction packet with Retry = 1 and NumP = 0). */
6109 uint32_t enoverlapchk : 1; /**< [ 13: 13](R/W) Enable check for LFPS overlap during remote Ux Exit. If this bit is set to:
6110 0 = When the link exists U1/U2/U3 because of a remote exit, it does not look for an LFPS
6111 overlap.
6112 1 = The SuperSpeed link, when exiting U1/U2/U3, waits for either the remote link LFPS or
6113 TS1/TS2 training symbols before it confirms that the LFPS handshake is complete. This is
6114 done to handle the case where the LFPS glitch causes the link to start exiting from the
6115 low power state. Looking for the LFPS overlap makes sure that the link partner also sees
6116 the LFPS. */
6117 uint32_t extcapsupten : 1; /**< [ 12: 12](R/W) External extended capability support enable. If disabled, a read
6118 USBDRD()_UAHC_SUPTPRT3_DW0
6119 [NEXTCAPPTR] returns 0 in the next capability pointer field. This indicates there are no
6120 more capabilities. If enabled, a read to USBDRD()_UAHC_SUPTPRT3_DW0[NEXTCAPPTR] returns 4
6121 in
6122 the
6123 next capability pointer field.
6124 Always set to 0x0. */
6125 uint32_t insrtextrfsbodi : 1; /**< [ 11: 11](R/W) Insert extra delay between full-speed bulk OUT transactions. Some full-speed devices are
6126 slow to receive bulk OUT data and can get stuck when there are consecutive bulk OUT
6127 transactions with short inter-transaction delays. This bit is used to control whether the
6128 host inserts extra delay between consecutive bulk OUT transactions to a full-speed
6129 endpoint.
6130 0 = Host does not insert extra delay.
6131 Setting this bit to 1 reduces the bulk OUT transfer performance for most of the full-speed
6132 devices.
6133 1 = Host inserts about 12 us extra delay between consecutive bulk OUT transactions to an
6134 full-speed endpoint to work around the device issue. */
6135 uint32_t dtct : 2; /**< [ 10: 9](R/W) Device timeout coarse tuning. This field determines how long the host waits for a response
6136 from device before considering a timeout.
6137 The core first checks the [DTCT] value. If it is 0, then the timeout value is defined by
6138 the
6139 [DTFT]. If it is nonzero, then it uses the following timeout values:
6140 0x0 = 0 us; use [DTFT] value instead.
6141 0x1 = 500 us.
6142 0x2 = 1.5 ms.
6143 0x3 = 6.5 ms. */
6144 uint32_t dtft : 9; /**< [ 8: 0](R/W) Device timeout fine tuning. This field determines how long the host waits for a response
6145 from a device before considering a timeout. For [DTFT] to take effect, [DTCT] must be set
6146 to
6147 0x0.
6148 The [DTFT] value specifies the number of 125 MHz clock cycles * 256 to count before
6149 considering a device timeout. For the 125 MHz clock cycles (8 ns period), this is
6150 calculated as follows:
6151 _ [DTFT value] * 256 * 8 (ns)
6152 0x2 = 2 * 256 * 8 -\> 4 us.
6153 0x5 = 5 * 256 * 8 -\> 10 us.
6154 0xA = 10 * 256 * 8 -\> 20 us.
6155 0x10 = 16 * 256 * 8 -\> 32 us.
6156 0x19 = 25 * 256 * 8 -\> 51 us.
6157 0x31 = 49 * 256 * 8 -\> 100 us.
6158 0x62 = 98 * 256 * 8 -\> 200 us. */
6159 #else /* Word 0 - Little Endian */
6160 uint32_t dtft : 9; /**< [ 8: 0](R/W) Device timeout fine tuning. This field determines how long the host waits for a response
6161 from a device before considering a timeout. For [DTFT] to take effect, [DTCT] must be set
6162 to
6163 0x0.
6164 The [DTFT] value specifies the number of 125 MHz clock cycles * 256 to count before
6165 considering a device timeout. For the 125 MHz clock cycles (8 ns period), this is
6166 calculated as follows:
6167 _ [DTFT value] * 256 * 8 (ns)
6168 0x2 = 2 * 256 * 8 -\> 4 us.
6169 0x5 = 5 * 256 * 8 -\> 10 us.
6170 0xA = 10 * 256 * 8 -\> 20 us.
6171 0x10 = 16 * 256 * 8 -\> 32 us.
6172 0x19 = 25 * 256 * 8 -\> 51 us.
6173 0x31 = 49 * 256 * 8 -\> 100 us.
6174 0x62 = 98 * 256 * 8 -\> 200 us. */
6175 uint32_t dtct : 2; /**< [ 10: 9](R/W) Device timeout coarse tuning. This field determines how long the host waits for a response
6176 from device before considering a timeout.
6177 The core first checks the [DTCT] value. If it is 0, then the timeout value is defined by
6178 the
6179 [DTFT]. If it is nonzero, then it uses the following timeout values:
6180 0x0 = 0 us; use [DTFT] value instead.
6181 0x1 = 500 us.
6182 0x2 = 1.5 ms.
6183 0x3 = 6.5 ms. */
6184 uint32_t insrtextrfsbodi : 1; /**< [ 11: 11](R/W) Insert extra delay between full-speed bulk OUT transactions. Some full-speed devices are
6185 slow to receive bulk OUT data and can get stuck when there are consecutive bulk OUT
6186 transactions with short inter-transaction delays. This bit is used to control whether the
6187 host inserts extra delay between consecutive bulk OUT transactions to a full-speed
6188 endpoint.
6189 0 = Host does not insert extra delay.
6190 Setting this bit to 1 reduces the bulk OUT transfer performance for most of the full-speed
6191 devices.
6192 1 = Host inserts about 12 us extra delay between consecutive bulk OUT transactions to an
6193 full-speed endpoint to work around the device issue. */
6194 uint32_t extcapsupten : 1; /**< [ 12: 12](R/W) External extended capability support enable. If disabled, a read
6195 USBDRD()_UAHC_SUPTPRT3_DW0
6196 [NEXTCAPPTR] returns 0 in the next capability pointer field. This indicates there are no
6197 more capabilities. If enabled, a read to USBDRD()_UAHC_SUPTPRT3_DW0[NEXTCAPPTR] returns 4
6198 in
6199 the
6200 next capability pointer field.
6201 Always set to 0x0. */
6202 uint32_t enoverlapchk : 1; /**< [ 13: 13](R/W) Enable check for LFPS overlap during remote Ux Exit. If this bit is set to:
6203 0 = When the link exists U1/U2/U3 because of a remote exit, it does not look for an LFPS
6204 overlap.
6205 1 = The SuperSpeed link, when exiting U1/U2/U3, waits for either the remote link LFPS or
6206 TS1/TS2 training symbols before it confirms that the LFPS handshake is complete. This is
6207 done to handle the case where the LFPS glitch causes the link to start exiting from the
6208 low power state. Looking for the LFPS overlap makes sure that the link partner also sees
6209 the LFPS. */
6210 uint32_t usbdrdstinautoretryen : 1; /**< [ 14: 14](R/W) Host IN auto-retry enable. When set, this field enables the auto-retry feature. For IN
6211 transfers (non-isochronous) that encounter data packets with CRC errors or internal
6212 overrun scenarios, the auto-retry feature causes the host core to reply to the device with
6213 a non-terminating retry ACK (i.e. an ACK transaction packet with Retry = 1 and NumP != 0).
6214 If the auto-retry feature is disabled (default), the core responds with a terminating
6215 retry ACK (i.e. an ACK transaction packet with Retry = 1 and NumP = 0). */
6216 uint32_t cmdevaddr : 1; /**< [ 15: 15](R/W) Compliance mode for device address. When set to 1, slot ID can have different value than
6217 device address if max_slot_enabled \< 128.
6218 0 = Device address is equal to slot ID.
6219 1 = Increment device address on each address device command.
6220
6221 The xHCI compliance requires this bit to be set to 1. The 0 mode is for debug purpose
6222 only. This allows you to easily identify a device connected to a port in the Lecroy or
6223 Eliisys trace during hardware debug.
6224
6225 This bit is used in host mode only. */
6226 uint32_t resbwhseps : 1; /**< [ 16: 16](R/W) Reserving 85% bandwidth for high-speed periodic EPs. By default, host controller reserves
6227 80% of the bandwidth for periodic EPs. If this bit is set, the bandwidth is relaxed to 85%
6228 to accommodate two high-speed, high-bandwidth ISOC EPs.
6229
6230 USB 2.0 required 80% bandwidth allocated for ISOC traffic. If two high bandwidth ISOC
6231 devices (HD webcams) are connected, and if each requires 1024-bytes * 3 packets per
6232 microframe, then the bandwidth required is around 82%. If this bit is set to 1, it is
6233 possible to connect two webcams of 1024 bytes * 3 payload per microframe each. Otherwise,
6234 you may have to reduce the resolution of the webcams. */
6235 uint32_t sprsctrltransen : 1; /**< [ 17: 17](R/W) Sparse control transaction enable. Some devices are slow in responding to control
6236 transfers. Scheduling multiple transactions in one microframe/frame can cause these
6237 devices to misbehave. If this bit is set to 1, the host controller schedules transactions
6238 for a control transfer in different microframes/frames. */
6239 uint32_t psqextrressp : 3; /**< [ 20: 18](R/W) PSQ extra reserved space. This is a debug feature, and is not intended for normal usage.
6240 This parameter specifies how much additional space in the PSQ (protocol-status queue) must
6241 be reserved before the U3PTL initiates a new USB transaction and burst beats. */
6242 uint32_t noextrdl : 1; /**< [ 21: 21](R/W) No extra delay between SOF and the first packet.
6243 Some high-speed devices misbehave when the host sends a packet immediately after an SOF.
6244 However, adding an extra delay between an SOF and the first packet can reduce the USB data
6245 rate and performance.
6246
6247 This bit is used to control whether the host should wait for 2 us before it sends the
6248 first packet after a SOF, or not. You can set this bit to 1 to improve the performance if
6249 those problematic devices are not a concern in your host environment.
6250 0 = host waits for 2 us after an SOF before it sends the first USB packet.
6251 1 = host does not wait after an SOF before it sends the first USB packet. */
6252 uint32_t refclkper : 10; /**< [ 31: 22](R/W) Reference-clock period. Indicates (in terms of ns) the period of REF_CLK. The default
6253 value is set to 0x8
6254 (8 ns/125 MHz). This field must be updated during power on initialization if
6255 USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1 or USBDRD()_UAHC_GFLADJ [GFLADJ_REFCLK_LPM_SEL] = 1.
6256 The
6257 programmable maximum value 62 ns, and the minimum value is 8 ns. You use a reference clock
6258 with a period that is a integer multiple, so that ITP can meet the jitter margin of 32 ns.
6259 The allowable REF_CLK frequencies whose period is not integer multiples are
6260 16/17/19.2/24/39.7 MHz.
6261
6262 This field should not be set to 0x0 at any time. If you do not plan to use this feature,
6263 then you need to set this field to 0x8, the default value. */
6264 #endif /* Word 0 - End */
6265 } s;
6266 /* struct bdk_usbdrdx_uahc_guctl_s cn; */
6267 };
6268 typedef union bdk_usbdrdx_uahc_guctl bdk_usbdrdx_uahc_guctl_t;
6269
6270 static inline uint64_t BDK_USBDRDX_UAHC_GUCTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GUCTL(unsigned long a)6271 static inline uint64_t BDK_USBDRDX_UAHC_GUCTL(unsigned long a)
6272 {
6273 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6274 return 0x86800000c12cll + 0x1000000000ll * ((a) & 0x1);
6275 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
6276 return 0x86800000c12cll + 0x1000000000ll * ((a) & 0x1);
6277 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6278 return 0x86800000c12cll + 0x1000000000ll * ((a) & 0x1);
6279 __bdk_csr_fatal("USBDRDX_UAHC_GUCTL", 1, a, 0, 0, 0);
6280 }
6281
6282 #define typedef_BDK_USBDRDX_UAHC_GUCTL(a) bdk_usbdrdx_uahc_guctl_t
6283 #define bustype_BDK_USBDRDX_UAHC_GUCTL(a) BDK_CSR_TYPE_NCB32b
6284 #define basename_BDK_USBDRDX_UAHC_GUCTL(a) "USBDRDX_UAHC_GUCTL"
6285 #define device_bar_BDK_USBDRDX_UAHC_GUCTL(a) 0x0 /* PF_BAR0 */
6286 #define busnum_BDK_USBDRDX_UAHC_GUCTL(a) (a)
6287 #define arguments_BDK_USBDRDX_UAHC_GUCTL(a) (a),-1,-1,-1
6288
6289 /**
6290 * Register (NCB32b) usbdrd#_uahc_guctl1
6291 *
6292 * USB UAHC Global User Control Register 1
6293 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
6294 * Internal:
6295 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.8
6296 */
6297 union bdk_usbdrdx_uahc_guctl1
6298 {
6299 uint32_t u;
6300 struct bdk_usbdrdx_uahc_guctl1_s
6301 {
6302 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6303 uint32_t reserved_18_31 : 14;
6304 uint32_t parkmode_disable_ss : 1; /**< [ 17: 17](R/W) This bit is for debug purpose only.
6305 When this bit is set to 1 all SS bus instances in park mode are
6306 disabled. */
6307 uint32_t parkmode_disable_hs : 1; /**< [ 16: 16](R/W) When this bit is set to 1 all HS bus instances park mode are
6308 disabled. */
6309 uint32_t parkmode_disable_fsls : 1; /**< [ 15: 15](R/W) When this bit is set to 1 all FS/LS bus instances park mode are
6310 disabled. */
6311 uint32_t reserved_9_14 : 6;
6312 uint32_t l1_susp_thrld_en_for_host : 1;/**< [ 8: 8](R/W) The controller puts the PHY into deep low-power mode in L1 when both of the
6313 following are true:
6314
6315 * The HIRD/BESL value used is greater than or equal to the
6316 value in [L1_SUSP_THRLD_FOR_HOST].
6317 * The [L1_SUSP_THRLD_EN_FOR_HOST] bit is set.
6318
6319 The controller the UTMI PHY transitions to shallow low-power
6320 mode in L1 by powering down necessary blocks when one of the
6321 following is true:
6322
6323 * The HIRD/BESL value used is less than the value in
6324 [L1_SUSP_THRLD_FOR_HOST].
6325 * [L1_SUSP_THRLD_EN_FOR_HOST] is clear. */
6326 uint32_t l1_susp_thrld_for_host : 4; /**< [ 7: 4](R/W) This field is effective only when the [L1_SUSP_THRLD_EN_FOR_HOST] is set to 1. */
6327 uint32_t helden : 1; /**< [ 3: 3](R/W) When this bit is set to 1, it enables the exit latency delta (ELD)
6328 support defined in the xHCI 1.0 Errata. */
6329 uint32_t hparchkdisable : 1; /**< [ 2: 2](R/W) When this bit is set to 0 (by default), the xHC checks that the input
6330 slot/EP context fields comply to the xHCI Specification. Upon
6331 detection of a parameter error during command execution, the
6332 xHC generates an event TRB with completion code indicating
6333 'PARAMETER ERROR'.
6334 When the bit is set to 1, the xHC does not perform parameter
6335 checks and does not generate 'PARAMETER ERROR' completion
6336 code. */
6337 uint32_t ovrld_l1_susp_com : 1; /**< [ 1: 1](R/W) Always set to 0. */
6338 uint32_t loa_filter_en : 1; /**< [ 0: 0](R/W) If this bit is set, the USB 2.0 port babble is checked at least three consecutive times
6339 before the port is disabled. This prevents false triggering of the babble condition when
6340 using low quality cables. */
6341 #else /* Word 0 - Little Endian */
6342 uint32_t loa_filter_en : 1; /**< [ 0: 0](R/W) If this bit is set, the USB 2.0 port babble is checked at least three consecutive times
6343 before the port is disabled. This prevents false triggering of the babble condition when
6344 using low quality cables. */
6345 uint32_t ovrld_l1_susp_com : 1; /**< [ 1: 1](R/W) Always set to 0. */
6346 uint32_t hparchkdisable : 1; /**< [ 2: 2](R/W) When this bit is set to 0 (by default), the xHC checks that the input
6347 slot/EP context fields comply to the xHCI Specification. Upon
6348 detection of a parameter error during command execution, the
6349 xHC generates an event TRB with completion code indicating
6350 'PARAMETER ERROR'.
6351 When the bit is set to 1, the xHC does not perform parameter
6352 checks and does not generate 'PARAMETER ERROR' completion
6353 code. */
6354 uint32_t helden : 1; /**< [ 3: 3](R/W) When this bit is set to 1, it enables the exit latency delta (ELD)
6355 support defined in the xHCI 1.0 Errata. */
6356 uint32_t l1_susp_thrld_for_host : 4; /**< [ 7: 4](R/W) This field is effective only when the [L1_SUSP_THRLD_EN_FOR_HOST] is set to 1. */
6357 uint32_t l1_susp_thrld_en_for_host : 1;/**< [ 8: 8](R/W) The controller puts the PHY into deep low-power mode in L1 when both of the
6358 following are true:
6359
6360 * The HIRD/BESL value used is greater than or equal to the
6361 value in [L1_SUSP_THRLD_FOR_HOST].
6362 * The [L1_SUSP_THRLD_EN_FOR_HOST] bit is set.
6363
6364 The controller the UTMI PHY transitions to shallow low-power
6365 mode in L1 by powering down necessary blocks when one of the
6366 following is true:
6367
6368 * The HIRD/BESL value used is less than the value in
6369 [L1_SUSP_THRLD_FOR_HOST].
6370 * [L1_SUSP_THRLD_EN_FOR_HOST] is clear. */
6371 uint32_t reserved_9_14 : 6;
6372 uint32_t parkmode_disable_fsls : 1; /**< [ 15: 15](R/W) When this bit is set to 1 all FS/LS bus instances park mode are
6373 disabled. */
6374 uint32_t parkmode_disable_hs : 1; /**< [ 16: 16](R/W) When this bit is set to 1 all HS bus instances park mode are
6375 disabled. */
6376 uint32_t parkmode_disable_ss : 1; /**< [ 17: 17](R/W) This bit is for debug purpose only.
6377 When this bit is set to 1 all SS bus instances in park mode are
6378 disabled. */
6379 uint32_t reserved_18_31 : 14;
6380 #endif /* Word 0 - End */
6381 } s;
6382 /* struct bdk_usbdrdx_uahc_guctl1_s cn; */
6383 };
6384 typedef union bdk_usbdrdx_uahc_guctl1 bdk_usbdrdx_uahc_guctl1_t;
6385
6386 static inline uint64_t BDK_USBDRDX_UAHC_GUCTL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GUCTL1(unsigned long a)6387 static inline uint64_t BDK_USBDRDX_UAHC_GUCTL1(unsigned long a)
6388 {
6389 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6390 return 0x86800000c11cll + 0x1000000000ll * ((a) & 0x1);
6391 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
6392 return 0x86800000c11cll + 0x1000000000ll * ((a) & 0x1);
6393 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6394 return 0x86800000c11cll + 0x1000000000ll * ((a) & 0x1);
6395 __bdk_csr_fatal("USBDRDX_UAHC_GUCTL1", 1, a, 0, 0, 0);
6396 }
6397
6398 #define typedef_BDK_USBDRDX_UAHC_GUCTL1(a) bdk_usbdrdx_uahc_guctl1_t
6399 #define bustype_BDK_USBDRDX_UAHC_GUCTL1(a) BDK_CSR_TYPE_NCB32b
6400 #define basename_BDK_USBDRDX_UAHC_GUCTL1(a) "USBDRDX_UAHC_GUCTL1"
6401 #define device_bar_BDK_USBDRDX_UAHC_GUCTL1(a) 0x0 /* PF_BAR0 */
6402 #define busnum_BDK_USBDRDX_UAHC_GUCTL1(a) (a)
6403 #define arguments_BDK_USBDRDX_UAHC_GUCTL1(a) (a),-1,-1,-1
6404
6405 /**
6406 * Register (NCB32b) usbdrd#_uahc_guctl2
6407 *
6408 * UAHC Global User Control Register 2
6409 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
6410 * Internal:
6411 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.44.
6412 */
6413 union bdk_usbdrdx_uahc_guctl2
6414 {
6415 uint32_t u;
6416 struct bdk_usbdrdx_uahc_guctl2_s
6417 {
6418 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6419 uint32_t reserved_15_31 : 17;
6420 uint32_t rst_actbitlater : 1; /**< [ 14: 14](R/W) Enable clearing of the command active bit for the ENDXFER command. */
6421 uint32_t reserved_13 : 1;
6422 uint32_t enableepcacheevict : 1; /**< [ 12: 12](R/W) Enable evicting endpoint cache after flow control for bulk endpoints. */
6423 uint32_t disablecfc : 1; /**< [ 11: 11](R/W) Disable xHCI errata feature contiguous frame ID capability. */
6424 uint32_t rxpingduration : 6; /**< [ 10: 5](R/W) Receive ping maximum duration. */
6425 uint32_t txpingduration : 5; /**< [ 4: 0](R/W) Transmit ping maximum duration. */
6426 #else /* Word 0 - Little Endian */
6427 uint32_t txpingduration : 5; /**< [ 4: 0](R/W) Transmit ping maximum duration. */
6428 uint32_t rxpingduration : 6; /**< [ 10: 5](R/W) Receive ping maximum duration. */
6429 uint32_t disablecfc : 1; /**< [ 11: 11](R/W) Disable xHCI errata feature contiguous frame ID capability. */
6430 uint32_t enableepcacheevict : 1; /**< [ 12: 12](R/W) Enable evicting endpoint cache after flow control for bulk endpoints. */
6431 uint32_t reserved_13 : 1;
6432 uint32_t rst_actbitlater : 1; /**< [ 14: 14](R/W) Enable clearing of the command active bit for the ENDXFER command. */
6433 uint32_t reserved_15_31 : 17;
6434 #endif /* Word 0 - End */
6435 } s;
6436 /* struct bdk_usbdrdx_uahc_guctl2_s cn; */
6437 };
6438 typedef union bdk_usbdrdx_uahc_guctl2 bdk_usbdrdx_uahc_guctl2_t;
6439
6440 static inline uint64_t BDK_USBDRDX_UAHC_GUCTL2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GUCTL2(unsigned long a)6441 static inline uint64_t BDK_USBDRDX_UAHC_GUCTL2(unsigned long a)
6442 {
6443 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6444 return 0x86800000c19cll + 0x1000000000ll * ((a) & 0x1);
6445 __bdk_csr_fatal("USBDRDX_UAHC_GUCTL2", 1, a, 0, 0, 0);
6446 }
6447
6448 #define typedef_BDK_USBDRDX_UAHC_GUCTL2(a) bdk_usbdrdx_uahc_guctl2_t
6449 #define bustype_BDK_USBDRDX_UAHC_GUCTL2(a) BDK_CSR_TYPE_NCB32b
6450 #define basename_BDK_USBDRDX_UAHC_GUCTL2(a) "USBDRDX_UAHC_GUCTL2"
6451 #define device_bar_BDK_USBDRDX_UAHC_GUCTL2(a) 0x0 /* PF_BAR0 */
6452 #define busnum_BDK_USBDRDX_UAHC_GUCTL2(a) (a)
6453 #define arguments_BDK_USBDRDX_UAHC_GUCTL2(a) (a),-1,-1,-1
6454
6455 /**
6456 * Register (NCB32b) usbdrd#_uahc_guid
6457 *
6458 * USB UAHC Core User ID Register
6459 * This is a read/write register containing the User ID. The power-on value for this register is
6460 * specified as the user identification register. This register can be used in the following
6461 * ways:
6462 * * To store the version or revision of your system.
6463 * * To store hardware configurations that are outside of the core.
6464 * * As a scratch register.
6465 *
6466 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
6467 *
6468 * Internal:
6469 * See Synopsys DWC_usb3 Databook v3.10a, section 6.2.11.
6470 */
6471 union bdk_usbdrdx_uahc_guid
6472 {
6473 uint32_t u;
6474 struct bdk_usbdrdx_uahc_guid_s
6475 {
6476 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6477 uint32_t userid : 32; /**< [ 31: 0](R/W) User ID. Application-programmable ID field. */
6478 #else /* Word 0 - Little Endian */
6479 uint32_t userid : 32; /**< [ 31: 0](R/W) User ID. Application-programmable ID field. */
6480 #endif /* Word 0 - End */
6481 } s;
6482 /* struct bdk_usbdrdx_uahc_guid_s cn; */
6483 };
6484 typedef union bdk_usbdrdx_uahc_guid bdk_usbdrdx_uahc_guid_t;
6485
6486 static inline uint64_t BDK_USBDRDX_UAHC_GUID(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GUID(unsigned long a)6487 static inline uint64_t BDK_USBDRDX_UAHC_GUID(unsigned long a)
6488 {
6489 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6490 return 0x86800000c128ll + 0x1000000000ll * ((a) & 0x1);
6491 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
6492 return 0x86800000c128ll + 0x1000000000ll * ((a) & 0x1);
6493 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
6494 return 0x86800000c128ll + 0x1000000000ll * ((a) & 0x1);
6495 __bdk_csr_fatal("USBDRDX_UAHC_GUID", 1, a, 0, 0, 0);
6496 }
6497
6498 #define typedef_BDK_USBDRDX_UAHC_GUID(a) bdk_usbdrdx_uahc_guid_t
6499 #define bustype_BDK_USBDRDX_UAHC_GUID(a) BDK_CSR_TYPE_NCB32b
6500 #define basename_BDK_USBDRDX_UAHC_GUID(a) "USBDRDX_UAHC_GUID"
6501 #define device_bar_BDK_USBDRDX_UAHC_GUID(a) 0x0 /* PF_BAR0 */
6502 #define busnum_BDK_USBDRDX_UAHC_GUID(a) (a)
6503 #define arguments_BDK_USBDRDX_UAHC_GUID(a) (a),-1,-1,-1
6504
6505 /**
6506 * Register (NCB32b) usbdrd#_uahc_gusb2i2cctl#
6507 *
6508 * USB UAHC USB2 I2C Control Register
6509 * This register is reserved for future use.
6510 *
6511 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
6512 *
6513 * Internal:
6514 * See Synopsys DWC_usb3 Databook v2.20a, section 6.2.5.2.
6515 */
6516 union bdk_usbdrdx_uahc_gusb2i2cctlx
6517 {
6518 uint32_t u;
6519 struct bdk_usbdrdx_uahc_gusb2i2cctlx_s
6520 {
6521 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6522 uint32_t reserved_0_31 : 32;
6523 #else /* Word 0 - Little Endian */
6524 uint32_t reserved_0_31 : 32;
6525 #endif /* Word 0 - End */
6526 } s;
6527 /* struct bdk_usbdrdx_uahc_gusb2i2cctlx_s cn; */
6528 };
6529 typedef union bdk_usbdrdx_uahc_gusb2i2cctlx bdk_usbdrdx_uahc_gusb2i2cctlx_t;
6530
6531 static inline uint64_t BDK_USBDRDX_UAHC_GUSB2I2CCTLX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GUSB2I2CCTLX(unsigned long a,unsigned long b)6532 static inline uint64_t BDK_USBDRDX_UAHC_GUSB2I2CCTLX(unsigned long a, unsigned long b)
6533 {
6534 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
6535 return 0x86800000c240ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
6536 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
6537 return 0x86800000c240ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
6538 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
6539 return 0x86800000c240ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
6540 __bdk_csr_fatal("USBDRDX_UAHC_GUSB2I2CCTLX", 2, a, b, 0, 0);
6541 }
6542
6543 #define typedef_BDK_USBDRDX_UAHC_GUSB2I2CCTLX(a,b) bdk_usbdrdx_uahc_gusb2i2cctlx_t
6544 #define bustype_BDK_USBDRDX_UAHC_GUSB2I2CCTLX(a,b) BDK_CSR_TYPE_NCB32b
6545 #define basename_BDK_USBDRDX_UAHC_GUSB2I2CCTLX(a,b) "USBDRDX_UAHC_GUSB2I2CCTLX"
6546 #define device_bar_BDK_USBDRDX_UAHC_GUSB2I2CCTLX(a,b) 0x0 /* PF_BAR0 */
6547 #define busnum_BDK_USBDRDX_UAHC_GUSB2I2CCTLX(a,b) (a)
6548 #define arguments_BDK_USBDRDX_UAHC_GUSB2I2CCTLX(a,b) (a),(b),-1,-1
6549
6550 /**
6551 * Register (NCB32b) usbdrd#_uahc_gusb2phycfg#
6552 *
6553 * USB UAHC USB2 PHY-Configuration Register
6554 * This register is used to configure the core after power-on. It contains USB 2.0 and USB 2.0
6555 * PHY-related configuration parameters. The application must program this register before
6556 * starting any transactions on either the SoC bus or the USB. Per-port registers are
6557 * implemented.
6558 *
6559 * Do not make changes to this register after the initial programming.
6560 *
6561 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
6562 *
6563 * Internal:
6564 * See Synopsys DWC_usb3 Databook v2.20a, section 6.2.5.1.
6565 */
6566 union bdk_usbdrdx_uahc_gusb2phycfgx
6567 {
6568 uint32_t u;
6569 struct bdk_usbdrdx_uahc_gusb2phycfgx_s
6570 {
6571 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6572 uint32_t physoftrst : 1; /**< [ 31: 31](R/W) PHY soft reset. Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. */
6573 uint32_t u2_freeclk_exists : 1; /**< [ 30: 30](R/W) Specifies whether your USB 2.0 PHY provides a free-running PHY clock, which is active when
6574 the clock control input is active. If your USB 2.0 PHY provides a free-running PHY clock,
6575 it must be connected to the utmi_clk[0] input. The remaining utmi_clk[n] must be connected
6576 to the respective port clocks. The core uses the Port-0 clock for generating the internal
6577 mac2 clock.
6578 0 = USB 2.0 free clock does not exist.
6579 1 = USB 2.0 free clock exists.
6580
6581 This field must be set to zero if you enable ITP generation based on the REF_CLK
6582 counter, USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1, or USBDRD()_UAHC_GFLADJ
6583 [GFLADJ_REFCLK_LPM_SEL] =
6584 1. */
6585 uint32_t ulpi_lpm_with_opmode_chk : 1;/**< [ 29: 29](R/W) Support the LPM over ULPI without NOPID token to the ULPI PHY. Always 0x0. */
6586 uint32_t hsic_con_width_adj : 2; /**< [ 28: 27](RO) This bit is used in the HSIC device mode of operation. Always 0x0 */
6587 uint32_t inv_sel_hsic : 1; /**< [ 26: 26](RO) The application driver uses this bit to control the HSIC enable/disable function. */
6588 uint32_t reserved_19_25 : 7;
6589 uint32_t ulpiextvbusindicator : 1; /**< [ 18: 18](R/W) Reserved (unused in this configuration). */
6590 uint32_t ulpiextvbusdrv : 1; /**< [ 17: 17](R/W) Reserved (unused in this configuration). */
6591 uint32_t ulpiclksusm : 1; /**< [ 16: 16](R/W) Reserved (unused in this configuration). */
6592 uint32_t ulpiautores : 1; /**< [ 15: 15](R/W) Reserved (unused in this configuration). */
6593 uint32_t reserved_14 : 1;
6594 uint32_t usbtrdtim : 4; /**< [ 13: 10](R/W) USB 2.0 turnaround time. Sets the turnaround time in PHY clock cycles. Specifies the
6595 response time for a MAC request to the packet FIFO controller (PFC) to fetch data from the
6596 DFIFO (SPRAM).
6597 USB turnaround time is a critical certification criteria when using long cables and five
6598 hub levels.
6599 When the MAC interface is 8-bit UTMI+/ULPI, the required values for this field is 0x9. */
6600 uint32_t xcvrdly : 1; /**< [ 9: 9](R/W) Transceiver delay.
6601 Enables a delay between the assertion of the UTMI transceiver select signal (for
6602 high-speed) and the assertion of the TxValid signal during a high-speed chirp.
6603 When this bit is set to 1, a delay of approximately 2.5 us is introduced from
6604 the time when the transceiver select is set to 0x0, to the time when the TxValid
6605 is driven to 0 for sending the chirp-K. This delay is required for some UTMI PHYs.
6606 This bit is only valid in device mode. */
6607 uint32_t enblslpm : 1; /**< [ 8: 8](R/W) Enable utmi_sleep_n and utmi_l1_suspend_n. The application uses this field to control
6608 utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state.
6609 0 = utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferred to the
6610 external PHY.
6611 1 = utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the
6612 external PHY.
6613
6614 When hardware LPM is enabled, this bit should be set high for Port0. */
6615 uint32_t physel : 1; /**< [ 7: 7](WO) USB 2.0 high-speed PHY or USB 1.1 full-speed serial transceiver select. */
6616 uint32_t susphy : 1; /**< [ 6: 6](R/W) Suspend USB2.0 high-speed/full-speed/low-speed PHY. When set, USB2.0 PHY enters suspend
6617 mode if suspend conditions are valid. */
6618 uint32_t fsintf : 1; /**< [ 5: 5](RO) Full-speed serial-interface select. Always reads as 0x0. */
6619 uint32_t ulpi_utmi_sel : 1; /**< [ 4: 4](RO) ULPI or UTMI+ select. Always reads as 0x0, indicating UTMI+. */
6620 uint32_t phyif : 1; /**< [ 3: 3](R/W) PHY interface width: 1 = 16-bit, 0 = 8-bit.
6621 All the enabled 2.0 ports should have the same clock frequency as Port0 clock frequency
6622 (utmi_clk[0]).
6623 The UTMI 8-bit and 16-bit modes cannot be used together for different ports at the same
6624 time (i.e., all the ports should be in 8-bit mode, or all of them should be in 16-bit
6625 mode). */
6626 uint32_t toutcal : 3; /**< [ 2: 0](R/W) High-speed/full-speed timeout calibration.
6627 The number of PHY clock cycles, as indicated by the application in this field, is
6628 multiplied by a bit-time factor; this factor is added to the high-speed/full-speed
6629 interpacket timeout duration in the core to account for additional delays introduced by
6630 the PHY. This might be required, since the delay introduced by the PHY in generating the
6631 linestate condition can vary among PHYs.
6632
6633 The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit
6634 times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit
6635 times. The application must program this field based on the speed of connection.
6636
6637 The number of bit times added per PHY clock are:
6638 * High-speed operation:
6639 _ one 30-MHz PHY clock = 16 bit times.
6640 _ one 60-MHz PHY clock = 8 bit times.
6641
6642 * Full-speed operation:
6643 _ one 30-MHz PHY clock = 0.4 bit times.
6644 _ one 60-MHz PHY clock = 0.2 bit times.
6645 _ one 48-MHz PHY clock = 0.25 bit times. */
6646 #else /* Word 0 - Little Endian */
6647 uint32_t toutcal : 3; /**< [ 2: 0](R/W) High-speed/full-speed timeout calibration.
6648 The number of PHY clock cycles, as indicated by the application in this field, is
6649 multiplied by a bit-time factor; this factor is added to the high-speed/full-speed
6650 interpacket timeout duration in the core to account for additional delays introduced by
6651 the PHY. This might be required, since the delay introduced by the PHY in generating the
6652 linestate condition can vary among PHYs.
6653
6654 The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit
6655 times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit
6656 times. The application must program this field based on the speed of connection.
6657
6658 The number of bit times added per PHY clock are:
6659 * High-speed operation:
6660 _ one 30-MHz PHY clock = 16 bit times.
6661 _ one 60-MHz PHY clock = 8 bit times.
6662
6663 * Full-speed operation:
6664 _ one 30-MHz PHY clock = 0.4 bit times.
6665 _ one 60-MHz PHY clock = 0.2 bit times.
6666 _ one 48-MHz PHY clock = 0.25 bit times. */
6667 uint32_t phyif : 1; /**< [ 3: 3](R/W) PHY interface width: 1 = 16-bit, 0 = 8-bit.
6668 All the enabled 2.0 ports should have the same clock frequency as Port0 clock frequency
6669 (utmi_clk[0]).
6670 The UTMI 8-bit and 16-bit modes cannot be used together for different ports at the same
6671 time (i.e., all the ports should be in 8-bit mode, or all of them should be in 16-bit
6672 mode). */
6673 uint32_t ulpi_utmi_sel : 1; /**< [ 4: 4](RO) ULPI or UTMI+ select. Always reads as 0x0, indicating UTMI+. */
6674 uint32_t fsintf : 1; /**< [ 5: 5](RO) Full-speed serial-interface select. Always reads as 0x0. */
6675 uint32_t susphy : 1; /**< [ 6: 6](R/W) Suspend USB2.0 high-speed/full-speed/low-speed PHY. When set, USB2.0 PHY enters suspend
6676 mode if suspend conditions are valid. */
6677 uint32_t physel : 1; /**< [ 7: 7](WO) USB 2.0 high-speed PHY or USB 1.1 full-speed serial transceiver select. */
6678 uint32_t enblslpm : 1; /**< [ 8: 8](R/W) Enable utmi_sleep_n and utmi_l1_suspend_n. The application uses this field to control
6679 utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state.
6680 0 = utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferred to the
6681 external PHY.
6682 1 = utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the
6683 external PHY.
6684
6685 When hardware LPM is enabled, this bit should be set high for Port0. */
6686 uint32_t xcvrdly : 1; /**< [ 9: 9](R/W) Transceiver delay.
6687 Enables a delay between the assertion of the UTMI transceiver select signal (for
6688 high-speed) and the assertion of the TxValid signal during a high-speed chirp.
6689 When this bit is set to 1, a delay of approximately 2.5 us is introduced from
6690 the time when the transceiver select is set to 0x0, to the time when the TxValid
6691 is driven to 0 for sending the chirp-K. This delay is required for some UTMI PHYs.
6692 This bit is only valid in device mode. */
6693 uint32_t usbtrdtim : 4; /**< [ 13: 10](R/W) USB 2.0 turnaround time. Sets the turnaround time in PHY clock cycles. Specifies the
6694 response time for a MAC request to the packet FIFO controller (PFC) to fetch data from the
6695 DFIFO (SPRAM).
6696 USB turnaround time is a critical certification criteria when using long cables and five
6697 hub levels.
6698 When the MAC interface is 8-bit UTMI+/ULPI, the required values for this field is 0x9. */
6699 uint32_t reserved_14 : 1;
6700 uint32_t ulpiautores : 1; /**< [ 15: 15](R/W) Reserved (unused in this configuration). */
6701 uint32_t ulpiclksusm : 1; /**< [ 16: 16](R/W) Reserved (unused in this configuration). */
6702 uint32_t ulpiextvbusdrv : 1; /**< [ 17: 17](R/W) Reserved (unused in this configuration). */
6703 uint32_t ulpiextvbusindicator : 1; /**< [ 18: 18](R/W) Reserved (unused in this configuration). */
6704 uint32_t reserved_19_25 : 7;
6705 uint32_t inv_sel_hsic : 1; /**< [ 26: 26](RO) The application driver uses this bit to control the HSIC enable/disable function. */
6706 uint32_t hsic_con_width_adj : 2; /**< [ 28: 27](RO) This bit is used in the HSIC device mode of operation. Always 0x0 */
6707 uint32_t ulpi_lpm_with_opmode_chk : 1;/**< [ 29: 29](R/W) Support the LPM over ULPI without NOPID token to the ULPI PHY. Always 0x0. */
6708 uint32_t u2_freeclk_exists : 1; /**< [ 30: 30](R/W) Specifies whether your USB 2.0 PHY provides a free-running PHY clock, which is active when
6709 the clock control input is active. If your USB 2.0 PHY provides a free-running PHY clock,
6710 it must be connected to the utmi_clk[0] input. The remaining utmi_clk[n] must be connected
6711 to the respective port clocks. The core uses the Port-0 clock for generating the internal
6712 mac2 clock.
6713 0 = USB 2.0 free clock does not exist.
6714 1 = USB 2.0 free clock exists.
6715
6716 This field must be set to zero if you enable ITP generation based on the REF_CLK
6717 counter, USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1, or USBDRD()_UAHC_GFLADJ
6718 [GFLADJ_REFCLK_LPM_SEL] =
6719 1. */
6720 uint32_t physoftrst : 1; /**< [ 31: 31](R/W) PHY soft reset. Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. */
6721 #endif /* Word 0 - End */
6722 } s;
6723 struct bdk_usbdrdx_uahc_gusb2phycfgx_cn
6724 {
6725 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6726 uint32_t physoftrst : 1; /**< [ 31: 31](R/W) PHY soft reset. Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. */
6727 uint32_t u2_freeclk_exists : 1; /**< [ 30: 30](R/W) Specifies whether your USB 2.0 PHY provides a free-running PHY clock, which is active when
6728 the clock control input is active. If your USB 2.0 PHY provides a free-running PHY clock,
6729 it must be connected to the utmi_clk[0] input. The remaining utmi_clk[n] must be connected
6730 to the respective port clocks. The core uses the Port-0 clock for generating the internal
6731 mac2 clock.
6732 0 = USB 2.0 free clock does not exist.
6733 1 = USB 2.0 free clock exists.
6734
6735 This field must be set to zero if you enable ITP generation based on the REF_CLK
6736 counter, USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1, or USBDRD()_UAHC_GFLADJ
6737 [GFLADJ_REFCLK_LPM_SEL] =
6738 1. */
6739 uint32_t ulpi_lpm_with_opmode_chk : 1;/**< [ 29: 29](R/W) Support the LPM over ULPI without NOPID token to the ULPI PHY. Always 0x0. */
6740 uint32_t hsic_con_width_adj : 2; /**< [ 28: 27](RO) This bit is used in the HSIC device mode of operation. Always 0x0 */
6741 uint32_t inv_sel_hsic : 1; /**< [ 26: 26](RO) The application driver uses this bit to control the HSIC enable/disable function. */
6742 uint32_t reserved_25 : 1;
6743 uint32_t reserved_19_24 : 6;
6744 uint32_t ulpiextvbusindicator : 1; /**< [ 18: 18](R/W) Reserved (unused in this configuration). */
6745 uint32_t ulpiextvbusdrv : 1; /**< [ 17: 17](R/W) Reserved (unused in this configuration). */
6746 uint32_t ulpiclksusm : 1; /**< [ 16: 16](R/W) Reserved (unused in this configuration). */
6747 uint32_t ulpiautores : 1; /**< [ 15: 15](R/W) Reserved (unused in this configuration). */
6748 uint32_t reserved_14 : 1;
6749 uint32_t usbtrdtim : 4; /**< [ 13: 10](R/W) USB 2.0 turnaround time. Sets the turnaround time in PHY clock cycles. Specifies the
6750 response time for a MAC request to the packet FIFO controller (PFC) to fetch data from the
6751 DFIFO (SPRAM).
6752 USB turnaround time is a critical certification criteria when using long cables and five
6753 hub levels.
6754 When the MAC interface is 8-bit UTMI+/ULPI, the required values for this field is 0x9. */
6755 uint32_t xcvrdly : 1; /**< [ 9: 9](R/W) Transceiver delay.
6756 Enables a delay between the assertion of the UTMI transceiver select signal (for
6757 high-speed) and the assertion of the TxValid signal during a high-speed chirp.
6758 When this bit is set to 1, a delay of approximately 2.5 us is introduced from
6759 the time when the transceiver select is set to 0x0, to the time when the TxValid
6760 is driven to 0 for sending the chirp-K. This delay is required for some UTMI PHYs.
6761 This bit is only valid in device mode. */
6762 uint32_t enblslpm : 1; /**< [ 8: 8](R/W) Enable utmi_sleep_n and utmi_l1_suspend_n. The application uses this field to control
6763 utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state.
6764 0 = utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferred to the
6765 external PHY.
6766 1 = utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the
6767 external PHY.
6768
6769 When hardware LPM is enabled, this bit should be set high for Port0. */
6770 uint32_t physel : 1; /**< [ 7: 7](WO) USB 2.0 high-speed PHY or USB 1.1 full-speed serial transceiver select. */
6771 uint32_t susphy : 1; /**< [ 6: 6](R/W) Suspend USB2.0 high-speed/full-speed/low-speed PHY. When set, USB2.0 PHY enters suspend
6772 mode if suspend conditions are valid. */
6773 uint32_t fsintf : 1; /**< [ 5: 5](RO) Full-speed serial-interface select. Always reads as 0x0. */
6774 uint32_t ulpi_utmi_sel : 1; /**< [ 4: 4](RO) ULPI or UTMI+ select. Always reads as 0x0, indicating UTMI+. */
6775 uint32_t phyif : 1; /**< [ 3: 3](R/W) PHY interface width: 1 = 16-bit, 0 = 8-bit.
6776 All the enabled 2.0 ports should have the same clock frequency as Port0 clock frequency
6777 (utmi_clk[0]).
6778 The UTMI 8-bit and 16-bit modes cannot be used together for different ports at the same
6779 time (i.e., all the ports should be in 8-bit mode, or all of them should be in 16-bit
6780 mode). */
6781 uint32_t toutcal : 3; /**< [ 2: 0](R/W) High-speed/full-speed timeout calibration.
6782 The number of PHY clock cycles, as indicated by the application in this field, is
6783 multiplied by a bit-time factor; this factor is added to the high-speed/full-speed
6784 interpacket timeout duration in the core to account for additional delays introduced by
6785 the PHY. This might be required, since the delay introduced by the PHY in generating the
6786 linestate condition can vary among PHYs.
6787
6788 The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit
6789 times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit
6790 times. The application must program this field based on the speed of connection.
6791
6792 The number of bit times added per PHY clock are:
6793 * High-speed operation:
6794 _ one 30-MHz PHY clock = 16 bit times.
6795 _ one 60-MHz PHY clock = 8 bit times.
6796
6797 * Full-speed operation:
6798 _ one 30-MHz PHY clock = 0.4 bit times.
6799 _ one 60-MHz PHY clock = 0.2 bit times.
6800 _ one 48-MHz PHY clock = 0.25 bit times. */
6801 #else /* Word 0 - Little Endian */
6802 uint32_t toutcal : 3; /**< [ 2: 0](R/W) High-speed/full-speed timeout calibration.
6803 The number of PHY clock cycles, as indicated by the application in this field, is
6804 multiplied by a bit-time factor; this factor is added to the high-speed/full-speed
6805 interpacket timeout duration in the core to account for additional delays introduced by
6806 the PHY. This might be required, since the delay introduced by the PHY in generating the
6807 linestate condition can vary among PHYs.
6808
6809 The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit
6810 times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit
6811 times. The application must program this field based on the speed of connection.
6812
6813 The number of bit times added per PHY clock are:
6814 * High-speed operation:
6815 _ one 30-MHz PHY clock = 16 bit times.
6816 _ one 60-MHz PHY clock = 8 bit times.
6817
6818 * Full-speed operation:
6819 _ one 30-MHz PHY clock = 0.4 bit times.
6820 _ one 60-MHz PHY clock = 0.2 bit times.
6821 _ one 48-MHz PHY clock = 0.25 bit times. */
6822 uint32_t phyif : 1; /**< [ 3: 3](R/W) PHY interface width: 1 = 16-bit, 0 = 8-bit.
6823 All the enabled 2.0 ports should have the same clock frequency as Port0 clock frequency
6824 (utmi_clk[0]).
6825 The UTMI 8-bit and 16-bit modes cannot be used together for different ports at the same
6826 time (i.e., all the ports should be in 8-bit mode, or all of them should be in 16-bit
6827 mode). */
6828 uint32_t ulpi_utmi_sel : 1; /**< [ 4: 4](RO) ULPI or UTMI+ select. Always reads as 0x0, indicating UTMI+. */
6829 uint32_t fsintf : 1; /**< [ 5: 5](RO) Full-speed serial-interface select. Always reads as 0x0. */
6830 uint32_t susphy : 1; /**< [ 6: 6](R/W) Suspend USB2.0 high-speed/full-speed/low-speed PHY. When set, USB2.0 PHY enters suspend
6831 mode if suspend conditions are valid. */
6832 uint32_t physel : 1; /**< [ 7: 7](WO) USB 2.0 high-speed PHY or USB 1.1 full-speed serial transceiver select. */
6833 uint32_t enblslpm : 1; /**< [ 8: 8](R/W) Enable utmi_sleep_n and utmi_l1_suspend_n. The application uses this field to control
6834 utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state.
6835 0 = utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferred to the
6836 external PHY.
6837 1 = utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the
6838 external PHY.
6839
6840 When hardware LPM is enabled, this bit should be set high for Port0. */
6841 uint32_t xcvrdly : 1; /**< [ 9: 9](R/W) Transceiver delay.
6842 Enables a delay between the assertion of the UTMI transceiver select signal (for
6843 high-speed) and the assertion of the TxValid signal during a high-speed chirp.
6844 When this bit is set to 1, a delay of approximately 2.5 us is introduced from
6845 the time when the transceiver select is set to 0x0, to the time when the TxValid
6846 is driven to 0 for sending the chirp-K. This delay is required for some UTMI PHYs.
6847 This bit is only valid in device mode. */
6848 uint32_t usbtrdtim : 4; /**< [ 13: 10](R/W) USB 2.0 turnaround time. Sets the turnaround time in PHY clock cycles. Specifies the
6849 response time for a MAC request to the packet FIFO controller (PFC) to fetch data from the
6850 DFIFO (SPRAM).
6851 USB turnaround time is a critical certification criteria when using long cables and five
6852 hub levels.
6853 When the MAC interface is 8-bit UTMI+/ULPI, the required values for this field is 0x9. */
6854 uint32_t reserved_14 : 1;
6855 uint32_t ulpiautores : 1; /**< [ 15: 15](R/W) Reserved (unused in this configuration). */
6856 uint32_t ulpiclksusm : 1; /**< [ 16: 16](R/W) Reserved (unused in this configuration). */
6857 uint32_t ulpiextvbusdrv : 1; /**< [ 17: 17](R/W) Reserved (unused in this configuration). */
6858 uint32_t ulpiextvbusindicator : 1; /**< [ 18: 18](R/W) Reserved (unused in this configuration). */
6859 uint32_t reserved_19_24 : 6;
6860 uint32_t reserved_25 : 1;
6861 uint32_t inv_sel_hsic : 1; /**< [ 26: 26](RO) The application driver uses this bit to control the HSIC enable/disable function. */
6862 uint32_t hsic_con_width_adj : 2; /**< [ 28: 27](RO) This bit is used in the HSIC device mode of operation. Always 0x0 */
6863 uint32_t ulpi_lpm_with_opmode_chk : 1;/**< [ 29: 29](R/W) Support the LPM over ULPI without NOPID token to the ULPI PHY. Always 0x0. */
6864 uint32_t u2_freeclk_exists : 1; /**< [ 30: 30](R/W) Specifies whether your USB 2.0 PHY provides a free-running PHY clock, which is active when
6865 the clock control input is active. If your USB 2.0 PHY provides a free-running PHY clock,
6866 it must be connected to the utmi_clk[0] input. The remaining utmi_clk[n] must be connected
6867 to the respective port clocks. The core uses the Port-0 clock for generating the internal
6868 mac2 clock.
6869 0 = USB 2.0 free clock does not exist.
6870 1 = USB 2.0 free clock exists.
6871
6872 This field must be set to zero if you enable ITP generation based on the REF_CLK
6873 counter, USBDRD()_UAHC_GCTL[SOFITPSYNC] = 1, or USBDRD()_UAHC_GFLADJ
6874 [GFLADJ_REFCLK_LPM_SEL] =
6875 1. */
6876 uint32_t physoftrst : 1; /**< [ 31: 31](R/W) PHY soft reset. Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. */
6877 #endif /* Word 0 - End */
6878 } cn;
6879 };
6880 typedef union bdk_usbdrdx_uahc_gusb2phycfgx bdk_usbdrdx_uahc_gusb2phycfgx_t;
6881
6882 static inline uint64_t BDK_USBDRDX_UAHC_GUSB2PHYCFGX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GUSB2PHYCFGX(unsigned long a,unsigned long b)6883 static inline uint64_t BDK_USBDRDX_UAHC_GUSB2PHYCFGX(unsigned long a, unsigned long b)
6884 {
6885 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
6886 return 0x86800000c200ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
6887 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
6888 return 0x86800000c200ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
6889 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
6890 return 0x86800000c200ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
6891 __bdk_csr_fatal("USBDRDX_UAHC_GUSB2PHYCFGX", 2, a, b, 0, 0);
6892 }
6893
6894 #define typedef_BDK_USBDRDX_UAHC_GUSB2PHYCFGX(a,b) bdk_usbdrdx_uahc_gusb2phycfgx_t
6895 #define bustype_BDK_USBDRDX_UAHC_GUSB2PHYCFGX(a,b) BDK_CSR_TYPE_NCB32b
6896 #define basename_BDK_USBDRDX_UAHC_GUSB2PHYCFGX(a,b) "USBDRDX_UAHC_GUSB2PHYCFGX"
6897 #define device_bar_BDK_USBDRDX_UAHC_GUSB2PHYCFGX(a,b) 0x0 /* PF_BAR0 */
6898 #define busnum_BDK_USBDRDX_UAHC_GUSB2PHYCFGX(a,b) (a)
6899 #define arguments_BDK_USBDRDX_UAHC_GUSB2PHYCFGX(a,b) (a),(b),-1,-1
6900
6901 /**
6902 * Register (NCB32b) usbdrd#_uahc_gusb3pipectl#
6903 *
6904 * USB UAHC USB3 Pipe-Control Register
6905 * This register is used to configure the core after power-on. It contains USB 3.0 and USB 3.0
6906 * PHY-related configuration parameters. The application must program this register before
6907 * starting any transactions on either the SoC bus or the USB. Per-port registers are
6908 * implemented.
6909 *
6910 * Do not make changes to this register after the initial programming.
6911 *
6912 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UAHC_RST].
6913 *
6914 * Internal:
6915 * See Synopsys DWC_usb3 Databook v2.20a, section 6.2.5.4.
6916 */
6917 union bdk_usbdrdx_uahc_gusb3pipectlx
6918 {
6919 uint32_t u;
6920 struct bdk_usbdrdx_uahc_gusb3pipectlx_s
6921 {
6922 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6923 uint32_t physoftrst : 1; /**< [ 31: 31](R/W) USB3 PHY soft reset (PHYSoftRst). When set to 1, initiates a PHY soft reset. After setting
6924 this bit to 1, the software needs to clear this bit. */
6925 uint32_t hstprtcmpl : 1; /**< [ 30: 30](R/W) Host port compliance. Setting this bit to 1 enables placing the SuperSpeed port link into
6926 a compliance state, which allows testing of the PIPE PHY compliance patterns without
6927 having to have a test fixture on the USB 3.0 cable. By default, this bit should be set to
6928 0.
6929
6930 In compliance-lab testing, the SuperSpeed port link enters compliance after failing the
6931 first polling sequence after power on. Set this bit to 0 when you run compliance tests.
6932
6933 The sequence for using this functionality is as follows:
6934 * Disconnect any plugged-in devices.
6935 * Set USBDRD()_UAHC_USBCMD[HCRST] = 1 or power-on-chip reset.
6936 * Set USBDRD()_UAHC_PORTSC()[PP] = 0.
6937 * Set HSTPRTCMPL = 1. This places the link into compliance state.
6938
6939 To advance the compliance pattern, follow this sequence (toggle HSTPRTCMPL):
6940 * Set HSTPRTCMPL = 0.
6941 * Set HSTPRTCMPL = 1. This advances the link to the next compliance pattern.
6942
6943 To exit from the compliance state, set USBDRD()_UAHC_USBCMD[HCRST] = 1 or power-on-chip
6944 reset. */
6945 uint32_t u2ssinactp3ok : 1; /**< [ 29: 29](R/W) P3 OK for U2/SS.Inactive:
6946 0 = During link state U2/SS.Inactive, put PHY in P2 (default).
6947 1 = During link state U2/SS.Inactive, put PHY in P3. */
6948 uint32_t disrxdetp3 : 1; /**< [ 28: 28](R/W) Disables receiver detection in P3. If PHY is in P3 and the core needs to perform receiver
6949 detection:
6950 0 = Core performs receiver detection in P3 (default).
6951 1 = Core changes the PHY power state to P2 and then performs receiver detection. After
6952 receiver detection, core changes PHY power state to P3. */
6953 uint32_t ux_exit_in_px : 1; /**< [ 27: 27](R/W) UX exit in Px:
6954 0 = Core does U1/U2/U3 exit in PHY power state P0 (default behavior).
6955 1 = Core does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively.
6956
6957 This bit is added for SuperSpeed PHY workaround where SuperSpeed PHY injects a glitch on
6958 pipe3_RxElecIdle while receiving Ux exit LFPS, and pipe3_PowerDown change is in progress.
6959
6960 Internal:
6961 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
6962 Synopsys PHY. */
6963 uint32_t ping_enchance_en : 1; /**< [ 26: 26](R/W) Ping enhancement enable. When set to 1, the downstream-port U1-ping-receive timeout
6964 becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk
6965 cycle). This field is valid for the downstream port only.
6966
6967 Internal:
6968 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
6969 Synopsys PHY. */
6970 uint32_t u1u2exitfail_to_recov : 1; /**< [ 25: 25](R/W) U1U2exit fail to recovery. When set to 1, and U1/U2 LFPS handshake fails, the LTSSM
6971 transitions from U1/U2 to recovery instead of SS.inactive.
6972 If recovery fails, then the LTSSM can enter SS.Inactive. This is an enhancement only. It
6973 prevents interoperability issue if the remote link does not do the proper handshake. */
6974 uint32_t request_p1p2p3 : 1; /**< [ 24: 24](R/W) Always request P1/P2/P3 for U1/U2/U3.
6975 0 = if immediate Ux exit (remotely initiated, or locally initiated) happens, the core does
6976 not request P1/P2/P3 power state change.
6977 1 = the core always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3
6978 transition.
6979
6980 Internal:
6981 Note: This bit should be set to 1 for Synopsys PHY. For third-party SuperSpeed
6982 PHY, check with your PHY vendor. */
6983 uint32_t startrxdetu3rxdet : 1; /**< [ 23: 23](WO) Start receiver detection in U3/Rx.Detect.
6984 If DISRXDETU3RXDET is set to 1 during reset, and the link is in U3 or Rx.Detect state, the
6985 core starts receiver detection on rising edge of this bit.
6986 This bit is valid for downstream ports only, and this feature must not be enabled for
6987 normal operation.
6988
6989 Internal:
6990 If have to use this feature, contact Synopsys. */
6991 uint32_t disrxdetu3rxdet : 1; /**< [ 22: 22](R/W) Disable receiver detection in U3/Rx.Detect. When set to 1, the core does not do receiver
6992 detection in U3 or Rx.Detect state. If STARTRXDETU3RXDET is set to 1 during reset,
6993 receiver detection starts manually.
6994 This bit is valid for downstream ports only, and this feature must not be enabled for
6995 normal operation.
6996
6997 Internal:
6998 If have to use this feature, contact Synopsys. */
6999 uint32_t delaypx : 3; /**< [ 21: 19](R/W) Delay P1P2P3. Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DELAYPX * 8)
7000 8B10B error occurs, or Pipe3_RxValid drops to 0.
7001 DELAYPXTRANSENTERUX must reset to 1 to enable this functionality.
7002
7003 Internal:
7004 Should always be 0x1 for a Synopsys PHY. */
7005 uint32_t delaypxtransenterux : 1; /**< [ 18: 18](R/W) Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3
7006 respectively.
7007 0 = when entering U1/U2/U3, transition to P1/P2/P3 without checking for Pipe3_RxElecIlde
7008 and pipe3_RxValid.
7009 1 = when entering U1/U2/U3, delay the transition to P1/P2/P3 until the pipe3 signals,
7010 Pipe3_RxElecIlde is 1 and pipe3_RxValid is 0.
7011
7012 Internal:
7013 Note: This bit should be set to 1 for Synopsys PHY. It is also used by third-
7014 party SuperSpeed PHY. */
7015 uint32_t suspend_en : 1; /**< [ 17: 17](R/W) Suspend USB3.0 SuperSpeed PHY (Suspend_en). When set to 1, and if suspend conditions are
7016 valid, the USB 3.0 PHY enters suspend mode. */
7017 uint32_t datwidth : 2; /**< [ 16: 15](RO) PIPE data width.
7018 0x0 = 32 bits.
7019 0x1 = 16 bits.
7020 0x2 = 8 bits.
7021 0x3 = reserved.
7022
7023 One clock cycle after reset, these bits receive the value seen on the pipe3_DataBusWidth.
7024 This will always be 0x0.
7025
7026 Internal:
7027 The simulation testbench uses the coreConsultant parameter to configure the VIP.
7028 INTERNAL: These bits in the coreConsultant parameter should match your PHY data width and
7029 the pipe3_DataBusWidth port. */
7030 uint32_t abortrxdetinu2 : 1; /**< [ 14: 14](R/W) Abort RX Detect in U2. When set to 1, and the link state is U2, the core aborts receiver
7031 detection if it receives U2 exit LFPS from the remote link partner.
7032
7033 This bit is for downstream port only.
7034
7035 Internal:
7036 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7037 Synopsys PHY. */
7038 uint32_t skiprxdet : 1; /**< [ 13: 13](R/W) Skip RX detect. When set to 1, the core skips RX detection if pipe3_RxElecIdle is low.
7039 Skip is defined as waiting for the appropriate timeout, then repeating the operation. */
7040 uint32_t lfpsp0algn : 1; /**< [ 12: 12](R/W) LFPS P0 align. When set to 1:
7041 * Core deasserts LFPS transmission on the clock edge that it requests PHY power state
7042 0 when exiting U1, U2, or U3 low power states. Otherwise, LFPS transmission is asserted
7043 one clock earlier.
7044 * Core requests symbol transmission two pipe3_rx_pclks periods after the PHY asserts
7045 PhyStatus as a result of the PHY switching from P1 or P2 state to P0 state.
7046 For USB 3.0 host, this is not required. */
7047 uint32_t p3p2tranok : 1; /**< [ 11: 11](R/W) P3 P2 transitions OK.
7048 0 = P0 is always entered as an intermediate state during transitions between P2 and P3, as
7049 defined in the PIPE3 specification.
7050 1 = the core transitions directly from PHY power state P2 to P3 or from state P3 to P2.
7051
7052 According to PIPE3 specification, any direct transition between P3 and P2 is illegal.
7053
7054 Internal:
7055 This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3.
7056 INTERNAL: Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7057 Synopsys PHY. */
7058 uint32_t p3exsigp2 : 1; /**< [ 10: 10](R/W) P3 exit signal in P2. When set to 1, the core always changes the PHY power state to P2,
7059 before attempting a U3 exit handshake.
7060
7061 Internal:
7062 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7063 Synopsys PHY. */
7064 uint32_t lfpsfilt : 1; /**< [ 9: 9](R/W) LFPS filter. When set to 1, filter LFPS reception with pipe3_RxValid in PHY power state
7065 P0, ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are
7066 deasserted. */
7067 uint32_t rxdet2polllfpsctrl : 1; /**< [ 8: 8](R/W) RX_DETECT to polling.
7068 0 = Enables a 400 us delay to start polling LFPS after RX_DETECT. This allows VCM offset
7069 to settle to a proper level.
7070 1 = Disables the 400 us delay to start polling LFPS after RX_DETECT. */
7071 uint32_t ssicen : 1; /**< [ 7: 7](R/W) SSIC is not supported. This bit must be set to 0. */
7072 uint32_t txswing : 1; /**< [ 6: 6](R/W) TX swing. Refer to the PIPE3 specification. */
7073 uint32_t txmargin : 3; /**< [ 5: 3](R/W) TX margin. Refer to the PIPE3 specification, table 5-3. */
7074 uint32_t txdeemphasis : 2; /**< [ 2: 1](R/W) TX deemphasis. The value driven to the PHY is controlled by the LTSSM during USB3
7075 compliance mode. Refer to the PIPE3 specification, table 5-3.
7076
7077 Use the following values for the appropriate level of de-emphasis (From pipe3 spec):
7078 0x0 = -6 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_6DB].
7079 0x1 = -3.5 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_3P5DB].
7080 0x2 = No de-emphasis.
7081 0x3 = Reserved. */
7082 uint32_t elasticbuffermode : 1; /**< [ 0: 0](R/W) Elastic buffer mode. Refer to the PIPE3 specification, table 5-3. */
7083 #else /* Word 0 - Little Endian */
7084 uint32_t elasticbuffermode : 1; /**< [ 0: 0](R/W) Elastic buffer mode. Refer to the PIPE3 specification, table 5-3. */
7085 uint32_t txdeemphasis : 2; /**< [ 2: 1](R/W) TX deemphasis. The value driven to the PHY is controlled by the LTSSM during USB3
7086 compliance mode. Refer to the PIPE3 specification, table 5-3.
7087
7088 Use the following values for the appropriate level of de-emphasis (From pipe3 spec):
7089 0x0 = -6 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_6DB].
7090 0x1 = -3.5 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_3P5DB].
7091 0x2 = No de-emphasis.
7092 0x3 = Reserved. */
7093 uint32_t txmargin : 3; /**< [ 5: 3](R/W) TX margin. Refer to the PIPE3 specification, table 5-3. */
7094 uint32_t txswing : 1; /**< [ 6: 6](R/W) TX swing. Refer to the PIPE3 specification. */
7095 uint32_t ssicen : 1; /**< [ 7: 7](R/W) SSIC is not supported. This bit must be set to 0. */
7096 uint32_t rxdet2polllfpsctrl : 1; /**< [ 8: 8](R/W) RX_DETECT to polling.
7097 0 = Enables a 400 us delay to start polling LFPS after RX_DETECT. This allows VCM offset
7098 to settle to a proper level.
7099 1 = Disables the 400 us delay to start polling LFPS after RX_DETECT. */
7100 uint32_t lfpsfilt : 1; /**< [ 9: 9](R/W) LFPS filter. When set to 1, filter LFPS reception with pipe3_RxValid in PHY power state
7101 P0, ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are
7102 deasserted. */
7103 uint32_t p3exsigp2 : 1; /**< [ 10: 10](R/W) P3 exit signal in P2. When set to 1, the core always changes the PHY power state to P2,
7104 before attempting a U3 exit handshake.
7105
7106 Internal:
7107 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7108 Synopsys PHY. */
7109 uint32_t p3p2tranok : 1; /**< [ 11: 11](R/W) P3 P2 transitions OK.
7110 0 = P0 is always entered as an intermediate state during transitions between P2 and P3, as
7111 defined in the PIPE3 specification.
7112 1 = the core transitions directly from PHY power state P2 to P3 or from state P3 to P2.
7113
7114 According to PIPE3 specification, any direct transition between P3 and P2 is illegal.
7115
7116 Internal:
7117 This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3.
7118 INTERNAL: Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7119 Synopsys PHY. */
7120 uint32_t lfpsp0algn : 1; /**< [ 12: 12](R/W) LFPS P0 align. When set to 1:
7121 * Core deasserts LFPS transmission on the clock edge that it requests PHY power state
7122 0 when exiting U1, U2, or U3 low power states. Otherwise, LFPS transmission is asserted
7123 one clock earlier.
7124 * Core requests symbol transmission two pipe3_rx_pclks periods after the PHY asserts
7125 PhyStatus as a result of the PHY switching from P1 or P2 state to P0 state.
7126 For USB 3.0 host, this is not required. */
7127 uint32_t skiprxdet : 1; /**< [ 13: 13](R/W) Skip RX detect. When set to 1, the core skips RX detection if pipe3_RxElecIdle is low.
7128 Skip is defined as waiting for the appropriate timeout, then repeating the operation. */
7129 uint32_t abortrxdetinu2 : 1; /**< [ 14: 14](R/W) Abort RX Detect in U2. When set to 1, and the link state is U2, the core aborts receiver
7130 detection if it receives U2 exit LFPS from the remote link partner.
7131
7132 This bit is for downstream port only.
7133
7134 Internal:
7135 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7136 Synopsys PHY. */
7137 uint32_t datwidth : 2; /**< [ 16: 15](RO) PIPE data width.
7138 0x0 = 32 bits.
7139 0x1 = 16 bits.
7140 0x2 = 8 bits.
7141 0x3 = reserved.
7142
7143 One clock cycle after reset, these bits receive the value seen on the pipe3_DataBusWidth.
7144 This will always be 0x0.
7145
7146 Internal:
7147 The simulation testbench uses the coreConsultant parameter to configure the VIP.
7148 INTERNAL: These bits in the coreConsultant parameter should match your PHY data width and
7149 the pipe3_DataBusWidth port. */
7150 uint32_t suspend_en : 1; /**< [ 17: 17](R/W) Suspend USB3.0 SuperSpeed PHY (Suspend_en). When set to 1, and if suspend conditions are
7151 valid, the USB 3.0 PHY enters suspend mode. */
7152 uint32_t delaypxtransenterux : 1; /**< [ 18: 18](R/W) Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3
7153 respectively.
7154 0 = when entering U1/U2/U3, transition to P1/P2/P3 without checking for Pipe3_RxElecIlde
7155 and pipe3_RxValid.
7156 1 = when entering U1/U2/U3, delay the transition to P1/P2/P3 until the pipe3 signals,
7157 Pipe3_RxElecIlde is 1 and pipe3_RxValid is 0.
7158
7159 Internal:
7160 Note: This bit should be set to 1 for Synopsys PHY. It is also used by third-
7161 party SuperSpeed PHY. */
7162 uint32_t delaypx : 3; /**< [ 21: 19](R/W) Delay P1P2P3. Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DELAYPX * 8)
7163 8B10B error occurs, or Pipe3_RxValid drops to 0.
7164 DELAYPXTRANSENTERUX must reset to 1 to enable this functionality.
7165
7166 Internal:
7167 Should always be 0x1 for a Synopsys PHY. */
7168 uint32_t disrxdetu3rxdet : 1; /**< [ 22: 22](R/W) Disable receiver detection in U3/Rx.Detect. When set to 1, the core does not do receiver
7169 detection in U3 or Rx.Detect state. If STARTRXDETU3RXDET is set to 1 during reset,
7170 receiver detection starts manually.
7171 This bit is valid for downstream ports only, and this feature must not be enabled for
7172 normal operation.
7173
7174 Internal:
7175 If have to use this feature, contact Synopsys. */
7176 uint32_t startrxdetu3rxdet : 1; /**< [ 23: 23](WO) Start receiver detection in U3/Rx.Detect.
7177 If DISRXDETU3RXDET is set to 1 during reset, and the link is in U3 or Rx.Detect state, the
7178 core starts receiver detection on rising edge of this bit.
7179 This bit is valid for downstream ports only, and this feature must not be enabled for
7180 normal operation.
7181
7182 Internal:
7183 If have to use this feature, contact Synopsys. */
7184 uint32_t request_p1p2p3 : 1; /**< [ 24: 24](R/W) Always request P1/P2/P3 for U1/U2/U3.
7185 0 = if immediate Ux exit (remotely initiated, or locally initiated) happens, the core does
7186 not request P1/P2/P3 power state change.
7187 1 = the core always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3
7188 transition.
7189
7190 Internal:
7191 Note: This bit should be set to 1 for Synopsys PHY. For third-party SuperSpeed
7192 PHY, check with your PHY vendor. */
7193 uint32_t u1u2exitfail_to_recov : 1; /**< [ 25: 25](R/W) U1U2exit fail to recovery. When set to 1, and U1/U2 LFPS handshake fails, the LTSSM
7194 transitions from U1/U2 to recovery instead of SS.inactive.
7195 If recovery fails, then the LTSSM can enter SS.Inactive. This is an enhancement only. It
7196 prevents interoperability issue if the remote link does not do the proper handshake. */
7197 uint32_t ping_enchance_en : 1; /**< [ 26: 26](R/W) Ping enhancement enable. When set to 1, the downstream-port U1-ping-receive timeout
7198 becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk
7199 cycle). This field is valid for the downstream port only.
7200
7201 Internal:
7202 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7203 Synopsys PHY. */
7204 uint32_t ux_exit_in_px : 1; /**< [ 27: 27](R/W) UX exit in Px:
7205 0 = Core does U1/U2/U3 exit in PHY power state P0 (default behavior).
7206 1 = Core does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively.
7207
7208 This bit is added for SuperSpeed PHY workaround where SuperSpeed PHY injects a glitch on
7209 pipe3_RxElecIdle while receiving Ux exit LFPS, and pipe3_PowerDown change is in progress.
7210
7211 Internal:
7212 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7213 Synopsys PHY. */
7214 uint32_t disrxdetp3 : 1; /**< [ 28: 28](R/W) Disables receiver detection in P3. If PHY is in P3 and the core needs to perform receiver
7215 detection:
7216 0 = Core performs receiver detection in P3 (default).
7217 1 = Core changes the PHY power state to P2 and then performs receiver detection. After
7218 receiver detection, core changes PHY power state to P3. */
7219 uint32_t u2ssinactp3ok : 1; /**< [ 29: 29](R/W) P3 OK for U2/SS.Inactive:
7220 0 = During link state U2/SS.Inactive, put PHY in P2 (default).
7221 1 = During link state U2/SS.Inactive, put PHY in P3. */
7222 uint32_t hstprtcmpl : 1; /**< [ 30: 30](R/W) Host port compliance. Setting this bit to 1 enables placing the SuperSpeed port link into
7223 a compliance state, which allows testing of the PIPE PHY compliance patterns without
7224 having to have a test fixture on the USB 3.0 cable. By default, this bit should be set to
7225 0.
7226
7227 In compliance-lab testing, the SuperSpeed port link enters compliance after failing the
7228 first polling sequence after power on. Set this bit to 0 when you run compliance tests.
7229
7230 The sequence for using this functionality is as follows:
7231 * Disconnect any plugged-in devices.
7232 * Set USBDRD()_UAHC_USBCMD[HCRST] = 1 or power-on-chip reset.
7233 * Set USBDRD()_UAHC_PORTSC()[PP] = 0.
7234 * Set HSTPRTCMPL = 1. This places the link into compliance state.
7235
7236 To advance the compliance pattern, follow this sequence (toggle HSTPRTCMPL):
7237 * Set HSTPRTCMPL = 0.
7238 * Set HSTPRTCMPL = 1. This advances the link to the next compliance pattern.
7239
7240 To exit from the compliance state, set USBDRD()_UAHC_USBCMD[HCRST] = 1 or power-on-chip
7241 reset. */
7242 uint32_t physoftrst : 1; /**< [ 31: 31](R/W) USB3 PHY soft reset (PHYSoftRst). When set to 1, initiates a PHY soft reset. After setting
7243 this bit to 1, the software needs to clear this bit. */
7244 #endif /* Word 0 - End */
7245 } s;
7246 /* struct bdk_usbdrdx_uahc_gusb3pipectlx_s cn81xx; */
7247 struct bdk_usbdrdx_uahc_gusb3pipectlx_cn83xx
7248 {
7249 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7250 uint32_t physoftrst : 1; /**< [ 31: 31](R/W) USB3 PHY soft reset (PHYSoftRst). When set to 1, initiates a PHY soft reset. After setting
7251 this bit to 1, the software needs to clear this bit. */
7252 uint32_t hstprtcmpl : 1; /**< [ 30: 30](R/W) Host port compliance. Setting this bit to 1 enables placing the SuperSpeed port link into
7253 a compliance state, which allows testing of the PIPE PHY compliance patterns without
7254 having to have a test fixture on the USB 3.0 cable. By default, this bit should be set to
7255 0.
7256
7257 In compliance-lab testing, the SuperSpeed port link enters compliance after failing the
7258 first polling sequence after power on. Set this bit to 0 when you run compliance tests.
7259
7260 The sequence for using this functionality is as follows:
7261 * Disconnect any plugged-in devices.
7262 * Set USBDRD()_UAHC_USBCMD[HCRST] = 1 or power-on-chip reset.
7263 * Set USBDRD()_UAHC_PORTSC()[PP] = 0.
7264 * Set HSTPRTCMPL = 1. This places the link into compliance state.
7265
7266 To advance the compliance pattern, follow this sequence (toggle HSTPRTCMPL):
7267 * Set HSTPRTCMPL = 0.
7268 * Set HSTPRTCMPL = 1. This advances the link to the next compliance pattern.
7269
7270 To exit from the compliance state, set USBDRD()_UAHC_USBCMD[HCRST] = 1 or power-on-chip
7271 reset. */
7272 uint32_t u2ssinactp3ok : 1; /**< [ 29: 29](R/W) P3 OK for U2/SS.Inactive:
7273 0 = During link state U2/SS.Inactive, put PHY in P2 (default).
7274 1 = During link state U2/SS.Inactive, put PHY in P3. */
7275 uint32_t disrxdetp3 : 1; /**< [ 28: 28](R/W) Disables receiver detection in P3. If PHY is in P3 and the core needs to perform receiver
7276 detection:
7277 0 = Core performs receiver detection in P3 (default).
7278 1 = Core changes the PHY power state to P2 and then performs receiver detection. After
7279 receiver detection, core changes PHY power state to P3. */
7280 uint32_t ux_exit_in_px : 1; /**< [ 27: 27](R/W) UX exit in Px:
7281 0 = Core does U1/U2/U3 exit in PHY power state P0 (default behavior).
7282 1 = Core does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively.
7283
7284 This bit is added for SuperSpeed PHY workaround where SuperSpeed PHY injects a glitch on
7285 pipe3_RxElecIdle while receiving Ux exit LFPS, and pipe3_PowerDown change is in progress.
7286
7287 Internal:
7288 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7289 Synopsys PHY. */
7290 uint32_t ping_enchance_en : 1; /**< [ 26: 26](R/W) Ping enhancement enable. When set to 1, the downstream-port U1-ping-receive timeout
7291 becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk
7292 cycle). This field is valid for the downstream port only.
7293
7294 Internal:
7295 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7296 Synopsys PHY. */
7297 uint32_t u1u2exitfail_to_recov : 1; /**< [ 25: 25](R/W) U1U2exit fail to recovery. When set to 1, and U1/U2 LFPS handshake fails, the LTSSM
7298 transitions from U1/U2 to recovery instead of SS.inactive.
7299 If recovery fails, then the LTSSM can enter SS.Inactive. This is an enhancement only. It
7300 prevents interoperability issue if the remote link does not do the proper handshake. */
7301 uint32_t request_p1p2p3 : 1; /**< [ 24: 24](R/W) Always request P1/P2/P3 for U1/U2/U3.
7302 0 = if immediate Ux exit (remotely initiated, or locally initiated) happens, the core does
7303 not request P1/P2/P3 power state change.
7304 1 = the core always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3
7305 transition.
7306
7307 Internal:
7308 Note: This bit should be set to 1 for Synopsys PHY. For third-party SuperSpeed
7309 PHY, check with your PHY vendor. */
7310 uint32_t startrxdetu3rxdet : 1; /**< [ 23: 23](WO) Start receiver detection in U3/Rx.Detect.
7311 If DISRXDETU3RXDET is set to 1 during reset, and the link is in U3 or Rx.Detect state, the
7312 core starts receiver detection on rising edge of this bit.
7313 This bit is valid for downstream ports only, and this feature must not be enabled for
7314 normal operation.
7315
7316 Internal:
7317 If have to use this feature, contact Synopsys. */
7318 uint32_t disrxdetu3rxdet : 1; /**< [ 22: 22](R/W) Disable receiver detection in U3/Rx.Detect. When set to 1, the core does not do receiver
7319 detection in U3 or Rx.Detect state. If STARTRXDETU3RXDET is set to 1 during reset,
7320 receiver detection starts manually.
7321 This bit is valid for downstream ports only, and this feature must not be enabled for
7322 normal operation.
7323
7324 Internal:
7325 If have to use this feature, contact Synopsys. */
7326 uint32_t delaypx : 3; /**< [ 21: 19](R/W) Delay P1P2P3. Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DELAYPX * 8)
7327 8B10B error occurs, or Pipe3_RxValid drops to 0.
7328 DELAYPXTRANSENTERUX must reset to 1 to enable this functionality.
7329
7330 Internal:
7331 Should always be 0x1 for a Synopsys PHY. */
7332 uint32_t delaypxtransenterux : 1; /**< [ 18: 18](R/W) Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3
7333 respectively.
7334 0 = when entering U1/U2/U3, transition to P1/P2/P3 without checking for Pipe3_RxElecIlde
7335 and pipe3_RxValid.
7336 1 = when entering U1/U2/U3, delay the transition to P1/P2/P3 until the pipe3 signals,
7337 Pipe3_RxElecIlde is 1 and pipe3_RxValid is 0.
7338
7339 Internal:
7340 Note: This bit should be set to 1 for Synopsys PHY. It is also used by third-
7341 party SuperSpeed PHY. */
7342 uint32_t suspend_en : 1; /**< [ 17: 17](R/W) Suspend USB3.0 SuperSpeed PHY (Suspend_en). When set to 1, and if suspend conditions are
7343 valid, the USB 3.0 PHY enters suspend mode. */
7344 uint32_t datwidth : 2; /**< [ 16: 15](RO) PIPE data width.
7345 0x0 = 32 bits.
7346 0x1 = 16 bits.
7347 0x2 = 8 bits.
7348 0x3 = reserved.
7349
7350 One clock cycle after reset, these bits receive the value seen on the pipe3_DataBusWidth.
7351 This will always be 0x0.
7352
7353 Internal:
7354 The simulation testbench uses the coreConsultant parameter to configure the VIP.
7355 INTERNAL: These bits in the coreConsultant parameter should match your PHY data width and
7356 the pipe3_DataBusWidth port. */
7357 uint32_t abortrxdetinu2 : 1; /**< [ 14: 14](R/W) Abort RX Detect in U2. When set to 1, and the link state is U2, the core aborts receiver
7358 detection if it receives U2 exit LFPS from the remote link partner.
7359
7360 This bit is for downstream port only.
7361
7362 Internal:
7363 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7364 Synopsys PHY. */
7365 uint32_t skiprxdet : 1; /**< [ 13: 13](R/W) Skip RX detect. When set to 1, the core skips RX detection if pipe3_RxElecIdle is low.
7366 Skip is defined as waiting for the appropriate timeout, then repeating the operation. */
7367 uint32_t lfpsp0algn : 1; /**< [ 12: 12](R/W) LFPS P0 align. When set to 1:
7368 * Core deasserts LFPS transmission on the clock edge that it requests PHY power state
7369 0 when exiting U1, U2, or U3 low power states. Otherwise, LFPS transmission is asserted
7370 one clock earlier.
7371 * Core requests symbol transmission two pipe3_rx_pclks periods after the PHY asserts
7372 PhyStatus as a result of the PHY switching from P1 or P2 state to P0 state.
7373 For USB 3.0 host, this is not required. */
7374 uint32_t p3p2tranok : 1; /**< [ 11: 11](R/W) P3 P2 transitions OK.
7375 0 = P0 is always entered as an intermediate state during transitions between P2 and P3, as
7376 defined in the PIPE3 specification.
7377 1 = the core transitions directly from PHY power state P2 to P3 or from state P3 to P2.
7378
7379 According to PIPE3 specification, any direct transition between P3 and P2 is illegal.
7380
7381 Internal:
7382 This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3.
7383 INTERNAL: Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7384 Synopsys PHY. */
7385 uint32_t p3exsigp2 : 1; /**< [ 10: 10](R/W) P3 exit signal in P2. When set to 1, the core always changes the PHY power state to P2,
7386 before attempting a U3 exit handshake.
7387
7388 Internal:
7389 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7390 Synopsys PHY. */
7391 uint32_t lfpsfilt : 1; /**< [ 9: 9](R/W) LFPS filter. When set to 1, filter LFPS reception with pipe3_RxValid in PHY power state
7392 P0, ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are
7393 deasserted. */
7394 uint32_t rxdet2polllfpsctrl : 1; /**< [ 8: 8](R/W) RX_DETECT to polling.
7395 0 = Enables a 400 us delay to start polling LFPS after RX_DETECT. This allows VCM offset
7396 to settle to a proper level.
7397 1 = Disables the 400 us delay to start polling LFPS after RX_DETECT. */
7398 uint32_t ssicen : 1; /**< [ 7: 7](R/W) SSIC is not supported. This bit must be set to 0. */
7399 uint32_t txswing : 1; /**< [ 6: 6](R/W) TX swing. Refer to the PIPE3 specification. */
7400 uint32_t txmargin : 3; /**< [ 5: 3](R/W) TX margin. Refer to the PIPE3 specification, table 5-3. */
7401 uint32_t txdeemphasis : 2; /**< [ 2: 1](R/W) TX deemphasis. The value driven to the PHY is controlled by the LTSSM during USB3
7402 compliance mode. Refer to the PIPE3 specification, table 5-3.
7403
7404 Use the following values for the appropriate level of de-emphasis (From pipe3 spec):
7405 0x0 = -6 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_6DB].
7406 0x1 = -3.5 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_3P5DB].
7407 0x2 = No de-emphasis.
7408 0x3 = Reserved.
7409
7410 Use the following values for the appropriate level of de-emphasis (From pipe3 spec):
7411 0x0 = -6 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_6DB].
7412 0x1 = -3.5 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_3P5DB].
7413 0x2 = No de-emphasis.
7414 0x3 = Reserved. */
7415 uint32_t elasticbuffermode : 1; /**< [ 0: 0](R/W) Elastic buffer mode. Refer to the PIPE3 specification, table 5-3. */
7416 #else /* Word 0 - Little Endian */
7417 uint32_t elasticbuffermode : 1; /**< [ 0: 0](R/W) Elastic buffer mode. Refer to the PIPE3 specification, table 5-3. */
7418 uint32_t txdeemphasis : 2; /**< [ 2: 1](R/W) TX deemphasis. The value driven to the PHY is controlled by the LTSSM during USB3
7419 compliance mode. Refer to the PIPE3 specification, table 5-3.
7420
7421 Use the following values for the appropriate level of de-emphasis (From pipe3 spec):
7422 0x0 = -6 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_6DB].
7423 0x1 = -3.5 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_3P5DB].
7424 0x2 = No de-emphasis.
7425 0x3 = Reserved.
7426
7427 Use the following values for the appropriate level of de-emphasis (From pipe3 spec):
7428 0x0 = -6 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_6DB].
7429 0x1 = -3.5 dB de-emphasis, use USBDRD()_UCTL_PORT()_CFG_SS[PCS_TX_DEEMPH_3P5DB].
7430 0x2 = No de-emphasis.
7431 0x3 = Reserved. */
7432 uint32_t txmargin : 3; /**< [ 5: 3](R/W) TX margin. Refer to the PIPE3 specification, table 5-3. */
7433 uint32_t txswing : 1; /**< [ 6: 6](R/W) TX swing. Refer to the PIPE3 specification. */
7434 uint32_t ssicen : 1; /**< [ 7: 7](R/W) SSIC is not supported. This bit must be set to 0. */
7435 uint32_t rxdet2polllfpsctrl : 1; /**< [ 8: 8](R/W) RX_DETECT to polling.
7436 0 = Enables a 400 us delay to start polling LFPS after RX_DETECT. This allows VCM offset
7437 to settle to a proper level.
7438 1 = Disables the 400 us delay to start polling LFPS after RX_DETECT. */
7439 uint32_t lfpsfilt : 1; /**< [ 9: 9](R/W) LFPS filter. When set to 1, filter LFPS reception with pipe3_RxValid in PHY power state
7440 P0, ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are
7441 deasserted. */
7442 uint32_t p3exsigp2 : 1; /**< [ 10: 10](R/W) P3 exit signal in P2. When set to 1, the core always changes the PHY power state to P2,
7443 before attempting a U3 exit handshake.
7444
7445 Internal:
7446 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7447 Synopsys PHY. */
7448 uint32_t p3p2tranok : 1; /**< [ 11: 11](R/W) P3 P2 transitions OK.
7449 0 = P0 is always entered as an intermediate state during transitions between P2 and P3, as
7450 defined in the PIPE3 specification.
7451 1 = the core transitions directly from PHY power state P2 to P3 or from state P3 to P2.
7452
7453 According to PIPE3 specification, any direct transition between P3 and P2 is illegal.
7454
7455 Internal:
7456 This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3.
7457 INTERNAL: Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7458 Synopsys PHY. */
7459 uint32_t lfpsp0algn : 1; /**< [ 12: 12](R/W) LFPS P0 align. When set to 1:
7460 * Core deasserts LFPS transmission on the clock edge that it requests PHY power state
7461 0 when exiting U1, U2, or U3 low power states. Otherwise, LFPS transmission is asserted
7462 one clock earlier.
7463 * Core requests symbol transmission two pipe3_rx_pclks periods after the PHY asserts
7464 PhyStatus as a result of the PHY switching from P1 or P2 state to P0 state.
7465 For USB 3.0 host, this is not required. */
7466 uint32_t skiprxdet : 1; /**< [ 13: 13](R/W) Skip RX detect. When set to 1, the core skips RX detection if pipe3_RxElecIdle is low.
7467 Skip is defined as waiting for the appropriate timeout, then repeating the operation. */
7468 uint32_t abortrxdetinu2 : 1; /**< [ 14: 14](R/W) Abort RX Detect in U2. When set to 1, and the link state is U2, the core aborts receiver
7469 detection if it receives U2 exit LFPS from the remote link partner.
7470
7471 This bit is for downstream port only.
7472
7473 Internal:
7474 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7475 Synopsys PHY. */
7476 uint32_t datwidth : 2; /**< [ 16: 15](RO) PIPE data width.
7477 0x0 = 32 bits.
7478 0x1 = 16 bits.
7479 0x2 = 8 bits.
7480 0x3 = reserved.
7481
7482 One clock cycle after reset, these bits receive the value seen on the pipe3_DataBusWidth.
7483 This will always be 0x0.
7484
7485 Internal:
7486 The simulation testbench uses the coreConsultant parameter to configure the VIP.
7487 INTERNAL: These bits in the coreConsultant parameter should match your PHY data width and
7488 the pipe3_DataBusWidth port. */
7489 uint32_t suspend_en : 1; /**< [ 17: 17](R/W) Suspend USB3.0 SuperSpeed PHY (Suspend_en). When set to 1, and if suspend conditions are
7490 valid, the USB 3.0 PHY enters suspend mode. */
7491 uint32_t delaypxtransenterux : 1; /**< [ 18: 18](R/W) Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3
7492 respectively.
7493 0 = when entering U1/U2/U3, transition to P1/P2/P3 without checking for Pipe3_RxElecIlde
7494 and pipe3_RxValid.
7495 1 = when entering U1/U2/U3, delay the transition to P1/P2/P3 until the pipe3 signals,
7496 Pipe3_RxElecIlde is 1 and pipe3_RxValid is 0.
7497
7498 Internal:
7499 Note: This bit should be set to 1 for Synopsys PHY. It is also used by third-
7500 party SuperSpeed PHY. */
7501 uint32_t delaypx : 3; /**< [ 21: 19](R/W) Delay P1P2P3. Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DELAYPX * 8)
7502 8B10B error occurs, or Pipe3_RxValid drops to 0.
7503 DELAYPXTRANSENTERUX must reset to 1 to enable this functionality.
7504
7505 Internal:
7506 Should always be 0x1 for a Synopsys PHY. */
7507 uint32_t disrxdetu3rxdet : 1; /**< [ 22: 22](R/W) Disable receiver detection in U3/Rx.Detect. When set to 1, the core does not do receiver
7508 detection in U3 or Rx.Detect state. If STARTRXDETU3RXDET is set to 1 during reset,
7509 receiver detection starts manually.
7510 This bit is valid for downstream ports only, and this feature must not be enabled for
7511 normal operation.
7512
7513 Internal:
7514 If have to use this feature, contact Synopsys. */
7515 uint32_t startrxdetu3rxdet : 1; /**< [ 23: 23](WO) Start receiver detection in U3/Rx.Detect.
7516 If DISRXDETU3RXDET is set to 1 during reset, and the link is in U3 or Rx.Detect state, the
7517 core starts receiver detection on rising edge of this bit.
7518 This bit is valid for downstream ports only, and this feature must not be enabled for
7519 normal operation.
7520
7521 Internal:
7522 If have to use this feature, contact Synopsys. */
7523 uint32_t request_p1p2p3 : 1; /**< [ 24: 24](R/W) Always request P1/P2/P3 for U1/U2/U3.
7524 0 = if immediate Ux exit (remotely initiated, or locally initiated) happens, the core does
7525 not request P1/P2/P3 power state change.
7526 1 = the core always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3
7527 transition.
7528
7529 Internal:
7530 Note: This bit should be set to 1 for Synopsys PHY. For third-party SuperSpeed
7531 PHY, check with your PHY vendor. */
7532 uint32_t u1u2exitfail_to_recov : 1; /**< [ 25: 25](R/W) U1U2exit fail to recovery. When set to 1, and U1/U2 LFPS handshake fails, the LTSSM
7533 transitions from U1/U2 to recovery instead of SS.inactive.
7534 If recovery fails, then the LTSSM can enter SS.Inactive. This is an enhancement only. It
7535 prevents interoperability issue if the remote link does not do the proper handshake. */
7536 uint32_t ping_enchance_en : 1; /**< [ 26: 26](R/W) Ping enhancement enable. When set to 1, the downstream-port U1-ping-receive timeout
7537 becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk
7538 cycle). This field is valid for the downstream port only.
7539
7540 Internal:
7541 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7542 Synopsys PHY. */
7543 uint32_t ux_exit_in_px : 1; /**< [ 27: 27](R/W) UX exit in Px:
7544 0 = Core does U1/U2/U3 exit in PHY power state P0 (default behavior).
7545 1 = Core does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively.
7546
7547 This bit is added for SuperSpeed PHY workaround where SuperSpeed PHY injects a glitch on
7548 pipe3_RxElecIdle while receiving Ux exit LFPS, and pipe3_PowerDown change is in progress.
7549
7550 Internal:
7551 Note: This bit is used by third-party SuperSpeed PHY. It should be set to 0 for
7552 Synopsys PHY. */
7553 uint32_t disrxdetp3 : 1; /**< [ 28: 28](R/W) Disables receiver detection in P3. If PHY is in P3 and the core needs to perform receiver
7554 detection:
7555 0 = Core performs receiver detection in P3 (default).
7556 1 = Core changes the PHY power state to P2 and then performs receiver detection. After
7557 receiver detection, core changes PHY power state to P3. */
7558 uint32_t u2ssinactp3ok : 1; /**< [ 29: 29](R/W) P3 OK for U2/SS.Inactive:
7559 0 = During link state U2/SS.Inactive, put PHY in P2 (default).
7560 1 = During link state U2/SS.Inactive, put PHY in P3. */
7561 uint32_t hstprtcmpl : 1; /**< [ 30: 30](R/W) Host port compliance. Setting this bit to 1 enables placing the SuperSpeed port link into
7562 a compliance state, which allows testing of the PIPE PHY compliance patterns without
7563 having to have a test fixture on the USB 3.0 cable. By default, this bit should be set to
7564 0.
7565
7566 In compliance-lab testing, the SuperSpeed port link enters compliance after failing the
7567 first polling sequence after power on. Set this bit to 0 when you run compliance tests.
7568
7569 The sequence for using this functionality is as follows:
7570 * Disconnect any plugged-in devices.
7571 * Set USBDRD()_UAHC_USBCMD[HCRST] = 1 or power-on-chip reset.
7572 * Set USBDRD()_UAHC_PORTSC()[PP] = 0.
7573 * Set HSTPRTCMPL = 1. This places the link into compliance state.
7574
7575 To advance the compliance pattern, follow this sequence (toggle HSTPRTCMPL):
7576 * Set HSTPRTCMPL = 0.
7577 * Set HSTPRTCMPL = 1. This advances the link to the next compliance pattern.
7578
7579 To exit from the compliance state, set USBDRD()_UAHC_USBCMD[HCRST] = 1 or power-on-chip
7580 reset. */
7581 uint32_t physoftrst : 1; /**< [ 31: 31](R/W) USB3 PHY soft reset (PHYSoftRst). When set to 1, initiates a PHY soft reset. After setting
7582 this bit to 1, the software needs to clear this bit. */
7583 #endif /* Word 0 - End */
7584 } cn83xx;
7585 /* struct bdk_usbdrdx_uahc_gusb3pipectlx_cn83xx cn9; */
7586 };
7587 typedef union bdk_usbdrdx_uahc_gusb3pipectlx bdk_usbdrdx_uahc_gusb3pipectlx_t;
7588
7589 static inline uint64_t BDK_USBDRDX_UAHC_GUSB3PIPECTLX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_GUSB3PIPECTLX(unsigned long a,unsigned long b)7590 static inline uint64_t BDK_USBDRDX_UAHC_GUSB3PIPECTLX(unsigned long a, unsigned long b)
7591 {
7592 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
7593 return 0x86800000c2c0ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
7594 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
7595 return 0x86800000c2c0ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
7596 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
7597 return 0x86800000c2c0ll + 0x1000000000ll * ((a) & 0x1) + 4ll * ((b) & 0x0);
7598 __bdk_csr_fatal("USBDRDX_UAHC_GUSB3PIPECTLX", 2, a, b, 0, 0);
7599 }
7600
7601 #define typedef_BDK_USBDRDX_UAHC_GUSB3PIPECTLX(a,b) bdk_usbdrdx_uahc_gusb3pipectlx_t
7602 #define bustype_BDK_USBDRDX_UAHC_GUSB3PIPECTLX(a,b) BDK_CSR_TYPE_NCB32b
7603 #define basename_BDK_USBDRDX_UAHC_GUSB3PIPECTLX(a,b) "USBDRDX_UAHC_GUSB3PIPECTLX"
7604 #define device_bar_BDK_USBDRDX_UAHC_GUSB3PIPECTLX(a,b) 0x0 /* PF_BAR0 */
7605 #define busnum_BDK_USBDRDX_UAHC_GUSB3PIPECTLX(a,b) (a)
7606 #define arguments_BDK_USBDRDX_UAHC_GUSB3PIPECTLX(a,b) (a),(b),-1,-1
7607
7608 /**
7609 * Register (NCB32b) usbdrd#_uahc_hccparams
7610 *
7611 * USB XHCI Controller Capability Parameters Register
7612 * For information on this register, refer to the xHCI Specification, v1.0, section 5.3.6.
7613 */
7614 union bdk_usbdrdx_uahc_hccparams
7615 {
7616 uint32_t u;
7617 struct bdk_usbdrdx_uahc_hccparams_s
7618 {
7619 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7620 uint32_t xecp : 16; /**< [ 31: 16](RO) xHCI extended capabilities pointer. */
7621 uint32_t maxpsasize : 4; /**< [ 15: 12](RO) Maximum primary-stream-array size. */
7622 uint32_t reserved_11 : 1;
7623 uint32_t sec : 1; /**< [ 10: 10](RO/H) Stopped EDLTA capability. */
7624 uint32_t spc : 1; /**< [ 9: 9](RO/H) Stopped - short packet capability. */
7625 uint32_t pae : 1; /**< [ 8: 8](RO) Parse all event data. */
7626 uint32_t nss : 1; /**< [ 7: 7](RO) No secondary SID support. */
7627 uint32_t ltc : 1; /**< [ 6: 6](RO) Latency tolerance messaging capability. */
7628 uint32_t lhrc : 1; /**< [ 5: 5](RO) Light HC reset capability. */
7629 uint32_t pind : 1; /**< [ 4: 4](RO) Port indicators. */
7630 uint32_t ppc : 1; /**< [ 3: 3](RO) Port power control. Value is based on USBDRD()_UCTL_HOST_CFG[PPC_EN]. */
7631 uint32_t csz : 1; /**< [ 2: 2](RO) Context size. */
7632 uint32_t bnc : 1; /**< [ 1: 1](RO) BW negotiation capability. */
7633 uint32_t ac64 : 1; /**< [ 0: 0](RO) 64-bit addressing capability. */
7634 #else /* Word 0 - Little Endian */
7635 uint32_t ac64 : 1; /**< [ 0: 0](RO) 64-bit addressing capability. */
7636 uint32_t bnc : 1; /**< [ 1: 1](RO) BW negotiation capability. */
7637 uint32_t csz : 1; /**< [ 2: 2](RO) Context size. */
7638 uint32_t ppc : 1; /**< [ 3: 3](RO) Port power control. Value is based on USBDRD()_UCTL_HOST_CFG[PPC_EN]. */
7639 uint32_t pind : 1; /**< [ 4: 4](RO) Port indicators. */
7640 uint32_t lhrc : 1; /**< [ 5: 5](RO) Light HC reset capability. */
7641 uint32_t ltc : 1; /**< [ 6: 6](RO) Latency tolerance messaging capability. */
7642 uint32_t nss : 1; /**< [ 7: 7](RO) No secondary SID support. */
7643 uint32_t pae : 1; /**< [ 8: 8](RO) Parse all event data. */
7644 uint32_t spc : 1; /**< [ 9: 9](RO/H) Stopped - short packet capability. */
7645 uint32_t sec : 1; /**< [ 10: 10](RO/H) Stopped EDLTA capability. */
7646 uint32_t reserved_11 : 1;
7647 uint32_t maxpsasize : 4; /**< [ 15: 12](RO) Maximum primary-stream-array size. */
7648 uint32_t xecp : 16; /**< [ 31: 16](RO) xHCI extended capabilities pointer. */
7649 #endif /* Word 0 - End */
7650 } s;
7651 /* struct bdk_usbdrdx_uahc_hccparams_s cn; */
7652 };
7653 typedef union bdk_usbdrdx_uahc_hccparams bdk_usbdrdx_uahc_hccparams_t;
7654
7655 static inline uint64_t BDK_USBDRDX_UAHC_HCCPARAMS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_HCCPARAMS(unsigned long a)7656 static inline uint64_t BDK_USBDRDX_UAHC_HCCPARAMS(unsigned long a)
7657 {
7658 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
7659 return 0x868000000010ll + 0x1000000000ll * ((a) & 0x1);
7660 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
7661 return 0x868000000010ll + 0x1000000000ll * ((a) & 0x1);
7662 __bdk_csr_fatal("USBDRDX_UAHC_HCCPARAMS", 1, a, 0, 0, 0);
7663 }
7664
7665 #define typedef_BDK_USBDRDX_UAHC_HCCPARAMS(a) bdk_usbdrdx_uahc_hccparams_t
7666 #define bustype_BDK_USBDRDX_UAHC_HCCPARAMS(a) BDK_CSR_TYPE_NCB32b
7667 #define basename_BDK_USBDRDX_UAHC_HCCPARAMS(a) "USBDRDX_UAHC_HCCPARAMS"
7668 #define device_bar_BDK_USBDRDX_UAHC_HCCPARAMS(a) 0x0 /* PF_BAR0 */
7669 #define busnum_BDK_USBDRDX_UAHC_HCCPARAMS(a) (a)
7670 #define arguments_BDK_USBDRDX_UAHC_HCCPARAMS(a) (a),-1,-1,-1
7671
7672 /**
7673 * Register (NCB32b) usbdrd#_uahc_hccparams1
7674 *
7675 * USB XHCI Controller Capability Parameters Register 1
7676 * For information on this register, refer to the xHCI Specification, v1.1, section 5.3.6.
7677 */
7678 union bdk_usbdrdx_uahc_hccparams1
7679 {
7680 uint32_t u;
7681 struct bdk_usbdrdx_uahc_hccparams1_s
7682 {
7683 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7684 uint32_t xecp : 16; /**< [ 31: 16](RO) xHCI extended capabilities pointer. */
7685 uint32_t maxpsasize : 4; /**< [ 15: 12](RO) Maximum primary-stream-array size. */
7686 uint32_t cfc : 1; /**< [ 11: 11](RO) Contiguous frame ID capability. */
7687 uint32_t sec : 1; /**< [ 10: 10](RO/H) Stopped EDLTA capability. */
7688 uint32_t spc : 1; /**< [ 9: 9](RO/H) Stopped - short packet capability. */
7689 uint32_t pae : 1; /**< [ 8: 8](RO) Parse all event data. */
7690 uint32_t nss : 1; /**< [ 7: 7](RO) No secondary SID support. */
7691 uint32_t ltc : 1; /**< [ 6: 6](RO) Latency tolerance messaging capability. */
7692 uint32_t lhrc : 1; /**< [ 5: 5](RO) Light HC reset capability. */
7693 uint32_t pind : 1; /**< [ 4: 4](RO) Port indicators. */
7694 uint32_t ppc : 1; /**< [ 3: 3](RO) Port power control. Value is based on USBDRD()_UCTL_HOST_CFG[PPC_EN]. */
7695 uint32_t csz : 1; /**< [ 2: 2](RO) Context size. */
7696 uint32_t bnc : 1; /**< [ 1: 1](RO) BW negotiation capability. */
7697 uint32_t ac64 : 1; /**< [ 0: 0](RO) 64-bit addressing capability. */
7698 #else /* Word 0 - Little Endian */
7699 uint32_t ac64 : 1; /**< [ 0: 0](RO) 64-bit addressing capability. */
7700 uint32_t bnc : 1; /**< [ 1: 1](RO) BW negotiation capability. */
7701 uint32_t csz : 1; /**< [ 2: 2](RO) Context size. */
7702 uint32_t ppc : 1; /**< [ 3: 3](RO) Port power control. Value is based on USBDRD()_UCTL_HOST_CFG[PPC_EN]. */
7703 uint32_t pind : 1; /**< [ 4: 4](RO) Port indicators. */
7704 uint32_t lhrc : 1; /**< [ 5: 5](RO) Light HC reset capability. */
7705 uint32_t ltc : 1; /**< [ 6: 6](RO) Latency tolerance messaging capability. */
7706 uint32_t nss : 1; /**< [ 7: 7](RO) No secondary SID support. */
7707 uint32_t pae : 1; /**< [ 8: 8](RO) Parse all event data. */
7708 uint32_t spc : 1; /**< [ 9: 9](RO/H) Stopped - short packet capability. */
7709 uint32_t sec : 1; /**< [ 10: 10](RO/H) Stopped EDLTA capability. */
7710 uint32_t cfc : 1; /**< [ 11: 11](RO) Contiguous frame ID capability. */
7711 uint32_t maxpsasize : 4; /**< [ 15: 12](RO) Maximum primary-stream-array size. */
7712 uint32_t xecp : 16; /**< [ 31: 16](RO) xHCI extended capabilities pointer. */
7713 #endif /* Word 0 - End */
7714 } s;
7715 /* struct bdk_usbdrdx_uahc_hccparams1_s cn; */
7716 };
7717 typedef union bdk_usbdrdx_uahc_hccparams1 bdk_usbdrdx_uahc_hccparams1_t;
7718
7719 static inline uint64_t BDK_USBDRDX_UAHC_HCCPARAMS1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_HCCPARAMS1(unsigned long a)7720 static inline uint64_t BDK_USBDRDX_UAHC_HCCPARAMS1(unsigned long a)
7721 {
7722 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
7723 return 0x868000000010ll + 0x1000000000ll * ((a) & 0x1);
7724 __bdk_csr_fatal("USBDRDX_UAHC_HCCPARAMS1", 1, a, 0, 0, 0);
7725 }
7726
7727 #define typedef_BDK_USBDRDX_UAHC_HCCPARAMS1(a) bdk_usbdrdx_uahc_hccparams1_t
7728 #define bustype_BDK_USBDRDX_UAHC_HCCPARAMS1(a) BDK_CSR_TYPE_NCB32b
7729 #define basename_BDK_USBDRDX_UAHC_HCCPARAMS1(a) "USBDRDX_UAHC_HCCPARAMS1"
7730 #define device_bar_BDK_USBDRDX_UAHC_HCCPARAMS1(a) 0x0 /* PF_BAR0 */
7731 #define busnum_BDK_USBDRDX_UAHC_HCCPARAMS1(a) (a)
7732 #define arguments_BDK_USBDRDX_UAHC_HCCPARAMS1(a) (a),-1,-1,-1
7733
7734 /**
7735 * Register (NCB32b) usbdrd#_uahc_hccparams2
7736 *
7737 * USB XHCI Controller Capability Parameters Register 2
7738 * The default values for all fields in this register are implementation dependent. For
7739 * information on this register, refer to the xHCI Specification, v1.1, section 5.3.9.
7740 */
7741 union bdk_usbdrdx_uahc_hccparams2
7742 {
7743 uint32_t u;
7744 struct bdk_usbdrdx_uahc_hccparams2_s
7745 {
7746 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7747 uint32_t reserved_6_31 : 26;
7748 uint32_t cic : 1; /**< [ 5: 5](RO) Configuration information capability. */
7749 uint32_t lec : 1; /**< [ 4: 4](RO) Large ESIT payload capability. */
7750 uint32_t ctc : 1; /**< [ 3: 3](RO) Compliance transition capability. */
7751 uint32_t fsc : 1; /**< [ 2: 2](RO) Force save context capability. */
7752 uint32_t cmc : 1; /**< [ 1: 1](RO) Configure endpoint command max exit latency too large capability. */
7753 uint32_t u3c : 1; /**< [ 0: 0](RO) U3 entry capability. */
7754 #else /* Word 0 - Little Endian */
7755 uint32_t u3c : 1; /**< [ 0: 0](RO) U3 entry capability. */
7756 uint32_t cmc : 1; /**< [ 1: 1](RO) Configure endpoint command max exit latency too large capability. */
7757 uint32_t fsc : 1; /**< [ 2: 2](RO) Force save context capability. */
7758 uint32_t ctc : 1; /**< [ 3: 3](RO) Compliance transition capability. */
7759 uint32_t lec : 1; /**< [ 4: 4](RO) Large ESIT payload capability. */
7760 uint32_t cic : 1; /**< [ 5: 5](RO) Configuration information capability. */
7761 uint32_t reserved_6_31 : 26;
7762 #endif /* Word 0 - End */
7763 } s;
7764 /* struct bdk_usbdrdx_uahc_hccparams2_s cn; */
7765 };
7766 typedef union bdk_usbdrdx_uahc_hccparams2 bdk_usbdrdx_uahc_hccparams2_t;
7767
7768 static inline uint64_t BDK_USBDRDX_UAHC_HCCPARAMS2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_HCCPARAMS2(unsigned long a)7769 static inline uint64_t BDK_USBDRDX_UAHC_HCCPARAMS2(unsigned long a)
7770 {
7771 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
7772 return 0x86800000001cll + 0x1000000000ll * ((a) & 0x1);
7773 __bdk_csr_fatal("USBDRDX_UAHC_HCCPARAMS2", 1, a, 0, 0, 0);
7774 }
7775
7776 #define typedef_BDK_USBDRDX_UAHC_HCCPARAMS2(a) bdk_usbdrdx_uahc_hccparams2_t
7777 #define bustype_BDK_USBDRDX_UAHC_HCCPARAMS2(a) BDK_CSR_TYPE_NCB32b
7778 #define basename_BDK_USBDRDX_UAHC_HCCPARAMS2(a) "USBDRDX_UAHC_HCCPARAMS2"
7779 #define device_bar_BDK_USBDRDX_UAHC_HCCPARAMS2(a) 0x0 /* PF_BAR0 */
7780 #define busnum_BDK_USBDRDX_UAHC_HCCPARAMS2(a) (a)
7781 #define arguments_BDK_USBDRDX_UAHC_HCCPARAMS2(a) (a),-1,-1,-1
7782
7783 /**
7784 * Register (NCB32b) usbdrd#_uahc_hcsparams1
7785 *
7786 * USB XHCI Controller Structural Parameters Register 1
7787 * This register defines basic structural parameters supported by this xHC implementation: number
7788 * of device slots support, Interrupters, root hub ports, etc. For information on this
7789 * register, refer to the xHCI Specification, v1.1, section 5.3.3.
7790 */
7791 union bdk_usbdrdx_uahc_hcsparams1
7792 {
7793 uint32_t u;
7794 struct bdk_usbdrdx_uahc_hcsparams1_s
7795 {
7796 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7797 uint32_t maxports : 8; /**< [ 31: 24](RO) Maximum number of ports. */
7798 uint32_t reserved_19_23 : 5;
7799 uint32_t maxintrs : 11; /**< [ 18: 8](RO) Maximum number of interrupters. */
7800 uint32_t maxslots : 8; /**< [ 7: 0](RO) Maximum number of device slots. */
7801 #else /* Word 0 - Little Endian */
7802 uint32_t maxslots : 8; /**< [ 7: 0](RO) Maximum number of device slots. */
7803 uint32_t maxintrs : 11; /**< [ 18: 8](RO) Maximum number of interrupters. */
7804 uint32_t reserved_19_23 : 5;
7805 uint32_t maxports : 8; /**< [ 31: 24](RO) Maximum number of ports. */
7806 #endif /* Word 0 - End */
7807 } s;
7808 /* struct bdk_usbdrdx_uahc_hcsparams1_s cn; */
7809 };
7810 typedef union bdk_usbdrdx_uahc_hcsparams1 bdk_usbdrdx_uahc_hcsparams1_t;
7811
7812 static inline uint64_t BDK_USBDRDX_UAHC_HCSPARAMS1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_HCSPARAMS1(unsigned long a)7813 static inline uint64_t BDK_USBDRDX_UAHC_HCSPARAMS1(unsigned long a)
7814 {
7815 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
7816 return 0x868000000004ll + 0x1000000000ll * ((a) & 0x1);
7817 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
7818 return 0x868000000004ll + 0x1000000000ll * ((a) & 0x1);
7819 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
7820 return 0x868000000004ll + 0x1000000000ll * ((a) & 0x1);
7821 __bdk_csr_fatal("USBDRDX_UAHC_HCSPARAMS1", 1, a, 0, 0, 0);
7822 }
7823
7824 #define typedef_BDK_USBDRDX_UAHC_HCSPARAMS1(a) bdk_usbdrdx_uahc_hcsparams1_t
7825 #define bustype_BDK_USBDRDX_UAHC_HCSPARAMS1(a) BDK_CSR_TYPE_NCB32b
7826 #define basename_BDK_USBDRDX_UAHC_HCSPARAMS1(a) "USBDRDX_UAHC_HCSPARAMS1"
7827 #define device_bar_BDK_USBDRDX_UAHC_HCSPARAMS1(a) 0x0 /* PF_BAR0 */
7828 #define busnum_BDK_USBDRDX_UAHC_HCSPARAMS1(a) (a)
7829 #define arguments_BDK_USBDRDX_UAHC_HCSPARAMS1(a) (a),-1,-1,-1
7830
7831 /**
7832 * Register (NCB32b) usbdrd#_uahc_hcsparams2
7833 *
7834 * USB XHCI Controller Structural Parameters Register 2
7835 * This register defines additional xHC structural parameters. For information on this register,
7836 * refer to the xHCI Specification, v1.1, section 5.3.4.
7837 */
7838 union bdk_usbdrdx_uahc_hcsparams2
7839 {
7840 uint32_t u;
7841 struct bdk_usbdrdx_uahc_hcsparams2_s
7842 {
7843 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7844 uint32_t maxscratchpadbufs_l : 5; /**< [ 31: 27](RO) Maximum number of scratchpad buffers[4:0]. */
7845 uint32_t spr : 1; /**< [ 26: 26](RO) Scratchpad restore. */
7846 uint32_t maxscratchpadbufs_h : 5; /**< [ 25: 21](RO) Maximum number of scratchpad buffers[9:5]. */
7847 uint32_t reserved_8_20 : 13;
7848 uint32_t erst_max : 4; /**< [ 7: 4](RO) Event ring segment table maximum. */
7849 uint32_t ist : 4; /**< [ 3: 0](RO) Isochronous scheduling threshold. */
7850 #else /* Word 0 - Little Endian */
7851 uint32_t ist : 4; /**< [ 3: 0](RO) Isochronous scheduling threshold. */
7852 uint32_t erst_max : 4; /**< [ 7: 4](RO) Event ring segment table maximum. */
7853 uint32_t reserved_8_20 : 13;
7854 uint32_t maxscratchpadbufs_h : 5; /**< [ 25: 21](RO) Maximum number of scratchpad buffers[9:5]. */
7855 uint32_t spr : 1; /**< [ 26: 26](RO) Scratchpad restore. */
7856 uint32_t maxscratchpadbufs_l : 5; /**< [ 31: 27](RO) Maximum number of scratchpad buffers[4:0]. */
7857 #endif /* Word 0 - End */
7858 } s;
7859 /* struct bdk_usbdrdx_uahc_hcsparams2_s cn; */
7860 };
7861 typedef union bdk_usbdrdx_uahc_hcsparams2 bdk_usbdrdx_uahc_hcsparams2_t;
7862
7863 static inline uint64_t BDK_USBDRDX_UAHC_HCSPARAMS2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_HCSPARAMS2(unsigned long a)7864 static inline uint64_t BDK_USBDRDX_UAHC_HCSPARAMS2(unsigned long a)
7865 {
7866 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
7867 return 0x868000000008ll + 0x1000000000ll * ((a) & 0x1);
7868 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
7869 return 0x868000000008ll + 0x1000000000ll * ((a) & 0x1);
7870 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
7871 return 0x868000000008ll + 0x1000000000ll * ((a) & 0x1);
7872 __bdk_csr_fatal("USBDRDX_UAHC_HCSPARAMS2", 1, a, 0, 0, 0);
7873 }
7874
7875 #define typedef_BDK_USBDRDX_UAHC_HCSPARAMS2(a) bdk_usbdrdx_uahc_hcsparams2_t
7876 #define bustype_BDK_USBDRDX_UAHC_HCSPARAMS2(a) BDK_CSR_TYPE_NCB32b
7877 #define basename_BDK_USBDRDX_UAHC_HCSPARAMS2(a) "USBDRDX_UAHC_HCSPARAMS2"
7878 #define device_bar_BDK_USBDRDX_UAHC_HCSPARAMS2(a) 0x0 /* PF_BAR0 */
7879 #define busnum_BDK_USBDRDX_UAHC_HCSPARAMS2(a) (a)
7880 #define arguments_BDK_USBDRDX_UAHC_HCSPARAMS2(a) (a),-1,-1,-1
7881
7882 /**
7883 * Register (NCB32b) usbdrd#_uahc_hcsparams3
7884 *
7885 * USB XHCI Controller Structural Parameters Register 3
7886 * For information on this register, refer to the xHCI Specification, v1.1, section 5.3.5.
7887 */
7888 union bdk_usbdrdx_uahc_hcsparams3
7889 {
7890 uint32_t u;
7891 struct bdk_usbdrdx_uahc_hcsparams3_s
7892 {
7893 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7894 uint32_t u2_device_exit_latency : 16;/**< [ 31: 16](RO) U2 device exit latency. */
7895 uint32_t reserved_8_15 : 8;
7896 uint32_t u1_device_exit_latency : 8; /**< [ 7: 0](RO) U1 device exit latency. */
7897 #else /* Word 0 - Little Endian */
7898 uint32_t u1_device_exit_latency : 8; /**< [ 7: 0](RO) U1 device exit latency. */
7899 uint32_t reserved_8_15 : 8;
7900 uint32_t u2_device_exit_latency : 16;/**< [ 31: 16](RO) U2 device exit latency. */
7901 #endif /* Word 0 - End */
7902 } s;
7903 /* struct bdk_usbdrdx_uahc_hcsparams3_s cn; */
7904 };
7905 typedef union bdk_usbdrdx_uahc_hcsparams3 bdk_usbdrdx_uahc_hcsparams3_t;
7906
7907 static inline uint64_t BDK_USBDRDX_UAHC_HCSPARAMS3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_HCSPARAMS3(unsigned long a)7908 static inline uint64_t BDK_USBDRDX_UAHC_HCSPARAMS3(unsigned long a)
7909 {
7910 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
7911 return 0x86800000000cll + 0x1000000000ll * ((a) & 0x1);
7912 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
7913 return 0x86800000000cll + 0x1000000000ll * ((a) & 0x1);
7914 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
7915 return 0x86800000000cll + 0x1000000000ll * ((a) & 0x1);
7916 __bdk_csr_fatal("USBDRDX_UAHC_HCSPARAMS3", 1, a, 0, 0, 0);
7917 }
7918
7919 #define typedef_BDK_USBDRDX_UAHC_HCSPARAMS3(a) bdk_usbdrdx_uahc_hcsparams3_t
7920 #define bustype_BDK_USBDRDX_UAHC_HCSPARAMS3(a) BDK_CSR_TYPE_NCB32b
7921 #define basename_BDK_USBDRDX_UAHC_HCSPARAMS3(a) "USBDRDX_UAHC_HCSPARAMS3"
7922 #define device_bar_BDK_USBDRDX_UAHC_HCSPARAMS3(a) 0x0 /* PF_BAR0 */
7923 #define busnum_BDK_USBDRDX_UAHC_HCSPARAMS3(a) (a)
7924 #define arguments_BDK_USBDRDX_UAHC_HCSPARAMS3(a) (a),-1,-1,-1
7925
7926 /**
7927 * Register (NCB32b) usbdrd#_uahc_iman#
7928 *
7929 * USB XHCI Interrupt Management Register
7930 * For information on this register, refer to the xHCI Specification, v1.1, section 5.5.2.1.
7931 *
7932 * This register can be reset by NCB reset,
7933 * or USBDRD()_UCTL_CTL[UAHC_RST],
7934 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
7935 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
7936 */
7937 union bdk_usbdrdx_uahc_imanx
7938 {
7939 uint32_t u;
7940 struct bdk_usbdrdx_uahc_imanx_s
7941 {
7942 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7943 uint32_t reserved_2_31 : 30;
7944 uint32_t ie : 1; /**< [ 1: 1](R/W) Interrupt enable. */
7945 uint32_t ip : 1; /**< [ 0: 0](R/W1C/H) Interrupt pending. */
7946 #else /* Word 0 - Little Endian */
7947 uint32_t ip : 1; /**< [ 0: 0](R/W1C/H) Interrupt pending. */
7948 uint32_t ie : 1; /**< [ 1: 1](R/W) Interrupt enable. */
7949 uint32_t reserved_2_31 : 30;
7950 #endif /* Word 0 - End */
7951 } s;
7952 /* struct bdk_usbdrdx_uahc_imanx_s cn; */
7953 };
7954 typedef union bdk_usbdrdx_uahc_imanx bdk_usbdrdx_uahc_imanx_t;
7955
7956 static inline uint64_t BDK_USBDRDX_UAHC_IMANX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_IMANX(unsigned long a,unsigned long b)7957 static inline uint64_t BDK_USBDRDX_UAHC_IMANX(unsigned long a, unsigned long b)
7958 {
7959 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
7960 return 0x868000000460ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
7961 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
7962 return 0x868000000460ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
7963 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
7964 return 0x868000000460ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
7965 __bdk_csr_fatal("USBDRDX_UAHC_IMANX", 2, a, b, 0, 0);
7966 }
7967
7968 #define typedef_BDK_USBDRDX_UAHC_IMANX(a,b) bdk_usbdrdx_uahc_imanx_t
7969 #define bustype_BDK_USBDRDX_UAHC_IMANX(a,b) BDK_CSR_TYPE_NCB32b
7970 #define basename_BDK_USBDRDX_UAHC_IMANX(a,b) "USBDRDX_UAHC_IMANX"
7971 #define device_bar_BDK_USBDRDX_UAHC_IMANX(a,b) 0x0 /* PF_BAR0 */
7972 #define busnum_BDK_USBDRDX_UAHC_IMANX(a,b) (a)
7973 #define arguments_BDK_USBDRDX_UAHC_IMANX(a,b) (a),(b),-1,-1
7974
7975 /**
7976 * Register (NCB32b) usbdrd#_uahc_imod#
7977 *
7978 * USB XHCI Interrupt Moderation Register
7979 * For information on this register, refer to the xHCI Specification, v1.1, section 5.5.2.2.
7980 *
7981 * This register can be reset by NCB reset,
7982 * or USBDRD()_UCTL_CTL[UAHC_RST],
7983 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
7984 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
7985 */
7986 union bdk_usbdrdx_uahc_imodx
7987 {
7988 uint32_t u;
7989 struct bdk_usbdrdx_uahc_imodx_s
7990 {
7991 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7992 uint32_t imodc : 16; /**< [ 31: 16](R/W) Interrupt moderation counter. */
7993 uint32_t imodi : 16; /**< [ 15: 0](R/W) Interrupt moderation interval. */
7994 #else /* Word 0 - Little Endian */
7995 uint32_t imodi : 16; /**< [ 15: 0](R/W) Interrupt moderation interval. */
7996 uint32_t imodc : 16; /**< [ 31: 16](R/W) Interrupt moderation counter. */
7997 #endif /* Word 0 - End */
7998 } s;
7999 /* struct bdk_usbdrdx_uahc_imodx_s cn; */
8000 };
8001 typedef union bdk_usbdrdx_uahc_imodx bdk_usbdrdx_uahc_imodx_t;
8002
8003 static inline uint64_t BDK_USBDRDX_UAHC_IMODX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_IMODX(unsigned long a,unsigned long b)8004 static inline uint64_t BDK_USBDRDX_UAHC_IMODX(unsigned long a, unsigned long b)
8005 {
8006 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
8007 return 0x868000000464ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
8008 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
8009 return 0x868000000464ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
8010 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
8011 return 0x868000000464ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
8012 __bdk_csr_fatal("USBDRDX_UAHC_IMODX", 2, a, b, 0, 0);
8013 }
8014
8015 #define typedef_BDK_USBDRDX_UAHC_IMODX(a,b) bdk_usbdrdx_uahc_imodx_t
8016 #define bustype_BDK_USBDRDX_UAHC_IMODX(a,b) BDK_CSR_TYPE_NCB32b
8017 #define basename_BDK_USBDRDX_UAHC_IMODX(a,b) "USBDRDX_UAHC_IMODX"
8018 #define device_bar_BDK_USBDRDX_UAHC_IMODX(a,b) 0x0 /* PF_BAR0 */
8019 #define busnum_BDK_USBDRDX_UAHC_IMODX(a,b) (a)
8020 #define arguments_BDK_USBDRDX_UAHC_IMODX(a,b) (a),(b),-1,-1
8021
8022 /**
8023 * Register (NCB32b) usbdrd#_uahc_mfindex
8024 *
8025 * USB XHCI Microframe Index Register
8026 * For information on this register, refer to the xHCI Specification, v1.1, section 5.5.1.
8027 *
8028 * This register can be reset by NCB reset,
8029 * or USBDRD()_UCTL_CTL[UAHC_RST],
8030 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
8031 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
8032 */
8033 union bdk_usbdrdx_uahc_mfindex
8034 {
8035 uint32_t u;
8036 struct bdk_usbdrdx_uahc_mfindex_s
8037 {
8038 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8039 uint32_t reserved_14_31 : 18;
8040 uint32_t mfindex : 14; /**< [ 13: 0](RO/H) Microframe index. */
8041 #else /* Word 0 - Little Endian */
8042 uint32_t mfindex : 14; /**< [ 13: 0](RO/H) Microframe index. */
8043 uint32_t reserved_14_31 : 18;
8044 #endif /* Word 0 - End */
8045 } s;
8046 /* struct bdk_usbdrdx_uahc_mfindex_s cn; */
8047 };
8048 typedef union bdk_usbdrdx_uahc_mfindex bdk_usbdrdx_uahc_mfindex_t;
8049
8050 static inline uint64_t BDK_USBDRDX_UAHC_MFINDEX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_MFINDEX(unsigned long a)8051 static inline uint64_t BDK_USBDRDX_UAHC_MFINDEX(unsigned long a)
8052 {
8053 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8054 return 0x868000000440ll + 0x1000000000ll * ((a) & 0x1);
8055 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8056 return 0x868000000440ll + 0x1000000000ll * ((a) & 0x1);
8057 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8058 return 0x868000000440ll + 0x1000000000ll * ((a) & 0x1);
8059 __bdk_csr_fatal("USBDRDX_UAHC_MFINDEX", 1, a, 0, 0, 0);
8060 }
8061
8062 #define typedef_BDK_USBDRDX_UAHC_MFINDEX(a) bdk_usbdrdx_uahc_mfindex_t
8063 #define bustype_BDK_USBDRDX_UAHC_MFINDEX(a) BDK_CSR_TYPE_NCB32b
8064 #define basename_BDK_USBDRDX_UAHC_MFINDEX(a) "USBDRDX_UAHC_MFINDEX"
8065 #define device_bar_BDK_USBDRDX_UAHC_MFINDEX(a) 0x0 /* PF_BAR0 */
8066 #define busnum_BDK_USBDRDX_UAHC_MFINDEX(a) (a)
8067 #define arguments_BDK_USBDRDX_UAHC_MFINDEX(a) (a),-1,-1,-1
8068
8069 /**
8070 * Register (NCB32b) usbdrd#_uahc_pagesize
8071 *
8072 * USB XHCI Page-Size Register
8073 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.3.
8074 */
8075 union bdk_usbdrdx_uahc_pagesize
8076 {
8077 uint32_t u;
8078 struct bdk_usbdrdx_uahc_pagesize_s
8079 {
8080 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8081 uint32_t reserved_16_31 : 16;
8082 uint32_t pagesize : 16; /**< [ 15: 0](RO) Page size. */
8083 #else /* Word 0 - Little Endian */
8084 uint32_t pagesize : 16; /**< [ 15: 0](RO) Page size. */
8085 uint32_t reserved_16_31 : 16;
8086 #endif /* Word 0 - End */
8087 } s;
8088 /* struct bdk_usbdrdx_uahc_pagesize_s cn; */
8089 };
8090 typedef union bdk_usbdrdx_uahc_pagesize bdk_usbdrdx_uahc_pagesize_t;
8091
8092 static inline uint64_t BDK_USBDRDX_UAHC_PAGESIZE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_PAGESIZE(unsigned long a)8093 static inline uint64_t BDK_USBDRDX_UAHC_PAGESIZE(unsigned long a)
8094 {
8095 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8096 return 0x868000000028ll + 0x1000000000ll * ((a) & 0x1);
8097 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8098 return 0x868000000028ll + 0x1000000000ll * ((a) & 0x1);
8099 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8100 return 0x868000000028ll + 0x1000000000ll * ((a) & 0x1);
8101 __bdk_csr_fatal("USBDRDX_UAHC_PAGESIZE", 1, a, 0, 0, 0);
8102 }
8103
8104 #define typedef_BDK_USBDRDX_UAHC_PAGESIZE(a) bdk_usbdrdx_uahc_pagesize_t
8105 #define bustype_BDK_USBDRDX_UAHC_PAGESIZE(a) BDK_CSR_TYPE_NCB32b
8106 #define basename_BDK_USBDRDX_UAHC_PAGESIZE(a) "USBDRDX_UAHC_PAGESIZE"
8107 #define device_bar_BDK_USBDRDX_UAHC_PAGESIZE(a) 0x0 /* PF_BAR0 */
8108 #define busnum_BDK_USBDRDX_UAHC_PAGESIZE(a) (a)
8109 #define arguments_BDK_USBDRDX_UAHC_PAGESIZE(a) (a),-1,-1,-1
8110
8111 /**
8112 * Register (NCB32b) usbdrd#_uahc_porthlpmc_20#
8113 *
8114 * USB XHCI Port Hardware LPM Control (High-Speed) Register
8115 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.11.2.
8116 *
8117 * This register can be reset by NCB reset,
8118 * or USBDRD()_UCTL_CTL[UAHC_RST],
8119 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
8120 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
8121 */
8122 union bdk_usbdrdx_uahc_porthlpmc_20x
8123 {
8124 uint32_t u;
8125 struct bdk_usbdrdx_uahc_porthlpmc_20x_s
8126 {
8127 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8128 uint32_t reserved_14_31 : 18;
8129 uint32_t hirdd : 4; /**< [ 13: 10](R/W) See section 5.4.11.2 of the XHCI Spec 1.1.
8130 If USBDRD()_UAHC_SUPTPRT2_DW2[BLC] = 0, then HIRD timing is applied to this field.
8131 If USBDRD()_UAHC_SUPTPRT2_DW2[BLC] = 1, then BESL timing is applied to this field. */
8132 uint32_t l1_timeout : 8; /**< [ 9: 2](R/W) Timeout value for the L1 inactivity timer (LPM timer). This field is set to 0x0 by the
8133 assertion of PR to 1. Refer to section 4.23.5.1.1.1 (in XHCI spec 1.1) for more
8134 information on L1 Timeout operation.
8135 The following are permissible values:
8136 0x0 = 128 us. (default).
8137 0x1 = 256 us.
8138 0x2 = 512 us.
8139 0x3 = 768 us.
8140 _ ...
8141 0xFF = 65280 us. */
8142 uint32_t hirdm : 2; /**< [ 1: 0](R/W) Host-initiated resume-duration mode. */
8143 #else /* Word 0 - Little Endian */
8144 uint32_t hirdm : 2; /**< [ 1: 0](R/W) Host-initiated resume-duration mode. */
8145 uint32_t l1_timeout : 8; /**< [ 9: 2](R/W) Timeout value for the L1 inactivity timer (LPM timer). This field is set to 0x0 by the
8146 assertion of PR to 1. Refer to section 4.23.5.1.1.1 (in XHCI spec 1.1) for more
8147 information on L1 Timeout operation.
8148 The following are permissible values:
8149 0x0 = 128 us. (default).
8150 0x1 = 256 us.
8151 0x2 = 512 us.
8152 0x3 = 768 us.
8153 _ ...
8154 0xFF = 65280 us. */
8155 uint32_t hirdd : 4; /**< [ 13: 10](R/W) See section 5.4.11.2 of the XHCI Spec 1.1.
8156 If USBDRD()_UAHC_SUPTPRT2_DW2[BLC] = 0, then HIRD timing is applied to this field.
8157 If USBDRD()_UAHC_SUPTPRT2_DW2[BLC] = 1, then BESL timing is applied to this field. */
8158 uint32_t reserved_14_31 : 18;
8159 #endif /* Word 0 - End */
8160 } s;
8161 /* struct bdk_usbdrdx_uahc_porthlpmc_20x_s cn; */
8162 };
8163 typedef union bdk_usbdrdx_uahc_porthlpmc_20x bdk_usbdrdx_uahc_porthlpmc_20x_t;
8164
8165 static inline uint64_t BDK_USBDRDX_UAHC_PORTHLPMC_20X(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_PORTHLPMC_20X(unsigned long a,unsigned long b)8166 static inline uint64_t BDK_USBDRDX_UAHC_PORTHLPMC_20X(unsigned long a, unsigned long b)
8167 {
8168 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
8169 return 0x86800000042cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8170 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
8171 return 0x86800000042cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8172 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
8173 return 0x86800000042cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8174 __bdk_csr_fatal("USBDRDX_UAHC_PORTHLPMC_20X", 2, a, b, 0, 0);
8175 }
8176
8177 #define typedef_BDK_USBDRDX_UAHC_PORTHLPMC_20X(a,b) bdk_usbdrdx_uahc_porthlpmc_20x_t
8178 #define bustype_BDK_USBDRDX_UAHC_PORTHLPMC_20X(a,b) BDK_CSR_TYPE_NCB32b
8179 #define basename_BDK_USBDRDX_UAHC_PORTHLPMC_20X(a,b) "USBDRDX_UAHC_PORTHLPMC_20X"
8180 #define device_bar_BDK_USBDRDX_UAHC_PORTHLPMC_20X(a,b) 0x0 /* PF_BAR0 */
8181 #define busnum_BDK_USBDRDX_UAHC_PORTHLPMC_20X(a,b) (a)
8182 #define arguments_BDK_USBDRDX_UAHC_PORTHLPMC_20X(a,b) (a),(b),-1,-1
8183
8184 /**
8185 * Register (NCB32b) usbdrd#_uahc_porthlpmc_ss#
8186 *
8187 * USB XHCI Port Hardware LPM Control (SuperSpeed) Register
8188 * The USB3 port hardware LPM control register is reserved and shall be treated as RsvdP by
8189 * software. See xHCI specification v1.1 section 5.4.11.1.
8190 *
8191 * This register can be reset by NCB reset,
8192 * or USBDRD()_UCTL_CTL[UAHC_RST],
8193 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
8194 * or USBDRD()_UAHC_USBCMD[HCRST].
8195 */
8196 union bdk_usbdrdx_uahc_porthlpmc_ssx
8197 {
8198 uint32_t u;
8199 struct bdk_usbdrdx_uahc_porthlpmc_ssx_s
8200 {
8201 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8202 uint32_t reserved_0_31 : 32;
8203 #else /* Word 0 - Little Endian */
8204 uint32_t reserved_0_31 : 32;
8205 #endif /* Word 0 - End */
8206 } s;
8207 /* struct bdk_usbdrdx_uahc_porthlpmc_ssx_s cn; */
8208 };
8209 typedef union bdk_usbdrdx_uahc_porthlpmc_ssx bdk_usbdrdx_uahc_porthlpmc_ssx_t;
8210
8211 static inline uint64_t BDK_USBDRDX_UAHC_PORTHLPMC_SSX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_PORTHLPMC_SSX(unsigned long a,unsigned long b)8212 static inline uint64_t BDK_USBDRDX_UAHC_PORTHLPMC_SSX(unsigned long a, unsigned long b)
8213 {
8214 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==1)))
8215 return 0x86800000042cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8216 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==1)))
8217 return 0x86800000042cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8218 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==1)))
8219 return 0x86800000042cll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8220 __bdk_csr_fatal("USBDRDX_UAHC_PORTHLPMC_SSX", 2, a, b, 0, 0);
8221 }
8222
8223 #define typedef_BDK_USBDRDX_UAHC_PORTHLPMC_SSX(a,b) bdk_usbdrdx_uahc_porthlpmc_ssx_t
8224 #define bustype_BDK_USBDRDX_UAHC_PORTHLPMC_SSX(a,b) BDK_CSR_TYPE_NCB32b
8225 #define basename_BDK_USBDRDX_UAHC_PORTHLPMC_SSX(a,b) "USBDRDX_UAHC_PORTHLPMC_SSX"
8226 #define device_bar_BDK_USBDRDX_UAHC_PORTHLPMC_SSX(a,b) 0x0 /* PF_BAR0 */
8227 #define busnum_BDK_USBDRDX_UAHC_PORTHLPMC_SSX(a,b) (a)
8228 #define arguments_BDK_USBDRDX_UAHC_PORTHLPMC_SSX(a,b) (a),(b),-1,-1
8229
8230 /**
8231 * Register (NCB32b) usbdrd#_uahc_portli_20#
8232 *
8233 * USB XHCI Port Link (High-Speed) Register
8234 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.10.
8235 */
8236 union bdk_usbdrdx_uahc_portli_20x
8237 {
8238 uint32_t u;
8239 struct bdk_usbdrdx_uahc_portli_20x_s
8240 {
8241 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8242 uint32_t reserved_0_31 : 32;
8243 #else /* Word 0 - Little Endian */
8244 uint32_t reserved_0_31 : 32;
8245 #endif /* Word 0 - End */
8246 } s;
8247 /* struct bdk_usbdrdx_uahc_portli_20x_s cn; */
8248 };
8249 typedef union bdk_usbdrdx_uahc_portli_20x bdk_usbdrdx_uahc_portli_20x_t;
8250
8251 static inline uint64_t BDK_USBDRDX_UAHC_PORTLI_20X(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_PORTLI_20X(unsigned long a,unsigned long b)8252 static inline uint64_t BDK_USBDRDX_UAHC_PORTLI_20X(unsigned long a, unsigned long b)
8253 {
8254 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
8255 return 0x868000000428ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8256 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
8257 return 0x868000000428ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8258 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
8259 return 0x868000000428ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8260 __bdk_csr_fatal("USBDRDX_UAHC_PORTLI_20X", 2, a, b, 0, 0);
8261 }
8262
8263 #define typedef_BDK_USBDRDX_UAHC_PORTLI_20X(a,b) bdk_usbdrdx_uahc_portli_20x_t
8264 #define bustype_BDK_USBDRDX_UAHC_PORTLI_20X(a,b) BDK_CSR_TYPE_NCB32b
8265 #define basename_BDK_USBDRDX_UAHC_PORTLI_20X(a,b) "USBDRDX_UAHC_PORTLI_20X"
8266 #define device_bar_BDK_USBDRDX_UAHC_PORTLI_20X(a,b) 0x0 /* PF_BAR0 */
8267 #define busnum_BDK_USBDRDX_UAHC_PORTLI_20X(a,b) (a)
8268 #define arguments_BDK_USBDRDX_UAHC_PORTLI_20X(a,b) (a),(b),-1,-1
8269
8270 /**
8271 * Register (NCB32b) usbdrd#_uahc_portli_ss#
8272 *
8273 * USB XHCI Port Link (SuperSpeed) Register
8274 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.10.
8275 */
8276 union bdk_usbdrdx_uahc_portli_ssx
8277 {
8278 uint32_t u;
8279 struct bdk_usbdrdx_uahc_portli_ssx_s
8280 {
8281 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8282 uint32_t reserved_16_31 : 16;
8283 uint32_t linkerrorcount : 16; /**< [ 15: 0](RO/H) Link error count. */
8284 #else /* Word 0 - Little Endian */
8285 uint32_t linkerrorcount : 16; /**< [ 15: 0](RO/H) Link error count. */
8286 uint32_t reserved_16_31 : 16;
8287 #endif /* Word 0 - End */
8288 } s;
8289 /* struct bdk_usbdrdx_uahc_portli_ssx_s cn; */
8290 };
8291 typedef union bdk_usbdrdx_uahc_portli_ssx bdk_usbdrdx_uahc_portli_ssx_t;
8292
8293 static inline uint64_t BDK_USBDRDX_UAHC_PORTLI_SSX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_PORTLI_SSX(unsigned long a,unsigned long b)8294 static inline uint64_t BDK_USBDRDX_UAHC_PORTLI_SSX(unsigned long a, unsigned long b)
8295 {
8296 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==1)))
8297 return 0x868000000428ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8298 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==1)))
8299 return 0x868000000428ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8300 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==1)))
8301 return 0x868000000428ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8302 __bdk_csr_fatal("USBDRDX_UAHC_PORTLI_SSX", 2, a, b, 0, 0);
8303 }
8304
8305 #define typedef_BDK_USBDRDX_UAHC_PORTLI_SSX(a,b) bdk_usbdrdx_uahc_portli_ssx_t
8306 #define bustype_BDK_USBDRDX_UAHC_PORTLI_SSX(a,b) BDK_CSR_TYPE_NCB32b
8307 #define basename_BDK_USBDRDX_UAHC_PORTLI_SSX(a,b) "USBDRDX_UAHC_PORTLI_SSX"
8308 #define device_bar_BDK_USBDRDX_UAHC_PORTLI_SSX(a,b) 0x0 /* PF_BAR0 */
8309 #define busnum_BDK_USBDRDX_UAHC_PORTLI_SSX(a,b) (a)
8310 #define arguments_BDK_USBDRDX_UAHC_PORTLI_SSX(a,b) (a),(b),-1,-1
8311
8312 /**
8313 * Register (NCB32b) usbdrd#_uahc_portpmsc_20#
8314 *
8315 * USB XHCI Port Power Management Status/Control (High-Speed) Register
8316 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.9.
8317 *
8318 * This register can be reset by NCB reset,
8319 * or USBDRD()_UCTL_CTL[UAHC_RST],
8320 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
8321 * or USBDRD()_UAHC_USBCMD[HCRST].
8322 */
8323 union bdk_usbdrdx_uahc_portpmsc_20x
8324 {
8325 uint32_t u;
8326 struct bdk_usbdrdx_uahc_portpmsc_20x_s
8327 {
8328 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8329 uint32_t port_test_control : 4; /**< [ 31: 28](R/W) Port test control. */
8330 uint32_t reserved_17_27 : 11;
8331 uint32_t hle : 1; /**< [ 16: 16](R/W) Hardware LPM enable. */
8332 uint32_t l1_device_slot : 8; /**< [ 15: 8](R/W) L1 device slot. */
8333 uint32_t hird : 4; /**< [ 7: 4](R/W) Host-initiated resume duration. */
8334 uint32_t rwe : 1; /**< [ 3: 3](R/W) Remove wake enable. */
8335 uint32_t l1s : 3; /**< [ 2: 0](RO/H) L1 status. */
8336 #else /* Word 0 - Little Endian */
8337 uint32_t l1s : 3; /**< [ 2: 0](RO/H) L1 status. */
8338 uint32_t rwe : 1; /**< [ 3: 3](R/W) Remove wake enable. */
8339 uint32_t hird : 4; /**< [ 7: 4](R/W) Host-initiated resume duration. */
8340 uint32_t l1_device_slot : 8; /**< [ 15: 8](R/W) L1 device slot. */
8341 uint32_t hle : 1; /**< [ 16: 16](R/W) Hardware LPM enable. */
8342 uint32_t reserved_17_27 : 11;
8343 uint32_t port_test_control : 4; /**< [ 31: 28](R/W) Port test control. */
8344 #endif /* Word 0 - End */
8345 } s;
8346 /* struct bdk_usbdrdx_uahc_portpmsc_20x_s cn; */
8347 };
8348 typedef union bdk_usbdrdx_uahc_portpmsc_20x bdk_usbdrdx_uahc_portpmsc_20x_t;
8349
8350 static inline uint64_t BDK_USBDRDX_UAHC_PORTPMSC_20X(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_PORTPMSC_20X(unsigned long a,unsigned long b)8351 static inline uint64_t BDK_USBDRDX_UAHC_PORTPMSC_20X(unsigned long a, unsigned long b)
8352 {
8353 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
8354 return 0x868000000424ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8355 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
8356 return 0x868000000424ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8357 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
8358 return 0x868000000424ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
8359 __bdk_csr_fatal("USBDRDX_UAHC_PORTPMSC_20X", 2, a, b, 0, 0);
8360 }
8361
8362 #define typedef_BDK_USBDRDX_UAHC_PORTPMSC_20X(a,b) bdk_usbdrdx_uahc_portpmsc_20x_t
8363 #define bustype_BDK_USBDRDX_UAHC_PORTPMSC_20X(a,b) BDK_CSR_TYPE_NCB32b
8364 #define basename_BDK_USBDRDX_UAHC_PORTPMSC_20X(a,b) "USBDRDX_UAHC_PORTPMSC_20X"
8365 #define device_bar_BDK_USBDRDX_UAHC_PORTPMSC_20X(a,b) 0x0 /* PF_BAR0 */
8366 #define busnum_BDK_USBDRDX_UAHC_PORTPMSC_20X(a,b) (a)
8367 #define arguments_BDK_USBDRDX_UAHC_PORTPMSC_20X(a,b) (a),(b),-1,-1
8368
8369 /**
8370 * Register (NCB32b) usbdrd#_uahc_portpmsc_ss#
8371 *
8372 * USB XHCI Port Power Management Status/Control (SuperSpeed) Register
8373 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.9.
8374 *
8375 * This register can be reset by NCB reset,
8376 * or USBDRD()_UCTL_CTL[UAHC_RST],
8377 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
8378 * or USBDRD()_UAHC_USBCMD[HCRST].
8379 */
8380 union bdk_usbdrdx_uahc_portpmsc_ssx
8381 {
8382 uint32_t u;
8383 struct bdk_usbdrdx_uahc_portpmsc_ssx_s
8384 {
8385 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8386 uint32_t reserved_17_31 : 15;
8387 uint32_t fla : 1; /**< [ 16: 16](R/W/H) Force link PM accept. */
8388 uint32_t u2_timeout : 8; /**< [ 15: 8](R/W/H) U2 timeout. */
8389 uint32_t u1_timeout : 8; /**< [ 7: 0](R/W/H) U1 timeout. */
8390 #else /* Word 0 - Little Endian */
8391 uint32_t u1_timeout : 8; /**< [ 7: 0](R/W/H) U1 timeout. */
8392 uint32_t u2_timeout : 8; /**< [ 15: 8](R/W/H) U2 timeout. */
8393 uint32_t fla : 1; /**< [ 16: 16](R/W/H) Force link PM accept. */
8394 uint32_t reserved_17_31 : 15;
8395 #endif /* Word 0 - End */
8396 } s;
8397 /* struct bdk_usbdrdx_uahc_portpmsc_ssx_s cn; */
8398 };
8399 typedef union bdk_usbdrdx_uahc_portpmsc_ssx bdk_usbdrdx_uahc_portpmsc_ssx_t;
8400
8401 static inline uint64_t BDK_USBDRDX_UAHC_PORTPMSC_SSX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_PORTPMSC_SSX(unsigned long a,unsigned long b)8402 static inline uint64_t BDK_USBDRDX_UAHC_PORTPMSC_SSX(unsigned long a, unsigned long b)
8403 {
8404 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==1)))
8405 return 0x868000000424ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8406 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==1)))
8407 return 0x868000000424ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8408 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==1)))
8409 return 0x868000000424ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8410 __bdk_csr_fatal("USBDRDX_UAHC_PORTPMSC_SSX", 2, a, b, 0, 0);
8411 }
8412
8413 #define typedef_BDK_USBDRDX_UAHC_PORTPMSC_SSX(a,b) bdk_usbdrdx_uahc_portpmsc_ssx_t
8414 #define bustype_BDK_USBDRDX_UAHC_PORTPMSC_SSX(a,b) BDK_CSR_TYPE_NCB32b
8415 #define basename_BDK_USBDRDX_UAHC_PORTPMSC_SSX(a,b) "USBDRDX_UAHC_PORTPMSC_SSX"
8416 #define device_bar_BDK_USBDRDX_UAHC_PORTPMSC_SSX(a,b) 0x0 /* PF_BAR0 */
8417 #define busnum_BDK_USBDRDX_UAHC_PORTPMSC_SSX(a,b) (a)
8418 #define arguments_BDK_USBDRDX_UAHC_PORTPMSC_SSX(a,b) (a),(b),-1,-1
8419
8420 /**
8421 * Register (NCB32b) usbdrd#_uahc_portsc#
8422 *
8423 * USB XHCI Port Status and Control Registers
8424 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.8. Port 1
8425 * is USB3.0 SuperSpeed link, Port 0 is USB2.0 high-speed/full-speed/low-speed link.
8426 *
8427 * This register can be reset by NCB reset,
8428 * or USBDRD()_UCTL_CTL[UAHC_RST],
8429 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
8430 * or USBDRD()_UAHC_USBCMD[HCRST].
8431 */
8432 union bdk_usbdrdx_uahc_portscx
8433 {
8434 uint32_t u;
8435 struct bdk_usbdrdx_uahc_portscx_s
8436 {
8437 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8438 uint32_t wpr : 1; /**< [ 31: 31](WO) Warm port reset. */
8439 uint32_t dr : 1; /**< [ 30: 30](RO/H) Device removable. */
8440 uint32_t reserved_28_29 : 2;
8441 uint32_t woe : 1; /**< [ 27: 27](R/W) Wake on overcurrent enable. */
8442 uint32_t wde : 1; /**< [ 26: 26](R/W) Wake on disconnect enable. */
8443 uint32_t wce : 1; /**< [ 25: 25](R/W) Wake on connect enable. */
8444 uint32_t cas : 1; /**< [ 24: 24](RO/H) Cold attach status. */
8445 uint32_t cec : 1; /**< [ 23: 23](R/W1C/H) Port configuration error change. */
8446 uint32_t plc : 1; /**< [ 22: 22](R/W1C/H) Port link state change. */
8447 uint32_t prc : 1; /**< [ 21: 21](R/W1C/H) Port reset change. */
8448 uint32_t occ : 1; /**< [ 20: 20](R/W1C/H) Overcurrent change. */
8449 uint32_t wrc : 1; /**< [ 19: 19](R/W1C/H) Warm port reset change. */
8450 uint32_t pec : 1; /**< [ 18: 18](R/W1C/H) Port enabled/disabled change. */
8451 uint32_t csc : 1; /**< [ 17: 17](R/W1C/H) Connect status change. */
8452 uint32_t lws : 1; /**< [ 16: 16](WO) Port link state write strobe. */
8453 uint32_t pic : 2; /**< [ 15: 14](R/W/H) Port indicator control. */
8454 uint32_t portspeed : 4; /**< [ 13: 10](RO/H) Port speed. */
8455 uint32_t pp : 1; /**< [ 9: 9](R/W/H) Port power. */
8456 uint32_t pls : 4; /**< [ 8: 5](R/W/H) Port link state. */
8457 uint32_t pr : 1; /**< [ 4: 4](R/W1S/H) Port reset. */
8458 uint32_t oca : 1; /**< [ 3: 3](RO/H) Overcurrent active. */
8459 uint32_t reserved_2 : 1;
8460 uint32_t ped : 1; /**< [ 1: 1](R/W1C/H) Port enabled/disabled. */
8461 uint32_t ccs : 1; /**< [ 0: 0](RO/H) Current connect status. */
8462 #else /* Word 0 - Little Endian */
8463 uint32_t ccs : 1; /**< [ 0: 0](RO/H) Current connect status. */
8464 uint32_t ped : 1; /**< [ 1: 1](R/W1C/H) Port enabled/disabled. */
8465 uint32_t reserved_2 : 1;
8466 uint32_t oca : 1; /**< [ 3: 3](RO/H) Overcurrent active. */
8467 uint32_t pr : 1; /**< [ 4: 4](R/W1S/H) Port reset. */
8468 uint32_t pls : 4; /**< [ 8: 5](R/W/H) Port link state. */
8469 uint32_t pp : 1; /**< [ 9: 9](R/W/H) Port power. */
8470 uint32_t portspeed : 4; /**< [ 13: 10](RO/H) Port speed. */
8471 uint32_t pic : 2; /**< [ 15: 14](R/W/H) Port indicator control. */
8472 uint32_t lws : 1; /**< [ 16: 16](WO) Port link state write strobe. */
8473 uint32_t csc : 1; /**< [ 17: 17](R/W1C/H) Connect status change. */
8474 uint32_t pec : 1; /**< [ 18: 18](R/W1C/H) Port enabled/disabled change. */
8475 uint32_t wrc : 1; /**< [ 19: 19](R/W1C/H) Warm port reset change. */
8476 uint32_t occ : 1; /**< [ 20: 20](R/W1C/H) Overcurrent change. */
8477 uint32_t prc : 1; /**< [ 21: 21](R/W1C/H) Port reset change. */
8478 uint32_t plc : 1; /**< [ 22: 22](R/W1C/H) Port link state change. */
8479 uint32_t cec : 1; /**< [ 23: 23](R/W1C/H) Port configuration error change. */
8480 uint32_t cas : 1; /**< [ 24: 24](RO/H) Cold attach status. */
8481 uint32_t wce : 1; /**< [ 25: 25](R/W) Wake on connect enable. */
8482 uint32_t wde : 1; /**< [ 26: 26](R/W) Wake on disconnect enable. */
8483 uint32_t woe : 1; /**< [ 27: 27](R/W) Wake on overcurrent enable. */
8484 uint32_t reserved_28_29 : 2;
8485 uint32_t dr : 1; /**< [ 30: 30](RO/H) Device removable. */
8486 uint32_t wpr : 1; /**< [ 31: 31](WO) Warm port reset. */
8487 #endif /* Word 0 - End */
8488 } s;
8489 /* struct bdk_usbdrdx_uahc_portscx_s cn; */
8490 };
8491 typedef union bdk_usbdrdx_uahc_portscx bdk_usbdrdx_uahc_portscx_t;
8492
8493 static inline uint64_t BDK_USBDRDX_UAHC_PORTSCX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_PORTSCX(unsigned long a,unsigned long b)8494 static inline uint64_t BDK_USBDRDX_UAHC_PORTSCX(unsigned long a, unsigned long b)
8495 {
8496 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=1)))
8497 return 0x868000000420ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8498 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=1)))
8499 return 0x868000000420ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8500 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b<=1)))
8501 return 0x868000000420ll + 0x1000000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
8502 __bdk_csr_fatal("USBDRDX_UAHC_PORTSCX", 2, a, b, 0, 0);
8503 }
8504
8505 #define typedef_BDK_USBDRDX_UAHC_PORTSCX(a,b) bdk_usbdrdx_uahc_portscx_t
8506 #define bustype_BDK_USBDRDX_UAHC_PORTSCX(a,b) BDK_CSR_TYPE_NCB32b
8507 #define basename_BDK_USBDRDX_UAHC_PORTSCX(a,b) "USBDRDX_UAHC_PORTSCX"
8508 #define device_bar_BDK_USBDRDX_UAHC_PORTSCX(a,b) 0x0 /* PF_BAR0 */
8509 #define busnum_BDK_USBDRDX_UAHC_PORTSCX(a,b) (a)
8510 #define arguments_BDK_USBDRDX_UAHC_PORTSCX(a,b) (a),(b),-1,-1
8511
8512 /**
8513 * Register (NCB32b) usbdrd#_uahc_rtsoff
8514 *
8515 * USB XHCI Runtime Register-Space Offset Register
8516 * This register defines the offset of the xHCI runtime registers from the base. For information
8517 * on this register, refer to the xHCI Specification, v1.1, section 5.3.8.
8518 */
8519 union bdk_usbdrdx_uahc_rtsoff
8520 {
8521 uint32_t u;
8522 struct bdk_usbdrdx_uahc_rtsoff_s
8523 {
8524 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8525 uint32_t rtsoff : 27; /**< [ 31: 5](RO) Runtime register-space offset. */
8526 uint32_t reserved_0_4 : 5;
8527 #else /* Word 0 - Little Endian */
8528 uint32_t reserved_0_4 : 5;
8529 uint32_t rtsoff : 27; /**< [ 31: 5](RO) Runtime register-space offset. */
8530 #endif /* Word 0 - End */
8531 } s;
8532 /* struct bdk_usbdrdx_uahc_rtsoff_s cn; */
8533 };
8534 typedef union bdk_usbdrdx_uahc_rtsoff bdk_usbdrdx_uahc_rtsoff_t;
8535
8536 static inline uint64_t BDK_USBDRDX_UAHC_RTSOFF(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_RTSOFF(unsigned long a)8537 static inline uint64_t BDK_USBDRDX_UAHC_RTSOFF(unsigned long a)
8538 {
8539 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8540 return 0x868000000018ll + 0x1000000000ll * ((a) & 0x1);
8541 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8542 return 0x868000000018ll + 0x1000000000ll * ((a) & 0x1);
8543 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8544 return 0x868000000018ll + 0x1000000000ll * ((a) & 0x1);
8545 __bdk_csr_fatal("USBDRDX_UAHC_RTSOFF", 1, a, 0, 0, 0);
8546 }
8547
8548 #define typedef_BDK_USBDRDX_UAHC_RTSOFF(a) bdk_usbdrdx_uahc_rtsoff_t
8549 #define bustype_BDK_USBDRDX_UAHC_RTSOFF(a) BDK_CSR_TYPE_NCB32b
8550 #define basename_BDK_USBDRDX_UAHC_RTSOFF(a) "USBDRDX_UAHC_RTSOFF"
8551 #define device_bar_BDK_USBDRDX_UAHC_RTSOFF(a) 0x0 /* PF_BAR0 */
8552 #define busnum_BDK_USBDRDX_UAHC_RTSOFF(a) (a)
8553 #define arguments_BDK_USBDRDX_UAHC_RTSOFF(a) (a),-1,-1,-1
8554
8555 /**
8556 * Register (NCB32b) usbdrd#_uahc_suptprt2_dw0
8557 *
8558 * USB XHCI Supported-Protocol-Capability (USB 2.0) Register 0
8559 * For information on this register, refer to the xHCI Specification, v1.1, section 7.2.
8560 */
8561 union bdk_usbdrdx_uahc_suptprt2_dw0
8562 {
8563 uint32_t u;
8564 struct bdk_usbdrdx_uahc_suptprt2_dw0_s
8565 {
8566 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8567 uint32_t majorrev : 8; /**< [ 31: 24](RO) Major revision. */
8568 uint32_t minorrev : 8; /**< [ 23: 16](RO) Minor revision. */
8569 uint32_t nextcapptr : 8; /**< [ 15: 8](RO) Next capability pointer. */
8570 uint32_t capid : 8; /**< [ 7: 0](RO) Capability ID = supported protocol. */
8571 #else /* Word 0 - Little Endian */
8572 uint32_t capid : 8; /**< [ 7: 0](RO) Capability ID = supported protocol. */
8573 uint32_t nextcapptr : 8; /**< [ 15: 8](RO) Next capability pointer. */
8574 uint32_t minorrev : 8; /**< [ 23: 16](RO) Minor revision. */
8575 uint32_t majorrev : 8; /**< [ 31: 24](RO) Major revision. */
8576 #endif /* Word 0 - End */
8577 } s;
8578 /* struct bdk_usbdrdx_uahc_suptprt2_dw0_s cn; */
8579 };
8580 typedef union bdk_usbdrdx_uahc_suptprt2_dw0 bdk_usbdrdx_uahc_suptprt2_dw0_t;
8581
8582 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT2_DW0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_SUPTPRT2_DW0(unsigned long a)8583 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT2_DW0(unsigned long a)
8584 {
8585 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8586 return 0x868000000890ll + 0x1000000000ll * ((a) & 0x1);
8587 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8588 return 0x868000000890ll + 0x1000000000ll * ((a) & 0x1);
8589 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8590 return 0x868000000890ll + 0x1000000000ll * ((a) & 0x1);
8591 __bdk_csr_fatal("USBDRDX_UAHC_SUPTPRT2_DW0", 1, a, 0, 0, 0);
8592 }
8593
8594 #define typedef_BDK_USBDRDX_UAHC_SUPTPRT2_DW0(a) bdk_usbdrdx_uahc_suptprt2_dw0_t
8595 #define bustype_BDK_USBDRDX_UAHC_SUPTPRT2_DW0(a) BDK_CSR_TYPE_NCB32b
8596 #define basename_BDK_USBDRDX_UAHC_SUPTPRT2_DW0(a) "USBDRDX_UAHC_SUPTPRT2_DW0"
8597 #define device_bar_BDK_USBDRDX_UAHC_SUPTPRT2_DW0(a) 0x0 /* PF_BAR0 */
8598 #define busnum_BDK_USBDRDX_UAHC_SUPTPRT2_DW0(a) (a)
8599 #define arguments_BDK_USBDRDX_UAHC_SUPTPRT2_DW0(a) (a),-1,-1,-1
8600
8601 /**
8602 * Register (NCB32b) usbdrd#_uahc_suptprt2_dw1
8603 *
8604 * USB XHCI Supported-Protocol-Capability (USB 2.0) Register 1
8605 * For information on this register, refer to the xHCI Specification, v1.1, section 7.2.
8606 */
8607 union bdk_usbdrdx_uahc_suptprt2_dw1
8608 {
8609 uint32_t u;
8610 struct bdk_usbdrdx_uahc_suptprt2_dw1_s
8611 {
8612 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8613 uint32_t name : 32; /**< [ 31: 0](RO) Name string: 'USB'. */
8614 #else /* Word 0 - Little Endian */
8615 uint32_t name : 32; /**< [ 31: 0](RO) Name string: 'USB'. */
8616 #endif /* Word 0 - End */
8617 } s;
8618 /* struct bdk_usbdrdx_uahc_suptprt2_dw1_s cn; */
8619 };
8620 typedef union bdk_usbdrdx_uahc_suptprt2_dw1 bdk_usbdrdx_uahc_suptprt2_dw1_t;
8621
8622 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT2_DW1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_SUPTPRT2_DW1(unsigned long a)8623 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT2_DW1(unsigned long a)
8624 {
8625 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8626 return 0x868000000894ll + 0x1000000000ll * ((a) & 0x1);
8627 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8628 return 0x868000000894ll + 0x1000000000ll * ((a) & 0x1);
8629 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8630 return 0x868000000894ll + 0x1000000000ll * ((a) & 0x1);
8631 __bdk_csr_fatal("USBDRDX_UAHC_SUPTPRT2_DW1", 1, a, 0, 0, 0);
8632 }
8633
8634 #define typedef_BDK_USBDRDX_UAHC_SUPTPRT2_DW1(a) bdk_usbdrdx_uahc_suptprt2_dw1_t
8635 #define bustype_BDK_USBDRDX_UAHC_SUPTPRT2_DW1(a) BDK_CSR_TYPE_NCB32b
8636 #define basename_BDK_USBDRDX_UAHC_SUPTPRT2_DW1(a) "USBDRDX_UAHC_SUPTPRT2_DW1"
8637 #define device_bar_BDK_USBDRDX_UAHC_SUPTPRT2_DW1(a) 0x0 /* PF_BAR0 */
8638 #define busnum_BDK_USBDRDX_UAHC_SUPTPRT2_DW1(a) (a)
8639 #define arguments_BDK_USBDRDX_UAHC_SUPTPRT2_DW1(a) (a),-1,-1,-1
8640
8641 /**
8642 * Register (NCB32b) usbdrd#_uahc_suptprt2_dw2
8643 *
8644 * USB XHCI Supported-Protocol-Capability (USB 2.0) Register 2
8645 * For information on this register, refer to the xHCI Specification, v1.1, section 7.2.
8646 */
8647 union bdk_usbdrdx_uahc_suptprt2_dw2
8648 {
8649 uint32_t u;
8650 struct bdk_usbdrdx_uahc_suptprt2_dw2_s
8651 {
8652 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8653 uint32_t psic : 4; /**< [ 31: 28](RO) Protocol speed ID count. */
8654 uint32_t reserved_21_27 : 7;
8655 uint32_t blc : 1; /**< [ 20: 20](RO) BESL LPM capability. */
8656 uint32_t hlc : 1; /**< [ 19: 19](RO) Hardware LMP capability. */
8657 uint32_t ihi : 1; /**< [ 18: 18](RO) Integrated hub implemented. */
8658 uint32_t hso : 1; /**< [ 17: 17](RO) High-speed only. */
8659 uint32_t reserved_16 : 1;
8660 uint32_t compatprtcnt : 8; /**< [ 15: 8](RO) Compatible port count. */
8661 uint32_t compatprtoff : 8; /**< [ 7: 0](RO) Compatible port offset. */
8662 #else /* Word 0 - Little Endian */
8663 uint32_t compatprtoff : 8; /**< [ 7: 0](RO) Compatible port offset. */
8664 uint32_t compatprtcnt : 8; /**< [ 15: 8](RO) Compatible port count. */
8665 uint32_t reserved_16 : 1;
8666 uint32_t hso : 1; /**< [ 17: 17](RO) High-speed only. */
8667 uint32_t ihi : 1; /**< [ 18: 18](RO) Integrated hub implemented. */
8668 uint32_t hlc : 1; /**< [ 19: 19](RO) Hardware LMP capability. */
8669 uint32_t blc : 1; /**< [ 20: 20](RO) BESL LPM capability. */
8670 uint32_t reserved_21_27 : 7;
8671 uint32_t psic : 4; /**< [ 31: 28](RO) Protocol speed ID count. */
8672 #endif /* Word 0 - End */
8673 } s;
8674 /* struct bdk_usbdrdx_uahc_suptprt2_dw2_s cn; */
8675 };
8676 typedef union bdk_usbdrdx_uahc_suptprt2_dw2 bdk_usbdrdx_uahc_suptprt2_dw2_t;
8677
8678 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT2_DW2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_SUPTPRT2_DW2(unsigned long a)8679 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT2_DW2(unsigned long a)
8680 {
8681 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8682 return 0x868000000898ll + 0x1000000000ll * ((a) & 0x1);
8683 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8684 return 0x868000000898ll + 0x1000000000ll * ((a) & 0x1);
8685 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8686 return 0x868000000898ll + 0x1000000000ll * ((a) & 0x1);
8687 __bdk_csr_fatal("USBDRDX_UAHC_SUPTPRT2_DW2", 1, a, 0, 0, 0);
8688 }
8689
8690 #define typedef_BDK_USBDRDX_UAHC_SUPTPRT2_DW2(a) bdk_usbdrdx_uahc_suptprt2_dw2_t
8691 #define bustype_BDK_USBDRDX_UAHC_SUPTPRT2_DW2(a) BDK_CSR_TYPE_NCB32b
8692 #define basename_BDK_USBDRDX_UAHC_SUPTPRT2_DW2(a) "USBDRDX_UAHC_SUPTPRT2_DW2"
8693 #define device_bar_BDK_USBDRDX_UAHC_SUPTPRT2_DW2(a) 0x0 /* PF_BAR0 */
8694 #define busnum_BDK_USBDRDX_UAHC_SUPTPRT2_DW2(a) (a)
8695 #define arguments_BDK_USBDRDX_UAHC_SUPTPRT2_DW2(a) (a),-1,-1,-1
8696
8697 /**
8698 * Register (NCB32b) usbdrd#_uahc_suptprt2_dw3
8699 *
8700 * USB XHCI Supported-Protocol-Capability (USB 2.0) Register 3
8701 * For information on this register, refer to the xHCI Specification, v1.1, section 7.2.
8702 */
8703 union bdk_usbdrdx_uahc_suptprt2_dw3
8704 {
8705 uint32_t u;
8706 struct bdk_usbdrdx_uahc_suptprt2_dw3_s
8707 {
8708 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8709 uint32_t reserved_5_31 : 27;
8710 uint32_t protslottype : 5; /**< [ 4: 0](RO) Protocol slot type. */
8711 #else /* Word 0 - Little Endian */
8712 uint32_t protslottype : 5; /**< [ 4: 0](RO) Protocol slot type. */
8713 uint32_t reserved_5_31 : 27;
8714 #endif /* Word 0 - End */
8715 } s;
8716 /* struct bdk_usbdrdx_uahc_suptprt2_dw3_s cn; */
8717 };
8718 typedef union bdk_usbdrdx_uahc_suptprt2_dw3 bdk_usbdrdx_uahc_suptprt2_dw3_t;
8719
8720 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT2_DW3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_SUPTPRT2_DW3(unsigned long a)8721 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT2_DW3(unsigned long a)
8722 {
8723 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8724 return 0x86800000089cll + 0x1000000000ll * ((a) & 0x1);
8725 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8726 return 0x86800000089cll + 0x1000000000ll * ((a) & 0x1);
8727 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8728 return 0x86800000089cll + 0x1000000000ll * ((a) & 0x1);
8729 __bdk_csr_fatal("USBDRDX_UAHC_SUPTPRT2_DW3", 1, a, 0, 0, 0);
8730 }
8731
8732 #define typedef_BDK_USBDRDX_UAHC_SUPTPRT2_DW3(a) bdk_usbdrdx_uahc_suptprt2_dw3_t
8733 #define bustype_BDK_USBDRDX_UAHC_SUPTPRT2_DW3(a) BDK_CSR_TYPE_NCB32b
8734 #define basename_BDK_USBDRDX_UAHC_SUPTPRT2_DW3(a) "USBDRDX_UAHC_SUPTPRT2_DW3"
8735 #define device_bar_BDK_USBDRDX_UAHC_SUPTPRT2_DW3(a) 0x0 /* PF_BAR0 */
8736 #define busnum_BDK_USBDRDX_UAHC_SUPTPRT2_DW3(a) (a)
8737 #define arguments_BDK_USBDRDX_UAHC_SUPTPRT2_DW3(a) (a),-1,-1,-1
8738
8739 /**
8740 * Register (NCB32b) usbdrd#_uahc_suptprt3_dw0
8741 *
8742 * USB XHCI Supported-Protocol-Capability (USB 3.0) Register 0
8743 * For information on this register, refer to the xHCI Specification, v1.1, section 7.2.
8744 */
8745 union bdk_usbdrdx_uahc_suptprt3_dw0
8746 {
8747 uint32_t u;
8748 struct bdk_usbdrdx_uahc_suptprt3_dw0_s
8749 {
8750 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8751 uint32_t majorrev : 8; /**< [ 31: 24](RO) Major revision. */
8752 uint32_t minorrev : 8; /**< [ 23: 16](RO) Minor revision. */
8753 uint32_t nextcapptr : 8; /**< [ 15: 8](RO/H) Next capability pointer. Value depends on USBDRD()_UAHC_GUCTL[EXTCAPSUPTEN]. If
8754 EXTCAPSUPTEN
8755 =
8756 0, value is 0x0. If EXTCAPSUPTEN = 1, value is 0x4. */
8757 uint32_t capid : 8; /**< [ 7: 0](RO) Capability ID = supported protocol. */
8758 #else /* Word 0 - Little Endian */
8759 uint32_t capid : 8; /**< [ 7: 0](RO) Capability ID = supported protocol. */
8760 uint32_t nextcapptr : 8; /**< [ 15: 8](RO/H) Next capability pointer. Value depends on USBDRD()_UAHC_GUCTL[EXTCAPSUPTEN]. If
8761 EXTCAPSUPTEN
8762 =
8763 0, value is 0x0. If EXTCAPSUPTEN = 1, value is 0x4. */
8764 uint32_t minorrev : 8; /**< [ 23: 16](RO) Minor revision. */
8765 uint32_t majorrev : 8; /**< [ 31: 24](RO) Major revision. */
8766 #endif /* Word 0 - End */
8767 } s;
8768 /* struct bdk_usbdrdx_uahc_suptprt3_dw0_s cn; */
8769 };
8770 typedef union bdk_usbdrdx_uahc_suptprt3_dw0 bdk_usbdrdx_uahc_suptprt3_dw0_t;
8771
8772 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT3_DW0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_SUPTPRT3_DW0(unsigned long a)8773 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT3_DW0(unsigned long a)
8774 {
8775 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8776 return 0x8680000008a0ll + 0x1000000000ll * ((a) & 0x1);
8777 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8778 return 0x8680000008a0ll + 0x1000000000ll * ((a) & 0x1);
8779 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8780 return 0x8680000008a0ll + 0x1000000000ll * ((a) & 0x1);
8781 __bdk_csr_fatal("USBDRDX_UAHC_SUPTPRT3_DW0", 1, a, 0, 0, 0);
8782 }
8783
8784 #define typedef_BDK_USBDRDX_UAHC_SUPTPRT3_DW0(a) bdk_usbdrdx_uahc_suptprt3_dw0_t
8785 #define bustype_BDK_USBDRDX_UAHC_SUPTPRT3_DW0(a) BDK_CSR_TYPE_NCB32b
8786 #define basename_BDK_USBDRDX_UAHC_SUPTPRT3_DW0(a) "USBDRDX_UAHC_SUPTPRT3_DW0"
8787 #define device_bar_BDK_USBDRDX_UAHC_SUPTPRT3_DW0(a) 0x0 /* PF_BAR0 */
8788 #define busnum_BDK_USBDRDX_UAHC_SUPTPRT3_DW0(a) (a)
8789 #define arguments_BDK_USBDRDX_UAHC_SUPTPRT3_DW0(a) (a),-1,-1,-1
8790
8791 /**
8792 * Register (NCB32b) usbdrd#_uahc_suptprt3_dw1
8793 *
8794 * USB XHCI Supported-Protocol-Capability (USB 3.0) Register 1
8795 * For information on this register, refer to the xHCI Specification, v1.1, section 7.2.
8796 */
8797 union bdk_usbdrdx_uahc_suptprt3_dw1
8798 {
8799 uint32_t u;
8800 struct bdk_usbdrdx_uahc_suptprt3_dw1_s
8801 {
8802 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8803 uint32_t name : 32; /**< [ 31: 0](RO) Name string: 'USB'. */
8804 #else /* Word 0 - Little Endian */
8805 uint32_t name : 32; /**< [ 31: 0](RO) Name string: 'USB'. */
8806 #endif /* Word 0 - End */
8807 } s;
8808 /* struct bdk_usbdrdx_uahc_suptprt3_dw1_s cn; */
8809 };
8810 typedef union bdk_usbdrdx_uahc_suptprt3_dw1 bdk_usbdrdx_uahc_suptprt3_dw1_t;
8811
8812 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT3_DW1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_SUPTPRT3_DW1(unsigned long a)8813 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT3_DW1(unsigned long a)
8814 {
8815 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8816 return 0x8680000008a4ll + 0x1000000000ll * ((a) & 0x1);
8817 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8818 return 0x8680000008a4ll + 0x1000000000ll * ((a) & 0x1);
8819 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8820 return 0x8680000008a4ll + 0x1000000000ll * ((a) & 0x1);
8821 __bdk_csr_fatal("USBDRDX_UAHC_SUPTPRT3_DW1", 1, a, 0, 0, 0);
8822 }
8823
8824 #define typedef_BDK_USBDRDX_UAHC_SUPTPRT3_DW1(a) bdk_usbdrdx_uahc_suptprt3_dw1_t
8825 #define bustype_BDK_USBDRDX_UAHC_SUPTPRT3_DW1(a) BDK_CSR_TYPE_NCB32b
8826 #define basename_BDK_USBDRDX_UAHC_SUPTPRT3_DW1(a) "USBDRDX_UAHC_SUPTPRT3_DW1"
8827 #define device_bar_BDK_USBDRDX_UAHC_SUPTPRT3_DW1(a) 0x0 /* PF_BAR0 */
8828 #define busnum_BDK_USBDRDX_UAHC_SUPTPRT3_DW1(a) (a)
8829 #define arguments_BDK_USBDRDX_UAHC_SUPTPRT3_DW1(a) (a),-1,-1,-1
8830
8831 /**
8832 * Register (NCB32b) usbdrd#_uahc_suptprt3_dw2
8833 *
8834 * USB XHCI Supported-Protocol-Capability (USB 3.0) Register 2
8835 * For information on this register, refer to the xHCI Specification, v1.1, section 7.2.
8836 */
8837 union bdk_usbdrdx_uahc_suptprt3_dw2
8838 {
8839 uint32_t u;
8840 struct bdk_usbdrdx_uahc_suptprt3_dw2_s
8841 {
8842 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8843 uint32_t psic : 4; /**< [ 31: 28](RO) Protocol speed ID count. */
8844 uint32_t reserved_16_27 : 12;
8845 uint32_t compatprtcnt : 8; /**< [ 15: 8](RO) Compatible port count. */
8846 uint32_t compatprtoff : 8; /**< [ 7: 0](RO) Compatible port offset. */
8847 #else /* Word 0 - Little Endian */
8848 uint32_t compatprtoff : 8; /**< [ 7: 0](RO) Compatible port offset. */
8849 uint32_t compatprtcnt : 8; /**< [ 15: 8](RO) Compatible port count. */
8850 uint32_t reserved_16_27 : 12;
8851 uint32_t psic : 4; /**< [ 31: 28](RO) Protocol speed ID count. */
8852 #endif /* Word 0 - End */
8853 } s;
8854 /* struct bdk_usbdrdx_uahc_suptprt3_dw2_s cn; */
8855 };
8856 typedef union bdk_usbdrdx_uahc_suptprt3_dw2 bdk_usbdrdx_uahc_suptprt3_dw2_t;
8857
8858 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT3_DW2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_SUPTPRT3_DW2(unsigned long a)8859 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT3_DW2(unsigned long a)
8860 {
8861 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8862 return 0x8680000008a8ll + 0x1000000000ll * ((a) & 0x1);
8863 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8864 return 0x8680000008a8ll + 0x1000000000ll * ((a) & 0x1);
8865 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8866 return 0x8680000008a8ll + 0x1000000000ll * ((a) & 0x1);
8867 __bdk_csr_fatal("USBDRDX_UAHC_SUPTPRT3_DW2", 1, a, 0, 0, 0);
8868 }
8869
8870 #define typedef_BDK_USBDRDX_UAHC_SUPTPRT3_DW2(a) bdk_usbdrdx_uahc_suptprt3_dw2_t
8871 #define bustype_BDK_USBDRDX_UAHC_SUPTPRT3_DW2(a) BDK_CSR_TYPE_NCB32b
8872 #define basename_BDK_USBDRDX_UAHC_SUPTPRT3_DW2(a) "USBDRDX_UAHC_SUPTPRT3_DW2"
8873 #define device_bar_BDK_USBDRDX_UAHC_SUPTPRT3_DW2(a) 0x0 /* PF_BAR0 */
8874 #define busnum_BDK_USBDRDX_UAHC_SUPTPRT3_DW2(a) (a)
8875 #define arguments_BDK_USBDRDX_UAHC_SUPTPRT3_DW2(a) (a),-1,-1,-1
8876
8877 /**
8878 * Register (NCB32b) usbdrd#_uahc_suptprt3_dw3
8879 *
8880 * USB XHCI Supported-Protocol-Capability (USB 3.0) Register 3
8881 * For information on this register, refer to the xHCI Specification, v1.1, section 7.2.
8882 */
8883 union bdk_usbdrdx_uahc_suptprt3_dw3
8884 {
8885 uint32_t u;
8886 struct bdk_usbdrdx_uahc_suptprt3_dw3_s
8887 {
8888 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8889 uint32_t reserved_5_31 : 27;
8890 uint32_t protslottype : 5; /**< [ 4: 0](RO) Protocol slot type. */
8891 #else /* Word 0 - Little Endian */
8892 uint32_t protslottype : 5; /**< [ 4: 0](RO) Protocol slot type. */
8893 uint32_t reserved_5_31 : 27;
8894 #endif /* Word 0 - End */
8895 } s;
8896 /* struct bdk_usbdrdx_uahc_suptprt3_dw3_s cn; */
8897 };
8898 typedef union bdk_usbdrdx_uahc_suptprt3_dw3 bdk_usbdrdx_uahc_suptprt3_dw3_t;
8899
8900 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT3_DW3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_SUPTPRT3_DW3(unsigned long a)8901 static inline uint64_t BDK_USBDRDX_UAHC_SUPTPRT3_DW3(unsigned long a)
8902 {
8903 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8904 return 0x8680000008acll + 0x1000000000ll * ((a) & 0x1);
8905 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8906 return 0x8680000008acll + 0x1000000000ll * ((a) & 0x1);
8907 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8908 return 0x8680000008acll + 0x1000000000ll * ((a) & 0x1);
8909 __bdk_csr_fatal("USBDRDX_UAHC_SUPTPRT3_DW3", 1, a, 0, 0, 0);
8910 }
8911
8912 #define typedef_BDK_USBDRDX_UAHC_SUPTPRT3_DW3(a) bdk_usbdrdx_uahc_suptprt3_dw3_t
8913 #define bustype_BDK_USBDRDX_UAHC_SUPTPRT3_DW3(a) BDK_CSR_TYPE_NCB32b
8914 #define basename_BDK_USBDRDX_UAHC_SUPTPRT3_DW3(a) "USBDRDX_UAHC_SUPTPRT3_DW3"
8915 #define device_bar_BDK_USBDRDX_UAHC_SUPTPRT3_DW3(a) 0x0 /* PF_BAR0 */
8916 #define busnum_BDK_USBDRDX_UAHC_SUPTPRT3_DW3(a) (a)
8917 #define arguments_BDK_USBDRDX_UAHC_SUPTPRT3_DW3(a) (a),-1,-1,-1
8918
8919 /**
8920 * Register (NCB32b) usbdrd#_uahc_usbcmd
8921 *
8922 * USB XHCI Command Register
8923 * The command register indicates the command to be executed by the serial bus host controller.
8924 * Writing to
8925 * the register causes a command to be executed.
8926 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.1.
8927 *
8928 * This register can be reset by NCB reset,
8929 * or USBDRD()_UCTL_CTL[UAHC_RST],
8930 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
8931 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
8932 */
8933 union bdk_usbdrdx_uahc_usbcmd
8934 {
8935 uint32_t u;
8936 struct bdk_usbdrdx_uahc_usbcmd_s
8937 {
8938 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8939 uint32_t reserved_12_31 : 20;
8940 uint32_t eu3s : 1; /**< [ 11: 11](R/W) Enable U3 MFINDEX stop. */
8941 uint32_t ewe : 1; /**< [ 10: 10](R/W) Enable wrap event. */
8942 uint32_t crs : 1; /**< [ 9: 9](WO) Controller restore state. */
8943 uint32_t css : 1; /**< [ 8: 8](WO) Controller save state. */
8944 uint32_t lhcrst : 1; /**< [ 7: 7](R/W1S/H) Light host controller reset. */
8945 uint32_t reserved_4_6 : 3;
8946 uint32_t hsee : 1; /**< [ 3: 3](R/W) Host system error enable. */
8947 uint32_t inte : 1; /**< [ 2: 2](R/W) Interrupter enable. */
8948 uint32_t hcrst : 1; /**< [ 1: 1](R/W1S/H) Host controller reset. */
8949 uint32_t r_s : 1; /**< [ 0: 0](R/W) Run/stop. */
8950 #else /* Word 0 - Little Endian */
8951 uint32_t r_s : 1; /**< [ 0: 0](R/W) Run/stop. */
8952 uint32_t hcrst : 1; /**< [ 1: 1](R/W1S/H) Host controller reset. */
8953 uint32_t inte : 1; /**< [ 2: 2](R/W) Interrupter enable. */
8954 uint32_t hsee : 1; /**< [ 3: 3](R/W) Host system error enable. */
8955 uint32_t reserved_4_6 : 3;
8956 uint32_t lhcrst : 1; /**< [ 7: 7](R/W1S/H) Light host controller reset. */
8957 uint32_t css : 1; /**< [ 8: 8](WO) Controller save state. */
8958 uint32_t crs : 1; /**< [ 9: 9](WO) Controller restore state. */
8959 uint32_t ewe : 1; /**< [ 10: 10](R/W) Enable wrap event. */
8960 uint32_t eu3s : 1; /**< [ 11: 11](R/W) Enable U3 MFINDEX stop. */
8961 uint32_t reserved_12_31 : 20;
8962 #endif /* Word 0 - End */
8963 } s;
8964 /* struct bdk_usbdrdx_uahc_usbcmd_s cn; */
8965 };
8966 typedef union bdk_usbdrdx_uahc_usbcmd bdk_usbdrdx_uahc_usbcmd_t;
8967
8968 static inline uint64_t BDK_USBDRDX_UAHC_USBCMD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_USBCMD(unsigned long a)8969 static inline uint64_t BDK_USBDRDX_UAHC_USBCMD(unsigned long a)
8970 {
8971 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
8972 return 0x868000000020ll + 0x1000000000ll * ((a) & 0x1);
8973 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
8974 return 0x868000000020ll + 0x1000000000ll * ((a) & 0x1);
8975 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
8976 return 0x868000000020ll + 0x1000000000ll * ((a) & 0x1);
8977 __bdk_csr_fatal("USBDRDX_UAHC_USBCMD", 1, a, 0, 0, 0);
8978 }
8979
8980 #define typedef_BDK_USBDRDX_UAHC_USBCMD(a) bdk_usbdrdx_uahc_usbcmd_t
8981 #define bustype_BDK_USBDRDX_UAHC_USBCMD(a) BDK_CSR_TYPE_NCB32b
8982 #define basename_BDK_USBDRDX_UAHC_USBCMD(a) "USBDRDX_UAHC_USBCMD"
8983 #define device_bar_BDK_USBDRDX_UAHC_USBCMD(a) 0x0 /* PF_BAR0 */
8984 #define busnum_BDK_USBDRDX_UAHC_USBCMD(a) (a)
8985 #define arguments_BDK_USBDRDX_UAHC_USBCMD(a) (a),-1,-1,-1
8986
8987 /**
8988 * Register (NCB32b) usbdrd#_uahc_usblegctlsts
8989 *
8990 * USB XHCI Legacy Support Control/Status Register
8991 * For information on this register, refer to the xHCI Specification, v1.1, section 7.1.2. Note
8992 * that the SMI interrupts are not connected to anything in a CNXXXX configuration.
8993 *
8994 * This register can be reset by NCB reset,
8995 * or USBDRD()_UCTL_CTL[UAHC_RST],
8996 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
8997 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
8998 */
8999 union bdk_usbdrdx_uahc_usblegctlsts
9000 {
9001 uint32_t u;
9002 struct bdk_usbdrdx_uahc_usblegctlsts_s
9003 {
9004 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9005 uint32_t smi_on_bar : 1; /**< [ 31: 31](R/W1C/H) System management interrupt on BAR. Never generated. */
9006 uint32_t smi_on_pci_command : 1; /**< [ 30: 30](R/W1C/H) System management interrupt on PCI command. Never generated. */
9007 uint32_t smi_on_os_ownership : 1; /**< [ 29: 29](R/W1C/H) System management interrupt on OS ownership change. This bit is set to 1 whenever
9008 USBDRD()_UAHC_USBLEGSUP[HC_OS_OWNED_SEMAPHORES] transitions. */
9009 uint32_t reserved_21_28 : 8;
9010 uint32_t smi_on_hostsystemerr : 1; /**< [ 20: 20](RO/H) System-management interrupt on host-system error. Shadow bit of USBDRD()_UAHC_USBSTS[HSE].
9011 Refer to
9012 xHCI Section 5.4.2 for definition and effects of the events associated with this bit being
9013 set to 1.
9014
9015 To clear this bit to a 0, system software must write a 1 to USBDRD()_UAHC_USBSTS[HSE]. */
9016 uint32_t reserved_17_19 : 3;
9017 uint32_t smi_on_event_interrupt : 1; /**< [ 16: 16](RO/H) System-management interrupt on event interrupt. Shadow bit of USBDRD()_UAHC_USBSTS[EINT].
9018 Refer to
9019 xHCI Section 5.4.2 for definition. This bit automatically clears when [EINT] clears and
9020 sets when [EINT] sets. */
9021 uint32_t smi_on_bar_en : 1; /**< [ 15: 15](R/W) System-management interrupt on BAR enable. */
9022 uint32_t smi_on_pci_command_en : 1; /**< [ 14: 14](R/W) System-management interrupt on PCI command enable. */
9023 uint32_t smi_on_os_ownership_en : 1; /**< [ 13: 13](R/W) System-management interrupt on OS ownership enable. */
9024 uint32_t reserved_5_12 : 8;
9025 uint32_t smi_on_hostsystemerr_en : 1;/**< [ 4: 4](R/W) System-management interrupt on host-system error enable */
9026 uint32_t reserved_1_3 : 3;
9027 uint32_t usb_smi_en : 1; /**< [ 0: 0](R/W) USB system-management interrupt enable. */
9028 #else /* Word 0 - Little Endian */
9029 uint32_t usb_smi_en : 1; /**< [ 0: 0](R/W) USB system-management interrupt enable. */
9030 uint32_t reserved_1_3 : 3;
9031 uint32_t smi_on_hostsystemerr_en : 1;/**< [ 4: 4](R/W) System-management interrupt on host-system error enable */
9032 uint32_t reserved_5_12 : 8;
9033 uint32_t smi_on_os_ownership_en : 1; /**< [ 13: 13](R/W) System-management interrupt on OS ownership enable. */
9034 uint32_t smi_on_pci_command_en : 1; /**< [ 14: 14](R/W) System-management interrupt on PCI command enable. */
9035 uint32_t smi_on_bar_en : 1; /**< [ 15: 15](R/W) System-management interrupt on BAR enable. */
9036 uint32_t smi_on_event_interrupt : 1; /**< [ 16: 16](RO/H) System-management interrupt on event interrupt. Shadow bit of USBDRD()_UAHC_USBSTS[EINT].
9037 Refer to
9038 xHCI Section 5.4.2 for definition. This bit automatically clears when [EINT] clears and
9039 sets when [EINT] sets. */
9040 uint32_t reserved_17_19 : 3;
9041 uint32_t smi_on_hostsystemerr : 1; /**< [ 20: 20](RO/H) System-management interrupt on host-system error. Shadow bit of USBDRD()_UAHC_USBSTS[HSE].
9042 Refer to
9043 xHCI Section 5.4.2 for definition and effects of the events associated with this bit being
9044 set to 1.
9045
9046 To clear this bit to a 0, system software must write a 1 to USBDRD()_UAHC_USBSTS[HSE]. */
9047 uint32_t reserved_21_28 : 8;
9048 uint32_t smi_on_os_ownership : 1; /**< [ 29: 29](R/W1C/H) System management interrupt on OS ownership change. This bit is set to 1 whenever
9049 USBDRD()_UAHC_USBLEGSUP[HC_OS_OWNED_SEMAPHORES] transitions. */
9050 uint32_t smi_on_pci_command : 1; /**< [ 30: 30](R/W1C/H) System management interrupt on PCI command. Never generated. */
9051 uint32_t smi_on_bar : 1; /**< [ 31: 31](R/W1C/H) System management interrupt on BAR. Never generated. */
9052 #endif /* Word 0 - End */
9053 } s;
9054 /* struct bdk_usbdrdx_uahc_usblegctlsts_s cn; */
9055 };
9056 typedef union bdk_usbdrdx_uahc_usblegctlsts bdk_usbdrdx_uahc_usblegctlsts_t;
9057
9058 static inline uint64_t BDK_USBDRDX_UAHC_USBLEGCTLSTS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_USBLEGCTLSTS(unsigned long a)9059 static inline uint64_t BDK_USBDRDX_UAHC_USBLEGCTLSTS(unsigned long a)
9060 {
9061 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9062 return 0x868000000884ll + 0x1000000000ll * ((a) & 0x1);
9063 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
9064 return 0x868000000884ll + 0x1000000000ll * ((a) & 0x1);
9065 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
9066 return 0x868000000884ll + 0x1000000000ll * ((a) & 0x1);
9067 __bdk_csr_fatal("USBDRDX_UAHC_USBLEGCTLSTS", 1, a, 0, 0, 0);
9068 }
9069
9070 #define typedef_BDK_USBDRDX_UAHC_USBLEGCTLSTS(a) bdk_usbdrdx_uahc_usblegctlsts_t
9071 #define bustype_BDK_USBDRDX_UAHC_USBLEGCTLSTS(a) BDK_CSR_TYPE_NCB32b
9072 #define basename_BDK_USBDRDX_UAHC_USBLEGCTLSTS(a) "USBDRDX_UAHC_USBLEGCTLSTS"
9073 #define device_bar_BDK_USBDRDX_UAHC_USBLEGCTLSTS(a) 0x0 /* PF_BAR0 */
9074 #define busnum_BDK_USBDRDX_UAHC_USBLEGCTLSTS(a) (a)
9075 #define arguments_BDK_USBDRDX_UAHC_USBLEGCTLSTS(a) (a),-1,-1,-1
9076
9077 /**
9078 * Register (NCB32b) usbdrd#_uahc_usblegsup
9079 *
9080 * USB XHCI Legacy Support Capability Register
9081 * For information on this register, refer to the xHCI Specification, v1.1, section 7.1.1.
9082 *
9083 * This register can be reset by NCB reset,
9084 * or USBDRD()_UCTL_CTL[UAHC_RST],
9085 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
9086 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
9087 */
9088 union bdk_usbdrdx_uahc_usblegsup
9089 {
9090 uint32_t u;
9091 struct bdk_usbdrdx_uahc_usblegsup_s
9092 {
9093 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9094 uint32_t reserved_25_31 : 7;
9095 uint32_t hc_os_owned_semaphores : 1; /**< [ 24: 24](R/W) HC OS-owned semaphore. */
9096 uint32_t reserved_17_23 : 7;
9097 uint32_t hc_bios_owned_semaphores : 1;/**< [ 16: 16](R/W) HC BIOS-owned semaphore. */
9098 uint32_t nextcapptr : 8; /**< [ 15: 8](RO) Next xHCI extended-capability pointer. */
9099 uint32_t capid : 8; /**< [ 7: 0](RO) Capability ID = USB legacy support. */
9100 #else /* Word 0 - Little Endian */
9101 uint32_t capid : 8; /**< [ 7: 0](RO) Capability ID = USB legacy support. */
9102 uint32_t nextcapptr : 8; /**< [ 15: 8](RO) Next xHCI extended-capability pointer. */
9103 uint32_t hc_bios_owned_semaphores : 1;/**< [ 16: 16](R/W) HC BIOS-owned semaphore. */
9104 uint32_t reserved_17_23 : 7;
9105 uint32_t hc_os_owned_semaphores : 1; /**< [ 24: 24](R/W) HC OS-owned semaphore. */
9106 uint32_t reserved_25_31 : 7;
9107 #endif /* Word 0 - End */
9108 } s;
9109 /* struct bdk_usbdrdx_uahc_usblegsup_s cn; */
9110 };
9111 typedef union bdk_usbdrdx_uahc_usblegsup bdk_usbdrdx_uahc_usblegsup_t;
9112
9113 static inline uint64_t BDK_USBDRDX_UAHC_USBLEGSUP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_USBLEGSUP(unsigned long a)9114 static inline uint64_t BDK_USBDRDX_UAHC_USBLEGSUP(unsigned long a)
9115 {
9116 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9117 return 0x868000000880ll + 0x1000000000ll * ((a) & 0x1);
9118 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
9119 return 0x868000000880ll + 0x1000000000ll * ((a) & 0x1);
9120 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
9121 return 0x868000000880ll + 0x1000000000ll * ((a) & 0x1);
9122 __bdk_csr_fatal("USBDRDX_UAHC_USBLEGSUP", 1, a, 0, 0, 0);
9123 }
9124
9125 #define typedef_BDK_USBDRDX_UAHC_USBLEGSUP(a) bdk_usbdrdx_uahc_usblegsup_t
9126 #define bustype_BDK_USBDRDX_UAHC_USBLEGSUP(a) BDK_CSR_TYPE_NCB32b
9127 #define basename_BDK_USBDRDX_UAHC_USBLEGSUP(a) "USBDRDX_UAHC_USBLEGSUP"
9128 #define device_bar_BDK_USBDRDX_UAHC_USBLEGSUP(a) 0x0 /* PF_BAR0 */
9129 #define busnum_BDK_USBDRDX_UAHC_USBLEGSUP(a) (a)
9130 #define arguments_BDK_USBDRDX_UAHC_USBLEGSUP(a) (a),-1,-1,-1
9131
9132 /**
9133 * Register (NCB32b) usbdrd#_uahc_usbsts
9134 *
9135 * USB XHCI Status Register
9136 * This register indicates pending interrupts and various states of the host controller.
9137 * For information on this register, refer to the xHCI Specification, v1.1, section 5.4.2.
9138 *
9139 * This register can be reset by NCB reset,
9140 * or USBDRD()_UCTL_CTL[UAHC_RST],
9141 * or USBDRD()_UAHC_GCTL[CORESOFTRESET],
9142 * or USBDRD()_UAHC_USBCMD[HCRST], or USBDRD()_UAHC_USBCMD[LHCRST].
9143 */
9144 union bdk_usbdrdx_uahc_usbsts
9145 {
9146 uint32_t u;
9147 struct bdk_usbdrdx_uahc_usbsts_s
9148 {
9149 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9150 uint32_t reserved_13_31 : 19;
9151 uint32_t hce : 1; /**< [ 12: 12](RO/H) Host controller error. */
9152 uint32_t cnr : 1; /**< [ 11: 11](RO/H) Controller not ready. */
9153 uint32_t sre : 1; /**< [ 10: 10](R/W1C/H) Save/restore error. */
9154 uint32_t rss : 1; /**< [ 9: 9](RO/H) Restore state status. */
9155 uint32_t sss : 1; /**< [ 8: 8](RO/H) Save state status. */
9156 uint32_t reserved_5_7 : 3;
9157 uint32_t pcd : 1; /**< [ 4: 4](R/W1C/H) Port change detect. */
9158 uint32_t eint : 1; /**< [ 3: 3](R/W1C/H) Event interrupt. */
9159 uint32_t hse : 1; /**< [ 2: 2](R/W1C/H) Host system error. The typical software response to an HSE is to reset the core. */
9160 uint32_t reserved_1 : 1;
9161 uint32_t hch : 1; /**< [ 0: 0](RO/H) HC halted. */
9162 #else /* Word 0 - Little Endian */
9163 uint32_t hch : 1; /**< [ 0: 0](RO/H) HC halted. */
9164 uint32_t reserved_1 : 1;
9165 uint32_t hse : 1; /**< [ 2: 2](R/W1C/H) Host system error. The typical software response to an HSE is to reset the core. */
9166 uint32_t eint : 1; /**< [ 3: 3](R/W1C/H) Event interrupt. */
9167 uint32_t pcd : 1; /**< [ 4: 4](R/W1C/H) Port change detect. */
9168 uint32_t reserved_5_7 : 3;
9169 uint32_t sss : 1; /**< [ 8: 8](RO/H) Save state status. */
9170 uint32_t rss : 1; /**< [ 9: 9](RO/H) Restore state status. */
9171 uint32_t sre : 1; /**< [ 10: 10](R/W1C/H) Save/restore error. */
9172 uint32_t cnr : 1; /**< [ 11: 11](RO/H) Controller not ready. */
9173 uint32_t hce : 1; /**< [ 12: 12](RO/H) Host controller error. */
9174 uint32_t reserved_13_31 : 19;
9175 #endif /* Word 0 - End */
9176 } s;
9177 /* struct bdk_usbdrdx_uahc_usbsts_s cn; */
9178 };
9179 typedef union bdk_usbdrdx_uahc_usbsts bdk_usbdrdx_uahc_usbsts_t;
9180
9181 static inline uint64_t BDK_USBDRDX_UAHC_USBSTS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UAHC_USBSTS(unsigned long a)9182 static inline uint64_t BDK_USBDRDX_UAHC_USBSTS(unsigned long a)
9183 {
9184 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9185 return 0x868000000024ll + 0x1000000000ll * ((a) & 0x1);
9186 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
9187 return 0x868000000024ll + 0x1000000000ll * ((a) & 0x1);
9188 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
9189 return 0x868000000024ll + 0x1000000000ll * ((a) & 0x1);
9190 __bdk_csr_fatal("USBDRDX_UAHC_USBSTS", 1, a, 0, 0, 0);
9191 }
9192
9193 #define typedef_BDK_USBDRDX_UAHC_USBSTS(a) bdk_usbdrdx_uahc_usbsts_t
9194 #define bustype_BDK_USBDRDX_UAHC_USBSTS(a) BDK_CSR_TYPE_NCB32b
9195 #define basename_BDK_USBDRDX_UAHC_USBSTS(a) "USBDRDX_UAHC_USBSTS"
9196 #define device_bar_BDK_USBDRDX_UAHC_USBSTS(a) 0x0 /* PF_BAR0 */
9197 #define busnum_BDK_USBDRDX_UAHC_USBSTS(a) (a)
9198 #define arguments_BDK_USBDRDX_UAHC_USBSTS(a) (a),-1,-1,-1
9199
9200 /**
9201 * Register (NCB) usbdrd#_uctl_bist_status
9202 *
9203 * USB UCTL BIST Status Register
9204 * This register indicates the results from the built-in self-test (BIST) runs of USBDRD
9205 * memories.
9206 * A 0 indicates pass or never run, a 1 indicates fail. This register can be reset by NCB reset.
9207 */
9208 union bdk_usbdrdx_uctl_bist_status
9209 {
9210 uint64_t u;
9211 struct bdk_usbdrdx_uctl_bist_status_s
9212 {
9213 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9214 uint64_t reserved_42_63 : 22;
9215 uint64_t uctl_xm_r_bist_ndone : 1; /**< [ 41: 41](RO/H) BIST is not complete for the UCTL AxiMaster read-data FIFO. */
9216 uint64_t uctl_xm_w_bist_ndone : 1; /**< [ 40: 40](RO/H) BIST is not complete for the UCTL AxiMaster write-data FIFO. */
9217 uint64_t reserved_35_39 : 5;
9218 uint64_t uahc_ram2_bist_ndone : 1; /**< [ 34: 34](RO/H) BIST is not complete for the UAHC RxFIFO RAM (RAM2). */
9219 uint64_t uahc_ram1_bist_ndone : 1; /**< [ 33: 33](RO/H) BIST is not complete for the UAHC TxFIFO RAM (RAM1). */
9220 uint64_t uahc_ram0_bist_ndone : 1; /**< [ 32: 32](RO/H) BIST is not complete for the UAHC descriptor/register cache (RAM0). */
9221 uint64_t reserved_10_31 : 22;
9222 uint64_t uctl_xm_r_bist_status : 1; /**< [ 9: 9](RO/H) BIST status of the UCTL AxiMaster read-data FIFO. */
9223 uint64_t uctl_xm_w_bist_status : 1; /**< [ 8: 8](RO/H) BIST status of the UCTL AxiMaster write-data FIFO. */
9224 uint64_t reserved_3_7 : 5;
9225 uint64_t uahc_ram2_bist_status : 1; /**< [ 2: 2](RO/H) BIST status of the UAHC RxFIFO RAM (RAM2). */
9226 uint64_t uahc_ram1_bist_status : 1; /**< [ 1: 1](RO/H) BIST status of the UAHC TxFIFO RAM (RAM1). */
9227 uint64_t uahc_ram0_bist_status : 1; /**< [ 0: 0](RO/H) BIST status of the UAHC descriptor/register cache (RAM0). */
9228 #else /* Word 0 - Little Endian */
9229 uint64_t uahc_ram0_bist_status : 1; /**< [ 0: 0](RO/H) BIST status of the UAHC descriptor/register cache (RAM0). */
9230 uint64_t uahc_ram1_bist_status : 1; /**< [ 1: 1](RO/H) BIST status of the UAHC TxFIFO RAM (RAM1). */
9231 uint64_t uahc_ram2_bist_status : 1; /**< [ 2: 2](RO/H) BIST status of the UAHC RxFIFO RAM (RAM2). */
9232 uint64_t reserved_3_7 : 5;
9233 uint64_t uctl_xm_w_bist_status : 1; /**< [ 8: 8](RO/H) BIST status of the UCTL AxiMaster write-data FIFO. */
9234 uint64_t uctl_xm_r_bist_status : 1; /**< [ 9: 9](RO/H) BIST status of the UCTL AxiMaster read-data FIFO. */
9235 uint64_t reserved_10_31 : 22;
9236 uint64_t uahc_ram0_bist_ndone : 1; /**< [ 32: 32](RO/H) BIST is not complete for the UAHC descriptor/register cache (RAM0). */
9237 uint64_t uahc_ram1_bist_ndone : 1; /**< [ 33: 33](RO/H) BIST is not complete for the UAHC TxFIFO RAM (RAM1). */
9238 uint64_t uahc_ram2_bist_ndone : 1; /**< [ 34: 34](RO/H) BIST is not complete for the UAHC RxFIFO RAM (RAM2). */
9239 uint64_t reserved_35_39 : 5;
9240 uint64_t uctl_xm_w_bist_ndone : 1; /**< [ 40: 40](RO/H) BIST is not complete for the UCTL AxiMaster write-data FIFO. */
9241 uint64_t uctl_xm_r_bist_ndone : 1; /**< [ 41: 41](RO/H) BIST is not complete for the UCTL AxiMaster read-data FIFO. */
9242 uint64_t reserved_42_63 : 22;
9243 #endif /* Word 0 - End */
9244 } s;
9245 /* struct bdk_usbdrdx_uctl_bist_status_s cn; */
9246 };
9247 typedef union bdk_usbdrdx_uctl_bist_status bdk_usbdrdx_uctl_bist_status_t;
9248
9249 static inline uint64_t BDK_USBDRDX_UCTL_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_BIST_STATUS(unsigned long a)9250 static inline uint64_t BDK_USBDRDX_UCTL_BIST_STATUS(unsigned long a)
9251 {
9252 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9253 return 0x868000100008ll + 0x1000000000ll * ((a) & 0x1);
9254 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
9255 return 0x868000100008ll + 0x1000000000ll * ((a) & 0x1);
9256 __bdk_csr_fatal("USBDRDX_UCTL_BIST_STATUS", 1, a, 0, 0, 0);
9257 }
9258
9259 #define typedef_BDK_USBDRDX_UCTL_BIST_STATUS(a) bdk_usbdrdx_uctl_bist_status_t
9260 #define bustype_BDK_USBDRDX_UCTL_BIST_STATUS(a) BDK_CSR_TYPE_NCB
9261 #define basename_BDK_USBDRDX_UCTL_BIST_STATUS(a) "USBDRDX_UCTL_BIST_STATUS"
9262 #define device_bar_BDK_USBDRDX_UCTL_BIST_STATUS(a) 0x0 /* PF_BAR0 */
9263 #define busnum_BDK_USBDRDX_UCTL_BIST_STATUS(a) (a)
9264 #define arguments_BDK_USBDRDX_UCTL_BIST_STATUS(a) (a),-1,-1,-1
9265
9266 /**
9267 * Register (NCB) usbdrd#_uctl_csclk_active_pc
9268 *
9269 * USB UCTL Conditional Sclk Clock Counter Register
9270 * This register counts conditional clocks, for power analysis.
9271 * Reset by NCB reset.
9272 */
9273 union bdk_usbdrdx_uctl_csclk_active_pc
9274 {
9275 uint64_t u;
9276 struct bdk_usbdrdx_uctl_csclk_active_pc_s
9277 {
9278 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9279 uint64_t count : 64; /**< [ 63: 0](R/W/H) Counts conditional clock active cycles since reset. */
9280 #else /* Word 0 - Little Endian */
9281 uint64_t count : 64; /**< [ 63: 0](R/W/H) Counts conditional clock active cycles since reset. */
9282 #endif /* Word 0 - End */
9283 } s;
9284 /* struct bdk_usbdrdx_uctl_csclk_active_pc_s cn; */
9285 };
9286 typedef union bdk_usbdrdx_uctl_csclk_active_pc bdk_usbdrdx_uctl_csclk_active_pc_t;
9287
9288 static inline uint64_t BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(unsigned long a)9289 static inline uint64_t BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(unsigned long a)
9290 {
9291 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
9292 return 0x868000100028ll + 0x1000000000ll * ((a) & 0x1);
9293 __bdk_csr_fatal("USBDRDX_UCTL_CSCLK_ACTIVE_PC", 1, a, 0, 0, 0);
9294 }
9295
9296 #define typedef_BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(a) bdk_usbdrdx_uctl_csclk_active_pc_t
9297 #define bustype_BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(a) BDK_CSR_TYPE_NCB
9298 #define basename_BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(a) "USBDRDX_UCTL_CSCLK_ACTIVE_PC"
9299 #define device_bar_BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(a) 0x0 /* PF_BAR0 */
9300 #define busnum_BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(a) (a)
9301 #define arguments_BDK_USBDRDX_UCTL_CSCLK_ACTIVE_PC(a) (a),-1,-1,-1
9302
9303 /**
9304 * Register (NCB) usbdrd#_uctl_ctl
9305 *
9306 * USB UCTL Control Register
9307 * This register controls clocks, resets, power, and BIST.
9308 *
9309 * This register can be reset by NCB reset.
9310 */
9311 union bdk_usbdrdx_uctl_ctl
9312 {
9313 uint64_t u;
9314 struct bdk_usbdrdx_uctl_ctl_s
9315 {
9316 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9317 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. A BIST run with this bit set clears all entries in USBDRD
9318 RAMs
9319 to 0x0.
9320
9321 There are two major modes of BIST: full and clear. Full BIST is run by the BIST state
9322 machine when [CLEAR_BIST] is deasserted during BIST. Clear BIST is run if [CLEAR_BIST] is
9323 asserted during BIST.
9324
9325 To avoid race conditions, software must first perform a CSR write operation that puts the
9326 [CLEAR_BIST] setting into the correct state and then perform another CSR write operation
9327 to
9328 set the BIST trigger (keeping the [CLEAR_BIST] state constant).
9329 CLEAR BIST completion is indicated by USBDRD()_UCTL_BIST_STATUS. A BIST clear operation
9330 takes almost 2,000 controller-clock cycles for the largest RAM. */
9331 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Rising edge starts BIST on the memories in USBDRD.
9332 To run BIST, the controller clock must be both configured and enabled, and should be
9333 configured to the maximum available frequency given the available coprocessor clock and
9334 dividers.
9335 Also, the UCTL, UAHC, and UPHY should be held in software- initiated reset (using
9336 [UPHY_RST], [UAHC_RST], [UCTL_RST]) until BIST is complete.
9337 BIST defect status can be checked after FULL BIST completion, both of which are indicated
9338 in USBDRD()_UCTL_BIST_STATUS. The full BIST run takes almost 80,000 controller-clock
9339 cycles
9340 for
9341 the largest RAM. */
9342 uint64_t reserved_60_61 : 2;
9343 uint64_t ssc_en : 1; /**< [ 59: 59](R/W) Spread-spectrum clock enable. Enables spread-spectrum clock production in the SuperSpeed
9344 function. If the input reference clock for the SuperSpeed PLL is already spread-spectrum,
9345 then do not enable this feature. The clocks sourced to the SuperSpeed function must have
9346 spread-spectrum to be compliant with the USB specification.
9347
9348 The high-speed PLL cannot support a spread-spectrum input, so [REF_CLK_SEL] =
9349 0x0, 0x1, or 0x2 must enable this feature.
9350
9351 This value may only be changed during [UPHY_RST]. */
9352 uint64_t ssc_range : 3; /**< [ 58: 56](R/W) Spread-spectrum clock range. Selects the range of spread-spectrum modulation when SSC_EN
9353 is asserted and the PHY is spreading the SuperSpeed transmit clocks.
9354 Applies a fixed offset to the phase accumulator.
9355 0x0 = -4980 ppm downspread of clock.
9356 0x1 = -4492 ppm.
9357 0x2 = -4003 ppm.
9358 0x3-0x7 = reserved.
9359
9360 All of these settings are within the USB 3.0 specification. The amount of EMI emission
9361 reduction might decrease as the [SSC_RANGE] increases; therefore, the [SSC_RANGE] settings
9362 can
9363 be registered to enable the amount of spreading to be adjusted on a per-application basis.
9364 This value can be changed only during UPHY_RST. */
9365 uint64_t ssc_ref_clk_sel : 9; /**< [ 55: 47](R/W) Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
9366 corresponds to the frequency-synthesis coefficient.
9367
9368 [55:53]: modulus - 1,
9369 [52:47]: 2's complement push amount.
9370
9371 A value of 0x0 means this feature is disabled.
9372
9373 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
9374 * 0x0 is the only legal value.
9375
9376 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6, then the legal values are:
9377 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
9378 MPLL_MULTIPLIER description).
9379
9380 All other values are reserved.
9381
9382 This value may only be changed during [UPHY_RST].
9383
9384 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then [MPLL_MULTPLIER], [REF_CLK_DIV2], and
9385 [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
9386
9387 Internal:
9388 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
9389 * 0x0 is the only legal value.
9390
9391 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
9392 * 0x108: if DLMC_REF_CLK* is 19.2MHz, 24MHz, 26MHz, 38.4MHz, 48MHz,
9393 52MHz, 76.8MHz, 96MHz, 104MHz.
9394 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
9395 [MPLL_MULTIPLIER] description). */
9396 uint64_t mpll_multiplier : 7; /**< [ 46: 40](R/W) Multiplies the reference clock to a frequency suitable for intended operating speed.
9397
9398 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
9399
9400 0x19 = 100 MHz on DLMC_REF_CLK*.
9401
9402 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then the legal values are:
9403
9404 0x32 = 50 MHz on DLMC_REF_CLK*.
9405 0x19 = 100 MHz on DLMC_REF_CLK*.
9406 0x28 = 125 MHz on DLMC_REF_CLK*.
9407
9408 All other values are reserved.
9409
9410 This value may only be changed during UPHY_RST.
9411
9412 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then [MPLL_MULTPLIER], [REF_CLK_DIV2],
9413 and [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
9414
9415 Internal:
9416 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
9417 0x19 = 100 MHz on DLMC_REF_CLK*.
9418 0x68 = 24 MHz on DLMC_REF_CLK*.
9419 0x7D = 20 MHz on DLMC_REF_CLK*.
9420 0x02 = 19.2MHz on DLMC_REF_CLK*.
9421
9422 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x06, then:
9423 0x02 = 19.2MHz on DLMC_REF_CLK*.
9424 0x7D = 20 MHz on DLMC_REF_CLK*.
9425 0x68 = 24 MHz on DLMC_REF_CLK*.
9426 0x64 = 25 MHz on DLMC_REF_CLK*.
9427 0x60 = 26 MHz on DLMC_REF_CLK*.
9428 0x41 = 38.4MHz on DLMC_REF_CLK*.
9429 0x7D = 40 MHz on DLMC_REF_CLK*.
9430 0x34 = 48 MHz on DLMC_REF_CLK*.
9431 0x32 = 50 MHz on DLMC_REF_CLK*.
9432 0x30 = 52 MHz on DLMC_REF_CLK*.
9433 0x41 = 76.8MHz on DLMC_REF_CLK*.
9434 0x1A = 96 MHz on DLMC_REF_CLK*.
9435 0x19 = 100 MHz on DLMC_REF_CLK*.
9436 0x30 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x1.
9437 0x18 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x0.
9438 0x28 = 125 MHz on DLMC_REF_CLK*.
9439 0x19 = 200 MHz on DLMC_REF_CLK*. */
9440 uint64_t ref_ssp_en : 1; /**< [ 39: 39](R/W) Enables reference clock to the prescaler for SuperSpeed function. This should always be
9441 enabled since this output clock is used to drive the UAHC suspend-mode clock during
9442 low-power states.
9443
9444 This value can be changed only during UPHY_RST or during low-power states.
9445 The reference clock must be running and stable before [UPHY_RST] is deasserted and before
9446 [REF_SSP_EN] is asserted. */
9447 uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
9448
9449 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are:
9450 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
9451
9452 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are:
9453
9454 0x1: if DLMC_REF_CLK* is 125MHz.
9455
9456 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
9457 MPLL_MULTIPLIER description).
9458
9459 This value can be changed only during UPHY_RST.
9460
9461 If [REF_CLK_SEL] = 0x2 or 0x3, then [MPLL_MULTPLIER], [REF_CLK_DIV2], and
9462 [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
9463
9464 Internal:
9465 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
9466 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
9467
9468 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
9469 0x1: if DLMC_REF_CLK* is 125MHz.
9470 0x1: if DLMC_REF_CLK* is 40MHz, 76.8MHz, or 200MHz.
9471 0x0, 0x1 if DLMC_REF_CLK* is 104MHz (depending on [MPLL_MULTIPLIER]).
9472 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
9473 [MPLL_MULTIPLIER] description). */
9474 uint64_t ref_clk_fsel : 6; /**< [ 37: 32](R/W) Selects the reference clock frequency for the SuperSpeed and high-speed PLL blocks.
9475
9476 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
9477
9478 0x27 = 100 MHz on DLMC_REF_CLK*.
9479
9480 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6, then the legal values are:
9481
9482 0x07 is the only legal value.
9483
9484 All other values are reserved.
9485
9486 This value may only be changed during [UPHY_RST].
9487
9488 When [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, the [MPLL_MULTIPLIER], [REF_CLK_DIV2],
9489 and [SSC_REF_CLK_SEL] settings are used to configure the SuperSpeed reference
9490 clock multiplier.
9491
9492 Internal:
9493 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
9494 0x27 = 100 MHz on DLMC_REF_CLK*.
9495 0x2A = 24 MHz on DLMC_REF_CLK*.
9496 0x31 = 20 MHz on DLMC_REF_CLK*.
9497 0x38 = 19.2MHz on DLMC_REF_CLK*.
9498
9499 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6 then:
9500 0x07 is the only legal value. */
9501 uint64_t cmd_flr_en : 1; /**< [ 31: 31](R/W) The host controller will stop accepting commands if this bit is set. This bit is
9502 for host_mode only.
9503
9504 In normal FLR, this bit should be set to 0. If software wants the command to
9505 finish before FLR, write this bit to 1 and poll USBDRD()_UAHC_USBSTS[HCH] to
9506 make sure the command is finished before disabling USBDRD's PCCPF_XXX_CMD[ME]. */
9507 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) Controller-clock enable. When set to 1, the controller clock is generated. This also
9508 enables access to UCTL registers 0x30-0xF8. */
9509 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the controller-clock divider.
9510 0 = Use the divided coprocessor clock from the H_CLKDIV divider.
9511 1 = Use the bypass clock from the GPIO pins.
9512
9513 This signal is just a multiplexer-select signal; it does not enable the controller clock.
9514 You must still set H_CLKDIV_EN separately. [H_CLK_BYP_SEL] select should not be changed
9515 unless H_CLKDIV_EN is disabled.
9516
9517 The bypass clock can be selected and running even if the controller-clock dividers are not
9518 running.
9519
9520 Internal:
9521 Generally bypass is only used for scan purposes. */
9522 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) Controller clock divider reset. Divided clocks are not generated while the divider is
9523 being reset.
9524 This also resets the suspend-clock divider. */
9525 uint64_t reserved_27 : 1;
9526 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) Controller clock-frequency-divider select. The controller-clock frequency is the
9527 coprocessor-clock frequency divided by [H_CLKDIV_SEL] and must be at or below 300 MHz.
9528 The divider values are the following:
9529 0x0 = divide by 1.
9530 0x1 = divide by 2.
9531 0x2 = divide by 4.
9532 0x3 = divide by 6.
9533 0x4 = divide by 8.
9534 0x5 = divide by 16.
9535 0x6 = divide by 24.
9536 0x7 = divide by 32.
9537
9538 The hclk frequency must be at or below 300MHz.
9539 The hclk frequency must be at or above 150MHz for full-rate USB3
9540 operation.
9541 The hclk frequency must be at or above 125MHz for any USB3
9542 functionality.
9543
9544 If DRD_MODE = DEVICE, the hclk frequency must be at or above 125MHz for
9545 correct USB2 functionality.
9546
9547 If DRD_MODE = HOST, the hclk frequency must be at or above 90MHz
9548 for full-rate USB2 operation.
9549
9550 If DRD_MODE = HOST, the hclk frequency must be at or above 62.5MHz
9551 for any USB2 operation.
9552
9553 This field can be changed only when [H_CLKDIV_RST] = 1.
9554
9555 Internal:
9556 150MHz is from the maximum of:
9557 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 1, col 12.
9558 Synopsys DWC_usb3 Databook v2.80a, table A-17, row 7, col 9.
9559 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 7, col 9.
9560 DEVICE\>125MHz is from Synopsys DWC_usb3 Databook v2.80a, section A.12.4.
9561 HOST2\>62.5MHz in HOST mode is from Synopsys DWC_usb3 Databook v2.80a,
9562 section A.12.5, 3rd bullet in Note on page 894.
9563 HOST2\>90MHz was arrived at from some math: 62.5MHz +
9564 (diff between row 1 and 2, col 12 of table A-16). */
9565 uint64_t reserved_22_23 : 2;
9566 uint64_t usb3_port_perm_attach : 1; /**< [ 21: 21](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
9567 only when [UPHY_RST] is asserted. */
9568 uint64_t usb2_port_perm_attach : 1; /**< [ 20: 20](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
9569 only when [UPHY_RST] is asserted. */
9570 uint64_t reserved_19 : 1;
9571 uint64_t usb3_port_disable : 1; /**< [ 18: 18](R/W) Disables the USB3 (SuperSpeed) portion of this PHY. When set to 1, this signal stops
9572 reporting connect/disconnect events on the port and keeps the port in disabled state. This
9573 could be used for security reasons where hardware can disable a port regardless of whether
9574 xHCI driver enables a port or not.
9575 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
9576
9577 This is a strap signal; it should be modified only when [UPHY_RST] is asserted. */
9578 uint64_t reserved_17 : 1;
9579 uint64_t usb2_port_disable : 1; /**< [ 16: 16](R/W) Disables USB2 (high-speed/full-speed/low-speed) portion of this PHY. When set to 1, this
9580 signal stops reporting connect/disconnect events on the port and keeps the port in
9581 disabled state. This could be used for security reasons where hardware can disable a port
9582 regardless of whether xHCI driver enables a port or not.
9583 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
9584
9585 This is a strap signal; it should only be modified when [UPHY_RST] is asserted.
9586 If Port0 is required to be disabled, ensure that the utmi_clk[0] is running at the normal
9587 speed. Also, all the enabled USB2.0 ports should have the same clock frequency as Port0. */
9588 uint64_t reserved_15 : 1;
9589 uint64_t ss_power_en : 1; /**< [ 14: 14](R/W) PHY SuperSpeed block power enable.
9590 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
9591 uint64_t reserved_13 : 1;
9592 uint64_t hs_power_en : 1; /**< [ 12: 12](R/W) PHY high-speed block power enable.
9593 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
9594 uint64_t ref_clk_sel : 3; /**< [ 11: 9](R/W) Reference clock select. Choose reference-clock source for the SuperSpeed and high-speed
9595 PLL blocks. Both HighSpeed and SuperSpeed reference clocks must be supplied for USB
9596 operation.
9597
9598 \<pre\>
9599 Source for Source for
9600 [REF_CLK_SEL] SuperSpeed PLL HighSpeed PLL
9601 ------------- -------------- ------------------------
9602 0x0 DLMC_REF_CLK0 DLMC_REF_CLK0
9603 0x1 DLMC_REF_CLK1 DLMC_REF_CLK1
9604 0x2 PAD_REF_CLK PAD_REF_CLK
9605 0x3 Reserved.
9606 0x4 DLMC_REF_CLK0 PLL_REF_CLK
9607 0x5 DLMC_REF_CLK1 PLL_REF_CLK
9608 0x6 PAD_REF_CLK PLL_REF_CLK
9609 0x7 Reserved.
9610 \</pre\>
9611
9612 This value can be changed only during UPHY_RST.
9613
9614 If [REF_CLK_SEL] = 0x0, 0x1, or 0x2 then the reference clock input cannot be
9615 spread-spectrum.
9616
9617 Internal:
9618 For the 0x6 selection, reference clock source for SuperSpeed PLL is from the USB
9619 pads, reference clock source for high-speed PLL is PLL_REF_CLK. But in CNXXXX,
9620 PLL_REF_CLK cannot be routed to USB without violating jitter requirements */
9621 uint64_t reserved_6_8 : 3;
9622 uint64_t dma_psn_ign : 1; /**< [ 5: 5](R/W) Handling of poison indication on DMA read responses.
9623 0 = Treat poison data the same way as fault, sending an AXI error to the USB
9624 controller.
9625 1 = Ignore poison and proceed with the transaction as if no problems. */
9626 uint64_t reserved_4 : 1;
9627 uint64_t drd_mode : 1; /**< [ 3: 3](R/W) Switches between host or device mode for USBDRD.
9628 0 = Host.
9629 1 = Device. */
9630 uint64_t uphy_rst : 1; /**< [ 2: 2](R/W) PHY reset; resets UPHY; active-high. */
9631 uint64_t uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
9632 Internal:
9633 Note that soft-resetting the UAHC while it is active may cause violations of RSL
9634 or NCB protocols. */
9635 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
9636 Resets UAHC DMA and register shims. Resets UCTL registers 0x30-0xF8.
9637 Does not reset UCTL registers 0x0-0x28.
9638 UCTL registers starting from 0x30 can be accessed only after the controller clock is
9639 active and [UCTL_RST] is deasserted.
9640
9641 Internal:
9642 Note that soft-resetting the UCTL while it is active may cause violations of
9643 RSL, NCB, and CIB protocols. */
9644 #else /* Word 0 - Little Endian */
9645 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
9646 Resets UAHC DMA and register shims. Resets UCTL registers 0x30-0xF8.
9647 Does not reset UCTL registers 0x0-0x28.
9648 UCTL registers starting from 0x30 can be accessed only after the controller clock is
9649 active and [UCTL_RST] is deasserted.
9650
9651 Internal:
9652 Note that soft-resetting the UCTL while it is active may cause violations of
9653 RSL, NCB, and CIB protocols. */
9654 uint64_t uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
9655 Internal:
9656 Note that soft-resetting the UAHC while it is active may cause violations of RSL
9657 or NCB protocols. */
9658 uint64_t uphy_rst : 1; /**< [ 2: 2](R/W) PHY reset; resets UPHY; active-high. */
9659 uint64_t drd_mode : 1; /**< [ 3: 3](R/W) Switches between host or device mode for USBDRD.
9660 0 = Host.
9661 1 = Device. */
9662 uint64_t reserved_4 : 1;
9663 uint64_t dma_psn_ign : 1; /**< [ 5: 5](R/W) Handling of poison indication on DMA read responses.
9664 0 = Treat poison data the same way as fault, sending an AXI error to the USB
9665 controller.
9666 1 = Ignore poison and proceed with the transaction as if no problems. */
9667 uint64_t reserved_6_8 : 3;
9668 uint64_t ref_clk_sel : 3; /**< [ 11: 9](R/W) Reference clock select. Choose reference-clock source for the SuperSpeed and high-speed
9669 PLL blocks. Both HighSpeed and SuperSpeed reference clocks must be supplied for USB
9670 operation.
9671
9672 \<pre\>
9673 Source for Source for
9674 [REF_CLK_SEL] SuperSpeed PLL HighSpeed PLL
9675 ------------- -------------- ------------------------
9676 0x0 DLMC_REF_CLK0 DLMC_REF_CLK0
9677 0x1 DLMC_REF_CLK1 DLMC_REF_CLK1
9678 0x2 PAD_REF_CLK PAD_REF_CLK
9679 0x3 Reserved.
9680 0x4 DLMC_REF_CLK0 PLL_REF_CLK
9681 0x5 DLMC_REF_CLK1 PLL_REF_CLK
9682 0x6 PAD_REF_CLK PLL_REF_CLK
9683 0x7 Reserved.
9684 \</pre\>
9685
9686 This value can be changed only during UPHY_RST.
9687
9688 If [REF_CLK_SEL] = 0x0, 0x1, or 0x2 then the reference clock input cannot be
9689 spread-spectrum.
9690
9691 Internal:
9692 For the 0x6 selection, reference clock source for SuperSpeed PLL is from the USB
9693 pads, reference clock source for high-speed PLL is PLL_REF_CLK. But in CNXXXX,
9694 PLL_REF_CLK cannot be routed to USB without violating jitter requirements */
9695 uint64_t hs_power_en : 1; /**< [ 12: 12](R/W) PHY high-speed block power enable.
9696 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
9697 uint64_t reserved_13 : 1;
9698 uint64_t ss_power_en : 1; /**< [ 14: 14](R/W) PHY SuperSpeed block power enable.
9699 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
9700 uint64_t reserved_15 : 1;
9701 uint64_t usb2_port_disable : 1; /**< [ 16: 16](R/W) Disables USB2 (high-speed/full-speed/low-speed) portion of this PHY. When set to 1, this
9702 signal stops reporting connect/disconnect events on the port and keeps the port in
9703 disabled state. This could be used for security reasons where hardware can disable a port
9704 regardless of whether xHCI driver enables a port or not.
9705 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
9706
9707 This is a strap signal; it should only be modified when [UPHY_RST] is asserted.
9708 If Port0 is required to be disabled, ensure that the utmi_clk[0] is running at the normal
9709 speed. Also, all the enabled USB2.0 ports should have the same clock frequency as Port0. */
9710 uint64_t reserved_17 : 1;
9711 uint64_t usb3_port_disable : 1; /**< [ 18: 18](R/W) Disables the USB3 (SuperSpeed) portion of this PHY. When set to 1, this signal stops
9712 reporting connect/disconnect events on the port and keeps the port in disabled state. This
9713 could be used for security reasons where hardware can disable a port regardless of whether
9714 xHCI driver enables a port or not.
9715 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
9716
9717 This is a strap signal; it should be modified only when [UPHY_RST] is asserted. */
9718 uint64_t reserved_19 : 1;
9719 uint64_t usb2_port_perm_attach : 1; /**< [ 20: 20](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
9720 only when [UPHY_RST] is asserted. */
9721 uint64_t usb3_port_perm_attach : 1; /**< [ 21: 21](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
9722 only when [UPHY_RST] is asserted. */
9723 uint64_t reserved_22_23 : 2;
9724 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) Controller clock-frequency-divider select. The controller-clock frequency is the
9725 coprocessor-clock frequency divided by [H_CLKDIV_SEL] and must be at or below 300 MHz.
9726 The divider values are the following:
9727 0x0 = divide by 1.
9728 0x1 = divide by 2.
9729 0x2 = divide by 4.
9730 0x3 = divide by 6.
9731 0x4 = divide by 8.
9732 0x5 = divide by 16.
9733 0x6 = divide by 24.
9734 0x7 = divide by 32.
9735
9736 The hclk frequency must be at or below 300MHz.
9737 The hclk frequency must be at or above 150MHz for full-rate USB3
9738 operation.
9739 The hclk frequency must be at or above 125MHz for any USB3
9740 functionality.
9741
9742 If DRD_MODE = DEVICE, the hclk frequency must be at or above 125MHz for
9743 correct USB2 functionality.
9744
9745 If DRD_MODE = HOST, the hclk frequency must be at or above 90MHz
9746 for full-rate USB2 operation.
9747
9748 If DRD_MODE = HOST, the hclk frequency must be at or above 62.5MHz
9749 for any USB2 operation.
9750
9751 This field can be changed only when [H_CLKDIV_RST] = 1.
9752
9753 Internal:
9754 150MHz is from the maximum of:
9755 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 1, col 12.
9756 Synopsys DWC_usb3 Databook v2.80a, table A-17, row 7, col 9.
9757 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 7, col 9.
9758 DEVICE\>125MHz is from Synopsys DWC_usb3 Databook v2.80a, section A.12.4.
9759 HOST2\>62.5MHz in HOST mode is from Synopsys DWC_usb3 Databook v2.80a,
9760 section A.12.5, 3rd bullet in Note on page 894.
9761 HOST2\>90MHz was arrived at from some math: 62.5MHz +
9762 (diff between row 1 and 2, col 12 of table A-16). */
9763 uint64_t reserved_27 : 1;
9764 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) Controller clock divider reset. Divided clocks are not generated while the divider is
9765 being reset.
9766 This also resets the suspend-clock divider. */
9767 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the controller-clock divider.
9768 0 = Use the divided coprocessor clock from the H_CLKDIV divider.
9769 1 = Use the bypass clock from the GPIO pins.
9770
9771 This signal is just a multiplexer-select signal; it does not enable the controller clock.
9772 You must still set H_CLKDIV_EN separately. [H_CLK_BYP_SEL] select should not be changed
9773 unless H_CLKDIV_EN is disabled.
9774
9775 The bypass clock can be selected and running even if the controller-clock dividers are not
9776 running.
9777
9778 Internal:
9779 Generally bypass is only used for scan purposes. */
9780 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) Controller-clock enable. When set to 1, the controller clock is generated. This also
9781 enables access to UCTL registers 0x30-0xF8. */
9782 uint64_t cmd_flr_en : 1; /**< [ 31: 31](R/W) The host controller will stop accepting commands if this bit is set. This bit is
9783 for host_mode only.
9784
9785 In normal FLR, this bit should be set to 0. If software wants the command to
9786 finish before FLR, write this bit to 1 and poll USBDRD()_UAHC_USBSTS[HCH] to
9787 make sure the command is finished before disabling USBDRD's PCCPF_XXX_CMD[ME]. */
9788 uint64_t ref_clk_fsel : 6; /**< [ 37: 32](R/W) Selects the reference clock frequency for the SuperSpeed and high-speed PLL blocks.
9789
9790 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
9791
9792 0x27 = 100 MHz on DLMC_REF_CLK*.
9793
9794 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6, then the legal values are:
9795
9796 0x07 is the only legal value.
9797
9798 All other values are reserved.
9799
9800 This value may only be changed during [UPHY_RST].
9801
9802 When [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, the [MPLL_MULTIPLIER], [REF_CLK_DIV2],
9803 and [SSC_REF_CLK_SEL] settings are used to configure the SuperSpeed reference
9804 clock multiplier.
9805
9806 Internal:
9807 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
9808 0x27 = 100 MHz on DLMC_REF_CLK*.
9809 0x2A = 24 MHz on DLMC_REF_CLK*.
9810 0x31 = 20 MHz on DLMC_REF_CLK*.
9811 0x38 = 19.2MHz on DLMC_REF_CLK*.
9812
9813 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6 then:
9814 0x07 is the only legal value. */
9815 uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
9816
9817 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are:
9818 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
9819
9820 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are:
9821
9822 0x1: if DLMC_REF_CLK* is 125MHz.
9823
9824 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
9825 MPLL_MULTIPLIER description).
9826
9827 This value can be changed only during UPHY_RST.
9828
9829 If [REF_CLK_SEL] = 0x2 or 0x3, then [MPLL_MULTPLIER], [REF_CLK_DIV2], and
9830 [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
9831
9832 Internal:
9833 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
9834 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
9835
9836 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
9837 0x1: if DLMC_REF_CLK* is 125MHz.
9838 0x1: if DLMC_REF_CLK* is 40MHz, 76.8MHz, or 200MHz.
9839 0x0, 0x1 if DLMC_REF_CLK* is 104MHz (depending on [MPLL_MULTIPLIER]).
9840 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
9841 [MPLL_MULTIPLIER] description). */
9842 uint64_t ref_ssp_en : 1; /**< [ 39: 39](R/W) Enables reference clock to the prescaler for SuperSpeed function. This should always be
9843 enabled since this output clock is used to drive the UAHC suspend-mode clock during
9844 low-power states.
9845
9846 This value can be changed only during UPHY_RST or during low-power states.
9847 The reference clock must be running and stable before [UPHY_RST] is deasserted and before
9848 [REF_SSP_EN] is asserted. */
9849 uint64_t mpll_multiplier : 7; /**< [ 46: 40](R/W) Multiplies the reference clock to a frequency suitable for intended operating speed.
9850
9851 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
9852
9853 0x19 = 100 MHz on DLMC_REF_CLK*.
9854
9855 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then the legal values are:
9856
9857 0x32 = 50 MHz on DLMC_REF_CLK*.
9858 0x19 = 100 MHz on DLMC_REF_CLK*.
9859 0x28 = 125 MHz on DLMC_REF_CLK*.
9860
9861 All other values are reserved.
9862
9863 This value may only be changed during UPHY_RST.
9864
9865 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then [MPLL_MULTPLIER], [REF_CLK_DIV2],
9866 and [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
9867
9868 Internal:
9869 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
9870 0x19 = 100 MHz on DLMC_REF_CLK*.
9871 0x68 = 24 MHz on DLMC_REF_CLK*.
9872 0x7D = 20 MHz on DLMC_REF_CLK*.
9873 0x02 = 19.2MHz on DLMC_REF_CLK*.
9874
9875 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x06, then:
9876 0x02 = 19.2MHz on DLMC_REF_CLK*.
9877 0x7D = 20 MHz on DLMC_REF_CLK*.
9878 0x68 = 24 MHz on DLMC_REF_CLK*.
9879 0x64 = 25 MHz on DLMC_REF_CLK*.
9880 0x60 = 26 MHz on DLMC_REF_CLK*.
9881 0x41 = 38.4MHz on DLMC_REF_CLK*.
9882 0x7D = 40 MHz on DLMC_REF_CLK*.
9883 0x34 = 48 MHz on DLMC_REF_CLK*.
9884 0x32 = 50 MHz on DLMC_REF_CLK*.
9885 0x30 = 52 MHz on DLMC_REF_CLK*.
9886 0x41 = 76.8MHz on DLMC_REF_CLK*.
9887 0x1A = 96 MHz on DLMC_REF_CLK*.
9888 0x19 = 100 MHz on DLMC_REF_CLK*.
9889 0x30 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x1.
9890 0x18 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x0.
9891 0x28 = 125 MHz on DLMC_REF_CLK*.
9892 0x19 = 200 MHz on DLMC_REF_CLK*. */
9893 uint64_t ssc_ref_clk_sel : 9; /**< [ 55: 47](R/W) Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
9894 corresponds to the frequency-synthesis coefficient.
9895
9896 [55:53]: modulus - 1,
9897 [52:47]: 2's complement push amount.
9898
9899 A value of 0x0 means this feature is disabled.
9900
9901 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
9902 * 0x0 is the only legal value.
9903
9904 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6, then the legal values are:
9905 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
9906 MPLL_MULTIPLIER description).
9907
9908 All other values are reserved.
9909
9910 This value may only be changed during [UPHY_RST].
9911
9912 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then [MPLL_MULTPLIER], [REF_CLK_DIV2], and
9913 [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
9914
9915 Internal:
9916 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
9917 * 0x0 is the only legal value.
9918
9919 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
9920 * 0x108: if DLMC_REF_CLK* is 19.2MHz, 24MHz, 26MHz, 38.4MHz, 48MHz,
9921 52MHz, 76.8MHz, 96MHz, 104MHz.
9922 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
9923 [MPLL_MULTIPLIER] description). */
9924 uint64_t ssc_range : 3; /**< [ 58: 56](R/W) Spread-spectrum clock range. Selects the range of spread-spectrum modulation when SSC_EN
9925 is asserted and the PHY is spreading the SuperSpeed transmit clocks.
9926 Applies a fixed offset to the phase accumulator.
9927 0x0 = -4980 ppm downspread of clock.
9928 0x1 = -4492 ppm.
9929 0x2 = -4003 ppm.
9930 0x3-0x7 = reserved.
9931
9932 All of these settings are within the USB 3.0 specification. The amount of EMI emission
9933 reduction might decrease as the [SSC_RANGE] increases; therefore, the [SSC_RANGE] settings
9934 can
9935 be registered to enable the amount of spreading to be adjusted on a per-application basis.
9936 This value can be changed only during UPHY_RST. */
9937 uint64_t ssc_en : 1; /**< [ 59: 59](R/W) Spread-spectrum clock enable. Enables spread-spectrum clock production in the SuperSpeed
9938 function. If the input reference clock for the SuperSpeed PLL is already spread-spectrum,
9939 then do not enable this feature. The clocks sourced to the SuperSpeed function must have
9940 spread-spectrum to be compliant with the USB specification.
9941
9942 The high-speed PLL cannot support a spread-spectrum input, so [REF_CLK_SEL] =
9943 0x0, 0x1, or 0x2 must enable this feature.
9944
9945 This value may only be changed during [UPHY_RST]. */
9946 uint64_t reserved_60_61 : 2;
9947 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Rising edge starts BIST on the memories in USBDRD.
9948 To run BIST, the controller clock must be both configured and enabled, and should be
9949 configured to the maximum available frequency given the available coprocessor clock and
9950 dividers.
9951 Also, the UCTL, UAHC, and UPHY should be held in software- initiated reset (using
9952 [UPHY_RST], [UAHC_RST], [UCTL_RST]) until BIST is complete.
9953 BIST defect status can be checked after FULL BIST completion, both of which are indicated
9954 in USBDRD()_UCTL_BIST_STATUS. The full BIST run takes almost 80,000 controller-clock
9955 cycles
9956 for
9957 the largest RAM. */
9958 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. A BIST run with this bit set clears all entries in USBDRD
9959 RAMs
9960 to 0x0.
9961
9962 There are two major modes of BIST: full and clear. Full BIST is run by the BIST state
9963 machine when [CLEAR_BIST] is deasserted during BIST. Clear BIST is run if [CLEAR_BIST] is
9964 asserted during BIST.
9965
9966 To avoid race conditions, software must first perform a CSR write operation that puts the
9967 [CLEAR_BIST] setting into the correct state and then perform another CSR write operation
9968 to
9969 set the BIST trigger (keeping the [CLEAR_BIST] state constant).
9970 CLEAR BIST completion is indicated by USBDRD()_UCTL_BIST_STATUS. A BIST clear operation
9971 takes almost 2,000 controller-clock cycles for the largest RAM. */
9972 #endif /* Word 0 - End */
9973 } s;
9974 struct bdk_usbdrdx_uctl_ctl_cn81xx
9975 {
9976 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9977 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. A BIST run with this bit set clears all entries in USBDRD
9978 RAMs
9979 to 0x0.
9980
9981 There are two major modes of BIST: full and clear. Full BIST is run by the BIST state
9982 machine when [CLEAR_BIST] is deasserted during BIST. Clear BIST is run if [CLEAR_BIST] is
9983 asserted during BIST.
9984
9985 To avoid race conditions, software must first perform a CSR write operation that puts the
9986 [CLEAR_BIST] setting into the correct state and then perform another CSR write operation
9987 to
9988 set the BIST trigger (keeping the [CLEAR_BIST] state constant).
9989 CLEAR BIST completion is indicated by USBDRD()_UCTL_BIST_STATUS. A BIST clear operation
9990 takes almost 2,000 controller-clock cycles for the largest RAM. */
9991 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Rising edge starts BIST on the memories in USBDRD.
9992 To run BIST, the controller clock must be both configured and enabled, and should be
9993 configured to the maximum available frequency given the available coprocessor clock and
9994 dividers.
9995 Also, the UCTL, UAHC, and UPHY should be held in software- initiated reset (using
9996 [UPHY_RST], [UAHC_RST], [UCTL_RST]) until BIST is complete.
9997 BIST defect status can be checked after FULL BIST completion, both of which are indicated
9998 in USBDRD()_UCTL_BIST_STATUS. The full BIST run takes almost 80,000 controller-clock
9999 cycles
10000 for
10001 the largest RAM. */
10002 uint64_t reserved_60_61 : 2;
10003 uint64_t ssc_en : 1; /**< [ 59: 59](R/W) Spread-spectrum clock enable. Enables spread-spectrum clock production in the SuperSpeed
10004 function. If the input reference clock for the SuperSpeed PLL is already spread-spectrum,
10005 then do not enable this feature. The clocks sourced to the SuperSpeed function must have
10006 spread-spectrum to be compliant with the USB specification.
10007
10008 The high-speed PLL cannot support a spread-spectrum input, so [REF_CLK_SEL] =
10009 0x0, 0x1, or 0x2 must enable this feature.
10010
10011 This value may only be changed during [UPHY_RST]. */
10012 uint64_t ssc_range : 3; /**< [ 58: 56](R/W) Spread-spectrum clock range. Selects the range of spread-spectrum modulation when SSC_EN
10013 is asserted and the PHY is spreading the SuperSpeed transmit clocks.
10014 Applies a fixed offset to the phase accumulator.
10015 0x0 = -4980 ppm downspread of clock.
10016 0x1 = -4492 ppm.
10017 0x2 = -4003 ppm.
10018 0x3-0x7 = reserved.
10019
10020 All of these settings are within the USB 3.0 specification. The amount of EMI emission
10021 reduction might decrease as the [SSC_RANGE] increases; therefore, the [SSC_RANGE] settings
10022 can
10023 be registered to enable the amount of spreading to be adjusted on a per-application basis.
10024 This value can be changed only during UPHY_RST. */
10025 uint64_t ssc_ref_clk_sel : 9; /**< [ 55: 47](R/W) Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
10026 corresponds to the frequency-synthesis coefficient.
10027
10028 [55:53]: modulus - 1,
10029 [52:47]: 2's complement push amount.
10030
10031 A value of 0x0 means this feature is disabled.
10032
10033 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
10034 * 0x0 is the only legal value.
10035
10036 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6, then the legal values are:
10037 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10038 MPLL_MULTIPLIER description).
10039
10040 All other values are reserved.
10041
10042 This value may only be changed during [UPHY_RST].
10043
10044 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then [MPLL_MULTPLIER], [REF_CLK_DIV2], and
10045 [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
10046
10047 Internal:
10048 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
10049 * 0x0 is the only legal value.
10050
10051 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
10052 * 0x108: if DLMC_REF_CLK* is 19.2MHz, 24MHz, 26MHz, 38.4MHz, 48MHz,
10053 52MHz, 76.8MHz, 96MHz, 104MHz.
10054 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10055 [MPLL_MULTIPLIER] description). */
10056 uint64_t mpll_multiplier : 7; /**< [ 46: 40](R/W) Multiplies the reference clock to a frequency suitable for intended operating speed.
10057
10058 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
10059
10060 0x19 = 100 MHz on DLMC_REF_CLK*.
10061
10062 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then the legal values are:
10063
10064 0x32 = 50 MHz on DLMC_REF_CLK*.
10065 0x19 = 100 MHz on DLMC_REF_CLK*.
10066 0x28 = 125 MHz on DLMC_REF_CLK*.
10067
10068 All other values are reserved.
10069
10070 This value may only be changed during UPHY_RST.
10071
10072 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then [MPLL_MULTPLIER], [REF_CLK_DIV2],
10073 and [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
10074
10075 Internal:
10076 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
10077 0x19 = 100 MHz on DLMC_REF_CLK*.
10078 0x68 = 24 MHz on DLMC_REF_CLK*.
10079 0x7D = 20 MHz on DLMC_REF_CLK*.
10080 0x02 = 19.2MHz on DLMC_REF_CLK*.
10081
10082 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x06, then:
10083 0x02 = 19.2MHz on DLMC_REF_CLK*.
10084 0x7D = 20 MHz on DLMC_REF_CLK*.
10085 0x68 = 24 MHz on DLMC_REF_CLK*.
10086 0x64 = 25 MHz on DLMC_REF_CLK*.
10087 0x60 = 26 MHz on DLMC_REF_CLK*.
10088 0x41 = 38.4MHz on DLMC_REF_CLK*.
10089 0x7D = 40 MHz on DLMC_REF_CLK*.
10090 0x34 = 48 MHz on DLMC_REF_CLK*.
10091 0x32 = 50 MHz on DLMC_REF_CLK*.
10092 0x30 = 52 MHz on DLMC_REF_CLK*.
10093 0x41 = 76.8MHz on DLMC_REF_CLK*.
10094 0x1A = 96 MHz on DLMC_REF_CLK*.
10095 0x19 = 100 MHz on DLMC_REF_CLK*.
10096 0x30 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x1.
10097 0x18 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x0.
10098 0x28 = 125 MHz on DLMC_REF_CLK*.
10099 0x19 = 200 MHz on DLMC_REF_CLK*. */
10100 uint64_t ref_ssp_en : 1; /**< [ 39: 39](R/W) Enables reference clock to the prescaler for SuperSpeed function. This should always be
10101 enabled since this output clock is used to drive the UAHC suspend-mode clock during
10102 low-power states.
10103
10104 This value can be changed only during UPHY_RST or during low-power states.
10105 The reference clock must be running and stable before [UPHY_RST] is deasserted and before
10106 [REF_SSP_EN] is asserted. */
10107 uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
10108
10109 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are:
10110 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
10111
10112 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are:
10113
10114 0x1: if DLMC_REF_CLK* is 125MHz.
10115
10116 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10117 MPLL_MULTIPLIER description).
10118
10119 This value can be changed only during UPHY_RST.
10120
10121 If [REF_CLK_SEL] = 0x2 or 0x3, then [MPLL_MULTPLIER], [REF_CLK_DIV2], and
10122 [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
10123
10124 Internal:
10125 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
10126 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
10127
10128 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
10129 0x1: if DLMC_REF_CLK* is 125MHz.
10130 0x1: if DLMC_REF_CLK* is 40MHz, 76.8MHz, or 200MHz.
10131 0x0, 0x1 if DLMC_REF_CLK* is 104MHz (depending on [MPLL_MULTIPLIER]).
10132 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10133 [MPLL_MULTIPLIER] description). */
10134 uint64_t ref_clk_fsel : 6; /**< [ 37: 32](R/W) Selects the reference clock frequency for the SuperSpeed and high-speed PLL blocks.
10135
10136 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
10137
10138 0x27 = 100 MHz on DLMC_REF_CLK*.
10139
10140 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6, then the legal values are:
10141
10142 0x07 is the only legal value.
10143
10144 All other values are reserved.
10145
10146 This value may only be changed during [UPHY_RST].
10147
10148 When [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, the [MPLL_MULTIPLIER], [REF_CLK_DIV2],
10149 and [SSC_REF_CLK_SEL] settings are used to configure the SuperSpeed reference
10150 clock multiplier.
10151
10152 Internal:
10153 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
10154 0x27 = 100 MHz on DLMC_REF_CLK*.
10155 0x2A = 24 MHz on DLMC_REF_CLK*.
10156 0x31 = 20 MHz on DLMC_REF_CLK*.
10157 0x38 = 19.2MHz on DLMC_REF_CLK*.
10158
10159 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6 then:
10160 0x07 is the only legal value. */
10161 uint64_t reserved_31 : 1;
10162 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) Controller-clock enable. When set to 1, the controller clock is generated. This also
10163 enables access to UCTL registers 0x30-0xF8. */
10164 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the controller-clock divider.
10165 0 = Use the divided coprocessor clock from the H_CLKDIV divider.
10166 1 = Use the bypass clock from the GPIO pins.
10167
10168 This signal is just a multiplexer-select signal; it does not enable the controller clock.
10169 You must still set H_CLKDIV_EN separately. [H_CLK_BYP_SEL] select should not be changed
10170 unless H_CLKDIV_EN is disabled.
10171
10172 The bypass clock can be selected and running even if the controller-clock dividers are not
10173 running.
10174
10175 Internal:
10176 Generally bypass is only used for scan purposes. */
10177 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) Controller clock divider reset. Divided clocks are not generated while the divider is
10178 being reset.
10179 This also resets the suspend-clock divider. */
10180 uint64_t reserved_27 : 1;
10181 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) Controller clock-frequency-divider select. The controller-clock frequency is the
10182 coprocessor-clock frequency divided by [H_CLKDIV_SEL] and must be at or below 300 MHz.
10183 The divider values are the following:
10184 0x0 = divide by 1.
10185 0x1 = divide by 2.
10186 0x2 = divide by 4.
10187 0x3 = divide by 6.
10188 0x4 = divide by 8.
10189 0x5 = divide by 16.
10190 0x6 = divide by 24.
10191 0x7 = divide by 32.
10192
10193 The hclk frequency must be at or below 300MHz.
10194 The hclk frequency must be at or above 150MHz for full-rate USB3
10195 operation.
10196 The hclk frequency must be at or above 125MHz for any USB3
10197 functionality.
10198
10199 If DRD_MODE = DEVICE, the hclk frequency must be at or above 125MHz for
10200 correct USB2 functionality.
10201
10202 If DRD_MODE = HOST, the hclk frequency must be at or above 90MHz
10203 for full-rate USB2 operation.
10204
10205 If DRD_MODE = HOST, the hclk frequency must be at or above 62.5MHz
10206 for any USB2 operation.
10207
10208 This field can be changed only when [H_CLKDIV_RST] = 1.
10209
10210 Internal:
10211 150MHz is from the maximum of:
10212 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 1, col 12.
10213 Synopsys DWC_usb3 Databook v2.80a, table A-17, row 7, col 9.
10214 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 7, col 9.
10215 DEVICE\>125MHz is from Synopsys DWC_usb3 Databook v2.80a, section A.12.4.
10216 HOST2\>62.5MHz in HOST mode is from Synopsys DWC_usb3 Databook v2.80a,
10217 section A.12.5, 3rd bullet in Note on page 894.
10218 HOST2\>90MHz was arrived at from some math: 62.5MHz +
10219 (diff between row 1 and 2, col 12 of table A-16). */
10220 uint64_t reserved_22_23 : 2;
10221 uint64_t usb3_port_perm_attach : 1; /**< [ 21: 21](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
10222 only when [UPHY_RST] is asserted. */
10223 uint64_t usb2_port_perm_attach : 1; /**< [ 20: 20](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
10224 only when [UPHY_RST] is asserted. */
10225 uint64_t reserved_19 : 1;
10226 uint64_t usb3_port_disable : 1; /**< [ 18: 18](R/W) Disables the USB3 (SuperSpeed) portion of this PHY. When set to 1, this signal stops
10227 reporting connect/disconnect events on the port and keeps the port in disabled state. This
10228 could be used for security reasons where hardware can disable a port regardless of whether
10229 xHCI driver enables a port or not.
10230 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
10231
10232 This is a strap signal; it should be modified only when [UPHY_RST] is asserted. */
10233 uint64_t reserved_17 : 1;
10234 uint64_t usb2_port_disable : 1; /**< [ 16: 16](R/W) Disables USB2 (high-speed/full-speed/low-speed) portion of this PHY. When set to 1, this
10235 signal stops reporting connect/disconnect events on the port and keeps the port in
10236 disabled state. This could be used for security reasons where hardware can disable a port
10237 regardless of whether xHCI driver enables a port or not.
10238 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
10239
10240 This is a strap signal; it should only be modified when [UPHY_RST] is asserted.
10241 If Port0 is required to be disabled, ensure that the utmi_clk[0] is running at the normal
10242 speed. Also, all the enabled USB2.0 ports should have the same clock frequency as Port0. */
10243 uint64_t reserved_15 : 1;
10244 uint64_t ss_power_en : 1; /**< [ 14: 14](R/W) PHY SuperSpeed block power enable.
10245 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
10246 uint64_t reserved_13 : 1;
10247 uint64_t hs_power_en : 1; /**< [ 12: 12](R/W) PHY high-speed block power enable.
10248 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
10249 uint64_t ref_clk_sel : 3; /**< [ 11: 9](R/W) Reference clock select. Choose reference-clock source for the SuperSpeed and high-speed
10250 PLL blocks. Both HighSpeed and SuperSpeed reference clocks must be supplied for USB
10251 operation.
10252
10253 \<pre\>
10254 Source for Source for
10255 [REF_CLK_SEL] SuperSpeed PLL HighSpeed PLL
10256 ------------- -------------- ------------------------
10257 0x0 DLMC_REF_CLK0 DLMC_REF_CLK0
10258 0x1 DLMC_REF_CLK1 DLMC_REF_CLK1
10259 0x2 PAD_REF_CLK PAD_REF_CLK
10260 0x3 Reserved.
10261 0x4 DLMC_REF_CLK0 PLL_REF_CLK
10262 0x5 DLMC_REF_CLK1 PLL_REF_CLK
10263 0x6 PAD_REF_CLK PLL_REF_CLK
10264 0x7 Reserved.
10265 \</pre\>
10266
10267 This value can be changed only during UPHY_RST.
10268
10269 If [REF_CLK_SEL] = 0x0, 0x1, or 0x2 then the reference clock input cannot be
10270 spread-spectrum.
10271
10272 Internal:
10273 For the 0x6 selection, reference clock source for SuperSpeed PLL is from the USB
10274 pads, reference clock source for high-speed PLL is PLL_REF_CLK. But in CNXXXX,
10275 PLL_REF_CLK cannot be routed to USB without violating jitter requirements */
10276 uint64_t reserved_5_8 : 4;
10277 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the USB UCTL interface clock (coprocessor clock). This enables access to UAHC
10278 and UCTL registers starting from 0x30. */
10279 uint64_t drd_mode : 1; /**< [ 3: 3](R/W) Switches between host or device mode for USBDRD.
10280 0 = Host.
10281 1 = Device. */
10282 uint64_t uphy_rst : 1; /**< [ 2: 2](R/W) PHY reset; resets UPHY; active-high. */
10283 uint64_t uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
10284 Internal:
10285 Note that soft-resetting the UAHC while it is active may cause violations of RSL
10286 or NCB protocols. */
10287 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
10288 Resets UAHC DMA and register shims. Resets UCTL registers 0x30-0xF8.
10289 Does not reset UCTL registers 0x0-0x28.
10290 UCTL registers starting from 0x30 can be accessed only after the controller clock is
10291 active and [UCTL_RST] is deasserted.
10292
10293 Internal:
10294 Note that soft-resetting the UCTL while it is active may cause violations of
10295 RSL, NCB, and CIB protocols. */
10296 #else /* Word 0 - Little Endian */
10297 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
10298 Resets UAHC DMA and register shims. Resets UCTL registers 0x30-0xF8.
10299 Does not reset UCTL registers 0x0-0x28.
10300 UCTL registers starting from 0x30 can be accessed only after the controller clock is
10301 active and [UCTL_RST] is deasserted.
10302
10303 Internal:
10304 Note that soft-resetting the UCTL while it is active may cause violations of
10305 RSL, NCB, and CIB protocols. */
10306 uint64_t uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
10307 Internal:
10308 Note that soft-resetting the UAHC while it is active may cause violations of RSL
10309 or NCB protocols. */
10310 uint64_t uphy_rst : 1; /**< [ 2: 2](R/W) PHY reset; resets UPHY; active-high. */
10311 uint64_t drd_mode : 1; /**< [ 3: 3](R/W) Switches between host or device mode for USBDRD.
10312 0 = Host.
10313 1 = Device. */
10314 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the USB UCTL interface clock (coprocessor clock). This enables access to UAHC
10315 and UCTL registers starting from 0x30. */
10316 uint64_t reserved_5_8 : 4;
10317 uint64_t ref_clk_sel : 3; /**< [ 11: 9](R/W) Reference clock select. Choose reference-clock source for the SuperSpeed and high-speed
10318 PLL blocks. Both HighSpeed and SuperSpeed reference clocks must be supplied for USB
10319 operation.
10320
10321 \<pre\>
10322 Source for Source for
10323 [REF_CLK_SEL] SuperSpeed PLL HighSpeed PLL
10324 ------------- -------------- ------------------------
10325 0x0 DLMC_REF_CLK0 DLMC_REF_CLK0
10326 0x1 DLMC_REF_CLK1 DLMC_REF_CLK1
10327 0x2 PAD_REF_CLK PAD_REF_CLK
10328 0x3 Reserved.
10329 0x4 DLMC_REF_CLK0 PLL_REF_CLK
10330 0x5 DLMC_REF_CLK1 PLL_REF_CLK
10331 0x6 PAD_REF_CLK PLL_REF_CLK
10332 0x7 Reserved.
10333 \</pre\>
10334
10335 This value can be changed only during UPHY_RST.
10336
10337 If [REF_CLK_SEL] = 0x0, 0x1, or 0x2 then the reference clock input cannot be
10338 spread-spectrum.
10339
10340 Internal:
10341 For the 0x6 selection, reference clock source for SuperSpeed PLL is from the USB
10342 pads, reference clock source for high-speed PLL is PLL_REF_CLK. But in CNXXXX,
10343 PLL_REF_CLK cannot be routed to USB without violating jitter requirements */
10344 uint64_t hs_power_en : 1; /**< [ 12: 12](R/W) PHY high-speed block power enable.
10345 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
10346 uint64_t reserved_13 : 1;
10347 uint64_t ss_power_en : 1; /**< [ 14: 14](R/W) PHY SuperSpeed block power enable.
10348 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
10349 uint64_t reserved_15 : 1;
10350 uint64_t usb2_port_disable : 1; /**< [ 16: 16](R/W) Disables USB2 (high-speed/full-speed/low-speed) portion of this PHY. When set to 1, this
10351 signal stops reporting connect/disconnect events on the port and keeps the port in
10352 disabled state. This could be used for security reasons where hardware can disable a port
10353 regardless of whether xHCI driver enables a port or not.
10354 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
10355
10356 This is a strap signal; it should only be modified when [UPHY_RST] is asserted.
10357 If Port0 is required to be disabled, ensure that the utmi_clk[0] is running at the normal
10358 speed. Also, all the enabled USB2.0 ports should have the same clock frequency as Port0. */
10359 uint64_t reserved_17 : 1;
10360 uint64_t usb3_port_disable : 1; /**< [ 18: 18](R/W) Disables the USB3 (SuperSpeed) portion of this PHY. When set to 1, this signal stops
10361 reporting connect/disconnect events on the port and keeps the port in disabled state. This
10362 could be used for security reasons where hardware can disable a port regardless of whether
10363 xHCI driver enables a port or not.
10364 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
10365
10366 This is a strap signal; it should be modified only when [UPHY_RST] is asserted. */
10367 uint64_t reserved_19 : 1;
10368 uint64_t usb2_port_perm_attach : 1; /**< [ 20: 20](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
10369 only when [UPHY_RST] is asserted. */
10370 uint64_t usb3_port_perm_attach : 1; /**< [ 21: 21](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
10371 only when [UPHY_RST] is asserted. */
10372 uint64_t reserved_22_23 : 2;
10373 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) Controller clock-frequency-divider select. The controller-clock frequency is the
10374 coprocessor-clock frequency divided by [H_CLKDIV_SEL] and must be at or below 300 MHz.
10375 The divider values are the following:
10376 0x0 = divide by 1.
10377 0x1 = divide by 2.
10378 0x2 = divide by 4.
10379 0x3 = divide by 6.
10380 0x4 = divide by 8.
10381 0x5 = divide by 16.
10382 0x6 = divide by 24.
10383 0x7 = divide by 32.
10384
10385 The hclk frequency must be at or below 300MHz.
10386 The hclk frequency must be at or above 150MHz for full-rate USB3
10387 operation.
10388 The hclk frequency must be at or above 125MHz for any USB3
10389 functionality.
10390
10391 If DRD_MODE = DEVICE, the hclk frequency must be at or above 125MHz for
10392 correct USB2 functionality.
10393
10394 If DRD_MODE = HOST, the hclk frequency must be at or above 90MHz
10395 for full-rate USB2 operation.
10396
10397 If DRD_MODE = HOST, the hclk frequency must be at or above 62.5MHz
10398 for any USB2 operation.
10399
10400 This field can be changed only when [H_CLKDIV_RST] = 1.
10401
10402 Internal:
10403 150MHz is from the maximum of:
10404 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 1, col 12.
10405 Synopsys DWC_usb3 Databook v2.80a, table A-17, row 7, col 9.
10406 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 7, col 9.
10407 DEVICE\>125MHz is from Synopsys DWC_usb3 Databook v2.80a, section A.12.4.
10408 HOST2\>62.5MHz in HOST mode is from Synopsys DWC_usb3 Databook v2.80a,
10409 section A.12.5, 3rd bullet in Note on page 894.
10410 HOST2\>90MHz was arrived at from some math: 62.5MHz +
10411 (diff between row 1 and 2, col 12 of table A-16). */
10412 uint64_t reserved_27 : 1;
10413 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) Controller clock divider reset. Divided clocks are not generated while the divider is
10414 being reset.
10415 This also resets the suspend-clock divider. */
10416 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the controller-clock divider.
10417 0 = Use the divided coprocessor clock from the H_CLKDIV divider.
10418 1 = Use the bypass clock from the GPIO pins.
10419
10420 This signal is just a multiplexer-select signal; it does not enable the controller clock.
10421 You must still set H_CLKDIV_EN separately. [H_CLK_BYP_SEL] select should not be changed
10422 unless H_CLKDIV_EN is disabled.
10423
10424 The bypass clock can be selected and running even if the controller-clock dividers are not
10425 running.
10426
10427 Internal:
10428 Generally bypass is only used for scan purposes. */
10429 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) Controller-clock enable. When set to 1, the controller clock is generated. This also
10430 enables access to UCTL registers 0x30-0xF8. */
10431 uint64_t reserved_31 : 1;
10432 uint64_t ref_clk_fsel : 6; /**< [ 37: 32](R/W) Selects the reference clock frequency for the SuperSpeed and high-speed PLL blocks.
10433
10434 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
10435
10436 0x27 = 100 MHz on DLMC_REF_CLK*.
10437
10438 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6, then the legal values are:
10439
10440 0x07 is the only legal value.
10441
10442 All other values are reserved.
10443
10444 This value may only be changed during [UPHY_RST].
10445
10446 When [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, the [MPLL_MULTIPLIER], [REF_CLK_DIV2],
10447 and [SSC_REF_CLK_SEL] settings are used to configure the SuperSpeed reference
10448 clock multiplier.
10449
10450 Internal:
10451 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
10452 0x27 = 100 MHz on DLMC_REF_CLK*.
10453 0x2A = 24 MHz on DLMC_REF_CLK*.
10454 0x31 = 20 MHz on DLMC_REF_CLK*.
10455 0x38 = 19.2MHz on DLMC_REF_CLK*.
10456
10457 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6 then:
10458 0x07 is the only legal value. */
10459 uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
10460
10461 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are:
10462 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
10463
10464 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are:
10465
10466 0x1: if DLMC_REF_CLK* is 125MHz.
10467
10468 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10469 MPLL_MULTIPLIER description).
10470
10471 This value can be changed only during UPHY_RST.
10472
10473 If [REF_CLK_SEL] = 0x2 or 0x3, then [MPLL_MULTPLIER], [REF_CLK_DIV2], and
10474 [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
10475
10476 Internal:
10477 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
10478 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
10479
10480 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
10481 0x1: if DLMC_REF_CLK* is 125MHz.
10482 0x1: if DLMC_REF_CLK* is 40MHz, 76.8MHz, or 200MHz.
10483 0x0, 0x1 if DLMC_REF_CLK* is 104MHz (depending on [MPLL_MULTIPLIER]).
10484 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10485 [MPLL_MULTIPLIER] description). */
10486 uint64_t ref_ssp_en : 1; /**< [ 39: 39](R/W) Enables reference clock to the prescaler for SuperSpeed function. This should always be
10487 enabled since this output clock is used to drive the UAHC suspend-mode clock during
10488 low-power states.
10489
10490 This value can be changed only during UPHY_RST or during low-power states.
10491 The reference clock must be running and stable before [UPHY_RST] is deasserted and before
10492 [REF_SSP_EN] is asserted. */
10493 uint64_t mpll_multiplier : 7; /**< [ 46: 40](R/W) Multiplies the reference clock to a frequency suitable for intended operating speed.
10494
10495 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
10496
10497 0x19 = 100 MHz on DLMC_REF_CLK*.
10498
10499 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then the legal values are:
10500
10501 0x32 = 50 MHz on DLMC_REF_CLK*.
10502 0x19 = 100 MHz on DLMC_REF_CLK*.
10503 0x28 = 125 MHz on DLMC_REF_CLK*.
10504
10505 All other values are reserved.
10506
10507 This value may only be changed during UPHY_RST.
10508
10509 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then [MPLL_MULTPLIER], [REF_CLK_DIV2],
10510 and [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
10511
10512 Internal:
10513 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
10514 0x19 = 100 MHz on DLMC_REF_CLK*.
10515 0x68 = 24 MHz on DLMC_REF_CLK*.
10516 0x7D = 20 MHz on DLMC_REF_CLK*.
10517 0x02 = 19.2MHz on DLMC_REF_CLK*.
10518
10519 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x06, then:
10520 0x02 = 19.2MHz on DLMC_REF_CLK*.
10521 0x7D = 20 MHz on DLMC_REF_CLK*.
10522 0x68 = 24 MHz on DLMC_REF_CLK*.
10523 0x64 = 25 MHz on DLMC_REF_CLK*.
10524 0x60 = 26 MHz on DLMC_REF_CLK*.
10525 0x41 = 38.4MHz on DLMC_REF_CLK*.
10526 0x7D = 40 MHz on DLMC_REF_CLK*.
10527 0x34 = 48 MHz on DLMC_REF_CLK*.
10528 0x32 = 50 MHz on DLMC_REF_CLK*.
10529 0x30 = 52 MHz on DLMC_REF_CLK*.
10530 0x41 = 76.8MHz on DLMC_REF_CLK*.
10531 0x1A = 96 MHz on DLMC_REF_CLK*.
10532 0x19 = 100 MHz on DLMC_REF_CLK*.
10533 0x30 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x1.
10534 0x18 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x0.
10535 0x28 = 125 MHz on DLMC_REF_CLK*.
10536 0x19 = 200 MHz on DLMC_REF_CLK*. */
10537 uint64_t ssc_ref_clk_sel : 9; /**< [ 55: 47](R/W) Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
10538 corresponds to the frequency-synthesis coefficient.
10539
10540 [55:53]: modulus - 1,
10541 [52:47]: 2's complement push amount.
10542
10543 A value of 0x0 means this feature is disabled.
10544
10545 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then the legal values are:
10546 * 0x0 is the only legal value.
10547
10548 If [REF_CLK_SEL] = 0x4, 0x5 or 0x6, then the legal values are:
10549 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10550 MPLL_MULTIPLIER description).
10551
10552 All other values are reserved.
10553
10554 This value may only be changed during [UPHY_RST].
10555
10556 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then [MPLL_MULTPLIER], [REF_CLK_DIV2], and
10557 [SSC_REF_CLK_SEL] must all be programmed to the same frequency setting.
10558
10559 Internal:
10560 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
10561 * 0x0 is the only legal value.
10562
10563 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
10564 * 0x108: if DLMC_REF_CLK* is 19.2MHz, 24MHz, 26MHz, 38.4MHz, 48MHz,
10565 52MHz, 76.8MHz, 96MHz, 104MHz.
10566 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10567 [MPLL_MULTIPLIER] description). */
10568 uint64_t ssc_range : 3; /**< [ 58: 56](R/W) Spread-spectrum clock range. Selects the range of spread-spectrum modulation when SSC_EN
10569 is asserted and the PHY is spreading the SuperSpeed transmit clocks.
10570 Applies a fixed offset to the phase accumulator.
10571 0x0 = -4980 ppm downspread of clock.
10572 0x1 = -4492 ppm.
10573 0x2 = -4003 ppm.
10574 0x3-0x7 = reserved.
10575
10576 All of these settings are within the USB 3.0 specification. The amount of EMI emission
10577 reduction might decrease as the [SSC_RANGE] increases; therefore, the [SSC_RANGE] settings
10578 can
10579 be registered to enable the amount of spreading to be adjusted on a per-application basis.
10580 This value can be changed only during UPHY_RST. */
10581 uint64_t ssc_en : 1; /**< [ 59: 59](R/W) Spread-spectrum clock enable. Enables spread-spectrum clock production in the SuperSpeed
10582 function. If the input reference clock for the SuperSpeed PLL is already spread-spectrum,
10583 then do not enable this feature. The clocks sourced to the SuperSpeed function must have
10584 spread-spectrum to be compliant with the USB specification.
10585
10586 The high-speed PLL cannot support a spread-spectrum input, so [REF_CLK_SEL] =
10587 0x0, 0x1, or 0x2 must enable this feature.
10588
10589 This value may only be changed during [UPHY_RST]. */
10590 uint64_t reserved_60_61 : 2;
10591 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Rising edge starts BIST on the memories in USBDRD.
10592 To run BIST, the controller clock must be both configured and enabled, and should be
10593 configured to the maximum available frequency given the available coprocessor clock and
10594 dividers.
10595 Also, the UCTL, UAHC, and UPHY should be held in software- initiated reset (using
10596 [UPHY_RST], [UAHC_RST], [UCTL_RST]) until BIST is complete.
10597 BIST defect status can be checked after FULL BIST completion, both of which are indicated
10598 in USBDRD()_UCTL_BIST_STATUS. The full BIST run takes almost 80,000 controller-clock
10599 cycles
10600 for
10601 the largest RAM. */
10602 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. A BIST run with this bit set clears all entries in USBDRD
10603 RAMs
10604 to 0x0.
10605
10606 There are two major modes of BIST: full and clear. Full BIST is run by the BIST state
10607 machine when [CLEAR_BIST] is deasserted during BIST. Clear BIST is run if [CLEAR_BIST] is
10608 asserted during BIST.
10609
10610 To avoid race conditions, software must first perform a CSR write operation that puts the
10611 [CLEAR_BIST] setting into the correct state and then perform another CSR write operation
10612 to
10613 set the BIST trigger (keeping the [CLEAR_BIST] state constant).
10614 CLEAR BIST completion is indicated by USBDRD()_UCTL_BIST_STATUS. A BIST clear operation
10615 takes almost 2,000 controller-clock cycles for the largest RAM. */
10616 #endif /* Word 0 - End */
10617 } cn81xx;
10618 struct bdk_usbdrdx_uctl_ctl_cn83xx
10619 {
10620 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10621 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. A BIST run with this bit set clears all entries in USBDRD
10622 RAMs
10623 to 0x0.
10624
10625 There are two major modes of BIST: full and clear. Full BIST is run by the BIST state
10626 machine when [CLEAR_BIST] is deasserted during BIST. Clear BIST is run if [CLEAR_BIST] is
10627 asserted during BIST.
10628
10629 To avoid race conditions, software must first perform a CSR write operation that puts the
10630 [CLEAR_BIST] setting into the correct state and then perform another CSR write operation
10631 to
10632 set the BIST trigger (keeping the [CLEAR_BIST] state constant).
10633 CLEAR BIST completion is indicated by USBDRD()_UCTL_BIST_STATUS. A BIST clear operation
10634 takes almost 2,000 controller-clock cycles for the largest RAM. */
10635 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Rising edge starts BIST on the memories in USBDRD.
10636 To run BIST, the controller clock must be both configured and enabled, and should be
10637 configured to the maximum available frequency given the available coprocessor clock and
10638 dividers.
10639 Also, the UCTL, UAHC, and UPHY should be held in software- initiated reset (using
10640 [UPHY_RST], [UAHC_RST], [UCTL_RST]) until BIST is complete.
10641 BIST defect status can be checked after FULL BIST completion, both of which are indicated
10642 in USBDRD()_UCTL_BIST_STATUS. The full BIST run takes almost 80,000 controller-clock
10643 cycles
10644 for
10645 the largest RAM. */
10646 uint64_t reserved_60_61 : 2;
10647 uint64_t ssc_en : 1; /**< [ 59: 59](R/W) Spread-spectrum clock enable. Enables spread-spectrum clock production in the SuperSpeed
10648 function. If the input reference clock for the SuperSpeed PLL is already spread-spectrum,
10649 then do not enable this feature. The clocks sourced to the SuperSpeed function must have
10650 spread-spectrum to be compliant with the USB specification.
10651
10652 This value may only be changed during [UPHY_RST]. */
10653 uint64_t ssc_range : 3; /**< [ 58: 56](R/W) Spread-spectrum clock range. Selects the range of spread-spectrum modulation when SSC_EN
10654 is asserted and the PHY is spreading the SuperSpeed transmit clocks.
10655 Applies a fixed offset to the phase accumulator.
10656 0x0 = -4980 ppm downspread of clock.
10657 0x1 = -4492 ppm.
10658 0x2 = -4003 ppm.
10659 0x3-0x7 = reserved.
10660
10661 All of these settings are within the USB 3.0 specification. The amount of EMI emission
10662 reduction might decrease as the [SSC_RANGE] increases; therefore, the [SSC_RANGE] settings
10663 can
10664 be registered to enable the amount of spreading to be adjusted on a per-application basis.
10665 This value can be changed only during UPHY_RST. */
10666 uint64_t ssc_ref_clk_sel : 9; /**< [ 55: 47](R/W) Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
10667 corresponds to the frequency-synthesis coefficient.
10668
10669 [55:53]: modulus - 1,
10670 [52:47]: 2's complement push amount.
10671
10672 A value of 0x0 means this feature is disabled.
10673
10674 The legal values are 0x0.
10675
10676 All other values are reserved.
10677
10678 This value may only be changed during [UPHY_RST].
10679
10680 Internal:
10681 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
10682 * 0x0 is the only legal value.
10683
10684 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
10685 * 0x108: if DLMC_REF_CLK* is 19.2MHz, 24MHz, 26MHz, 38.4MHz, 48MHz,
10686 52MHz, 76.8MHz, 96MHz, 104MHz.
10687 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10688 [MPLL_MULTIPLIER] description). */
10689 uint64_t mpll_multiplier : 7; /**< [ 46: 40](R/W) Multiplies the reference clock to a frequency suitable for intended operating speed.
10690
10691 As [REF_CLK_SEL] = 0x0, the legal values are:
10692
10693 0x19 = 100 MHz on DLMC_REF_CLK*.
10694
10695 All other values are reserved.
10696
10697 This value may only be changed during [UPHY_RST].
10698
10699 Internal:
10700 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
10701 0x19 = 100 MHz on DLMC_REF_CLK*.
10702 0x68 = 24 MHz on DLMC_REF_CLK*.
10703 0x7D = 20 MHz on DLMC_REF_CLK*.
10704 0x02 = 19.2MHz on DLMC_REF_CLK*.
10705
10706 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x06, then:
10707 0x02 = 19.2MHz on DLMC_REF_CLK*.
10708 0x7D = 20 MHz on DLMC_REF_CLK*.
10709 0x68 = 24 MHz on DLMC_REF_CLK*.
10710 0x64 = 25 MHz on DLMC_REF_CLK*.
10711 0x60 = 26 MHz on DLMC_REF_CLK*.
10712 0x41 = 38.4MHz on DLMC_REF_CLK*.
10713 0x7D = 40 MHz on DLMC_REF_CLK*.
10714 0x34 = 48 MHz on DLMC_REF_CLK*.
10715 0x32 = 50 MHz on DLMC_REF_CLK*.
10716 0x30 = 52 MHz on DLMC_REF_CLK*.
10717 0x41 = 76.8MHz on DLMC_REF_CLK*.
10718 0x1A = 96 MHz on DLMC_REF_CLK*.
10719 0x19 = 100 MHz on DLMC_REF_CLK*.
10720 0x30 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x1.
10721 0x18 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x0.
10722 0x28 = 125 MHz on DLMC_REF_CLK*.
10723 0x19 = 200 MHz on DLMC_REF_CLK*. */
10724 uint64_t ref_ssp_en : 1; /**< [ 39: 39](R/W) Enables reference clock to the prescaler for SuperSpeed function. This should always be
10725 enabled since this output clock is used to drive the UAHC suspend-mode clock during
10726 low-power states.
10727
10728 This value can be changed only during UPHY_RST or during low-power states.
10729 The reference clock must be running and stable before [UPHY_RST] is deasserted and before
10730 [REF_SSP_EN] is asserted. */
10731 uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
10732
10733 As [REF_CLK_SEL] = 0x0, the legal value is 0x0.
10734
10735 This value can be changed only during UPHY_RST.
10736
10737 Internal:
10738 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
10739 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
10740
10741 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
10742 0x1: if DLMC_REF_CLK* is 125MHz.
10743 0x1: if DLMC_REF_CLK* is 40MHz, 76.8MHz, or 200MHz.
10744 0x0, 0x1 if DLMC_REF_CLK* is 104MHz (depending on [MPLL_MULTIPLIER]).
10745 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
10746 [MPLL_MULTIPLIER] description). */
10747 uint64_t ref_clk_fsel : 6; /**< [ 37: 32](R/W) Selects the reference clock frequency for the SuperSpeed and high-speed PLL blocks.
10748
10749 As [REF_CLK_SEL] = 0x0, the legal values are:
10750
10751 0x27 = 100 MHz on DLMC_REF_CLK*.
10752
10753 All other values are reserved.
10754
10755 This value may only be changed during [UPHY_RST].
10756
10757 Internal:
10758 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
10759 0x27 = 100 MHz on DLMC_REF_CLK*.
10760 0x2A = 24 MHz on DLMC_REF_CLK*.
10761 0x31 = 20 MHz on DLMC_REF_CLK*.
10762 0x38 = 19.2MHz on DLMC_REF_CLK*.
10763
10764 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6 then:
10765 0x07 is the only legal value. */
10766 uint64_t reserved_31 : 1;
10767 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) Controller-clock enable. When set to 1, the controller clock is generated. This also
10768 enables access to UCTL registers 0x30-0xF8. */
10769 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the controller-clock divider.
10770 0 = Use the divided coprocessor clock from the H_CLKDIV divider.
10771 1 = Use the bypass clock from the GPIO pins.
10772
10773 This signal is just a multiplexer-select signal; it does not enable the controller clock.
10774 You must still set H_CLKDIV_EN separately. [H_CLK_BYP_SEL] select should not be changed
10775 unless H_CLKDIV_EN is disabled.
10776
10777 The bypass clock can be selected and running even if the controller-clock dividers are not
10778 running.
10779
10780 Internal:
10781 Generally bypass is only used for scan purposes. */
10782 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) Controller clock divider reset. Divided clocks are not generated while the divider is
10783 being reset.
10784 This also resets the suspend-clock divider. */
10785 uint64_t reserved_27 : 1;
10786 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) Controller clock-frequency-divider select. The controller-clock frequency is the
10787 coprocessor-clock frequency divided by [H_CLKDIV_SEL] and must be at or below 300 MHz.
10788 The divider values are the following:
10789 0x0 = divide by 1.
10790 0x1 = divide by 2.
10791 0x2 = divide by 4.
10792 0x3 = divide by 6.
10793 0x4 = divide by 8.
10794 0x5 = divide by 16.
10795 0x6 = divide by 24.
10796 0x7 = divide by 32.
10797
10798 The HCLK frequency must be at or below 300 MHz.
10799 The HCLK frequency must be at or above 150 MHz for full-rate USB3
10800 operation.
10801 The HCLK frequency must be at or above 125 MHz for any USB3
10802 functionality.
10803
10804 If [DRD_MODE] = DEVICE, the HCLK frequency must be at or above 125 MHz for
10805 correct USB2 functionality.
10806
10807 If [DRD_MODE] = HOST, the HCLK frequency must be at or above 90 MHz
10808 for full-rate USB2 operation.
10809
10810 If [DRD_MODE] = HOST, the HCLK frequency must be at or above 62.5 MHz
10811 for any USB2 operation.
10812
10813 This field can be changed only when [H_CLKDIV_RST] = 1.
10814
10815 Internal:
10816 150MHz is from the maximum of:
10817 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 1, col 12.
10818 Synopsys DWC_usb3 Databook v2.80a, table A-17, row 7, col 9.
10819 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 7, col 9.
10820 DEVICE\>125MHz is from Synopsys DWC_usb3 Databook v2.80a, section A.12.4.
10821 HOST2\>62.5MHz in HOST mode is from Synopsys DWC_usb3 Databook v2.80a,
10822 section A.12.5, 3rd bullet in Note on page 894.
10823 HOST2\>90MHz was arrived at from some math: 62.5MHz +
10824 (diff between row 1 and 2, col 12 of table A-16). */
10825 uint64_t reserved_22_23 : 2;
10826 uint64_t usb3_port_perm_attach : 1; /**< [ 21: 21](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
10827 only when [UPHY_RST] is asserted. */
10828 uint64_t usb2_port_perm_attach : 1; /**< [ 20: 20](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
10829 only when [UPHY_RST] is asserted. */
10830 uint64_t reserved_19 : 1;
10831 uint64_t usb3_port_disable : 1; /**< [ 18: 18](R/W) Disables the USB3 (SuperSpeed) portion of this PHY. When set to 1, this signal stops
10832 reporting connect/disconnect events on the port and keeps the port in disabled state. This
10833 could be used for security reasons where hardware can disable a port regardless of whether
10834 xHCI driver enables a port or not.
10835 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
10836
10837 This is a strap signal; it should be modified only when [UPHY_RST] is asserted. */
10838 uint64_t reserved_17 : 1;
10839 uint64_t usb2_port_disable : 1; /**< [ 16: 16](R/W) Disables USB2 (high-speed/full-speed/low-speed) portion of this PHY. When set to 1, this
10840 signal stops reporting connect/disconnect events on the port and keeps the port in
10841 disabled state. This could be used for security reasons where hardware can disable a port
10842 regardless of whether xHCI driver enables a port or not.
10843 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
10844
10845 This is a strap signal; it should only be modified when [UPHY_RST] is asserted.
10846 If Port0 is required to be disabled, ensure that the utmi_clk[0] is running at the normal
10847 speed. Also, all the enabled USB2.0 ports should have the same clock frequency as Port0. */
10848 uint64_t reserved_15 : 1;
10849 uint64_t ss_power_en : 1; /**< [ 14: 14](R/W) PHY SuperSpeed block power enable.
10850 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
10851 uint64_t reserved_13 : 1;
10852 uint64_t hs_power_en : 1; /**< [ 12: 12](R/W) PHY high-speed block power enable.
10853 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
10854 uint64_t ref_clk_sel : 3; /**< [ 11: 9](R/W) Reference clock select. Choose reference-clock source for the SuperSpeed and high-speed
10855 PLL blocks.
10856 0x0 = Reference clock sources for both PLLs come from the USB pads.
10857 0x1 = Reserved.
10858 0x2 = Reserved.
10859 0x3 = Reserved.
10860 0x4 = Reserved.
10861 0x5 = Reserved.
10862 0x6 = Reserved.
10863 0x7 = Reserved.
10864
10865 This value can be changed only during UPHY_RST.
10866
10867 If [REF_CLK_SEL] = 0x0, 0x1, or 0x2 then the reference clock input cannot be
10868 spread-spectrum.
10869
10870 Internal:
10871 For the 0x6 selection, reference clock source for SuperSpeed PLL is from the USB
10872 pads, reference clock source for high-speed PLL is PLL_REF_CLK. But in CNXXXX,
10873 PLL_REF_CLK cannot be routed to USB without violating jitter requirements */
10874 uint64_t reserved_5_8 : 4;
10875 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the USB UCTL interface clock (coprocessor clock). This enables access to UAHC
10876 and UCTL registers starting from 0x30. */
10877 uint64_t drd_mode : 1; /**< [ 3: 3](R/W) Switches between host or device mode for USBDRD.
10878 0 = Host.
10879 1 = Device. */
10880 uint64_t uphy_rst : 1; /**< [ 2: 2](R/W) PHY reset; resets UPHY; active-high. */
10881 uint64_t uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
10882 Internal:
10883 Note that soft-resetting the UAHC while it is active may cause violations of RSL
10884 or NCB protocols. */
10885 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
10886 Resets UAHC DMA and register shims. Resets UCTL registers 0x30-0xF8.
10887 Does not reset UCTL registers 0x0-0x28.
10888 UCTL registers starting from 0x30 can be accessed only after the controller clock is
10889 active and [UCTL_RST] is deasserted.
10890
10891 Internal:
10892 Note that soft-resetting the UCTL while it is active may cause violations of
10893 RSL, NCB, and CIB protocols. */
10894 #else /* Word 0 - Little Endian */
10895 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
10896 Resets UAHC DMA and register shims. Resets UCTL registers 0x30-0xF8.
10897 Does not reset UCTL registers 0x0-0x28.
10898 UCTL registers starting from 0x30 can be accessed only after the controller clock is
10899 active and [UCTL_RST] is deasserted.
10900
10901 Internal:
10902 Note that soft-resetting the UCTL while it is active may cause violations of
10903 RSL, NCB, and CIB protocols. */
10904 uint64_t uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
10905 Internal:
10906 Note that soft-resetting the UAHC while it is active may cause violations of RSL
10907 or NCB protocols. */
10908 uint64_t uphy_rst : 1; /**< [ 2: 2](R/W) PHY reset; resets UPHY; active-high. */
10909 uint64_t drd_mode : 1; /**< [ 3: 3](R/W) Switches between host or device mode for USBDRD.
10910 0 = Host.
10911 1 = Device. */
10912 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the USB UCTL interface clock (coprocessor clock). This enables access to UAHC
10913 and UCTL registers starting from 0x30. */
10914 uint64_t reserved_5_8 : 4;
10915 uint64_t ref_clk_sel : 3; /**< [ 11: 9](R/W) Reference clock select. Choose reference-clock source for the SuperSpeed and high-speed
10916 PLL blocks.
10917 0x0 = Reference clock sources for both PLLs come from the USB pads.
10918 0x1 = Reserved.
10919 0x2 = Reserved.
10920 0x3 = Reserved.
10921 0x4 = Reserved.
10922 0x5 = Reserved.
10923 0x6 = Reserved.
10924 0x7 = Reserved.
10925
10926 This value can be changed only during UPHY_RST.
10927
10928 If [REF_CLK_SEL] = 0x0, 0x1, or 0x2 then the reference clock input cannot be
10929 spread-spectrum.
10930
10931 Internal:
10932 For the 0x6 selection, reference clock source for SuperSpeed PLL is from the USB
10933 pads, reference clock source for high-speed PLL is PLL_REF_CLK. But in CNXXXX,
10934 PLL_REF_CLK cannot be routed to USB without violating jitter requirements */
10935 uint64_t hs_power_en : 1; /**< [ 12: 12](R/W) PHY high-speed block power enable.
10936 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
10937 uint64_t reserved_13 : 1;
10938 uint64_t ss_power_en : 1; /**< [ 14: 14](R/W) PHY SuperSpeed block power enable.
10939 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
10940 uint64_t reserved_15 : 1;
10941 uint64_t usb2_port_disable : 1; /**< [ 16: 16](R/W) Disables USB2 (high-speed/full-speed/low-speed) portion of this PHY. When set to 1, this
10942 signal stops reporting connect/disconnect events on the port and keeps the port in
10943 disabled state. This could be used for security reasons where hardware can disable a port
10944 regardless of whether xHCI driver enables a port or not.
10945 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
10946
10947 This is a strap signal; it should only be modified when [UPHY_RST] is asserted.
10948 If Port0 is required to be disabled, ensure that the utmi_clk[0] is running at the normal
10949 speed. Also, all the enabled USB2.0 ports should have the same clock frequency as Port0. */
10950 uint64_t reserved_17 : 1;
10951 uint64_t usb3_port_disable : 1; /**< [ 18: 18](R/W) Disables the USB3 (SuperSpeed) portion of this PHY. When set to 1, this signal stops
10952 reporting connect/disconnect events on the port and keeps the port in disabled state. This
10953 could be used for security reasons where hardware can disable a port regardless of whether
10954 xHCI driver enables a port or not.
10955 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
10956
10957 This is a strap signal; it should be modified only when [UPHY_RST] is asserted. */
10958 uint64_t reserved_19 : 1;
10959 uint64_t usb2_port_perm_attach : 1; /**< [ 20: 20](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
10960 only when [UPHY_RST] is asserted. */
10961 uint64_t usb3_port_perm_attach : 1; /**< [ 21: 21](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
10962 only when [UPHY_RST] is asserted. */
10963 uint64_t reserved_22_23 : 2;
10964 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) Controller clock-frequency-divider select. The controller-clock frequency is the
10965 coprocessor-clock frequency divided by [H_CLKDIV_SEL] and must be at or below 300 MHz.
10966 The divider values are the following:
10967 0x0 = divide by 1.
10968 0x1 = divide by 2.
10969 0x2 = divide by 4.
10970 0x3 = divide by 6.
10971 0x4 = divide by 8.
10972 0x5 = divide by 16.
10973 0x6 = divide by 24.
10974 0x7 = divide by 32.
10975
10976 The HCLK frequency must be at or below 300 MHz.
10977 The HCLK frequency must be at or above 150 MHz for full-rate USB3
10978 operation.
10979 The HCLK frequency must be at or above 125 MHz for any USB3
10980 functionality.
10981
10982 If [DRD_MODE] = DEVICE, the HCLK frequency must be at or above 125 MHz for
10983 correct USB2 functionality.
10984
10985 If [DRD_MODE] = HOST, the HCLK frequency must be at or above 90 MHz
10986 for full-rate USB2 operation.
10987
10988 If [DRD_MODE] = HOST, the HCLK frequency must be at or above 62.5 MHz
10989 for any USB2 operation.
10990
10991 This field can be changed only when [H_CLKDIV_RST] = 1.
10992
10993 Internal:
10994 150MHz is from the maximum of:
10995 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 1, col 12.
10996 Synopsys DWC_usb3 Databook v2.80a, table A-17, row 7, col 9.
10997 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 7, col 9.
10998 DEVICE\>125MHz is from Synopsys DWC_usb3 Databook v2.80a, section A.12.4.
10999 HOST2\>62.5MHz in HOST mode is from Synopsys DWC_usb3 Databook v2.80a,
11000 section A.12.5, 3rd bullet in Note on page 894.
11001 HOST2\>90MHz was arrived at from some math: 62.5MHz +
11002 (diff between row 1 and 2, col 12 of table A-16). */
11003 uint64_t reserved_27 : 1;
11004 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) Controller clock divider reset. Divided clocks are not generated while the divider is
11005 being reset.
11006 This also resets the suspend-clock divider. */
11007 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the controller-clock divider.
11008 0 = Use the divided coprocessor clock from the H_CLKDIV divider.
11009 1 = Use the bypass clock from the GPIO pins.
11010
11011 This signal is just a multiplexer-select signal; it does not enable the controller clock.
11012 You must still set H_CLKDIV_EN separately. [H_CLK_BYP_SEL] select should not be changed
11013 unless H_CLKDIV_EN is disabled.
11014
11015 The bypass clock can be selected and running even if the controller-clock dividers are not
11016 running.
11017
11018 Internal:
11019 Generally bypass is only used for scan purposes. */
11020 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) Controller-clock enable. When set to 1, the controller clock is generated. This also
11021 enables access to UCTL registers 0x30-0xF8. */
11022 uint64_t reserved_31 : 1;
11023 uint64_t ref_clk_fsel : 6; /**< [ 37: 32](R/W) Selects the reference clock frequency for the SuperSpeed and high-speed PLL blocks.
11024
11025 As [REF_CLK_SEL] = 0x0, the legal values are:
11026
11027 0x27 = 100 MHz on DLMC_REF_CLK*.
11028
11029 All other values are reserved.
11030
11031 This value may only be changed during [UPHY_RST].
11032
11033 Internal:
11034 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
11035 0x27 = 100 MHz on DLMC_REF_CLK*.
11036 0x2A = 24 MHz on DLMC_REF_CLK*.
11037 0x31 = 20 MHz on DLMC_REF_CLK*.
11038 0x38 = 19.2MHz on DLMC_REF_CLK*.
11039
11040 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6 then:
11041 0x07 is the only legal value. */
11042 uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
11043
11044 As [REF_CLK_SEL] = 0x0, the legal value is 0x0.
11045
11046 This value can be changed only during UPHY_RST.
11047
11048 Internal:
11049 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
11050 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
11051
11052 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
11053 0x1: if DLMC_REF_CLK* is 125MHz.
11054 0x1: if DLMC_REF_CLK* is 40MHz, 76.8MHz, or 200MHz.
11055 0x0, 0x1 if DLMC_REF_CLK* is 104MHz (depending on [MPLL_MULTIPLIER]).
11056 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
11057 [MPLL_MULTIPLIER] description). */
11058 uint64_t ref_ssp_en : 1; /**< [ 39: 39](R/W) Enables reference clock to the prescaler for SuperSpeed function. This should always be
11059 enabled since this output clock is used to drive the UAHC suspend-mode clock during
11060 low-power states.
11061
11062 This value can be changed only during UPHY_RST or during low-power states.
11063 The reference clock must be running and stable before [UPHY_RST] is deasserted and before
11064 [REF_SSP_EN] is asserted. */
11065 uint64_t mpll_multiplier : 7; /**< [ 46: 40](R/W) Multiplies the reference clock to a frequency suitable for intended operating speed.
11066
11067 As [REF_CLK_SEL] = 0x0, the legal values are:
11068
11069 0x19 = 100 MHz on DLMC_REF_CLK*.
11070
11071 All other values are reserved.
11072
11073 This value may only be changed during [UPHY_RST].
11074
11075 Internal:
11076 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
11077 0x19 = 100 MHz on DLMC_REF_CLK*.
11078 0x68 = 24 MHz on DLMC_REF_CLK*.
11079 0x7D = 20 MHz on DLMC_REF_CLK*.
11080 0x02 = 19.2MHz on DLMC_REF_CLK*.
11081
11082 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x06, then:
11083 0x02 = 19.2MHz on DLMC_REF_CLK*.
11084 0x7D = 20 MHz on DLMC_REF_CLK*.
11085 0x68 = 24 MHz on DLMC_REF_CLK*.
11086 0x64 = 25 MHz on DLMC_REF_CLK*.
11087 0x60 = 26 MHz on DLMC_REF_CLK*.
11088 0x41 = 38.4MHz on DLMC_REF_CLK*.
11089 0x7D = 40 MHz on DLMC_REF_CLK*.
11090 0x34 = 48 MHz on DLMC_REF_CLK*.
11091 0x32 = 50 MHz on DLMC_REF_CLK*.
11092 0x30 = 52 MHz on DLMC_REF_CLK*.
11093 0x41 = 76.8MHz on DLMC_REF_CLK*.
11094 0x1A = 96 MHz on DLMC_REF_CLK*.
11095 0x19 = 100 MHz on DLMC_REF_CLK*.
11096 0x30 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x1.
11097 0x18 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x0.
11098 0x28 = 125 MHz on DLMC_REF_CLK*.
11099 0x19 = 200 MHz on DLMC_REF_CLK*. */
11100 uint64_t ssc_ref_clk_sel : 9; /**< [ 55: 47](R/W) Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
11101 corresponds to the frequency-synthesis coefficient.
11102
11103 [55:53]: modulus - 1,
11104 [52:47]: 2's complement push amount.
11105
11106 A value of 0x0 means this feature is disabled.
11107
11108 The legal values are 0x0.
11109
11110 All other values are reserved.
11111
11112 This value may only be changed during [UPHY_RST].
11113
11114 Internal:
11115 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
11116 * 0x0 is the only legal value.
11117
11118 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
11119 * 0x108: if DLMC_REF_CLK* is 19.2MHz, 24MHz, 26MHz, 38.4MHz, 48MHz,
11120 52MHz, 76.8MHz, 96MHz, 104MHz.
11121 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
11122 [MPLL_MULTIPLIER] description). */
11123 uint64_t ssc_range : 3; /**< [ 58: 56](R/W) Spread-spectrum clock range. Selects the range of spread-spectrum modulation when SSC_EN
11124 is asserted and the PHY is spreading the SuperSpeed transmit clocks.
11125 Applies a fixed offset to the phase accumulator.
11126 0x0 = -4980 ppm downspread of clock.
11127 0x1 = -4492 ppm.
11128 0x2 = -4003 ppm.
11129 0x3-0x7 = reserved.
11130
11131 All of these settings are within the USB 3.0 specification. The amount of EMI emission
11132 reduction might decrease as the [SSC_RANGE] increases; therefore, the [SSC_RANGE] settings
11133 can
11134 be registered to enable the amount of spreading to be adjusted on a per-application basis.
11135 This value can be changed only during UPHY_RST. */
11136 uint64_t ssc_en : 1; /**< [ 59: 59](R/W) Spread-spectrum clock enable. Enables spread-spectrum clock production in the SuperSpeed
11137 function. If the input reference clock for the SuperSpeed PLL is already spread-spectrum,
11138 then do not enable this feature. The clocks sourced to the SuperSpeed function must have
11139 spread-spectrum to be compliant with the USB specification.
11140
11141 This value may only be changed during [UPHY_RST]. */
11142 uint64_t reserved_60_61 : 2;
11143 uint64_t start_bist : 1; /**< [ 62: 62](R/W) Rising edge starts BIST on the memories in USBDRD.
11144 To run BIST, the controller clock must be both configured and enabled, and should be
11145 configured to the maximum available frequency given the available coprocessor clock and
11146 dividers.
11147 Also, the UCTL, UAHC, and UPHY should be held in software- initiated reset (using
11148 [UPHY_RST], [UAHC_RST], [UCTL_RST]) until BIST is complete.
11149 BIST defect status can be checked after FULL BIST completion, both of which are indicated
11150 in USBDRD()_UCTL_BIST_STATUS. The full BIST run takes almost 80,000 controller-clock
11151 cycles
11152 for
11153 the largest RAM. */
11154 uint64_t clear_bist : 1; /**< [ 63: 63](R/W) BIST fast-clear mode select. A BIST run with this bit set clears all entries in USBDRD
11155 RAMs
11156 to 0x0.
11157
11158 There are two major modes of BIST: full and clear. Full BIST is run by the BIST state
11159 machine when [CLEAR_BIST] is deasserted during BIST. Clear BIST is run if [CLEAR_BIST] is
11160 asserted during BIST.
11161
11162 To avoid race conditions, software must first perform a CSR write operation that puts the
11163 [CLEAR_BIST] setting into the correct state and then perform another CSR write operation
11164 to
11165 set the BIST trigger (keeping the [CLEAR_BIST] state constant).
11166 CLEAR BIST completion is indicated by USBDRD()_UCTL_BIST_STATUS. A BIST clear operation
11167 takes almost 2,000 controller-clock cycles for the largest RAM. */
11168 #endif /* Word 0 - End */
11169 } cn83xx;
11170 struct bdk_usbdrdx_uctl_ctl_cn9
11171 {
11172 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11173 uint64_t reserved_60_63 : 4;
11174 uint64_t ssc_en : 1; /**< [ 59: 59](R/W) Spread-spectrum clock enable. Enables spread-spectrum clock production in the SuperSpeed
11175 function. If the input reference clock for the SuperSpeed PLL is already spread-spectrum,
11176 then do not enable this feature. The clocks sourced to the SuperSpeed function must have
11177 spread-spectrum to be compliant with the USB specification.
11178
11179 This value may only be changed during [UPHY_RST]. */
11180 uint64_t ssc_range : 3; /**< [ 58: 56](R/W) Spread-spectrum clock range. Selects the range of spread-spectrum modulation when SSC_EN
11181 is asserted and the PHY is spreading the SuperSpeed transmit clocks.
11182 Applies a fixed offset to the phase accumulator.
11183 0x0 = -4980 ppm downspread of clock.
11184 0x1 = -4492 ppm.
11185 0x2 = -4003 ppm.
11186 0x3-0x7 = reserved.
11187
11188 All of these settings are within the USB 3.0 specification. The amount of EMI emission
11189 reduction might decrease as the [SSC_RANGE] increases; therefore, the [SSC_RANGE] settings
11190 can
11191 be registered to enable the amount of spreading to be adjusted on a per-application basis.
11192 This value can be changed only during UPHY_RST. */
11193 uint64_t ssc_ref_clk_sel : 9; /**< [ 55: 47](R/W) Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
11194 corresponds to the frequency-synthesis coefficient.
11195
11196 [55:53]: modulus - 1,
11197 [52:47]: 2's complement push amount.
11198
11199 A value of 0x0 means this feature is disabled.
11200
11201 The legal values are 0x0.
11202
11203 All other values are reserved.
11204
11205 This value may only be changed during [UPHY_RST].
11206
11207 Internal:
11208 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
11209 * 0x0 is the only legal value.
11210
11211 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
11212 * 0x108: if DLMC_REF_CLK* is 19.2MHz, 24MHz, 26MHz, 38.4MHz, 48MHz,
11213 52MHz, 76.8MHz, 96MHz, 104MHz.
11214 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
11215 [MPLL_MULTIPLIER] description). */
11216 uint64_t mpll_multiplier : 7; /**< [ 46: 40](R/W) Multiplies the reference clock to a frequency suitable for intended operating speed.
11217
11218 As [REF_CLK_SEL] = 0x0, the legal values are:
11219
11220 0x19 = 100 MHz on DLMC_REF_CLK*.
11221
11222 All other values are reserved.
11223
11224 This value may only be changed during [UPHY_RST].
11225
11226 Internal:
11227 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
11228 0x19 = 100 MHz on DLMC_REF_CLK*.
11229 0x68 = 24 MHz on DLMC_REF_CLK*.
11230 0x7D = 20 MHz on DLMC_REF_CLK*.
11231 0x02 = 19.2MHz on DLMC_REF_CLK*.
11232
11233 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x06, then:
11234 0x02 = 19.2MHz on DLMC_REF_CLK*.
11235 0x7D = 20 MHz on DLMC_REF_CLK*.
11236 0x68 = 24 MHz on DLMC_REF_CLK*.
11237 0x64 = 25 MHz on DLMC_REF_CLK*.
11238 0x60 = 26 MHz on DLMC_REF_CLK*.
11239 0x41 = 38.4MHz on DLMC_REF_CLK*.
11240 0x7D = 40 MHz on DLMC_REF_CLK*.
11241 0x34 = 48 MHz on DLMC_REF_CLK*.
11242 0x32 = 50 MHz on DLMC_REF_CLK*.
11243 0x30 = 52 MHz on DLMC_REF_CLK*.
11244 0x41 = 76.8MHz on DLMC_REF_CLK*.
11245 0x1A = 96 MHz on DLMC_REF_CLK*.
11246 0x19 = 100 MHz on DLMC_REF_CLK*.
11247 0x30 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x1.
11248 0x18 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x0.
11249 0x28 = 125 MHz on DLMC_REF_CLK*.
11250 0x19 = 200 MHz on DLMC_REF_CLK*. */
11251 uint64_t ref_ssp_en : 1; /**< [ 39: 39](R/W) Enables reference clock to the prescaler for SuperSpeed function. This should always be
11252 enabled since this output clock is used to drive the UAHC suspend-mode clock during
11253 low-power states.
11254
11255 This value can be changed only during UPHY_RST or during low-power states.
11256 The reference clock must be running and stable before [UPHY_RST] is deasserted and before
11257 [REF_SSP_EN] is asserted. */
11258 uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
11259
11260 As [REF_CLK_SEL] = 0x0, the legal value is 0x0.
11261
11262 This value can be changed only during UPHY_RST.
11263
11264 Internal:
11265 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
11266 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
11267
11268 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
11269 0x1: if DLMC_REF_CLK* is 125MHz.
11270 0x1: if DLMC_REF_CLK* is 40MHz, 76.8MHz, or 200MHz.
11271 0x0, 0x1 if DLMC_REF_CLK* is 104MHz (depending on [MPLL_MULTIPLIER]).
11272 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
11273 [MPLL_MULTIPLIER] description). */
11274 uint64_t ref_clk_fsel : 6; /**< [ 37: 32](R/W) Selects the reference clock frequency for the SuperSpeed and high-speed PLL blocks.
11275
11276 As [REF_CLK_SEL] = 0x0, the legal values are:
11277
11278 0x27 = 100 MHz on DLMC_REF_CLK*.
11279
11280 All other values are reserved.
11281
11282 This value may only be changed during [UPHY_RST].
11283
11284 Internal:
11285 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
11286 0x27 = 100 MHz on DLMC_REF_CLK*.
11287 0x2A = 24 MHz on DLMC_REF_CLK*.
11288 0x31 = 20 MHz on DLMC_REF_CLK*.
11289 0x38 = 19.2MHz on DLMC_REF_CLK*.
11290
11291 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6 then:
11292 0x07 is the only legal value. */
11293 uint64_t cmd_flr_en : 1; /**< [ 31: 31](R/W) The host controller will stop accepting commands if this bit is set. This bit is
11294 for host_mode only.
11295
11296 In normal FLR, this bit should be set to 0. If software wants the command to
11297 finish before FLR, write this bit to 1 and poll USBDRD()_UAHC_USBSTS[HCH] to
11298 make sure the command is finished before disabling USBDRD's PCCPF_XXX_CMD[ME]. */
11299 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) Controller-clock enable. When set to 1, the controller clock is generated. This also
11300 enables access to UCTL registers 0x30-0xF8. */
11301 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the controller-clock divider.
11302 0 = Use the divided coprocessor clock from the H_CLKDIV divider.
11303 1 = Use the bypass clock from the GPIO pins.
11304
11305 This signal is just a multiplexer-select signal; it does not enable the controller clock.
11306 You must still set H_CLKDIV_EN separately. [H_CLK_BYP_SEL] select should not be changed
11307 unless H_CLKDIV_EN is disabled.
11308
11309 The bypass clock can be selected and running even if the controller-clock dividers are not
11310 running.
11311
11312 Internal:
11313 Generally bypass is only used for scan purposes. */
11314 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) Controller clock divider reset. Divided clocks are not generated while the divider is
11315 being reset.
11316 This also resets the suspend-clock divider. */
11317 uint64_t reserved_27 : 1;
11318 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) Controller clock-frequency-divider select. The controller-clock frequency is the
11319 coprocessor-clock frequency divided by [H_CLKDIV_SEL] and must be at or below 300 MHz.
11320 The divider values are the following:
11321 0x0 = divide by 1.
11322 0x1 = divide by 2.
11323 0x2 = divide by 4.
11324 0x3 = divide by 6.
11325 0x4 = divide by 8.
11326 0x5 = divide by 16.
11327 0x6 = divide by 24.
11328 0x7 = divide by 32.
11329
11330 The HCLK frequency must be at or below 300 MHz.
11331 The HCLK frequency must be at or above 150 MHz for full-rate USB3
11332 operation.
11333 The HCLK frequency must be at or above 125 MHz for any USB3
11334 functionality.
11335
11336 If [DRD_MODE] = DEVICE, the HCLK frequency must be at or above 125 MHz for
11337 correct USB2 functionality.
11338
11339 If [DRD_MODE] = HOST, the HCLK frequency must be at or above 90 MHz
11340 for full-rate USB2 operation.
11341
11342 If [DRD_MODE] = HOST, the HCLK frequency must be at or above 62.5 MHz
11343 for any USB2 operation.
11344
11345 This field can be changed only when [H_CLKDIV_RST] = 1.
11346
11347 Internal:
11348 150MHz is from the maximum of:
11349 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 1, col 12.
11350 Synopsys DWC_usb3 Databook v2.80a, table A-17, row 7, col 9.
11351 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 7, col 9.
11352 DEVICE\>125MHz is from Synopsys DWC_usb3 Databook v2.80a, section A.12.4.
11353 HOST2\>62.5MHz in HOST mode is from Synopsys DWC_usb3 Databook v2.80a,
11354 section A.12.5, 3rd bullet in Note on page 894.
11355 HOST2\>90MHz was arrived at from some math: 62.5MHz +
11356 (diff between row 1 and 2, col 12 of table A-16). */
11357 uint64_t reserved_22_23 : 2;
11358 uint64_t usb3_port_perm_attach : 1; /**< [ 21: 21](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
11359 only when [UPHY_RST] is asserted. */
11360 uint64_t usb2_port_perm_attach : 1; /**< [ 20: 20](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
11361 only when [UPHY_RST] is asserted. */
11362 uint64_t reserved_19 : 1;
11363 uint64_t usb3_port_disable : 1; /**< [ 18: 18](R/W) Disables the USB3 (SuperSpeed) portion of this PHY. When set to 1, this signal stops
11364 reporting connect/disconnect events on the port and keeps the port in disabled state. This
11365 could be used for security reasons where hardware can disable a port regardless of whether
11366 xHCI driver enables a port or not.
11367 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
11368
11369 This is a strap signal; it should be modified only when [UPHY_RST] is asserted. */
11370 uint64_t reserved_17 : 1;
11371 uint64_t usb2_port_disable : 1; /**< [ 16: 16](R/W) Disables USB2 (high-speed/full-speed/low-speed) portion of this PHY. When set to 1, this
11372 signal stops reporting connect/disconnect events on the port and keeps the port in
11373 disabled state. This could be used for security reasons where hardware can disable a port
11374 regardless of whether xHCI driver enables a port or not.
11375 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
11376
11377 This is a strap signal; it should only be modified when [UPHY_RST] is asserted.
11378 If Port0 is required to be disabled, ensure that the utmi_clk[0] is running at the normal
11379 speed. Also, all the enabled USB2.0 ports should have the same clock frequency as Port0. */
11380 uint64_t reserved_15 : 1;
11381 uint64_t ss_power_en : 1; /**< [ 14: 14](R/W) PHY SuperSpeed block power enable.
11382 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
11383 uint64_t reserved_13 : 1;
11384 uint64_t hs_power_en : 1; /**< [ 12: 12](R/W) PHY high-speed block power enable.
11385 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
11386 uint64_t ref_clk_sel : 3; /**< [ 11: 9](R/W) Reference clock select. Choose reference-clock source for the SuperSpeed and high-speed
11387 PLL blocks.
11388 0x0 = Reference clock sources for both PLLs come from the USB pads.
11389 0x1 = Reserved.
11390 0x2 = Reserved.
11391 0x3 = Reserved.
11392 0x4 = Reserved.
11393 0x5 = Reserved.
11394 0x6 = Reserved.
11395 0x7 = Reserved.
11396
11397 This value can be changed only during UPHY_RST.
11398
11399 If [REF_CLK_SEL] = 0x0, 0x1, or 0x2 then the reference clock input cannot be
11400 spread-spectrum.
11401
11402 Internal:
11403 For the 0x6 selection, reference clock source for SuperSpeed PLL is from the USB
11404 pads, reference clock source for high-speed PLL is PLL_REF_CLK. But in CNXXXX,
11405 PLL_REF_CLK cannot be routed to USB without violating jitter requirements */
11406 uint64_t reserved_6_8 : 3;
11407 uint64_t dma_psn_ign : 1; /**< [ 5: 5](R/W) Handling of poison indication on DMA read responses.
11408 0 = Treat poison data the same way as fault, sending an AXI error to the USB
11409 controller.
11410 1 = Ignore poison and proceed with the transaction as if no problems. */
11411 uint64_t csclk_force : 1; /**< [ 4: 4](R/W) Force conditional clock to be running. For diagnostic use only.
11412 0 = No override.
11413 1 = Override the enable of conditional clock to force it running. */
11414 uint64_t drd_mode : 1; /**< [ 3: 3](R/W) Switches between host or device mode for USBDRD.
11415 0 = Host.
11416 1 = Device. */
11417 uint64_t uphy_rst : 1; /**< [ 2: 2](R/W) PHY reset; resets UPHY; active-high. */
11418 uint64_t uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
11419 Internal:
11420 Note that soft-resetting the UAHC while it is active may cause violations of RSL
11421 or NCB protocols. */
11422 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
11423 Resets UAHC DMA and register shims. Resets UCTL registers 0x30-0xF8.
11424 Does not reset UCTL registers 0x0-0x28.
11425 UCTL registers starting from 0x30 can be accessed only after the controller clock is
11426 active and [UCTL_RST] is deasserted.
11427
11428 Internal:
11429 Note that soft-resetting the UCTL while it is active may cause violations of
11430 RSL, NCB, and CIB protocols. */
11431 #else /* Word 0 - Little Endian */
11432 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
11433 Resets UAHC DMA and register shims. Resets UCTL registers 0x30-0xF8.
11434 Does not reset UCTL registers 0x0-0x28.
11435 UCTL registers starting from 0x30 can be accessed only after the controller clock is
11436 active and [UCTL_RST] is deasserted.
11437
11438 Internal:
11439 Note that soft-resetting the UCTL while it is active may cause violations of
11440 RSL, NCB, and CIB protocols. */
11441 uint64_t uahc_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAHC; active-high.
11442 Internal:
11443 Note that soft-resetting the UAHC while it is active may cause violations of RSL
11444 or NCB protocols. */
11445 uint64_t uphy_rst : 1; /**< [ 2: 2](R/W) PHY reset; resets UPHY; active-high. */
11446 uint64_t drd_mode : 1; /**< [ 3: 3](R/W) Switches between host or device mode for USBDRD.
11447 0 = Host.
11448 1 = Device. */
11449 uint64_t csclk_force : 1; /**< [ 4: 4](R/W) Force conditional clock to be running. For diagnostic use only.
11450 0 = No override.
11451 1 = Override the enable of conditional clock to force it running. */
11452 uint64_t dma_psn_ign : 1; /**< [ 5: 5](R/W) Handling of poison indication on DMA read responses.
11453 0 = Treat poison data the same way as fault, sending an AXI error to the USB
11454 controller.
11455 1 = Ignore poison and proceed with the transaction as if no problems. */
11456 uint64_t reserved_6_8 : 3;
11457 uint64_t ref_clk_sel : 3; /**< [ 11: 9](R/W) Reference clock select. Choose reference-clock source for the SuperSpeed and high-speed
11458 PLL blocks.
11459 0x0 = Reference clock sources for both PLLs come from the USB pads.
11460 0x1 = Reserved.
11461 0x2 = Reserved.
11462 0x3 = Reserved.
11463 0x4 = Reserved.
11464 0x5 = Reserved.
11465 0x6 = Reserved.
11466 0x7 = Reserved.
11467
11468 This value can be changed only during UPHY_RST.
11469
11470 If [REF_CLK_SEL] = 0x0, 0x1, or 0x2 then the reference clock input cannot be
11471 spread-spectrum.
11472
11473 Internal:
11474 For the 0x6 selection, reference clock source for SuperSpeed PLL is from the USB
11475 pads, reference clock source for high-speed PLL is PLL_REF_CLK. But in CNXXXX,
11476 PLL_REF_CLK cannot be routed to USB without violating jitter requirements */
11477 uint64_t hs_power_en : 1; /**< [ 12: 12](R/W) PHY high-speed block power enable.
11478 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
11479 uint64_t reserved_13 : 1;
11480 uint64_t ss_power_en : 1; /**< [ 14: 14](R/W) PHY SuperSpeed block power enable.
11481 This is a strap signal; it should only be modified when [UPHY_RST] is asserted. */
11482 uint64_t reserved_15 : 1;
11483 uint64_t usb2_port_disable : 1; /**< [ 16: 16](R/W) Disables USB2 (high-speed/full-speed/low-speed) portion of this PHY. When set to 1, this
11484 signal stops reporting connect/disconnect events on the port and keeps the port in
11485 disabled state. This could be used for security reasons where hardware can disable a port
11486 regardless of whether xHCI driver enables a port or not.
11487 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
11488
11489 This is a strap signal; it should only be modified when [UPHY_RST] is asserted.
11490 If Port0 is required to be disabled, ensure that the utmi_clk[0] is running at the normal
11491 speed. Also, all the enabled USB2.0 ports should have the same clock frequency as Port0. */
11492 uint64_t reserved_17 : 1;
11493 uint64_t usb3_port_disable : 1; /**< [ 18: 18](R/W) Disables the USB3 (SuperSpeed) portion of this PHY. When set to 1, this signal stops
11494 reporting connect/disconnect events on the port and keeps the port in disabled state. This
11495 could be used for security reasons where hardware can disable a port regardless of whether
11496 xHCI driver enables a port or not.
11497 USBDRD()_UAHC_HCSPARAMS1[MAXPORTS] is not affected by this signal.
11498
11499 This is a strap signal; it should be modified only when [UPHY_RST] is asserted. */
11500 uint64_t reserved_19 : 1;
11501 uint64_t usb2_port_perm_attach : 1; /**< [ 20: 20](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
11502 only when [UPHY_RST] is asserted. */
11503 uint64_t usb3_port_perm_attach : 1; /**< [ 21: 21](R/W) Indicates this port is permanently attached. This is a strap signal; it should be modified
11504 only when [UPHY_RST] is asserted. */
11505 uint64_t reserved_22_23 : 2;
11506 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) Controller clock-frequency-divider select. The controller-clock frequency is the
11507 coprocessor-clock frequency divided by [H_CLKDIV_SEL] and must be at or below 300 MHz.
11508 The divider values are the following:
11509 0x0 = divide by 1.
11510 0x1 = divide by 2.
11511 0x2 = divide by 4.
11512 0x3 = divide by 6.
11513 0x4 = divide by 8.
11514 0x5 = divide by 16.
11515 0x6 = divide by 24.
11516 0x7 = divide by 32.
11517
11518 The HCLK frequency must be at or below 300 MHz.
11519 The HCLK frequency must be at or above 150 MHz for full-rate USB3
11520 operation.
11521 The HCLK frequency must be at or above 125 MHz for any USB3
11522 functionality.
11523
11524 If [DRD_MODE] = DEVICE, the HCLK frequency must be at or above 125 MHz for
11525 correct USB2 functionality.
11526
11527 If [DRD_MODE] = HOST, the HCLK frequency must be at or above 90 MHz
11528 for full-rate USB2 operation.
11529
11530 If [DRD_MODE] = HOST, the HCLK frequency must be at or above 62.5 MHz
11531 for any USB2 operation.
11532
11533 This field can be changed only when [H_CLKDIV_RST] = 1.
11534
11535 Internal:
11536 150MHz is from the maximum of:
11537 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 1, col 12.
11538 Synopsys DWC_usb3 Databook v2.80a, table A-17, row 7, col 9.
11539 Synopsys DWC_usb3 Databook v2.80a, table A-16, row 7, col 9.
11540 DEVICE\>125MHz is from Synopsys DWC_usb3 Databook v2.80a, section A.12.4.
11541 HOST2\>62.5MHz in HOST mode is from Synopsys DWC_usb3 Databook v2.80a,
11542 section A.12.5, 3rd bullet in Note on page 894.
11543 HOST2\>90MHz was arrived at from some math: 62.5MHz +
11544 (diff between row 1 and 2, col 12 of table A-16). */
11545 uint64_t reserved_27 : 1;
11546 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) Controller clock divider reset. Divided clocks are not generated while the divider is
11547 being reset.
11548 This also resets the suspend-clock divider. */
11549 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the controller-clock divider.
11550 0 = Use the divided coprocessor clock from the H_CLKDIV divider.
11551 1 = Use the bypass clock from the GPIO pins.
11552
11553 This signal is just a multiplexer-select signal; it does not enable the controller clock.
11554 You must still set H_CLKDIV_EN separately. [H_CLK_BYP_SEL] select should not be changed
11555 unless H_CLKDIV_EN is disabled.
11556
11557 The bypass clock can be selected and running even if the controller-clock dividers are not
11558 running.
11559
11560 Internal:
11561 Generally bypass is only used for scan purposes. */
11562 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) Controller-clock enable. When set to 1, the controller clock is generated. This also
11563 enables access to UCTL registers 0x30-0xF8. */
11564 uint64_t cmd_flr_en : 1; /**< [ 31: 31](R/W) The host controller will stop accepting commands if this bit is set. This bit is
11565 for host_mode only.
11566
11567 In normal FLR, this bit should be set to 0. If software wants the command to
11568 finish before FLR, write this bit to 1 and poll USBDRD()_UAHC_USBSTS[HCH] to
11569 make sure the command is finished before disabling USBDRD's PCCPF_XXX_CMD[ME]. */
11570 uint64_t ref_clk_fsel : 6; /**< [ 37: 32](R/W) Selects the reference clock frequency for the SuperSpeed and high-speed PLL blocks.
11571
11572 As [REF_CLK_SEL] = 0x0, the legal values are:
11573
11574 0x27 = 100 MHz on DLMC_REF_CLK*.
11575
11576 All other values are reserved.
11577
11578 This value may only be changed during [UPHY_RST].
11579
11580 Internal:
11581 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
11582 0x27 = 100 MHz on DLMC_REF_CLK*.
11583 0x2A = 24 MHz on DLMC_REF_CLK*.
11584 0x31 = 20 MHz on DLMC_REF_CLK*.
11585 0x38 = 19.2MHz on DLMC_REF_CLK*.
11586
11587 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6 then:
11588 0x07 is the only legal value. */
11589 uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
11590
11591 As [REF_CLK_SEL] = 0x0, the legal value is 0x0.
11592
11593 This value can be changed only during UPHY_RST.
11594
11595 Internal:
11596 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then:
11597 all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
11598
11599 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
11600 0x1: if DLMC_REF_CLK* is 125MHz.
11601 0x1: if DLMC_REF_CLK* is 40MHz, 76.8MHz, or 200MHz.
11602 0x0, 0x1 if DLMC_REF_CLK* is 104MHz (depending on [MPLL_MULTIPLIER]).
11603 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
11604 [MPLL_MULTIPLIER] description). */
11605 uint64_t ref_ssp_en : 1; /**< [ 39: 39](R/W) Enables reference clock to the prescaler for SuperSpeed function. This should always be
11606 enabled since this output clock is used to drive the UAHC suspend-mode clock during
11607 low-power states.
11608
11609 This value can be changed only during UPHY_RST or during low-power states.
11610 The reference clock must be running and stable before [UPHY_RST] is deasserted and before
11611 [REF_SSP_EN] is asserted. */
11612 uint64_t mpll_multiplier : 7; /**< [ 46: 40](R/W) Multiplies the reference clock to a frequency suitable for intended operating speed.
11613
11614 As [REF_CLK_SEL] = 0x0, the legal values are:
11615
11616 0x19 = 100 MHz on DLMC_REF_CLK*.
11617
11618 All other values are reserved.
11619
11620 This value may only be changed during [UPHY_RST].
11621
11622 Internal:
11623 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
11624 0x19 = 100 MHz on DLMC_REF_CLK*.
11625 0x68 = 24 MHz on DLMC_REF_CLK*.
11626 0x7D = 20 MHz on DLMC_REF_CLK*.
11627 0x02 = 19.2MHz on DLMC_REF_CLK*.
11628
11629 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x06, then:
11630 0x02 = 19.2MHz on DLMC_REF_CLK*.
11631 0x7D = 20 MHz on DLMC_REF_CLK*.
11632 0x68 = 24 MHz on DLMC_REF_CLK*.
11633 0x64 = 25 MHz on DLMC_REF_CLK*.
11634 0x60 = 26 MHz on DLMC_REF_CLK*.
11635 0x41 = 38.4MHz on DLMC_REF_CLK*.
11636 0x7D = 40 MHz on DLMC_REF_CLK*.
11637 0x34 = 48 MHz on DLMC_REF_CLK*.
11638 0x32 = 50 MHz on DLMC_REF_CLK*.
11639 0x30 = 52 MHz on DLMC_REF_CLK*.
11640 0x41 = 76.8MHz on DLMC_REF_CLK*.
11641 0x1A = 96 MHz on DLMC_REF_CLK*.
11642 0x19 = 100 MHz on DLMC_REF_CLK*.
11643 0x30 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x1.
11644 0x18 = 104 MHz on DLMC_REF_CLK* if [REF_CLK_DIV2] = 0x0.
11645 0x28 = 125 MHz on DLMC_REF_CLK*.
11646 0x19 = 200 MHz on DLMC_REF_CLK*. */
11647 uint64_t ssc_ref_clk_sel : 9; /**< [ 55: 47](R/W) Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
11648 corresponds to the frequency-synthesis coefficient.
11649
11650 [55:53]: modulus - 1,
11651 [52:47]: 2's complement push amount.
11652
11653 A value of 0x0 means this feature is disabled.
11654
11655 The legal values are 0x0.
11656
11657 All other values are reserved.
11658
11659 This value may only be changed during [UPHY_RST].
11660
11661 Internal:
11662 If [REF_CLK_SEL] = 0x0, 0x1 or 0x2, then:
11663 * 0x0 is the only legal value.
11664
11665 If [REF_CLK_SEL] = 0x4 or 0x5 or 0x6, then:
11666 * 0x108: if DLMC_REF_CLK* is 19.2MHz, 24MHz, 26MHz, 38.4MHz, 48MHz,
11667 52MHz, 76.8MHz, 96MHz, 104MHz.
11668 * 0x0: if DLMC_REF_CLK* is another supported frequency (see list in
11669 [MPLL_MULTIPLIER] description). */
11670 uint64_t ssc_range : 3; /**< [ 58: 56](R/W) Spread-spectrum clock range. Selects the range of spread-spectrum modulation when SSC_EN
11671 is asserted and the PHY is spreading the SuperSpeed transmit clocks.
11672 Applies a fixed offset to the phase accumulator.
11673 0x0 = -4980 ppm downspread of clock.
11674 0x1 = -4492 ppm.
11675 0x2 = -4003 ppm.
11676 0x3-0x7 = reserved.
11677
11678 All of these settings are within the USB 3.0 specification. The amount of EMI emission
11679 reduction might decrease as the [SSC_RANGE] increases; therefore, the [SSC_RANGE] settings
11680 can
11681 be registered to enable the amount of spreading to be adjusted on a per-application basis.
11682 This value can be changed only during UPHY_RST. */
11683 uint64_t ssc_en : 1; /**< [ 59: 59](R/W) Spread-spectrum clock enable. Enables spread-spectrum clock production in the SuperSpeed
11684 function. If the input reference clock for the SuperSpeed PLL is already spread-spectrum,
11685 then do not enable this feature. The clocks sourced to the SuperSpeed function must have
11686 spread-spectrum to be compliant with the USB specification.
11687
11688 This value may only be changed during [UPHY_RST]. */
11689 uint64_t reserved_60_63 : 4;
11690 #endif /* Word 0 - End */
11691 } cn9;
11692 };
11693 typedef union bdk_usbdrdx_uctl_ctl bdk_usbdrdx_uctl_ctl_t;
11694
11695 static inline uint64_t BDK_USBDRDX_UCTL_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_CTL(unsigned long a)11696 static inline uint64_t BDK_USBDRDX_UCTL_CTL(unsigned long a)
11697 {
11698 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
11699 return 0x868000100000ll + 0x1000000000ll * ((a) & 0x1);
11700 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
11701 return 0x868000100000ll + 0x1000000000ll * ((a) & 0x1);
11702 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
11703 return 0x868000100000ll + 0x1000000000ll * ((a) & 0x1);
11704 __bdk_csr_fatal("USBDRDX_UCTL_CTL", 1, a, 0, 0, 0);
11705 }
11706
11707 #define typedef_BDK_USBDRDX_UCTL_CTL(a) bdk_usbdrdx_uctl_ctl_t
11708 #define bustype_BDK_USBDRDX_UCTL_CTL(a) BDK_CSR_TYPE_NCB
11709 #define basename_BDK_USBDRDX_UCTL_CTL(a) "USBDRDX_UCTL_CTL"
11710 #define device_bar_BDK_USBDRDX_UCTL_CTL(a) 0x0 /* PF_BAR0 */
11711 #define busnum_BDK_USBDRDX_UCTL_CTL(a) (a)
11712 #define arguments_BDK_USBDRDX_UCTL_CTL(a) (a),-1,-1,-1
11713
11714 /**
11715 * Register (NCB) usbdrd#_uctl_ecc
11716 *
11717 * USB UCTL ECC Control Register
11718 * This register can be used to disable ECC correction, insert ECC errors, and debug ECC
11719 * failures.
11720 * * The ECC_ERR* fields are captured when there are no outstanding ECC errors indicated in
11721 * INTSTAT and a new ECC error arrives. Prioritization for multiple events occurring on the same
11722 * cycle is indicated by the ECC_ERR_SOURCE enumeration: highest encoded value has highest
11723 * priority.
11724 * * The *ECC_*_DIS fields disable ECC correction; SBE and DBE errors are still reported. If
11725 * *ECC_*_DIS = 0x1, then no data-correction occurs.
11726 * * The *ECC_FLIP_SYND fields flip the syndrome\<1:0\> bits to generate single-bit/double-bit
11727 * error for testing.
11728 *
11729 * 0x0 = Normal operation.
11730 * 0x1 = SBE on bit[0].
11731 * 0x2 = SBE on bit[1].
11732 * 0x3 = DBE on bit[1:0].
11733 *
11734 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
11735 *
11736 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
11737 */
11738 union bdk_usbdrdx_uctl_ecc
11739 {
11740 uint64_t u;
11741 struct bdk_usbdrdx_uctl_ecc_s
11742 {
11743 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11744 uint64_t reserved_60_63 : 4;
11745 uint64_t ecc_err_source : 4; /**< [ 59: 56](RO/H) Source of ECC error, see UCTL_ECC_ERR_SOURCE_E. */
11746 uint64_t ecc_err_syndrome : 8; /**< [ 55: 48](RO/H) Syndrome bits of the ECC error. */
11747 uint64_t ecc_err_address : 16; /**< [ 47: 32](RO/H) RAM address of the ECC error. */
11748 uint64_t reserved_21_31 : 11;
11749 uint64_t uctl_xm_r_ecc_flip_synd : 2;/**< [ 20: 19](R/W) Insert ECC error for testing purposes. */
11750 uint64_t uctl_xm_r_ecc_cor_dis : 1; /**< [ 18: 18](R/W) Enables ECC correction on UCTL AxiMaster read-data FIFO. */
11751 uint64_t uctl_xm_w_ecc_flip_synd : 2;/**< [ 17: 16](R/W) Insert ECC error for testing purposes. */
11752 uint64_t uctl_xm_w_ecc_cor_dis : 1; /**< [ 15: 15](R/W) Enables ECC correction on UCTL AxiMaster write-data FIFO. */
11753 uint64_t reserved_9_14 : 6;
11754 uint64_t uahc_ram2_ecc_flip_synd : 2;/**< [ 8: 7](R/W) Insert ECC error for testing purposes. */
11755 uint64_t uahc_ram2_ecc_cor_dis : 1; /**< [ 6: 6](R/W) Enables ECC correction on UAHC RxFIFO RAMs (RAM2). */
11756 uint64_t uahc_ram1_ecc_flip_synd : 2;/**< [ 5: 4](R/W) Insert ECC error for testing purposes. */
11757 uint64_t uahc_ram1_ecc_cor_dis : 1; /**< [ 3: 3](R/W) Enables ECC correction on UAHC TxFIFO RAMs (RAM1). */
11758 uint64_t uahc_ram0_ecc_flip_synd : 2;/**< [ 2: 1](R/W) Insert ECC error for testing purposes. */
11759 uint64_t uahc_ram0_ecc_cor_dis : 1; /**< [ 0: 0](R/W) Enables ECC correction on UAHC Desc/Reg cache (RAM0). */
11760 #else /* Word 0 - Little Endian */
11761 uint64_t uahc_ram0_ecc_cor_dis : 1; /**< [ 0: 0](R/W) Enables ECC correction on UAHC Desc/Reg cache (RAM0). */
11762 uint64_t uahc_ram0_ecc_flip_synd : 2;/**< [ 2: 1](R/W) Insert ECC error for testing purposes. */
11763 uint64_t uahc_ram1_ecc_cor_dis : 1; /**< [ 3: 3](R/W) Enables ECC correction on UAHC TxFIFO RAMs (RAM1). */
11764 uint64_t uahc_ram1_ecc_flip_synd : 2;/**< [ 5: 4](R/W) Insert ECC error for testing purposes. */
11765 uint64_t uahc_ram2_ecc_cor_dis : 1; /**< [ 6: 6](R/W) Enables ECC correction on UAHC RxFIFO RAMs (RAM2). */
11766 uint64_t uahc_ram2_ecc_flip_synd : 2;/**< [ 8: 7](R/W) Insert ECC error for testing purposes. */
11767 uint64_t reserved_9_14 : 6;
11768 uint64_t uctl_xm_w_ecc_cor_dis : 1; /**< [ 15: 15](R/W) Enables ECC correction on UCTL AxiMaster write-data FIFO. */
11769 uint64_t uctl_xm_w_ecc_flip_synd : 2;/**< [ 17: 16](R/W) Insert ECC error for testing purposes. */
11770 uint64_t uctl_xm_r_ecc_cor_dis : 1; /**< [ 18: 18](R/W) Enables ECC correction on UCTL AxiMaster read-data FIFO. */
11771 uint64_t uctl_xm_r_ecc_flip_synd : 2;/**< [ 20: 19](R/W) Insert ECC error for testing purposes. */
11772 uint64_t reserved_21_31 : 11;
11773 uint64_t ecc_err_address : 16; /**< [ 47: 32](RO/H) RAM address of the ECC error. */
11774 uint64_t ecc_err_syndrome : 8; /**< [ 55: 48](RO/H) Syndrome bits of the ECC error. */
11775 uint64_t ecc_err_source : 4; /**< [ 59: 56](RO/H) Source of ECC error, see UCTL_ECC_ERR_SOURCE_E. */
11776 uint64_t reserved_60_63 : 4;
11777 #endif /* Word 0 - End */
11778 } s;
11779 /* struct bdk_usbdrdx_uctl_ecc_s cn; */
11780 };
11781 typedef union bdk_usbdrdx_uctl_ecc bdk_usbdrdx_uctl_ecc_t;
11782
11783 static inline uint64_t BDK_USBDRDX_UCTL_ECC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_ECC(unsigned long a)11784 static inline uint64_t BDK_USBDRDX_UCTL_ECC(unsigned long a)
11785 {
11786 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
11787 return 0x8680001000f0ll + 0x1000000000ll * ((a) & 0x1);
11788 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
11789 return 0x8680001000f0ll + 0x1000000000ll * ((a) & 0x1);
11790 __bdk_csr_fatal("USBDRDX_UCTL_ECC", 1, a, 0, 0, 0);
11791 }
11792
11793 #define typedef_BDK_USBDRDX_UCTL_ECC(a) bdk_usbdrdx_uctl_ecc_t
11794 #define bustype_BDK_USBDRDX_UCTL_ECC(a) BDK_CSR_TYPE_NCB
11795 #define basename_BDK_USBDRDX_UCTL_ECC(a) "USBDRDX_UCTL_ECC"
11796 #define device_bar_BDK_USBDRDX_UCTL_ECC(a) 0x0 /* PF_BAR0 */
11797 #define busnum_BDK_USBDRDX_UCTL_ECC(a) (a)
11798 #define arguments_BDK_USBDRDX_UCTL_ECC(a) (a),-1,-1,-1
11799
11800 /**
11801 * Register (NCB) usbdrd#_uctl_host_cfg
11802 *
11803 * USB UCTL Host Controller Configuration Register
11804 * This register allows configuration of various host controller (UAHC) features. Most of these
11805 * are strap signals and should be modified only while the controller is not running.
11806 *
11807 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
11808 *
11809 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
11810 */
11811 union bdk_usbdrdx_uctl_host_cfg
11812 {
11813 uint64_t u;
11814 struct bdk_usbdrdx_uctl_host_cfg_s
11815 {
11816 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11817 uint64_t reserved_60_63 : 4;
11818 uint64_t host_current_belt : 12; /**< [ 59: 48](RO) This signal indicates the minimum value of all received BELT values and the BELT that is
11819 set by the Set LTV command. */
11820 uint64_t reserved_38_47 : 10;
11821 uint64_t fla : 6; /**< [ 37: 32](R/W) High-speed jitter adjustment. Indicates the correction required to accommodate mac3 clock
11822 and utmi clock jitter to measure 125 us duration. With FLA tied to 0x0, the high-speed
11823 125 us micro-frame is counted for 123933 ns. The value needs to be programmed in terms of
11824 high-speed bit times in a 30 MHz cycle. Default value that needs to be driven is 0x20
11825 (assuming 30 MHz perfect clock).
11826
11827 FLA connects to the FLADJ register defined in the xHCI spec in the PCI configuration
11828 space. Each count is equal to 16 high-speed bit times. By default when this register is
11829 set to 0x20, it gives 125 us interval. Now, based on the clock accuracy, you can decrement
11830 the count or increment the count to get the 125 us uSOF window.
11831 This is a strap signal; it should only be modified when UAHC is in reset (soft-reset
11832 okay). */
11833 uint64_t reserved_29_31 : 3;
11834 uint64_t bme : 1; /**< [ 28: 28](R/W) Bus-master enable. This signal is used to disable the bus-mastering capability of the
11835 host. Disabling this capability stalls DMA accesses. */
11836 uint64_t oci_en : 1; /**< [ 27: 27](R/W) Overcurrent-indication enable. When enabled, OCI input to UAHC is taken from the GPIO
11837 signals and sense-converted based on [OCI_ACTIVE_HIGH_EN]. The MIO GPIO multiplexer must be
11838 programmed accordingly.
11839
11840 When disabled, OCI input to UAHC is forced to the correct inactive state based on
11841 [OCI_ACTIVE_HIGH_EN].
11842
11843 This is a strap signal; it should only be modified when UAHC is in reset (soft-reset
11844 okay). */
11845 uint64_t oci_active_high_en : 1; /**< [ 26: 26](R/W) Overcurrent sense selection. The off-chip sense (high/low) is converted to match the
11846 controller's active-high sense.
11847 0 = Overcurrent indication from off-chip source is active-low.
11848 1 = Overcurrent indication from off-chip source is active-high.
11849
11850 This is a strap signal; it should only be modified when UAHC is in reset (soft-reset
11851 okay). */
11852 uint64_t ppc_en : 1; /**< [ 25: 25](R/W) Port-power-control enable.
11853 0 = USBDRD()_UAHC_HCCPARAMS[PPC] report port-power-control feature is unavailable.
11854 1 = USBDRD()_UAHC_HCCPARAMS[PPC] reports port-power-control feature is available. PPC
11855 output
11856 from UAHC is taken to the GPIO signals and sense-converted based on [PPC_ACTIVE_HIGH_EN].
11857
11858 The MIO GPIO multiplexer must be programmed accordingly.
11859
11860 This is a strap signal; it should only be modified when either the UCTL_CTL[UAHC] or
11861 UAHC_GCTL[CoreSoftReset] is asserted. */
11862 uint64_t ppc_active_high_en : 1; /**< [ 24: 24](R/W) Port power control sense selection. The active-high port-power-control output to off-chip
11863 source is converted to match the off-chip sense.
11864 0 = Port-power control to off-chip source is active-low.
11865 1 = Port-power control to off-chip source is active-high.
11866
11867 This is a strap signal; it should only be modified when either the UCTL_CTL[UAHC] or
11868 UAHC_GCTL[CoreSoftReset] is asserted. */
11869 uint64_t reserved_0_23 : 24;
11870 #else /* Word 0 - Little Endian */
11871 uint64_t reserved_0_23 : 24;
11872 uint64_t ppc_active_high_en : 1; /**< [ 24: 24](R/W) Port power control sense selection. The active-high port-power-control output to off-chip
11873 source is converted to match the off-chip sense.
11874 0 = Port-power control to off-chip source is active-low.
11875 1 = Port-power control to off-chip source is active-high.
11876
11877 This is a strap signal; it should only be modified when either the UCTL_CTL[UAHC] or
11878 UAHC_GCTL[CoreSoftReset] is asserted. */
11879 uint64_t ppc_en : 1; /**< [ 25: 25](R/W) Port-power-control enable.
11880 0 = USBDRD()_UAHC_HCCPARAMS[PPC] report port-power-control feature is unavailable.
11881 1 = USBDRD()_UAHC_HCCPARAMS[PPC] reports port-power-control feature is available. PPC
11882 output
11883 from UAHC is taken to the GPIO signals and sense-converted based on [PPC_ACTIVE_HIGH_EN].
11884
11885 The MIO GPIO multiplexer must be programmed accordingly.
11886
11887 This is a strap signal; it should only be modified when either the UCTL_CTL[UAHC] or
11888 UAHC_GCTL[CoreSoftReset] is asserted. */
11889 uint64_t oci_active_high_en : 1; /**< [ 26: 26](R/W) Overcurrent sense selection. The off-chip sense (high/low) is converted to match the
11890 controller's active-high sense.
11891 0 = Overcurrent indication from off-chip source is active-low.
11892 1 = Overcurrent indication from off-chip source is active-high.
11893
11894 This is a strap signal; it should only be modified when UAHC is in reset (soft-reset
11895 okay). */
11896 uint64_t oci_en : 1; /**< [ 27: 27](R/W) Overcurrent-indication enable. When enabled, OCI input to UAHC is taken from the GPIO
11897 signals and sense-converted based on [OCI_ACTIVE_HIGH_EN]. The MIO GPIO multiplexer must be
11898 programmed accordingly.
11899
11900 When disabled, OCI input to UAHC is forced to the correct inactive state based on
11901 [OCI_ACTIVE_HIGH_EN].
11902
11903 This is a strap signal; it should only be modified when UAHC is in reset (soft-reset
11904 okay). */
11905 uint64_t bme : 1; /**< [ 28: 28](R/W) Bus-master enable. This signal is used to disable the bus-mastering capability of the
11906 host. Disabling this capability stalls DMA accesses. */
11907 uint64_t reserved_29_31 : 3;
11908 uint64_t fla : 6; /**< [ 37: 32](R/W) High-speed jitter adjustment. Indicates the correction required to accommodate mac3 clock
11909 and utmi clock jitter to measure 125 us duration. With FLA tied to 0x0, the high-speed
11910 125 us micro-frame is counted for 123933 ns. The value needs to be programmed in terms of
11911 high-speed bit times in a 30 MHz cycle. Default value that needs to be driven is 0x20
11912 (assuming 30 MHz perfect clock).
11913
11914 FLA connects to the FLADJ register defined in the xHCI spec in the PCI configuration
11915 space. Each count is equal to 16 high-speed bit times. By default when this register is
11916 set to 0x20, it gives 125 us interval. Now, based on the clock accuracy, you can decrement
11917 the count or increment the count to get the 125 us uSOF window.
11918 This is a strap signal; it should only be modified when UAHC is in reset (soft-reset
11919 okay). */
11920 uint64_t reserved_38_47 : 10;
11921 uint64_t host_current_belt : 12; /**< [ 59: 48](RO) This signal indicates the minimum value of all received BELT values and the BELT that is
11922 set by the Set LTV command. */
11923 uint64_t reserved_60_63 : 4;
11924 #endif /* Word 0 - End */
11925 } s;
11926 /* struct bdk_usbdrdx_uctl_host_cfg_s cn; */
11927 };
11928 typedef union bdk_usbdrdx_uctl_host_cfg bdk_usbdrdx_uctl_host_cfg_t;
11929
11930 static inline uint64_t BDK_USBDRDX_UCTL_HOST_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_HOST_CFG(unsigned long a)11931 static inline uint64_t BDK_USBDRDX_UCTL_HOST_CFG(unsigned long a)
11932 {
11933 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
11934 return 0x8680001000e0ll + 0x1000000000ll * ((a) & 0x1);
11935 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
11936 return 0x8680001000e0ll + 0x1000000000ll * ((a) & 0x1);
11937 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
11938 return 0x8680001000e0ll + 0x1000000000ll * ((a) & 0x1);
11939 __bdk_csr_fatal("USBDRDX_UCTL_HOST_CFG", 1, a, 0, 0, 0);
11940 }
11941
11942 #define typedef_BDK_USBDRDX_UCTL_HOST_CFG(a) bdk_usbdrdx_uctl_host_cfg_t
11943 #define bustype_BDK_USBDRDX_UCTL_HOST_CFG(a) BDK_CSR_TYPE_NCB
11944 #define basename_BDK_USBDRDX_UCTL_HOST_CFG(a) "USBDRDX_UCTL_HOST_CFG"
11945 #define device_bar_BDK_USBDRDX_UCTL_HOST_CFG(a) 0x0 /* PF_BAR0 */
11946 #define busnum_BDK_USBDRDX_UCTL_HOST_CFG(a) (a)
11947 #define arguments_BDK_USBDRDX_UCTL_HOST_CFG(a) (a),-1,-1,-1
11948
11949 /**
11950 * Register (NCB) usbdrd#_uctl_intena_w1c
11951 *
11952 * USB UCTL Interrupt Status Register
11953 * This register clears interrupt enable bits.
11954 */
11955 union bdk_usbdrdx_uctl_intena_w1c
11956 {
11957 uint64_t u;
11958 struct bdk_usbdrdx_uctl_intena_w1c_s
11959 {
11960 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11961 uint64_t reserved_30_63 : 34;
11962 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
11963 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
11964 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
11965 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
11966 uint64_t reserved_22_25 : 4;
11967 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
11968 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
11969 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
11970 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
11971 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
11972 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
11973 uint64_t reserved_8_15 : 8;
11974 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
11975 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
11976 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
11977 uint64_t reserved_3_4 : 2;
11978 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
11979 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
11980 uint64_t reserved_0 : 1;
11981 #else /* Word 0 - Little Endian */
11982 uint64_t reserved_0 : 1;
11983 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
11984 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
11985 uint64_t reserved_3_4 : 2;
11986 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
11987 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
11988 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
11989 uint64_t reserved_8_15 : 8;
11990 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
11991 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
11992 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
11993 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
11994 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
11995 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
11996 uint64_t reserved_22_25 : 4;
11997 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
11998 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
11999 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12000 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12001 uint64_t reserved_30_63 : 34;
12002 #endif /* Word 0 - End */
12003 } s;
12004 struct bdk_usbdrdx_uctl_intena_w1c_cn8
12005 {
12006 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12007 uint64_t reserved_30_63 : 34;
12008 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12009 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12010 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12011 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12012 uint64_t reserved_22_25 : 4;
12013 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12014 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12015 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12016 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12017 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12018 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12019 uint64_t reserved_8_15 : 8;
12020 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12021 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12022 uint64_t reserved_3_5 : 3;
12023 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12024 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12025 uint64_t reserved_0 : 1;
12026 #else /* Word 0 - Little Endian */
12027 uint64_t reserved_0 : 1;
12028 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12029 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12030 uint64_t reserved_3_5 : 3;
12031 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12032 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12033 uint64_t reserved_8_15 : 8;
12034 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12035 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12036 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12037 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12038 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12039 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12040 uint64_t reserved_22_25 : 4;
12041 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12042 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12043 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12044 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12045 uint64_t reserved_30_63 : 34;
12046 #endif /* Word 0 - End */
12047 } cn8;
12048 struct bdk_usbdrdx_uctl_intena_w1c_cn9
12049 {
12050 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12051 uint64_t reserved_8_63 : 56;
12052 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12053 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12054 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12055 uint64_t reserved_3_4 : 2;
12056 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12057 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12058 uint64_t reserved_0 : 1;
12059 #else /* Word 0 - Little Endian */
12060 uint64_t reserved_0 : 1;
12061 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12062 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12063 uint64_t reserved_3_4 : 2;
12064 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12065 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12066 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12067 uint64_t reserved_8_63 : 56;
12068 #endif /* Word 0 - End */
12069 } cn9;
12070 };
12071 typedef union bdk_usbdrdx_uctl_intena_w1c bdk_usbdrdx_uctl_intena_w1c_t;
12072
12073 static inline uint64_t BDK_USBDRDX_UCTL_INTENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_INTENA_W1C(unsigned long a)12074 static inline uint64_t BDK_USBDRDX_UCTL_INTENA_W1C(unsigned long a)
12075 {
12076 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
12077 return 0x868000100040ll + 0x1000000000ll * ((a) & 0x1);
12078 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
12079 return 0x868000100040ll + 0x1000000000ll * ((a) & 0x1);
12080 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
12081 return 0x868000100040ll + 0x1000000000ll * ((a) & 0x1);
12082 __bdk_csr_fatal("USBDRDX_UCTL_INTENA_W1C", 1, a, 0, 0, 0);
12083 }
12084
12085 #define typedef_BDK_USBDRDX_UCTL_INTENA_W1C(a) bdk_usbdrdx_uctl_intena_w1c_t
12086 #define bustype_BDK_USBDRDX_UCTL_INTENA_W1C(a) BDK_CSR_TYPE_NCB
12087 #define basename_BDK_USBDRDX_UCTL_INTENA_W1C(a) "USBDRDX_UCTL_INTENA_W1C"
12088 #define device_bar_BDK_USBDRDX_UCTL_INTENA_W1C(a) 0x0 /* PF_BAR0 */
12089 #define busnum_BDK_USBDRDX_UCTL_INTENA_W1C(a) (a)
12090 #define arguments_BDK_USBDRDX_UCTL_INTENA_W1C(a) (a),-1,-1,-1
12091
12092 /**
12093 * Register (NCB) usbdrd#_uctl_intena_w1s
12094 *
12095 * USB UCTL Interrupt Status Register
12096 * This register sets interrupt enable bits.
12097 */
12098 union bdk_usbdrdx_uctl_intena_w1s
12099 {
12100 uint64_t u;
12101 struct bdk_usbdrdx_uctl_intena_w1s_s
12102 {
12103 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12104 uint64_t reserved_30_63 : 34;
12105 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12106 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12107 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12108 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12109 uint64_t reserved_22_25 : 4;
12110 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12111 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12112 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12113 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12114 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12115 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12116 uint64_t reserved_8_15 : 8;
12117 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12118 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12119 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12120 uint64_t reserved_3_4 : 2;
12121 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12122 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12123 uint64_t reserved_0 : 1;
12124 #else /* Word 0 - Little Endian */
12125 uint64_t reserved_0 : 1;
12126 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12127 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12128 uint64_t reserved_3_4 : 2;
12129 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12130 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12131 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12132 uint64_t reserved_8_15 : 8;
12133 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12134 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12135 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12136 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12137 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12138 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12139 uint64_t reserved_22_25 : 4;
12140 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12141 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12142 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12143 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12144 uint64_t reserved_30_63 : 34;
12145 #endif /* Word 0 - End */
12146 } s;
12147 struct bdk_usbdrdx_uctl_intena_w1s_cn8
12148 {
12149 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12150 uint64_t reserved_30_63 : 34;
12151 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12152 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12153 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12154 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12155 uint64_t reserved_22_25 : 4;
12156 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12157 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12158 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12159 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12160 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12161 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12162 uint64_t reserved_8_15 : 8;
12163 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12164 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12165 uint64_t reserved_3_5 : 3;
12166 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12167 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12168 uint64_t reserved_0 : 1;
12169 #else /* Word 0 - Little Endian */
12170 uint64_t reserved_0 : 1;
12171 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12172 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12173 uint64_t reserved_3_5 : 3;
12174 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12175 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12176 uint64_t reserved_8_15 : 8;
12177 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12178 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12179 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12180 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12181 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12182 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12183 uint64_t reserved_22_25 : 4;
12184 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12185 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12186 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12187 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12188 uint64_t reserved_30_63 : 34;
12189 #endif /* Word 0 - End */
12190 } cn8;
12191 struct bdk_usbdrdx_uctl_intena_w1s_cn9
12192 {
12193 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12194 uint64_t reserved_8_63 : 56;
12195 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12196 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12197 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12198 uint64_t reserved_3_4 : 2;
12199 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12200 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12201 uint64_t reserved_0 : 1;
12202 #else /* Word 0 - Little Endian */
12203 uint64_t reserved_0 : 1;
12204 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12205 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12206 uint64_t reserved_3_4 : 2;
12207 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12208 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12209 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12210 uint64_t reserved_8_63 : 56;
12211 #endif /* Word 0 - End */
12212 } cn9;
12213 };
12214 typedef union bdk_usbdrdx_uctl_intena_w1s bdk_usbdrdx_uctl_intena_w1s_t;
12215
12216 static inline uint64_t BDK_USBDRDX_UCTL_INTENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_INTENA_W1S(unsigned long a)12217 static inline uint64_t BDK_USBDRDX_UCTL_INTENA_W1S(unsigned long a)
12218 {
12219 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
12220 return 0x868000100048ll + 0x1000000000ll * ((a) & 0x1);
12221 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
12222 return 0x868000100048ll + 0x1000000000ll * ((a) & 0x1);
12223 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
12224 return 0x868000100048ll + 0x1000000000ll * ((a) & 0x1);
12225 __bdk_csr_fatal("USBDRDX_UCTL_INTENA_W1S", 1, a, 0, 0, 0);
12226 }
12227
12228 #define typedef_BDK_USBDRDX_UCTL_INTENA_W1S(a) bdk_usbdrdx_uctl_intena_w1s_t
12229 #define bustype_BDK_USBDRDX_UCTL_INTENA_W1S(a) BDK_CSR_TYPE_NCB
12230 #define basename_BDK_USBDRDX_UCTL_INTENA_W1S(a) "USBDRDX_UCTL_INTENA_W1S"
12231 #define device_bar_BDK_USBDRDX_UCTL_INTENA_W1S(a) 0x0 /* PF_BAR0 */
12232 #define busnum_BDK_USBDRDX_UCTL_INTENA_W1S(a) (a)
12233 #define arguments_BDK_USBDRDX_UCTL_INTENA_W1S(a) (a),-1,-1,-1
12234
12235 /**
12236 * Register (NCB) usbdrd#_uctl_intstat
12237 *
12238 * USB UCTL Interrupt Status Register
12239 * This register provides a summary of interrupts. DBEs are detected and
12240 * SBE are corrected. For debugging output for ECC DBEs/SBEs, see USBDRD()_UCTL_ECC. This
12241 * register can be reset by NCB reset.
12242 */
12243 union bdk_usbdrdx_uctl_intstat
12244 {
12245 uint64_t u;
12246 struct bdk_usbdrdx_uctl_intstat_s
12247 {
12248 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12249 uint64_t reserved_30_63 : 34;
12250 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1C/H) Detected double-bit error on the UCTL AxiMaster read-data FIFO. */
12251 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1C/H) Detected single-bit error on the UCTL AxiMaster read-data FIFO. */
12252 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1C/H) Detected double-bit error on the UCTL AxiMaster write-data FIFO. */
12253 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1C/H) Detected single-bit error on the UCTL AxiMaster write-data FIFO. */
12254 uint64_t reserved_22_25 : 4;
12255 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1C/H) Detected double-bit error on the UAHC RxFIFO RAMs (RAM2). */
12256 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1C/H) Detected single-bit error on the UAHC RxFIFO RAMs (RAM2). */
12257 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1C/H) Detected double-bit error on the UAHC TxFIFO RAMs (RAM1). */
12258 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1C/H) Detected single-bit error on the UAHC TxFIFO RAMs (RAM1). */
12259 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1C/H) Detected double-bit error on the UAHC Desc/Reg Cache (RAM0). */
12260 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1C/H) Detected single-bit error on the UAHC Desc/Reg Cache (RAM0). */
12261 uint64_t reserved_8_15 : 8;
12262 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
12263 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
12264 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Received DMA read response with poisoned data from NCBO. Hardware also sets
12265 USBDRD()_UCTL_RAS[DMA_PSN]. */
12266 uint64_t reserved_3_4 : 2;
12267 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Detected bad DMA access from UAHC to NCB. Error information is logged in
12268 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates the
12269 assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
12270 combinations and address out-of-bounds.
12271
12272 For more information on exact failures, see the description in
12273 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE]. The hardware does not translate the request
12274 correctly
12275 and results may violate NCB protocols. */
12276 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1 MB of register
12277 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
12278 to be set to 1. Error information is logged in USBDRD()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
12279 uint64_t reserved_0 : 1;
12280 #else /* Word 0 - Little Endian */
12281 uint64_t reserved_0 : 1;
12282 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1 MB of register
12283 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
12284 to be set to 1. Error information is logged in USBDRD()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
12285 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Detected bad DMA access from UAHC to NCB. Error information is logged in
12286 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates the
12287 assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
12288 combinations and address out-of-bounds.
12289
12290 For more information on exact failures, see the description in
12291 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE]. The hardware does not translate the request
12292 correctly
12293 and results may violate NCB protocols. */
12294 uint64_t reserved_3_4 : 2;
12295 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Received DMA read response with poisoned data from NCBO. Hardware also sets
12296 USBDRD()_UCTL_RAS[DMA_PSN]. */
12297 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
12298 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
12299 uint64_t reserved_8_15 : 8;
12300 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1C/H) Detected single-bit error on the UAHC Desc/Reg Cache (RAM0). */
12301 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1C/H) Detected double-bit error on the UAHC Desc/Reg Cache (RAM0). */
12302 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1C/H) Detected single-bit error on the UAHC TxFIFO RAMs (RAM1). */
12303 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1C/H) Detected double-bit error on the UAHC TxFIFO RAMs (RAM1). */
12304 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1C/H) Detected single-bit error on the UAHC RxFIFO RAMs (RAM2). */
12305 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1C/H) Detected double-bit error on the UAHC RxFIFO RAMs (RAM2). */
12306 uint64_t reserved_22_25 : 4;
12307 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1C/H) Detected single-bit error on the UCTL AxiMaster write-data FIFO. */
12308 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1C/H) Detected double-bit error on the UCTL AxiMaster write-data FIFO. */
12309 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1C/H) Detected single-bit error on the UCTL AxiMaster read-data FIFO. */
12310 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1C/H) Detected double-bit error on the UCTL AxiMaster read-data FIFO. */
12311 uint64_t reserved_30_63 : 34;
12312 #endif /* Word 0 - End */
12313 } s;
12314 struct bdk_usbdrdx_uctl_intstat_cn8
12315 {
12316 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12317 uint64_t reserved_30_63 : 34;
12318 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1C/H) Detected double-bit error on the UCTL AxiMaster read-data FIFO. */
12319 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1C/H) Detected single-bit error on the UCTL AxiMaster read-data FIFO. */
12320 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1C/H) Detected double-bit error on the UCTL AxiMaster write-data FIFO. */
12321 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1C/H) Detected single-bit error on the UCTL AxiMaster write-data FIFO. */
12322 uint64_t reserved_22_25 : 4;
12323 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1C/H) Detected double-bit error on the UAHC RxFIFO RAMs (RAM2). */
12324 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1C/H) Detected single-bit error on the UAHC RxFIFO RAMs (RAM2). */
12325 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1C/H) Detected double-bit error on the UAHC TxFIFO RAMs (RAM1). */
12326 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1C/H) Detected single-bit error on the UAHC TxFIFO RAMs (RAM1). */
12327 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1C/H) Detected double-bit error on the UAHC Desc/Reg Cache (RAM0). */
12328 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1C/H) Detected single-bit error on the UAHC Desc/Reg Cache (RAM0). */
12329 uint64_t reserved_8_15 : 8;
12330 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
12331 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
12332 uint64_t reserved_3_5 : 3;
12333 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Detected bad DMA access from UAHC to NCB. Error information is logged in
12334 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates the
12335 assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
12336 combinations and address out-of-bounds.
12337
12338 For more information on exact failures, see the description in
12339 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE]. The hardware does not translate the request
12340 correctly
12341 and results may violate NCB protocols. */
12342 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1 MB of register
12343 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
12344 to be set to 1. Error information is logged in USBDRD()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
12345 uint64_t reserved_0 : 1;
12346 #else /* Word 0 - Little Endian */
12347 uint64_t reserved_0 : 1;
12348 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1 MB of register
12349 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
12350 to be set to 1. Error information is logged in USBDRD()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
12351 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Detected bad DMA access from UAHC to NCB. Error information is logged in
12352 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates the
12353 assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
12354 combinations and address out-of-bounds.
12355
12356 For more information on exact failures, see the description in
12357 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE]. The hardware does not translate the request
12358 correctly
12359 and results may violate NCB protocols. */
12360 uint64_t reserved_3_5 : 3;
12361 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
12362 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
12363 uint64_t reserved_8_15 : 8;
12364 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1C/H) Detected single-bit error on the UAHC Desc/Reg Cache (RAM0). */
12365 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1C/H) Detected double-bit error on the UAHC Desc/Reg Cache (RAM0). */
12366 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1C/H) Detected single-bit error on the UAHC TxFIFO RAMs (RAM1). */
12367 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1C/H) Detected double-bit error on the UAHC TxFIFO RAMs (RAM1). */
12368 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1C/H) Detected single-bit error on the UAHC RxFIFO RAMs (RAM2). */
12369 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1C/H) Detected double-bit error on the UAHC RxFIFO RAMs (RAM2). */
12370 uint64_t reserved_22_25 : 4;
12371 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1C/H) Detected single-bit error on the UCTL AxiMaster write-data FIFO. */
12372 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1C/H) Detected double-bit error on the UCTL AxiMaster write-data FIFO. */
12373 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1C/H) Detected single-bit error on the UCTL AxiMaster read-data FIFO. */
12374 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1C/H) Detected double-bit error on the UCTL AxiMaster read-data FIFO. */
12375 uint64_t reserved_30_63 : 34;
12376 #endif /* Word 0 - End */
12377 } cn8;
12378 struct bdk_usbdrdx_uctl_intstat_cn9
12379 {
12380 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12381 uint64_t reserved_8_63 : 56;
12382 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
12383 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
12384 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Received DMA read response with poisoned data from NCBO. Hardware also sets
12385 USBDRD()_UCTL_RAS[DMA_PSN]. */
12386 uint64_t reserved_3_4 : 2;
12387 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Detected bad DMA access from UAHC to NCB. Error information is logged in
12388 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates the
12389 assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
12390 combinations and address out-of-bounds.
12391
12392 For more information on exact failures, see the description in
12393 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE]. The hardware does not translate the request
12394 correctly
12395 and results may violate NCB protocols. */
12396 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1 MB of register
12397 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
12398 to be set to 1. Error information is logged in USBDRD()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
12399 uint64_t reserved_0 : 1;
12400 #else /* Word 0 - Little Endian */
12401 uint64_t reserved_0 : 1;
12402 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1C/H) Detected out-of-bound register access to UAHC over NCB. The UAHC defines 1 MB of register
12403 space, starting at offset 0x0. Any accesses outside of this register space cause this bit
12404 to be set to 1. Error information is logged in USBDRD()_UCTL_SHIM_CFG[XS_NCB_OOB_*]. */
12405 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1C/H) Detected bad DMA access from UAHC to NCB. Error information is logged in
12406 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_*]. Received a DMA request from UAHC that violates the
12407 assumptions made by the AXI-to-NCB shim. Such scenarios include: illegal length/size
12408 combinations and address out-of-bounds.
12409
12410 For more information on exact failures, see the description in
12411 USBDRD()_UCTL_SHIM_CFG[XM_BAD_DMA_TYPE]. The hardware does not translate the request
12412 correctly
12413 and results may violate NCB protocols. */
12414 uint64_t reserved_3_4 : 2;
12415 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1C/H) Received DMA read response with poisoned data from NCBO. Hardware also sets
12416 USBDRD()_UCTL_RAS[DMA_PSN]. */
12417 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1C/H) Received DMA write response fault error from NCBO. */
12418 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1C/H) Received DMA read response fault error from NCBO. */
12419 uint64_t reserved_8_63 : 56;
12420 #endif /* Word 0 - End */
12421 } cn9;
12422 };
12423 typedef union bdk_usbdrdx_uctl_intstat bdk_usbdrdx_uctl_intstat_t;
12424
12425 static inline uint64_t BDK_USBDRDX_UCTL_INTSTAT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_INTSTAT(unsigned long a)12426 static inline uint64_t BDK_USBDRDX_UCTL_INTSTAT(unsigned long a)
12427 {
12428 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
12429 return 0x868000100030ll + 0x1000000000ll * ((a) & 0x1);
12430 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
12431 return 0x868000100030ll + 0x1000000000ll * ((a) & 0x1);
12432 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
12433 return 0x868000100030ll + 0x1000000000ll * ((a) & 0x1);
12434 __bdk_csr_fatal("USBDRDX_UCTL_INTSTAT", 1, a, 0, 0, 0);
12435 }
12436
12437 #define typedef_BDK_USBDRDX_UCTL_INTSTAT(a) bdk_usbdrdx_uctl_intstat_t
12438 #define bustype_BDK_USBDRDX_UCTL_INTSTAT(a) BDK_CSR_TYPE_NCB
12439 #define basename_BDK_USBDRDX_UCTL_INTSTAT(a) "USBDRDX_UCTL_INTSTAT"
12440 #define device_bar_BDK_USBDRDX_UCTL_INTSTAT(a) 0x0 /* PF_BAR0 */
12441 #define busnum_BDK_USBDRDX_UCTL_INTSTAT(a) (a)
12442 #define arguments_BDK_USBDRDX_UCTL_INTSTAT(a) (a),-1,-1,-1
12443
12444 /**
12445 * Register (NCB) usbdrd#_uctl_intstat_w1s
12446 *
12447 * USB UCTL Interrupt Status Register
12448 * This register sets interrupt bits.
12449 */
12450 union bdk_usbdrdx_uctl_intstat_w1s
12451 {
12452 uint64_t u;
12453 struct bdk_usbdrdx_uctl_intstat_w1s_s
12454 {
12455 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12456 uint64_t reserved_30_63 : 34;
12457 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12458 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12459 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12460 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12461 uint64_t reserved_22_25 : 4;
12462 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12463 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12464 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12465 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12466 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12467 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12468 uint64_t reserved_8_15 : 8;
12469 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12470 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12471 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12472 uint64_t reserved_3_4 : 2;
12473 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12474 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12475 uint64_t reserved_0 : 1;
12476 #else /* Word 0 - Little Endian */
12477 uint64_t reserved_0 : 1;
12478 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12479 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12480 uint64_t reserved_3_4 : 2;
12481 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12482 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12483 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12484 uint64_t reserved_8_15 : 8;
12485 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12486 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12487 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12488 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12489 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12490 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12491 uint64_t reserved_22_25 : 4;
12492 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12493 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12494 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12495 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12496 uint64_t reserved_30_63 : 34;
12497 #endif /* Word 0 - End */
12498 } s;
12499 struct bdk_usbdrdx_uctl_intstat_w1s_cn8
12500 {
12501 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12502 uint64_t reserved_30_63 : 34;
12503 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12504 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12505 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12506 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12507 uint64_t reserved_22_25 : 4;
12508 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12509 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12510 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12511 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12512 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12513 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12514 uint64_t reserved_8_15 : 8;
12515 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12516 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12517 uint64_t reserved_3_5 : 3;
12518 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12519 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12520 uint64_t reserved_0 : 1;
12521 #else /* Word 0 - Little Endian */
12522 uint64_t reserved_0 : 1;
12523 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12524 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12525 uint64_t reserved_3_5 : 3;
12526 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12527 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12528 uint64_t reserved_8_15 : 8;
12529 uint64_t ram0_sbe : 1; /**< [ 16: 16](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM0_SBE]. */
12530 uint64_t ram0_dbe : 1; /**< [ 17: 17](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM0_DBE]. */
12531 uint64_t ram1_sbe : 1; /**< [ 18: 18](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM1_SBE]. */
12532 uint64_t ram1_dbe : 1; /**< [ 19: 19](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM1_DBE]. */
12533 uint64_t ram2_sbe : 1; /**< [ 20: 20](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM2_SBE]. */
12534 uint64_t ram2_dbe : 1; /**< [ 21: 21](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[RAM2_DBE]. */
12535 uint64_t reserved_22_25 : 4;
12536 uint64_t xm_w_sbe : 1; /**< [ 26: 26](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_W_SBE]. */
12537 uint64_t xm_w_dbe : 1; /**< [ 27: 27](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_W_DBE]. */
12538 uint64_t xm_r_sbe : 1; /**< [ 28: 28](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_R_SBE]. */
12539 uint64_t xm_r_dbe : 1; /**< [ 29: 29](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_R_DBE]. */
12540 uint64_t reserved_30_63 : 34;
12541 #endif /* Word 0 - End */
12542 } cn8;
12543 struct bdk_usbdrdx_uctl_intstat_w1s_cn9
12544 {
12545 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12546 uint64_t reserved_8_63 : 56;
12547 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12548 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12549 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12550 uint64_t reserved_3_4 : 2;
12551 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12552 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12553 uint64_t reserved_0 : 1;
12554 #else /* Word 0 - Little Endian */
12555 uint64_t reserved_0 : 1;
12556 uint64_t xs_ncb_oob : 1; /**< [ 1: 1](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XS_NCB_OOB]. */
12557 uint64_t xm_bad_dma : 1; /**< [ 2: 2](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[XM_BAD_DMA]. */
12558 uint64_t reserved_3_4 : 2;
12559 uint64_t dma_psn : 1; /**< [ 5: 5](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_PSN]. */
12560 uint64_t dma_wr_err : 1; /**< [ 6: 6](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_WR_ERR]. */
12561 uint64_t dma_rd_err : 1; /**< [ 7: 7](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_INTSTAT[DMA_RD_ERR]. */
12562 uint64_t reserved_8_63 : 56;
12563 #endif /* Word 0 - End */
12564 } cn9;
12565 };
12566 typedef union bdk_usbdrdx_uctl_intstat_w1s bdk_usbdrdx_uctl_intstat_w1s_t;
12567
12568 static inline uint64_t BDK_USBDRDX_UCTL_INTSTAT_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_INTSTAT_W1S(unsigned long a)12569 static inline uint64_t BDK_USBDRDX_UCTL_INTSTAT_W1S(unsigned long a)
12570 {
12571 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
12572 return 0x868000100038ll + 0x1000000000ll * ((a) & 0x1);
12573 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
12574 return 0x868000100038ll + 0x1000000000ll * ((a) & 0x1);
12575 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
12576 return 0x868000100038ll + 0x1000000000ll * ((a) & 0x1);
12577 __bdk_csr_fatal("USBDRDX_UCTL_INTSTAT_W1S", 1, a, 0, 0, 0);
12578 }
12579
12580 #define typedef_BDK_USBDRDX_UCTL_INTSTAT_W1S(a) bdk_usbdrdx_uctl_intstat_w1s_t
12581 #define bustype_BDK_USBDRDX_UCTL_INTSTAT_W1S(a) BDK_CSR_TYPE_NCB
12582 #define basename_BDK_USBDRDX_UCTL_INTSTAT_W1S(a) "USBDRDX_UCTL_INTSTAT_W1S"
12583 #define device_bar_BDK_USBDRDX_UCTL_INTSTAT_W1S(a) 0x0 /* PF_BAR0 */
12584 #define busnum_BDK_USBDRDX_UCTL_INTSTAT_W1S(a) (a)
12585 #define arguments_BDK_USBDRDX_UCTL_INTSTAT_W1S(a) (a),-1,-1,-1
12586
12587 /**
12588 * Register (NCB) usbdrd#_uctl_pipeclk_counter
12589 *
12590 * USB 3 Clock Counter Register
12591 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
12592 *
12593 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
12594 */
12595 union bdk_usbdrdx_uctl_pipeclk_counter
12596 {
12597 uint64_t u;
12598 struct bdk_usbdrdx_uctl_pipeclk_counter_s
12599 {
12600 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12601 uint64_t counter : 64; /**< [ 63: 0](R/W) Internal:
12602 USB 3.0 free running clock counter. Increments each edge of the USB 3.0 reference clock. */
12603 #else /* Word 0 - Little Endian */
12604 uint64_t counter : 64; /**< [ 63: 0](R/W) Internal:
12605 USB 3.0 free running clock counter. Increments each edge of the USB 3.0 reference clock. */
12606 #endif /* Word 0 - End */
12607 } s;
12608 /* struct bdk_usbdrdx_uctl_pipeclk_counter_s cn; */
12609 };
12610 typedef union bdk_usbdrdx_uctl_pipeclk_counter bdk_usbdrdx_uctl_pipeclk_counter_t;
12611
12612 static inline uint64_t BDK_USBDRDX_UCTL_PIPECLK_COUNTER(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_PIPECLK_COUNTER(unsigned long a)12613 static inline uint64_t BDK_USBDRDX_UCTL_PIPECLK_COUNTER(unsigned long a)
12614 {
12615 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
12616 return 0x868000100020ll + 0x1000000000ll * ((a) & 0x1);
12617 __bdk_csr_fatal("USBDRDX_UCTL_PIPECLK_COUNTER", 1, a, 0, 0, 0);
12618 }
12619
12620 #define typedef_BDK_USBDRDX_UCTL_PIPECLK_COUNTER(a) bdk_usbdrdx_uctl_pipeclk_counter_t
12621 #define bustype_BDK_USBDRDX_UCTL_PIPECLK_COUNTER(a) BDK_CSR_TYPE_NCB
12622 #define basename_BDK_USBDRDX_UCTL_PIPECLK_COUNTER(a) "USBDRDX_UCTL_PIPECLK_COUNTER"
12623 #define device_bar_BDK_USBDRDX_UCTL_PIPECLK_COUNTER(a) 0x0 /* PF_BAR0 */
12624 #define busnum_BDK_USBDRDX_UCTL_PIPECLK_COUNTER(a) (a)
12625 #define arguments_BDK_USBDRDX_UCTL_PIPECLK_COUNTER(a) (a),-1,-1,-1
12626
12627 /**
12628 * Register (NCB) usbdrd#_uctl_port#_cfg_hs
12629 *
12630 * USB UCTL Port Configuration High-Speed Register
12631 * This register controls configuration and test controls for the HS port 0 PHY.
12632 *
12633 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
12634 *
12635 * This register can be reset by NCB reset.
12636 *
12637 * Internal:
12638 * INTERNAL: All these settings are for HS functionality, connect on DVDD power domain.
12639 */
12640 union bdk_usbdrdx_uctl_portx_cfg_hs
12641 {
12642 uint64_t u;
12643 struct bdk_usbdrdx_uctl_portx_cfg_hs_s
12644 {
12645 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12646 uint64_t reserved_58_63 : 6;
12647 uint64_t comp_dis_tune : 3; /**< [ 57: 55](R/W) Disconnect threshold voltage. Adjusts the voltage level for the threshold used to detect a
12648 disconnect event at the host.
12649 A positive binary bit setting change results in a +1.5% incremental change in the
12650 threshold voltage level, while a negative binary bit setting change results in a -1.5%
12651 incremental change in the threshold voltage level. */
12652 uint64_t sq_rx_tune : 3; /**< [ 54: 52](R/W) Squelch threshold adjustment. Adjusts the voltage level for the threshold used to detect
12653 valid high-speed data.
12654 A positive binary bit setting change results in a -5% incremental change in threshold
12655 voltage level, while a negative binary bit setting change results in a +5% incremental
12656 change in threshold voltage level. */
12657 uint64_t tx_fsls_tune : 4; /**< [ 51: 48](R/W) Low-speed/full-speed source impedance adjustment. Adjusts the low- and full-speed single-
12658 ended source impedance while driving high. This parameter control is encoded in
12659 thermometer code.
12660 A positive thermometer code change results in a -2.5% incremental change in source
12661 impedance. A negative thermometer code change results in +2.5% incremental change in
12662 source impedance. Any non-thermometer code setting (that is, 0x9) is not supported and
12663 reserved. */
12664 uint64_t reserved_46_47 : 2;
12665 uint64_t tx_hs_xv_tune : 2; /**< [ 45: 44](R/W) Transmitter high-speed crossover adjustment. This bus adjusts the voltage at which the DP0
12666 and DM0 signals cross while transmitting in high-speed mode.
12667 0x3 = default setting.
12668 0x2 = +15 mV.
12669 0x1 = -15 mV.
12670 0x0 = reserved. */
12671 uint64_t tx_preemp_amp_tune : 2; /**< [ 43: 42](R/W) High-speed transmitter preemphasis current control. Controls the amount of current
12672 sourced to DP0 and DM0 after a J-to-K or K-to-J transition. The high-speed transmitter
12673 preemphasis current is defined in terms of unit amounts. One unit amount is approximately
12674 600 A and is defined as 1* preemphasis current.
12675 0x0 = High-speed TX preemphasis is disabled.
12676 0x1 = High-speed TX preemphasis circuit sources 1* preemphasis current.
12677 0x2 = High-speed TX preemphasis circuit sources 2* preemphasis current.
12678 0x3 = High-speed TX preemphasis circuit sources 3* preemphasis current.
12679
12680 If these signals are not used, set them to 0x0. */
12681 uint64_t reserved_41 : 1;
12682 uint64_t tx_preemp_pulse_tune : 1; /**< [ 40: 40](R/W) High-speed transmitter preemphasis duration control. Controls the duration for which the
12683 high-speed preemphasis current is sourced onto DP0 or DM0. The high-speed transmitter
12684 preemphasis duration is defined in terms of unit amounts. One unit of preemphasis duration
12685 is approximately 580 ps and is defined as 1* preemphasis duration. This signal is valid
12686 only if either TX_PREEMP_AMP_TUNE0[1] or TX_PREEMP_AMP_TUNE0[0] is set to 1.
12687 0 = 2*, long preemphasis current duration (design default).
12688 1 = 1*, short preemphasis current duration.
12689
12690 If this signal is not used, set it to 0. */
12691 uint64_t tx_res_tune : 2; /**< [ 39: 38](R/W) USB source-impedance adjustment. Some applications require additional devices to be added
12692 on the USB, such as a series switch, which can add significant series resistance. This bus
12693 adjusts the driver source impedance to compensate for added series resistance on the USB.
12694 0x0 = source impedance is decreased by approximately 1.5 ohm.
12695 0x1 = design default.
12696 0x2 = source impedance is decreased by approximately 2 ohm.
12697 0x3 = source impedance is decreased by approximately 4 ohm.
12698
12699 Any setting other than the default can result in source-impedance variation across
12700 process, voltage, and temperature conditions that does not meet USB 2.0 specification
12701 limits. If this bus is not used, leave it at the default setting. */
12702 uint64_t tx_rise_tune : 2; /**< [ 37: 36](R/W) High-speed transmitter rise-/fall-time adjustment. Adjusts the rise/fall times of the
12703 high-speed waveform. A positive binary bit setting change results in a -4% incremental
12704 change in the high-speed rise/fall time. A negative binary bit setting change results in a
12705 +4% incremental change in the high-speed rise/fall time. */
12706 uint64_t tx_vref_tune : 4; /**< [ 35: 32](R/W) High-speed DC voltage-level adjustment. Adjusts the high-speed DC level voltage.
12707 A positive binary-bit-setting change results in a +1.25% incremental change in high-speed
12708 DC voltage level, while a negative binary-bit-setting change results in a -1.25%
12709 incremental change in high-speed DC voltage level.
12710
12711 The default bit setting is intended to create a high-speed transmit
12712 DC level of approximately 400mV. */
12713 uint64_t reserved_7_31 : 25;
12714 uint64_t otgtune : 3; /**< [ 6: 4](R/W) "VBUS valid threshold adjustment.
12715 This bus adjusts the voltage level for the VBUS\<#\>
12716 valid threshold. To enable tuning at the board level, connect this
12717 bus to a register.
12718 Note: A positive binary bit setting change results in a +3%
12719 incremental change in threshold voltage level, while a negative
12720 binary bit setting change results in a -3% incremental change
12721 in threshold voltage level. " */
12722 uint64_t reserved_2_3 : 2;
12723 uint64_t loopback_enable : 1; /**< [ 1: 1](R/W) Places the high-speed PHY in loopback mode, which concurrently enables high-speed receive
12724 and transmit logic. */
12725 uint64_t atereset : 1; /**< [ 0: 0](R/W) Per-PHY ATE reset. When the USB core is powered up (not in suspend mode), an automatic
12726 tester can use this to disable PHYCLOCK and FREECLK, then re-enable them with an aligned
12727 phase.
12728 0 = PHYCLOCK and FREECLK are available within a specific period after ATERESET is
12729 deasserted.
12730 1 = PHYCLOCK and FREECLK outputs are disabled. */
12731 #else /* Word 0 - Little Endian */
12732 uint64_t atereset : 1; /**< [ 0: 0](R/W) Per-PHY ATE reset. When the USB core is powered up (not in suspend mode), an automatic
12733 tester can use this to disable PHYCLOCK and FREECLK, then re-enable them with an aligned
12734 phase.
12735 0 = PHYCLOCK and FREECLK are available within a specific period after ATERESET is
12736 deasserted.
12737 1 = PHYCLOCK and FREECLK outputs are disabled. */
12738 uint64_t loopback_enable : 1; /**< [ 1: 1](R/W) Places the high-speed PHY in loopback mode, which concurrently enables high-speed receive
12739 and transmit logic. */
12740 uint64_t reserved_2_3 : 2;
12741 uint64_t otgtune : 3; /**< [ 6: 4](R/W) "VBUS valid threshold adjustment.
12742 This bus adjusts the voltage level for the VBUS\<#\>
12743 valid threshold. To enable tuning at the board level, connect this
12744 bus to a register.
12745 Note: A positive binary bit setting change results in a +3%
12746 incremental change in threshold voltage level, while a negative
12747 binary bit setting change results in a -3% incremental change
12748 in threshold voltage level. " */
12749 uint64_t reserved_7_31 : 25;
12750 uint64_t tx_vref_tune : 4; /**< [ 35: 32](R/W) High-speed DC voltage-level adjustment. Adjusts the high-speed DC level voltage.
12751 A positive binary-bit-setting change results in a +1.25% incremental change in high-speed
12752 DC voltage level, while a negative binary-bit-setting change results in a -1.25%
12753 incremental change in high-speed DC voltage level.
12754
12755 The default bit setting is intended to create a high-speed transmit
12756 DC level of approximately 400mV. */
12757 uint64_t tx_rise_tune : 2; /**< [ 37: 36](R/W) High-speed transmitter rise-/fall-time adjustment. Adjusts the rise/fall times of the
12758 high-speed waveform. A positive binary bit setting change results in a -4% incremental
12759 change in the high-speed rise/fall time. A negative binary bit setting change results in a
12760 +4% incremental change in the high-speed rise/fall time. */
12761 uint64_t tx_res_tune : 2; /**< [ 39: 38](R/W) USB source-impedance adjustment. Some applications require additional devices to be added
12762 on the USB, such as a series switch, which can add significant series resistance. This bus
12763 adjusts the driver source impedance to compensate for added series resistance on the USB.
12764 0x0 = source impedance is decreased by approximately 1.5 ohm.
12765 0x1 = design default.
12766 0x2 = source impedance is decreased by approximately 2 ohm.
12767 0x3 = source impedance is decreased by approximately 4 ohm.
12768
12769 Any setting other than the default can result in source-impedance variation across
12770 process, voltage, and temperature conditions that does not meet USB 2.0 specification
12771 limits. If this bus is not used, leave it at the default setting. */
12772 uint64_t tx_preemp_pulse_tune : 1; /**< [ 40: 40](R/W) High-speed transmitter preemphasis duration control. Controls the duration for which the
12773 high-speed preemphasis current is sourced onto DP0 or DM0. The high-speed transmitter
12774 preemphasis duration is defined in terms of unit amounts. One unit of preemphasis duration
12775 is approximately 580 ps and is defined as 1* preemphasis duration. This signal is valid
12776 only if either TX_PREEMP_AMP_TUNE0[1] or TX_PREEMP_AMP_TUNE0[0] is set to 1.
12777 0 = 2*, long preemphasis current duration (design default).
12778 1 = 1*, short preemphasis current duration.
12779
12780 If this signal is not used, set it to 0. */
12781 uint64_t reserved_41 : 1;
12782 uint64_t tx_preemp_amp_tune : 2; /**< [ 43: 42](R/W) High-speed transmitter preemphasis current control. Controls the amount of current
12783 sourced to DP0 and DM0 after a J-to-K or K-to-J transition. The high-speed transmitter
12784 preemphasis current is defined in terms of unit amounts. One unit amount is approximately
12785 600 A and is defined as 1* preemphasis current.
12786 0x0 = High-speed TX preemphasis is disabled.
12787 0x1 = High-speed TX preemphasis circuit sources 1* preemphasis current.
12788 0x2 = High-speed TX preemphasis circuit sources 2* preemphasis current.
12789 0x3 = High-speed TX preemphasis circuit sources 3* preemphasis current.
12790
12791 If these signals are not used, set them to 0x0. */
12792 uint64_t tx_hs_xv_tune : 2; /**< [ 45: 44](R/W) Transmitter high-speed crossover adjustment. This bus adjusts the voltage at which the DP0
12793 and DM0 signals cross while transmitting in high-speed mode.
12794 0x3 = default setting.
12795 0x2 = +15 mV.
12796 0x1 = -15 mV.
12797 0x0 = reserved. */
12798 uint64_t reserved_46_47 : 2;
12799 uint64_t tx_fsls_tune : 4; /**< [ 51: 48](R/W) Low-speed/full-speed source impedance adjustment. Adjusts the low- and full-speed single-
12800 ended source impedance while driving high. This parameter control is encoded in
12801 thermometer code.
12802 A positive thermometer code change results in a -2.5% incremental change in source
12803 impedance. A negative thermometer code change results in +2.5% incremental change in
12804 source impedance. Any non-thermometer code setting (that is, 0x9) is not supported and
12805 reserved. */
12806 uint64_t sq_rx_tune : 3; /**< [ 54: 52](R/W) Squelch threshold adjustment. Adjusts the voltage level for the threshold used to detect
12807 valid high-speed data.
12808 A positive binary bit setting change results in a -5% incremental change in threshold
12809 voltage level, while a negative binary bit setting change results in a +5% incremental
12810 change in threshold voltage level. */
12811 uint64_t comp_dis_tune : 3; /**< [ 57: 55](R/W) Disconnect threshold voltage. Adjusts the voltage level for the threshold used to detect a
12812 disconnect event at the host.
12813 A positive binary bit setting change results in a +1.5% incremental change in the
12814 threshold voltage level, while a negative binary bit setting change results in a -1.5%
12815 incremental change in the threshold voltage level. */
12816 uint64_t reserved_58_63 : 6;
12817 #endif /* Word 0 - End */
12818 } s;
12819 struct bdk_usbdrdx_uctl_portx_cfg_hs_cn8
12820 {
12821 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12822 uint64_t reserved_58_63 : 6;
12823 uint64_t comp_dis_tune : 3; /**< [ 57: 55](R/W) Disconnect threshold voltage. Adjusts the voltage level for the threshold used to detect a
12824 disconnect event at the host.
12825 A positive binary bit setting change results in a +1.5% incremental change in the
12826 threshold voltage level, while a negative binary bit setting change results in a -1.5%
12827 incremental change in the threshold voltage level. */
12828 uint64_t sq_rx_tune : 3; /**< [ 54: 52](R/W) Squelch threshold adjustment. Adjusts the voltage level for the threshold used to detect
12829 valid high-speed data.
12830 A positive binary bit setting change results in a -5% incremental change in threshold
12831 voltage level, while a negative binary bit setting change results in a +5% incremental
12832 change in threshold voltage level. */
12833 uint64_t tx_fsls_tune : 4; /**< [ 51: 48](R/W) Low-speed/full-speed source impedance adjustment. Adjusts the low- and full-speed single-
12834 ended source impedance while driving high. This parameter control is encoded in
12835 thermometer code.
12836 A positive thermometer code change results in a -2.5% incremental change in source
12837 impedance. A negative thermometer code change results in +2.5% incremental change in
12838 source impedance. Any non-thermometer code setting (that is, 0x9) is not supported and
12839 reserved. */
12840 uint64_t reserved_46_47 : 2;
12841 uint64_t tx_hs_xv_tune : 2; /**< [ 45: 44](R/W) Transmitter high-speed crossover adjustment. This bus adjusts the voltage at which the DP0
12842 and DM0 signals cross while transmitting in high-speed mode.
12843 0x3 = default setting.
12844 0x2 = +15 mV.
12845 0x1 = -15 mV.
12846 0x0 = reserved. */
12847 uint64_t tx_preemp_amp_tune : 2; /**< [ 43: 42](R/W) High-speed transmitter preemphasis current control. Controls the amount of current
12848 sourced to DP0 and DM0 after a J-to-K or K-to-J transition. The high-speed transmitter
12849 preemphasis current is defined in terms of unit amounts. One unit amount is approximately
12850 600 A and is defined as 1* preemphasis current.
12851 0x0 = High-speed TX preemphasis is disabled.
12852 0x1 = High-speed TX preemphasis circuit sources 1* preemphasis current.
12853 0x2 = High-speed TX preemphasis circuit sources 2* preemphasis current.
12854 0x3 = High-speed TX preemphasis circuit sources 3* preemphasis current.
12855
12856 If these signals are not used, set them to 0x0. */
12857 uint64_t reserved_41 : 1;
12858 uint64_t tx_preemp_pulse_tune : 1; /**< [ 40: 40](R/W) High-speed transmitter preemphasis duration control. Controls the duration for which the
12859 high-speed preemphasis current is sourced onto DP0 or DM0. The high-speed transmitter
12860 preemphasis duration is defined in terms of unit amounts. One unit of preemphasis duration
12861 is approximately 580 ps and is defined as 1* preemphasis duration. This signal is valid
12862 only if either TX_PREEMP_AMP_TUNE0[1] or TX_PREEMP_AMP_TUNE0[0] is set to 1.
12863 0 = 2*, long preemphasis current duration (design default).
12864 1 = 1*, short preemphasis current duration.
12865
12866 If this signal is not used, set it to 0. */
12867 uint64_t tx_res_tune : 2; /**< [ 39: 38](R/W) USB source-impedance adjustment. Some applications require additional devices to be added
12868 on the USB, such as a series switch, which can add significant series resistance. This bus
12869 adjusts the driver source impedance to compensate for added series resistance on the USB.
12870 0x0 = source impedance is decreased by approximately 1.5 ohm.
12871 0x1 = design default.
12872 0x2 = source impedance is decreased by approximately 2 ohm.
12873 0x3 = source impedance is decreased by approximately 4 ohm.
12874
12875 Any setting other than the default can result in source-impedance variation across
12876 process, voltage, and temperature conditions that does not meet USB 2.0 specification
12877 limits. If this bus is not used, leave it at the default setting. */
12878 uint64_t tx_rise_tune : 2; /**< [ 37: 36](R/W) High-speed transmitter rise-/fall-time adjustment. Adjusts the rise/fall times of the
12879 high-speed waveform. A positive binary bit setting change results in a -4% incremental
12880 change in the high-speed rise/fall time. A negative binary bit setting change results in a
12881 +4% incremental change in the high-speed rise/fall time. */
12882 uint64_t tx_vref_tune : 4; /**< [ 35: 32](R/W) High-speed DC voltage-level adjustment. Adjusts the high-speed DC level voltage.
12883 A positive binary-bit-setting change results in a +1.25% incremental change in high-speed
12884 DC voltage level, while a negative binary-bit-setting change results in a -1.25%
12885 incremental change in high-speed DC voltage level.
12886
12887 The default bit setting is intended to create a high-speed transmit
12888 DC level of approximately 400mV. */
12889 uint64_t reserved_7_31 : 25;
12890 uint64_t otgtune : 3; /**< [ 6: 4](R/W) "VBUS valid threshold adjustment.
12891 This bus adjusts the voltage level for the VBUS\<#\>
12892 valid threshold. To enable tuning at the board level, connect this
12893 bus to a register.
12894 Note: A positive binary bit setting change results in a +3%
12895 incremental change in threshold voltage level, while a negative
12896 binary bit setting change results in a -3% incremental change
12897 in threshold voltage level. " */
12898 uint64_t vatest_enable : 2; /**< [ 3: 2](R/W) Analog test-pin select. Enables analog test voltages to be placed on the ID0 pin.
12899 0x0 = Test functionality disabled.
12900 0x1 = Test functionality enabled.
12901 0x2, 0x3 = Reserved, invalid settings.
12902
12903 See also the PHY databook for details on how to select which analog test voltage. */
12904 uint64_t loopback_enable : 1; /**< [ 1: 1](R/W) Places the high-speed PHY in loopback mode, which concurrently enables high-speed receive
12905 and transmit logic. */
12906 uint64_t atereset : 1; /**< [ 0: 0](R/W) Per-PHY ATE reset. When the USB core is powered up (not in suspend mode), an automatic
12907 tester can use this to disable PHYCLOCK and FREECLK, then re-enable them with an aligned
12908 phase.
12909 0 = PHYCLOCK and FREECLK are available within a specific period after ATERESET is
12910 deasserted.
12911 1 = PHYCLOCK and FREECLK outputs are disabled. */
12912 #else /* Word 0 - Little Endian */
12913 uint64_t atereset : 1; /**< [ 0: 0](R/W) Per-PHY ATE reset. When the USB core is powered up (not in suspend mode), an automatic
12914 tester can use this to disable PHYCLOCK and FREECLK, then re-enable them with an aligned
12915 phase.
12916 0 = PHYCLOCK and FREECLK are available within a specific period after ATERESET is
12917 deasserted.
12918 1 = PHYCLOCK and FREECLK outputs are disabled. */
12919 uint64_t loopback_enable : 1; /**< [ 1: 1](R/W) Places the high-speed PHY in loopback mode, which concurrently enables high-speed receive
12920 and transmit logic. */
12921 uint64_t vatest_enable : 2; /**< [ 3: 2](R/W) Analog test-pin select. Enables analog test voltages to be placed on the ID0 pin.
12922 0x0 = Test functionality disabled.
12923 0x1 = Test functionality enabled.
12924 0x2, 0x3 = Reserved, invalid settings.
12925
12926 See also the PHY databook for details on how to select which analog test voltage. */
12927 uint64_t otgtune : 3; /**< [ 6: 4](R/W) "VBUS valid threshold adjustment.
12928 This bus adjusts the voltage level for the VBUS\<#\>
12929 valid threshold. To enable tuning at the board level, connect this
12930 bus to a register.
12931 Note: A positive binary bit setting change results in a +3%
12932 incremental change in threshold voltage level, while a negative
12933 binary bit setting change results in a -3% incremental change
12934 in threshold voltage level. " */
12935 uint64_t reserved_7_31 : 25;
12936 uint64_t tx_vref_tune : 4; /**< [ 35: 32](R/W) High-speed DC voltage-level adjustment. Adjusts the high-speed DC level voltage.
12937 A positive binary-bit-setting change results in a +1.25% incremental change in high-speed
12938 DC voltage level, while a negative binary-bit-setting change results in a -1.25%
12939 incremental change in high-speed DC voltage level.
12940
12941 The default bit setting is intended to create a high-speed transmit
12942 DC level of approximately 400mV. */
12943 uint64_t tx_rise_tune : 2; /**< [ 37: 36](R/W) High-speed transmitter rise-/fall-time adjustment. Adjusts the rise/fall times of the
12944 high-speed waveform. A positive binary bit setting change results in a -4% incremental
12945 change in the high-speed rise/fall time. A negative binary bit setting change results in a
12946 +4% incremental change in the high-speed rise/fall time. */
12947 uint64_t tx_res_tune : 2; /**< [ 39: 38](R/W) USB source-impedance adjustment. Some applications require additional devices to be added
12948 on the USB, such as a series switch, which can add significant series resistance. This bus
12949 adjusts the driver source impedance to compensate for added series resistance on the USB.
12950 0x0 = source impedance is decreased by approximately 1.5 ohm.
12951 0x1 = design default.
12952 0x2 = source impedance is decreased by approximately 2 ohm.
12953 0x3 = source impedance is decreased by approximately 4 ohm.
12954
12955 Any setting other than the default can result in source-impedance variation across
12956 process, voltage, and temperature conditions that does not meet USB 2.0 specification
12957 limits. If this bus is not used, leave it at the default setting. */
12958 uint64_t tx_preemp_pulse_tune : 1; /**< [ 40: 40](R/W) High-speed transmitter preemphasis duration control. Controls the duration for which the
12959 high-speed preemphasis current is sourced onto DP0 or DM0. The high-speed transmitter
12960 preemphasis duration is defined in terms of unit amounts. One unit of preemphasis duration
12961 is approximately 580 ps and is defined as 1* preemphasis duration. This signal is valid
12962 only if either TX_PREEMP_AMP_TUNE0[1] or TX_PREEMP_AMP_TUNE0[0] is set to 1.
12963 0 = 2*, long preemphasis current duration (design default).
12964 1 = 1*, short preemphasis current duration.
12965
12966 If this signal is not used, set it to 0. */
12967 uint64_t reserved_41 : 1;
12968 uint64_t tx_preemp_amp_tune : 2; /**< [ 43: 42](R/W) High-speed transmitter preemphasis current control. Controls the amount of current
12969 sourced to DP0 and DM0 after a J-to-K or K-to-J transition. The high-speed transmitter
12970 preemphasis current is defined in terms of unit amounts. One unit amount is approximately
12971 600 A and is defined as 1* preemphasis current.
12972 0x0 = High-speed TX preemphasis is disabled.
12973 0x1 = High-speed TX preemphasis circuit sources 1* preemphasis current.
12974 0x2 = High-speed TX preemphasis circuit sources 2* preemphasis current.
12975 0x3 = High-speed TX preemphasis circuit sources 3* preemphasis current.
12976
12977 If these signals are not used, set them to 0x0. */
12978 uint64_t tx_hs_xv_tune : 2; /**< [ 45: 44](R/W) Transmitter high-speed crossover adjustment. This bus adjusts the voltage at which the DP0
12979 and DM0 signals cross while transmitting in high-speed mode.
12980 0x3 = default setting.
12981 0x2 = +15 mV.
12982 0x1 = -15 mV.
12983 0x0 = reserved. */
12984 uint64_t reserved_46_47 : 2;
12985 uint64_t tx_fsls_tune : 4; /**< [ 51: 48](R/W) Low-speed/full-speed source impedance adjustment. Adjusts the low- and full-speed single-
12986 ended source impedance while driving high. This parameter control is encoded in
12987 thermometer code.
12988 A positive thermometer code change results in a -2.5% incremental change in source
12989 impedance. A negative thermometer code change results in +2.5% incremental change in
12990 source impedance. Any non-thermometer code setting (that is, 0x9) is not supported and
12991 reserved. */
12992 uint64_t sq_rx_tune : 3; /**< [ 54: 52](R/W) Squelch threshold adjustment. Adjusts the voltage level for the threshold used to detect
12993 valid high-speed data.
12994 A positive binary bit setting change results in a -5% incremental change in threshold
12995 voltage level, while a negative binary bit setting change results in a +5% incremental
12996 change in threshold voltage level. */
12997 uint64_t comp_dis_tune : 3; /**< [ 57: 55](R/W) Disconnect threshold voltage. Adjusts the voltage level for the threshold used to detect a
12998 disconnect event at the host.
12999 A positive binary bit setting change results in a +1.5% incremental change in the
13000 threshold voltage level, while a negative binary bit setting change results in a -1.5%
13001 incremental change in the threshold voltage level. */
13002 uint64_t reserved_58_63 : 6;
13003 #endif /* Word 0 - End */
13004 } cn8;
13005 struct bdk_usbdrdx_uctl_portx_cfg_hs_cn9
13006 {
13007 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13008 uint64_t reserved_58_63 : 6;
13009 uint64_t comp_dis_tune : 3; /**< [ 57: 55](R/W) Disconnect threshold voltage. Adjusts the voltage level for the threshold used to detect a
13010 disconnect event at the host.
13011 A positive binary bit setting change results in a +1.5% incremental change in the
13012 threshold voltage level, while a negative binary bit setting change results in a -1.5%
13013 incremental change in the threshold voltage level. */
13014 uint64_t sq_rx_tune : 3; /**< [ 54: 52](R/W) Squelch threshold adjustment. Adjusts the voltage level for the threshold used to detect
13015 valid high-speed data.
13016 A positive binary bit setting change results in a -5% incremental change in threshold
13017 voltage level, while a negative binary bit setting change results in a +5% incremental
13018 change in threshold voltage level. */
13019 uint64_t tx_fsls_tune : 4; /**< [ 51: 48](R/W) Low-speed/full-speed source impedance adjustment. Adjusts the low- and full-speed single-
13020 ended source impedance while driving high. This parameter control is encoded in
13021 thermometer code.
13022 A positive thermometer code change results in a -2.5% incremental change in source
13023 impedance. A negative thermometer code change results in +2.5% incremental change in
13024 source impedance. Any non-thermometer code setting (that is, 0x9) is not supported and
13025 reserved. */
13026 uint64_t reserved_46_47 : 2;
13027 uint64_t tx_hs_xv_tune : 2; /**< [ 45: 44](R/W) Transmitter high-speed crossover adjustment. This bus adjusts the voltage at which the DP0
13028 and DM0 signals cross while transmitting in high-speed mode.
13029 0x3 = default setting.
13030 0x2 = +15 mV.
13031 0x1 = -15 mV.
13032 0x0 = reserved. */
13033 uint64_t tx_preemp_amp_tune : 2; /**< [ 43: 42](R/W) High-speed transmitter preemphasis current control. Controls the amount of current
13034 sourced to DP0 and DM0 after a J-to-K or K-to-J transition. The high-speed transmitter
13035 preemphasis current is defined in terms of unit amounts. One unit amount is approximately
13036 600 A and is defined as 1* preemphasis current.
13037 0x0 = High-speed TX preemphasis is disabled.
13038 0x1 = High-speed TX preemphasis circuit sources 1* preemphasis current.
13039 0x2 = High-speed TX preemphasis circuit sources 2* preemphasis current.
13040 0x3 = High-speed TX preemphasis circuit sources 3* preemphasis current.
13041
13042 If these signals are not used, set them to 0x0. */
13043 uint64_t reserved_41 : 1;
13044 uint64_t tx_preemp_pulse_tune : 1; /**< [ 40: 40](R/W) High-speed transmitter preemphasis duration control. Controls the duration for which the
13045 high-speed preemphasis current is sourced onto DP0 or DM0. The high-speed transmitter
13046 preemphasis duration is defined in terms of unit amounts. One unit of preemphasis duration
13047 is approximately 580 ps and is defined as 1* preemphasis duration. This signal is valid
13048 only if either TX_PREEMP_AMP_TUNE0[1] or TX_PREEMP_AMP_TUNE0[0] is set to 1.
13049 0 = 2*, long preemphasis current duration (design default).
13050 1 = 1*, short preemphasis current duration.
13051
13052 If this signal is not used, set it to 0. */
13053 uint64_t tx_res_tune : 2; /**< [ 39: 38](R/W) USB source-impedance adjustment. Some applications require additional devices to be added
13054 on the USB, such as a series switch, which can add significant series resistance. This bus
13055 adjusts the driver source impedance to compensate for added series resistance on the USB.
13056 0x0 = source impedance is decreased by approximately 1.5 ohm.
13057 0x1 = design default.
13058 0x2 = source impedance is decreased by approximately 2 ohm.
13059 0x3 = source impedance is decreased by approximately 4 ohm.
13060
13061 Any setting other than the default can result in source-impedance variation across
13062 process, voltage, and temperature conditions that does not meet USB 2.0 specification
13063 limits. If this bus is not used, leave it at the default setting. */
13064 uint64_t tx_rise_tune : 2; /**< [ 37: 36](R/W) High-speed transmitter rise-/fall-time adjustment. Adjusts the rise/fall times of the
13065 high-speed waveform. A positive binary bit setting change results in a -4% incremental
13066 change in the high-speed rise/fall time. A negative binary bit setting change results in a
13067 +4% incremental change in the high-speed rise/fall time. */
13068 uint64_t tx_vref_tune : 4; /**< [ 35: 32](R/W) High-speed DC voltage-level adjustment. Adjusts the high-speed DC level voltage.
13069 A positive binary-bit-setting change results in a +1.25% incremental change in high-speed
13070 DC voltage level, while a negative binary-bit-setting change results in a -1.25%
13071 incremental change in high-speed DC voltage level.
13072
13073 The default bit setting is intended to create a high-speed transmit
13074 DC level of approximately 400mV. */
13075 uint64_t reserved_7_31 : 25;
13076 uint64_t otgtune : 3; /**< [ 6: 4](R/W) "VBUS valid threshold adjustment.
13077 This bus adjusts the voltage level for the VBUS\<#\>
13078 valid threshold. To enable tuning at the board level, connect this
13079 bus to a register.
13080 Note: A positive binary bit setting change results in a +3%
13081 incremental change in threshold voltage level, while a negative
13082 binary bit setting change results in a -3% incremental change
13083 in threshold voltage level. " */
13084 uint64_t vatest_enable : 1; /**< [ 3: 3](R/W) Analog test-pin select. Enables analog test voltages to be placed on the ID0 pin.
13085 0x0 = Test functionality disabled.
13086 0x1 = Test functionality enabled.
13087 0x2, 0x3 = Reserved, invalid settings.
13088
13089 See also the PHY databook for details on how to select which analog test voltage. */
13090 uint64_t reserved_2 : 1;
13091 uint64_t loopback_enable : 1; /**< [ 1: 1](R/W) Places the high-speed PHY in loopback mode, which concurrently enables high-speed receive
13092 and transmit logic. */
13093 uint64_t atereset : 1; /**< [ 0: 0](R/W) Per-PHY ATE reset. When the USB core is powered up (not in suspend mode), an automatic
13094 tester can use this to disable PHYCLOCK and FREECLK, then re-enable them with an aligned
13095 phase.
13096 0 = PHYCLOCK and FREECLK are available within a specific period after ATERESET is
13097 deasserted.
13098 1 = PHYCLOCK and FREECLK outputs are disabled. */
13099 #else /* Word 0 - Little Endian */
13100 uint64_t atereset : 1; /**< [ 0: 0](R/W) Per-PHY ATE reset. When the USB core is powered up (not in suspend mode), an automatic
13101 tester can use this to disable PHYCLOCK and FREECLK, then re-enable them with an aligned
13102 phase.
13103 0 = PHYCLOCK and FREECLK are available within a specific period after ATERESET is
13104 deasserted.
13105 1 = PHYCLOCK and FREECLK outputs are disabled. */
13106 uint64_t loopback_enable : 1; /**< [ 1: 1](R/W) Places the high-speed PHY in loopback mode, which concurrently enables high-speed receive
13107 and transmit logic. */
13108 uint64_t reserved_2 : 1;
13109 uint64_t vatest_enable : 1; /**< [ 3: 3](R/W) Analog test-pin select. Enables analog test voltages to be placed on the ID0 pin.
13110 0x0 = Test functionality disabled.
13111 0x1 = Test functionality enabled.
13112 0x2, 0x3 = Reserved, invalid settings.
13113
13114 See also the PHY databook for details on how to select which analog test voltage. */
13115 uint64_t otgtune : 3; /**< [ 6: 4](R/W) "VBUS valid threshold adjustment.
13116 This bus adjusts the voltage level for the VBUS\<#\>
13117 valid threshold. To enable tuning at the board level, connect this
13118 bus to a register.
13119 Note: A positive binary bit setting change results in a +3%
13120 incremental change in threshold voltage level, while a negative
13121 binary bit setting change results in a -3% incremental change
13122 in threshold voltage level. " */
13123 uint64_t reserved_7_31 : 25;
13124 uint64_t tx_vref_tune : 4; /**< [ 35: 32](R/W) High-speed DC voltage-level adjustment. Adjusts the high-speed DC level voltage.
13125 A positive binary-bit-setting change results in a +1.25% incremental change in high-speed
13126 DC voltage level, while a negative binary-bit-setting change results in a -1.25%
13127 incremental change in high-speed DC voltage level.
13128
13129 The default bit setting is intended to create a high-speed transmit
13130 DC level of approximately 400mV. */
13131 uint64_t tx_rise_tune : 2; /**< [ 37: 36](R/W) High-speed transmitter rise-/fall-time adjustment. Adjusts the rise/fall times of the
13132 high-speed waveform. A positive binary bit setting change results in a -4% incremental
13133 change in the high-speed rise/fall time. A negative binary bit setting change results in a
13134 +4% incremental change in the high-speed rise/fall time. */
13135 uint64_t tx_res_tune : 2; /**< [ 39: 38](R/W) USB source-impedance adjustment. Some applications require additional devices to be added
13136 on the USB, such as a series switch, which can add significant series resistance. This bus
13137 adjusts the driver source impedance to compensate for added series resistance on the USB.
13138 0x0 = source impedance is decreased by approximately 1.5 ohm.
13139 0x1 = design default.
13140 0x2 = source impedance is decreased by approximately 2 ohm.
13141 0x3 = source impedance is decreased by approximately 4 ohm.
13142
13143 Any setting other than the default can result in source-impedance variation across
13144 process, voltage, and temperature conditions that does not meet USB 2.0 specification
13145 limits. If this bus is not used, leave it at the default setting. */
13146 uint64_t tx_preemp_pulse_tune : 1; /**< [ 40: 40](R/W) High-speed transmitter preemphasis duration control. Controls the duration for which the
13147 high-speed preemphasis current is sourced onto DP0 or DM0. The high-speed transmitter
13148 preemphasis duration is defined in terms of unit amounts. One unit of preemphasis duration
13149 is approximately 580 ps and is defined as 1* preemphasis duration. This signal is valid
13150 only if either TX_PREEMP_AMP_TUNE0[1] or TX_PREEMP_AMP_TUNE0[0] is set to 1.
13151 0 = 2*, long preemphasis current duration (design default).
13152 1 = 1*, short preemphasis current duration.
13153
13154 If this signal is not used, set it to 0. */
13155 uint64_t reserved_41 : 1;
13156 uint64_t tx_preemp_amp_tune : 2; /**< [ 43: 42](R/W) High-speed transmitter preemphasis current control. Controls the amount of current
13157 sourced to DP0 and DM0 after a J-to-K or K-to-J transition. The high-speed transmitter
13158 preemphasis current is defined in terms of unit amounts. One unit amount is approximately
13159 600 A and is defined as 1* preemphasis current.
13160 0x0 = High-speed TX preemphasis is disabled.
13161 0x1 = High-speed TX preemphasis circuit sources 1* preemphasis current.
13162 0x2 = High-speed TX preemphasis circuit sources 2* preemphasis current.
13163 0x3 = High-speed TX preemphasis circuit sources 3* preemphasis current.
13164
13165 If these signals are not used, set them to 0x0. */
13166 uint64_t tx_hs_xv_tune : 2; /**< [ 45: 44](R/W) Transmitter high-speed crossover adjustment. This bus adjusts the voltage at which the DP0
13167 and DM0 signals cross while transmitting in high-speed mode.
13168 0x3 = default setting.
13169 0x2 = +15 mV.
13170 0x1 = -15 mV.
13171 0x0 = reserved. */
13172 uint64_t reserved_46_47 : 2;
13173 uint64_t tx_fsls_tune : 4; /**< [ 51: 48](R/W) Low-speed/full-speed source impedance adjustment. Adjusts the low- and full-speed single-
13174 ended source impedance while driving high. This parameter control is encoded in
13175 thermometer code.
13176 A positive thermometer code change results in a -2.5% incremental change in source
13177 impedance. A negative thermometer code change results in +2.5% incremental change in
13178 source impedance. Any non-thermometer code setting (that is, 0x9) is not supported and
13179 reserved. */
13180 uint64_t sq_rx_tune : 3; /**< [ 54: 52](R/W) Squelch threshold adjustment. Adjusts the voltage level for the threshold used to detect
13181 valid high-speed data.
13182 A positive binary bit setting change results in a -5% incremental change in threshold
13183 voltage level, while a negative binary bit setting change results in a +5% incremental
13184 change in threshold voltage level. */
13185 uint64_t comp_dis_tune : 3; /**< [ 57: 55](R/W) Disconnect threshold voltage. Adjusts the voltage level for the threshold used to detect a
13186 disconnect event at the host.
13187 A positive binary bit setting change results in a +1.5% incremental change in the
13188 threshold voltage level, while a negative binary bit setting change results in a -1.5%
13189 incremental change in the threshold voltage level. */
13190 uint64_t reserved_58_63 : 6;
13191 #endif /* Word 0 - End */
13192 } cn9;
13193 };
13194 typedef union bdk_usbdrdx_uctl_portx_cfg_hs bdk_usbdrdx_uctl_portx_cfg_hs_t;
13195
13196 static inline uint64_t BDK_USBDRDX_UCTL_PORTX_CFG_HS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_PORTX_CFG_HS(unsigned long a,unsigned long b)13197 static inline uint64_t BDK_USBDRDX_UCTL_PORTX_CFG_HS(unsigned long a, unsigned long b)
13198 {
13199 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
13200 return 0x868000100050ll + 0x1000000000ll * ((a) & 0x1) + 0x20ll * ((b) & 0x0);
13201 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
13202 return 0x868000100050ll + 0x1000000000ll * ((a) & 0x1) + 0x20ll * ((b) & 0x0);
13203 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
13204 return 0x868000100050ll + 0x1000000000ll * ((a) & 0x1) + 0x20ll * ((b) & 0x0);
13205 __bdk_csr_fatal("USBDRDX_UCTL_PORTX_CFG_HS", 2, a, b, 0, 0);
13206 }
13207
13208 #define typedef_BDK_USBDRDX_UCTL_PORTX_CFG_HS(a,b) bdk_usbdrdx_uctl_portx_cfg_hs_t
13209 #define bustype_BDK_USBDRDX_UCTL_PORTX_CFG_HS(a,b) BDK_CSR_TYPE_NCB
13210 #define basename_BDK_USBDRDX_UCTL_PORTX_CFG_HS(a,b) "USBDRDX_UCTL_PORTX_CFG_HS"
13211 #define device_bar_BDK_USBDRDX_UCTL_PORTX_CFG_HS(a,b) 0x0 /* PF_BAR0 */
13212 #define busnum_BDK_USBDRDX_UCTL_PORTX_CFG_HS(a,b) (a)
13213 #define arguments_BDK_USBDRDX_UCTL_PORTX_CFG_HS(a,b) (a),(b),-1,-1
13214
13215 /**
13216 * Register (NCB) usbdrd#_uctl_port#_cfg_ss
13217 *
13218 * USB UCTL Port Configuration SuperSpeed Register
13219 * This register controls configuration and test controls for the SS port 0 PHY.
13220 *
13221 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
13222 *
13223 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
13224 *
13225 * Internal:
13226 * All these settings are for high-speed functionality, connect on DVDD power domain.
13227 */
13228 union bdk_usbdrdx_uctl_portx_cfg_ss
13229 {
13230 uint64_t u;
13231 struct bdk_usbdrdx_uctl_portx_cfg_ss_s
13232 {
13233 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13234 uint64_t tx_vboost_lvl : 3; /**< [ 63: 61](R/W) TX voltage-boost level. Sets the boosted transmit launch amplitude (mVppd). The default
13235 bit setting is intended to set the launch amplitude to approximately 1,008 mVppd. A
13236 single, positive binary bit setting change results in a +156 mVppd change in the TX launch
13237 amplitude.
13238 A single, negative binary bit setting change results in a -156 mVppd change in the TX
13239 launch amplitude. All settings more than one binary bit change should not be used.
13240 0x3 = 0.844 V launch amplitude.
13241 0x4 = 1.008 V launch amplitude.
13242 0x5 = 1.156 V launch amplitude.
13243 All others values are invalid. */
13244 uint64_t los_bias : 3; /**< [ 60: 58](R/W) Loss-of-signal detector threshold-level control. A positive, binary bit setting change
13245 results in a +15 mVp incremental change in the LOS threshold.
13246 A negative binary bit setting change results in a -15 mVp incremental change in the LOS
13247 threshold. The 0x0 setting is reserved and must not be used. The default 0x5 setting
13248 corresponds to approximately 105 mVp.
13249 0x0 = invalid.
13250 0x1 = 45 mV.
13251 0x2 = 60 mV.
13252 0x3 = 75 mV.
13253 0x4 = 90 mV.
13254 0x5 = 105 mV (default).
13255 0x6 = 120 mV.
13256 0x7 = 135 mV. */
13257 uint64_t lane0_ext_pclk_req : 1; /**< [ 57: 57](R/W) When asserted, this signal enables the pipe0_pclk output regardless of power state (along
13258 with the associated increase in power consumption). You can use this input to enable
13259 pipe0_pclk in the P3 state without going through a complete boot sequence. */
13260 uint64_t lane0_tx2rx_loopbk : 1; /**< [ 56: 56](R/W) When asserted, data from TX predriver is looped back to RX slicers. LOS is bypassed and
13261 based on the tx0_en input so that rx0_los = !tx_data_en. */
13262 uint64_t reserved_42_55 : 14;
13263 uint64_t pcs_rx_los_mask_val : 10; /**< [ 41: 32](R/W) Configurable loss-of-signal mask width. Sets the number of reference clock cycles to mask
13264 the incoming LFPS in U3 and U2 states. Masks the incoming LFPS for the number of reference
13265 clock cycles equal to the value of pcs_rx_los_mask_val\<9:0\>. This control filters out
13266 short, non-compliant LFPS glitches sent by a noncompliant host.
13267
13268 For normal operation, set to a targeted mask interval of 10us (value = 10us / Tref_clk).
13269 If the USBDRD()_UCTL_CTL[REF_CLK_DIV2] is used, then
13270 (value = 10us / (2 * Tref_clk)). These equations are based on the SuperSpeed reference
13271 clock frequency. The value of [PCS_RX_LOS_MASK_VAL] should be as follows:
13272
13273 \<pre\>
13274 Frequency DIV2 LOS_MASK
13275 --------- --- --------
13276 200 MHz 1 0x3E8
13277 125 MHz 0 0x4E2
13278 104 MHz 0 0x410
13279 100 MHz 0 0x3E8
13280 96 MHz 0 0x3C0
13281 76.8 MHz 1 0x180
13282 52 MHz 0 0x208
13283 50 MHz 0 0x1F4
13284 48 MHz 0 0x1E0
13285 40 MHz 1 0x0C8
13286 38.4 MHz 0 0x180
13287 26 MHz 0 0x104
13288 25 MHz 0 0x0FA
13289 24 MHz 0 0x0F0
13290 20 MHz 0 0x0C8
13291 19.2 MHz 0 0x0C0
13292 \</pre\>
13293
13294 Setting this bus to 0x0 disables masking. The value should be defined when the PHY is in
13295 reset. Changing this value during operation might disrupt normal operation of the link. */
13296 uint64_t pcs_tx_deemph_3p5db : 6; /**< [ 31: 26](R/W) Fine-tune transmitter driver deemphasis when set to 3.5db.
13297 This static value sets the TX driver deemphasis value when
13298 USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] is set to
13299 0x1 (according to the PIPE3 specification). The values for transmit deemphasis are derived
13300 from the following equation:
13301
13302 _ TX deemphasis (db) = 20 * log_base_10((128 - 2 * pcs_tx_deemph)/128)
13303
13304 In general, the parameter controls are static signals to be set prior to taking the PHY
13305 out of reset. However, you can dynamically change these values on-the-fly for test
13306 purposes. In this case, changes to the transmitter to reflect the current value occur only
13307 after USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] changes.
13308
13309 Internal:
13310 Default value is package dependant. */
13311 uint64_t pcs_tx_deemph_6db : 6; /**< [ 25: 20](R/W) Fine-tune transmitter driver deemphasis when set to 6 db.
13312 This static value sets the TX driver deemphasis value when
13313 USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] is set to
13314 0x0 (according to the PIPE3 specification). This bus is provided for completeness and as a
13315 second potential launch amplitude. The values for transmit deemphasis are derived from the
13316 following equation:
13317
13318 _ TX deemphasis (db) = 20 * log_base_10((128 - 2 * pcs_tx_deemph)/128)
13319
13320 In general, the parameter controls are static signals to be set prior to taking the PHY
13321 out of reset. However, you can dynamically change these values on-the-fly for test
13322 purposes. In this case, changes to the transmitter to reflect the current value occur only
13323 after USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] changes.
13324
13325 Internal:
13326 Default value is package dependant. */
13327 uint64_t pcs_tx_swing_full : 7; /**< [ 19: 13](R/W) Launch amplitude of the transmitter. Sets the launch amplitude of the transmitter. The
13328 values for transmit amplitude are derived from the following equation:
13329 TX amplitude (V) = vptx * ((pcs_tx_swing_full + 1)/128)
13330
13331 In general, the parameter controls are static signals to be set prior to taking the PHY
13332 out of reset. However, you can dynamically change these values on-the-fly for test
13333 purposes. In this case, changes to the transmitter to reflect the current value occur only
13334 after USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] changes.
13335
13336 Internal:
13337 Default value is package dependant. */
13338 uint64_t lane0_tx_term_offset : 5; /**< [ 12: 8](R/W) Transmitter termination offset. Reserved, set to 0x0. */
13339 uint64_t reserved_6_7 : 2;
13340 uint64_t res_tune_ack : 1; /**< [ 5: 5](RO/H) Resistor tune acknowledge. While asserted, indicates a resistor tune is in progress. */
13341 uint64_t res_tune_req : 1; /**< [ 4: 4](R/W) Resistor tune request. The rising edge triggers a resistor tune request (if one is not
13342 already in progress). When asserted, [RES_TUNE_ACK] is asserted high until calibration of
13343 the termination impedance is complete.
13344 Tuning disrupts the normal flow of data; therefore, assert [RES_TUNE_REQ] only when the
13345 PHY
13346 is inactive. The PHY automatically performs a tune when coming out of PRST. */
13347 uint64_t reserved_0_3 : 4;
13348 #else /* Word 0 - Little Endian */
13349 uint64_t reserved_0_3 : 4;
13350 uint64_t res_tune_req : 1; /**< [ 4: 4](R/W) Resistor tune request. The rising edge triggers a resistor tune request (if one is not
13351 already in progress). When asserted, [RES_TUNE_ACK] is asserted high until calibration of
13352 the termination impedance is complete.
13353 Tuning disrupts the normal flow of data; therefore, assert [RES_TUNE_REQ] only when the
13354 PHY
13355 is inactive. The PHY automatically performs a tune when coming out of PRST. */
13356 uint64_t res_tune_ack : 1; /**< [ 5: 5](RO/H) Resistor tune acknowledge. While asserted, indicates a resistor tune is in progress. */
13357 uint64_t reserved_6_7 : 2;
13358 uint64_t lane0_tx_term_offset : 5; /**< [ 12: 8](R/W) Transmitter termination offset. Reserved, set to 0x0. */
13359 uint64_t pcs_tx_swing_full : 7; /**< [ 19: 13](R/W) Launch amplitude of the transmitter. Sets the launch amplitude of the transmitter. The
13360 values for transmit amplitude are derived from the following equation:
13361 TX amplitude (V) = vptx * ((pcs_tx_swing_full + 1)/128)
13362
13363 In general, the parameter controls are static signals to be set prior to taking the PHY
13364 out of reset. However, you can dynamically change these values on-the-fly for test
13365 purposes. In this case, changes to the transmitter to reflect the current value occur only
13366 after USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] changes.
13367
13368 Internal:
13369 Default value is package dependant. */
13370 uint64_t pcs_tx_deemph_6db : 6; /**< [ 25: 20](R/W) Fine-tune transmitter driver deemphasis when set to 6 db.
13371 This static value sets the TX driver deemphasis value when
13372 USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] is set to
13373 0x0 (according to the PIPE3 specification). This bus is provided for completeness and as a
13374 second potential launch amplitude. The values for transmit deemphasis are derived from the
13375 following equation:
13376
13377 _ TX deemphasis (db) = 20 * log_base_10((128 - 2 * pcs_tx_deemph)/128)
13378
13379 In general, the parameter controls are static signals to be set prior to taking the PHY
13380 out of reset. However, you can dynamically change these values on-the-fly for test
13381 purposes. In this case, changes to the transmitter to reflect the current value occur only
13382 after USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] changes.
13383
13384 Internal:
13385 Default value is package dependant. */
13386 uint64_t pcs_tx_deemph_3p5db : 6; /**< [ 31: 26](R/W) Fine-tune transmitter driver deemphasis when set to 3.5db.
13387 This static value sets the TX driver deemphasis value when
13388 USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] is set to
13389 0x1 (according to the PIPE3 specification). The values for transmit deemphasis are derived
13390 from the following equation:
13391
13392 _ TX deemphasis (db) = 20 * log_base_10((128 - 2 * pcs_tx_deemph)/128)
13393
13394 In general, the parameter controls are static signals to be set prior to taking the PHY
13395 out of reset. However, you can dynamically change these values on-the-fly for test
13396 purposes. In this case, changes to the transmitter to reflect the current value occur only
13397 after USBDRD()_UAHC_GUSB3PIPECTL()[TXDEEMPHASIS] changes.
13398
13399 Internal:
13400 Default value is package dependant. */
13401 uint64_t pcs_rx_los_mask_val : 10; /**< [ 41: 32](R/W) Configurable loss-of-signal mask width. Sets the number of reference clock cycles to mask
13402 the incoming LFPS in U3 and U2 states. Masks the incoming LFPS for the number of reference
13403 clock cycles equal to the value of pcs_rx_los_mask_val\<9:0\>. This control filters out
13404 short, non-compliant LFPS glitches sent by a noncompliant host.
13405
13406 For normal operation, set to a targeted mask interval of 10us (value = 10us / Tref_clk).
13407 If the USBDRD()_UCTL_CTL[REF_CLK_DIV2] is used, then
13408 (value = 10us / (2 * Tref_clk)). These equations are based on the SuperSpeed reference
13409 clock frequency. The value of [PCS_RX_LOS_MASK_VAL] should be as follows:
13410
13411 \<pre\>
13412 Frequency DIV2 LOS_MASK
13413 --------- --- --------
13414 200 MHz 1 0x3E8
13415 125 MHz 0 0x4E2
13416 104 MHz 0 0x410
13417 100 MHz 0 0x3E8
13418 96 MHz 0 0x3C0
13419 76.8 MHz 1 0x180
13420 52 MHz 0 0x208
13421 50 MHz 0 0x1F4
13422 48 MHz 0 0x1E0
13423 40 MHz 1 0x0C8
13424 38.4 MHz 0 0x180
13425 26 MHz 0 0x104
13426 25 MHz 0 0x0FA
13427 24 MHz 0 0x0F0
13428 20 MHz 0 0x0C8
13429 19.2 MHz 0 0x0C0
13430 \</pre\>
13431
13432 Setting this bus to 0x0 disables masking. The value should be defined when the PHY is in
13433 reset. Changing this value during operation might disrupt normal operation of the link. */
13434 uint64_t reserved_42_55 : 14;
13435 uint64_t lane0_tx2rx_loopbk : 1; /**< [ 56: 56](R/W) When asserted, data from TX predriver is looped back to RX slicers. LOS is bypassed and
13436 based on the tx0_en input so that rx0_los = !tx_data_en. */
13437 uint64_t lane0_ext_pclk_req : 1; /**< [ 57: 57](R/W) When asserted, this signal enables the pipe0_pclk output regardless of power state (along
13438 with the associated increase in power consumption). You can use this input to enable
13439 pipe0_pclk in the P3 state without going through a complete boot sequence. */
13440 uint64_t los_bias : 3; /**< [ 60: 58](R/W) Loss-of-signal detector threshold-level control. A positive, binary bit setting change
13441 results in a +15 mVp incremental change in the LOS threshold.
13442 A negative binary bit setting change results in a -15 mVp incremental change in the LOS
13443 threshold. The 0x0 setting is reserved and must not be used. The default 0x5 setting
13444 corresponds to approximately 105 mVp.
13445 0x0 = invalid.
13446 0x1 = 45 mV.
13447 0x2 = 60 mV.
13448 0x3 = 75 mV.
13449 0x4 = 90 mV.
13450 0x5 = 105 mV (default).
13451 0x6 = 120 mV.
13452 0x7 = 135 mV. */
13453 uint64_t tx_vboost_lvl : 3; /**< [ 63: 61](R/W) TX voltage-boost level. Sets the boosted transmit launch amplitude (mVppd). The default
13454 bit setting is intended to set the launch amplitude to approximately 1,008 mVppd. A
13455 single, positive binary bit setting change results in a +156 mVppd change in the TX launch
13456 amplitude.
13457 A single, negative binary bit setting change results in a -156 mVppd change in the TX
13458 launch amplitude. All settings more than one binary bit change should not be used.
13459 0x3 = 0.844 V launch amplitude.
13460 0x4 = 1.008 V launch amplitude.
13461 0x5 = 1.156 V launch amplitude.
13462 All others values are invalid. */
13463 #endif /* Word 0 - End */
13464 } s;
13465 /* struct bdk_usbdrdx_uctl_portx_cfg_ss_s cn; */
13466 };
13467 typedef union bdk_usbdrdx_uctl_portx_cfg_ss bdk_usbdrdx_uctl_portx_cfg_ss_t;
13468
13469 static inline uint64_t BDK_USBDRDX_UCTL_PORTX_CFG_SS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_PORTX_CFG_SS(unsigned long a,unsigned long b)13470 static inline uint64_t BDK_USBDRDX_UCTL_PORTX_CFG_SS(unsigned long a, unsigned long b)
13471 {
13472 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
13473 return 0x868000100058ll + 0x1000000000ll * ((a) & 0x1) + 0x20ll * ((b) & 0x0);
13474 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
13475 return 0x868000100058ll + 0x1000000000ll * ((a) & 0x1) + 0x20ll * ((b) & 0x0);
13476 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
13477 return 0x868000100058ll + 0x1000000000ll * ((a) & 0x1) + 0x20ll * ((b) & 0x0);
13478 __bdk_csr_fatal("USBDRDX_UCTL_PORTX_CFG_SS", 2, a, b, 0, 0);
13479 }
13480
13481 #define typedef_BDK_USBDRDX_UCTL_PORTX_CFG_SS(a,b) bdk_usbdrdx_uctl_portx_cfg_ss_t
13482 #define bustype_BDK_USBDRDX_UCTL_PORTX_CFG_SS(a,b) BDK_CSR_TYPE_NCB
13483 #define basename_BDK_USBDRDX_UCTL_PORTX_CFG_SS(a,b) "USBDRDX_UCTL_PORTX_CFG_SS"
13484 #define device_bar_BDK_USBDRDX_UCTL_PORTX_CFG_SS(a,b) 0x0 /* PF_BAR0 */
13485 #define busnum_BDK_USBDRDX_UCTL_PORTX_CFG_SS(a,b) (a)
13486 #define arguments_BDK_USBDRDX_UCTL_PORTX_CFG_SS(a,b) (a),(b),-1,-1
13487
13488 /**
13489 * Register (NCB) usbdrd#_uctl_port#_cr_dbg_cfg
13490 *
13491 * USB UCTL Port Debug Configuration Register
13492 * This register allows indirect access to the configuration and test controls for the port 0
13493 * PHY.
13494 *
13495 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
13496 *
13497 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
13498 *
13499 * Internal:
13500 * (In body of HRM)
13501 * To access the PHY registers indirectly through the CR interface, the HCLK must be running,
13502 * UCTL_RST must be deasserted, and UPHY_RST must be deasserted. Software is responsible for
13503 * ensuring that only one indirect access is ongoing at a time.
13504 *
13505 * To read a PHY register via indirect CR interface:
13506 * 1. Write UCTL_PORTn_CR_DBG_CFG with:
13507 * * [DATA_IN] with the \<\<address\>\> of the register,
13508 * * [CAP_ADDR], [CAP_DATA], [READ], and [WRITE] fields 0x0.
13509 * 2. Write UCTL_PORTn_CR_DBG_CFG with:
13510 * * [DATA_IN] with the \<\<address\>\> of the register,
13511 * * [CAP_ADDR] field 0x1,
13512 * * [CAP_DATA], [READ], and [WRITE] fields 0x0.
13513 * 3. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x1.
13514 * 4. Write UCTL_PORTn_CR_DBG_CFG with all 0x0's.
13515 * 5. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x0.
13516 * 6. Write UCTL_PORTn_CR_DBG_CFG with:
13517 * * [READ] field 0x1,
13518 * * [DATA_IN], [CAP_ADDR], [CAP_DATA], and [WRITE] fields 0x0.
13519 * 7. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x1.
13520 * 8. Read UCTL_PORTn_CR_DBG_STATUS[DATA_OUT]. This is the \<\<read data\>\>.
13521 * 9. Write UCTL_PORTn_CR_DBG_CFG with all 0x0's.
13522 * 10. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x0.
13523 *
13524 * To write a PHY register via indirect CR interface:
13525 * 1. Write UCTL_PORTn_CR_DBG_CFG with:
13526 * * [DATA_IN] with the \<\<address\>\> of the register,
13527 * * [CAP_ADDR], [CAP_DATA], [READ], and [WRITE] fields 0x0.
13528 * 2. Write UCTL_PORTn_CR_DBG_CFG with:
13529 * * [DATA_IN] with the \<\<address\>\> of the register,
13530 * * [CAP_ADDR] field 0x1,
13531 * * [CAP_DATA], [READ], and [WRITE] fields 0x0.
13532 * 3. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x1.
13533 * 4. Write UCTL_PORTn_CR_DBG_CFG with all 0x0's.
13534 * 5. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x0.
13535 * 6. Write UCTL_PORTn_CR_DBG_CFG with:
13536 * * [DATA_IN] with the \<\<write data\>\>,
13537 * * [CAP_ADDR], [CAP_DATA], [READ], and [WRITE] fields 0x0.
13538 * 7. Write UCTL_PORTn_CR_DBG_CFG with:
13539 * * [DATA_IN] with the write data,
13540 * * [CAP_DATA] field 0x1,
13541 * * [CAP_ADDR], [READ], and [WRITE] fields 0x0.
13542 * 8. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x1.
13543 * 9. Write UCTL_PORTn_CR_DBG_CFG with all 0x0's.
13544 * 10. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x0.
13545 * 11. Write UCTL_PORTn_CR_DBG_CFG with:
13546 * * [WRITE] field 0x1,
13547 * * [DATA_IN], [CAP_ADDR], and [READ] fields 0x0.
13548 * 12. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x1.
13549 * 13. Write UCTL_PORTn_CR_DBG_CFG with all 0x0's.
13550 * 14. Poll for UCTL_PORTn_CR_DBG_STATUS[ACK] 0x0.
13551 *
13552 * For partial writes, a read-modify write is required. Note that the CAP_ADDR steps (1-5)
13553 * do not have to be repeated until the address needs changed.
13554 */
13555 union bdk_usbdrdx_uctl_portx_cr_dbg_cfg
13556 {
13557 uint64_t u;
13558 struct bdk_usbdrdx_uctl_portx_cr_dbg_cfg_s
13559 {
13560 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13561 uint64_t reserved_48_63 : 16;
13562 uint64_t data_in : 16; /**< [ 47: 32](R/W) Address or data to be written to the CR interface. */
13563 uint64_t reserved_4_31 : 28;
13564 uint64_t cap_addr : 1; /**< [ 3: 3](R/W) Rising edge triggers the [DATA_IN] field to be captured as the address. */
13565 uint64_t cap_data : 1; /**< [ 2: 2](R/W) Rising edge triggers the [DATA_IN] field to be captured as the write data. */
13566 uint64_t read : 1; /**< [ 1: 1](R/W) Rising edge triggers a register read operation of the captured address. */
13567 uint64_t write : 1; /**< [ 0: 0](R/W) Rising edge triggers a register write operation of the captured address with the captured data. */
13568 #else /* Word 0 - Little Endian */
13569 uint64_t write : 1; /**< [ 0: 0](R/W) Rising edge triggers a register write operation of the captured address with the captured data. */
13570 uint64_t read : 1; /**< [ 1: 1](R/W) Rising edge triggers a register read operation of the captured address. */
13571 uint64_t cap_data : 1; /**< [ 2: 2](R/W) Rising edge triggers the [DATA_IN] field to be captured as the write data. */
13572 uint64_t cap_addr : 1; /**< [ 3: 3](R/W) Rising edge triggers the [DATA_IN] field to be captured as the address. */
13573 uint64_t reserved_4_31 : 28;
13574 uint64_t data_in : 16; /**< [ 47: 32](R/W) Address or data to be written to the CR interface. */
13575 uint64_t reserved_48_63 : 16;
13576 #endif /* Word 0 - End */
13577 } s;
13578 /* struct bdk_usbdrdx_uctl_portx_cr_dbg_cfg_s cn; */
13579 };
13580 typedef union bdk_usbdrdx_uctl_portx_cr_dbg_cfg bdk_usbdrdx_uctl_portx_cr_dbg_cfg_t;
13581
13582 static inline uint64_t BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(unsigned long a,unsigned long b)13583 static inline uint64_t BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(unsigned long a, unsigned long b)
13584 {
13585 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
13586 return 0x868000100060ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
13587 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
13588 return 0x868000100060ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
13589 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
13590 return 0x868000100060ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
13591 __bdk_csr_fatal("USBDRDX_UCTL_PORTX_CR_DBG_CFG", 2, a, b, 0, 0);
13592 }
13593
13594 #define typedef_BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(a,b) bdk_usbdrdx_uctl_portx_cr_dbg_cfg_t
13595 #define bustype_BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(a,b) BDK_CSR_TYPE_NCB
13596 #define basename_BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(a,b) "USBDRDX_UCTL_PORTX_CR_DBG_CFG"
13597 #define device_bar_BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(a,b) 0x0 /* PF_BAR0 */
13598 #define busnum_BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(a,b) (a)
13599 #define arguments_BDK_USBDRDX_UCTL_PORTX_CR_DBG_CFG(a,b) (a),(b),-1,-1
13600
13601 /**
13602 * Register (NCB) usbdrd#_uctl_port#_cr_dbg_status
13603 *
13604 * USB UCTL Port Debug Status Register
13605 * This register allows indirect access to the configuration and test controls for the port 0
13606 * PHY.
13607 *
13608 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
13609 *
13610 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
13611 */
13612 union bdk_usbdrdx_uctl_portx_cr_dbg_status
13613 {
13614 uint64_t u;
13615 struct bdk_usbdrdx_uctl_portx_cr_dbg_status_s
13616 {
13617 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13618 uint64_t reserved_48_63 : 16;
13619 uint64_t data_out : 16; /**< [ 47: 32](RO/H) Last data read from the CR interface. */
13620 uint64_t reserved_1_31 : 31;
13621 uint64_t ack : 1; /**< [ 0: 0](RO/H) Acknowledge that the CAP_ADDR, CAP_DATA, READ, WRITE commands have completed. */
13622 #else /* Word 0 - Little Endian */
13623 uint64_t ack : 1; /**< [ 0: 0](RO/H) Acknowledge that the CAP_ADDR, CAP_DATA, READ, WRITE commands have completed. */
13624 uint64_t reserved_1_31 : 31;
13625 uint64_t data_out : 16; /**< [ 47: 32](RO/H) Last data read from the CR interface. */
13626 uint64_t reserved_48_63 : 16;
13627 #endif /* Word 0 - End */
13628 } s;
13629 /* struct bdk_usbdrdx_uctl_portx_cr_dbg_status_s cn; */
13630 };
13631 typedef union bdk_usbdrdx_uctl_portx_cr_dbg_status bdk_usbdrdx_uctl_portx_cr_dbg_status_t;
13632
13633 static inline uint64_t BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(unsigned long a,unsigned long b)13634 static inline uint64_t BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(unsigned long a, unsigned long b)
13635 {
13636 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
13637 return 0x868000100068ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
13638 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
13639 return 0x868000100068ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
13640 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=1) && (b==0)))
13641 return 0x868000100068ll + 0x1000000000ll * ((a) & 0x1) + 0ll * ((b) & 0x0);
13642 __bdk_csr_fatal("USBDRDX_UCTL_PORTX_CR_DBG_STATUS", 2, a, b, 0, 0);
13643 }
13644
13645 #define typedef_BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(a,b) bdk_usbdrdx_uctl_portx_cr_dbg_status_t
13646 #define bustype_BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(a,b) BDK_CSR_TYPE_NCB
13647 #define basename_BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(a,b) "USBDRDX_UCTL_PORTX_CR_DBG_STATUS"
13648 #define device_bar_BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(a,b) 0x0 /* PF_BAR0 */
13649 #define busnum_BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(a,b) (a)
13650 #define arguments_BDK_USBDRDX_UCTL_PORTX_CR_DBG_STATUS(a,b) (a),(b),-1,-1
13651
13652 /**
13653 * Register (NCB) usbdrd#_uctl_ras
13654 *
13655 * USB UCTL RAS Register
13656 * This register is intended for delivery of RAS events to the SCP, so should be
13657 * ignored by OS drivers.
13658 */
13659 union bdk_usbdrdx_uctl_ras
13660 {
13661 uint64_t u;
13662 struct bdk_usbdrdx_uctl_ras_s
13663 {
13664 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13665 uint64_t reserved_1_63 : 63;
13666 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1C/H) Received DMA read response with poisoned data from NCBO. Hardware also sets
13667 USBDRD()_UCTL_INTSTAT[DMA_PSN]. */
13668 #else /* Word 0 - Little Endian */
13669 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1C/H) Received DMA read response with poisoned data from NCBO. Hardware also sets
13670 USBDRD()_UCTL_INTSTAT[DMA_PSN]. */
13671 uint64_t reserved_1_63 : 63;
13672 #endif /* Word 0 - End */
13673 } s;
13674 /* struct bdk_usbdrdx_uctl_ras_s cn; */
13675 };
13676 typedef union bdk_usbdrdx_uctl_ras bdk_usbdrdx_uctl_ras_t;
13677
13678 static inline uint64_t BDK_USBDRDX_UCTL_RAS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_RAS(unsigned long a)13679 static inline uint64_t BDK_USBDRDX_UCTL_RAS(unsigned long a)
13680 {
13681 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
13682 return 0x868000100080ll + 0x1000000000ll * ((a) & 0x1);
13683 __bdk_csr_fatal("USBDRDX_UCTL_RAS", 1, a, 0, 0, 0);
13684 }
13685
13686 #define typedef_BDK_USBDRDX_UCTL_RAS(a) bdk_usbdrdx_uctl_ras_t
13687 #define bustype_BDK_USBDRDX_UCTL_RAS(a) BDK_CSR_TYPE_NCB
13688 #define basename_BDK_USBDRDX_UCTL_RAS(a) "USBDRDX_UCTL_RAS"
13689 #define device_bar_BDK_USBDRDX_UCTL_RAS(a) 0x0 /* PF_BAR0 */
13690 #define busnum_BDK_USBDRDX_UCTL_RAS(a) (a)
13691 #define arguments_BDK_USBDRDX_UCTL_RAS(a) (a),-1,-1,-1
13692
13693 /**
13694 * Register (NCB) usbdrd#_uctl_ras_w1s
13695 *
13696 * USB UCTL RAS Register
13697 * This register sets interrupt bits.
13698 */
13699 union bdk_usbdrdx_uctl_ras_w1s
13700 {
13701 uint64_t u;
13702 struct bdk_usbdrdx_uctl_ras_w1s_s
13703 {
13704 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13705 uint64_t reserved_1_63 : 63;
13706 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_RAS[DMA_PSN]. */
13707 #else /* Word 0 - Little Endian */
13708 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1S/H) Reads or sets USBDRD(0..1)_UCTL_RAS[DMA_PSN]. */
13709 uint64_t reserved_1_63 : 63;
13710 #endif /* Word 0 - End */
13711 } s;
13712 /* struct bdk_usbdrdx_uctl_ras_w1s_s cn; */
13713 };
13714 typedef union bdk_usbdrdx_uctl_ras_w1s bdk_usbdrdx_uctl_ras_w1s_t;
13715
13716 static inline uint64_t BDK_USBDRDX_UCTL_RAS_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_RAS_W1S(unsigned long a)13717 static inline uint64_t BDK_USBDRDX_UCTL_RAS_W1S(unsigned long a)
13718 {
13719 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
13720 return 0x868000100088ll + 0x1000000000ll * ((a) & 0x1);
13721 __bdk_csr_fatal("USBDRDX_UCTL_RAS_W1S", 1, a, 0, 0, 0);
13722 }
13723
13724 #define typedef_BDK_USBDRDX_UCTL_RAS_W1S(a) bdk_usbdrdx_uctl_ras_w1s_t
13725 #define bustype_BDK_USBDRDX_UCTL_RAS_W1S(a) BDK_CSR_TYPE_NCB
13726 #define basename_BDK_USBDRDX_UCTL_RAS_W1S(a) "USBDRDX_UCTL_RAS_W1S"
13727 #define device_bar_BDK_USBDRDX_UCTL_RAS_W1S(a) 0x0 /* PF_BAR0 */
13728 #define busnum_BDK_USBDRDX_UCTL_RAS_W1S(a) (a)
13729 #define arguments_BDK_USBDRDX_UCTL_RAS_W1S(a) (a),-1,-1,-1
13730
13731 /**
13732 * Register (NCB) usbdrd#_uctl_rasena_w1c
13733 *
13734 * USB UCTL RAS Register
13735 * This register clears interrupt enable bits.
13736 */
13737 union bdk_usbdrdx_uctl_rasena_w1c
13738 {
13739 uint64_t u;
13740 struct bdk_usbdrdx_uctl_rasena_w1c_s
13741 {
13742 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13743 uint64_t reserved_1_63 : 63;
13744 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_RAS[DMA_PSN]. */
13745 #else /* Word 0 - Little Endian */
13746 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for USBDRD(0..1)_UCTL_RAS[DMA_PSN]. */
13747 uint64_t reserved_1_63 : 63;
13748 #endif /* Word 0 - End */
13749 } s;
13750 /* struct bdk_usbdrdx_uctl_rasena_w1c_s cn; */
13751 };
13752 typedef union bdk_usbdrdx_uctl_rasena_w1c bdk_usbdrdx_uctl_rasena_w1c_t;
13753
13754 static inline uint64_t BDK_USBDRDX_UCTL_RASENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_RASENA_W1C(unsigned long a)13755 static inline uint64_t BDK_USBDRDX_UCTL_RASENA_W1C(unsigned long a)
13756 {
13757 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
13758 return 0x868000100090ll + 0x1000000000ll * ((a) & 0x1);
13759 __bdk_csr_fatal("USBDRDX_UCTL_RASENA_W1C", 1, a, 0, 0, 0);
13760 }
13761
13762 #define typedef_BDK_USBDRDX_UCTL_RASENA_W1C(a) bdk_usbdrdx_uctl_rasena_w1c_t
13763 #define bustype_BDK_USBDRDX_UCTL_RASENA_W1C(a) BDK_CSR_TYPE_NCB
13764 #define basename_BDK_USBDRDX_UCTL_RASENA_W1C(a) "USBDRDX_UCTL_RASENA_W1C"
13765 #define device_bar_BDK_USBDRDX_UCTL_RASENA_W1C(a) 0x0 /* PF_BAR0 */
13766 #define busnum_BDK_USBDRDX_UCTL_RASENA_W1C(a) (a)
13767 #define arguments_BDK_USBDRDX_UCTL_RASENA_W1C(a) (a),-1,-1,-1
13768
13769 /**
13770 * Register (NCB) usbdrd#_uctl_rasena_w1s
13771 *
13772 * USB UCTL RAS Register
13773 * This register sets interrupt enable bits.
13774 */
13775 union bdk_usbdrdx_uctl_rasena_w1s
13776 {
13777 uint64_t u;
13778 struct bdk_usbdrdx_uctl_rasena_w1s_s
13779 {
13780 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13781 uint64_t reserved_1_63 : 63;
13782 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_RAS[DMA_PSN]. */
13783 #else /* Word 0 - Little Endian */
13784 uint64_t dma_psn : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for USBDRD(0..1)_UCTL_RAS[DMA_PSN]. */
13785 uint64_t reserved_1_63 : 63;
13786 #endif /* Word 0 - End */
13787 } s;
13788 /* struct bdk_usbdrdx_uctl_rasena_w1s_s cn; */
13789 };
13790 typedef union bdk_usbdrdx_uctl_rasena_w1s bdk_usbdrdx_uctl_rasena_w1s_t;
13791
13792 static inline uint64_t BDK_USBDRDX_UCTL_RASENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_RASENA_W1S(unsigned long a)13793 static inline uint64_t BDK_USBDRDX_UCTL_RASENA_W1S(unsigned long a)
13794 {
13795 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
13796 return 0x868000100098ll + 0x1000000000ll * ((a) & 0x1);
13797 __bdk_csr_fatal("USBDRDX_UCTL_RASENA_W1S", 1, a, 0, 0, 0);
13798 }
13799
13800 #define typedef_BDK_USBDRDX_UCTL_RASENA_W1S(a) bdk_usbdrdx_uctl_rasena_w1s_t
13801 #define bustype_BDK_USBDRDX_UCTL_RASENA_W1S(a) BDK_CSR_TYPE_NCB
13802 #define basename_BDK_USBDRDX_UCTL_RASENA_W1S(a) "USBDRDX_UCTL_RASENA_W1S"
13803 #define device_bar_BDK_USBDRDX_UCTL_RASENA_W1S(a) 0x0 /* PF_BAR0 */
13804 #define busnum_BDK_USBDRDX_UCTL_RASENA_W1S(a) (a)
13805 #define arguments_BDK_USBDRDX_UCTL_RASENA_W1S(a) (a),-1,-1,-1
13806
13807 /**
13808 * Register (NCB) usbdrd#_uctl_shim_cfg
13809 *
13810 * USB UCTL Shim Configuration Register
13811 * This register allows configuration of various shim (UCTL) features. The fields XS_NCB_OOB_*
13812 * are captured when there are no outstanding OOB errors indicated in INTSTAT and a new OOB error
13813 * arrives. The fields XS_BAD_DMA_* are captured when there are no outstanding DMA errors
13814 * indicated in INTSTAT and a new DMA error arrives.
13815 *
13816 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
13817 *
13818 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
13819 */
13820 union bdk_usbdrdx_uctl_shim_cfg
13821 {
13822 uint64_t u;
13823 struct bdk_usbdrdx_uctl_shim_cfg_s
13824 {
13825 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13826 uint64_t xs_ncb_oob_wrn : 1; /**< [ 63: 63](RO/H) Read/write error log for out-of-bound UAHC register access.
13827 0 = read, 1 = write. */
13828 uint64_t reserved_60_62 : 3;
13829 uint64_t xs_ncb_oob_osrc : 12; /**< [ 59: 48](RO/H) SRCID error log for out-of-bound UAHC register access. The NCB outbound SRCID for the OOB
13830 error.
13831 \<59:58\> = chipID.
13832 \<57\> = Request source: 0 = core, 1 = NCB-device.
13833 \<56:51\> = Core/NCB-device number. Note that for NCB devices, \<56\> is always 0.
13834 \<50:48\> = SubID. */
13835 uint64_t xm_bad_dma_wrn : 1; /**< [ 47: 47](RO/H) Read/write error log for bad DMA access from UAHC.
13836 0 = Read error log.
13837 1 = Write error log. */
13838 uint64_t reserved_44_46 : 3;
13839 uint64_t xm_bad_dma_type : 4; /**< [ 43: 40](RO/H) ErrType error log for bad DMA access from UAHC. Encodes the type of error encountered
13840 (error largest encoded value has priority). See UCTL_XM_BAD_DMA_TYPE_E. */
13841 uint64_t reserved_14_39 : 26;
13842 uint64_t dma_read_cmd : 2; /**< [ 13: 12](R/W) Selects the NCB read command used by DMA accesses. See UCTL_DMA_READ_CMD_E. */
13843 uint64_t reserved_11 : 1;
13844 uint64_t dma_write_cmd : 1; /**< [ 10: 10](R/W) Selects the NCB write command used by DMA accesses. See UCTL_DMA_WRITE_CMD_E. */
13845 uint64_t reserved_0_9 : 10;
13846 #else /* Word 0 - Little Endian */
13847 uint64_t reserved_0_9 : 10;
13848 uint64_t dma_write_cmd : 1; /**< [ 10: 10](R/W) Selects the NCB write command used by DMA accesses. See UCTL_DMA_WRITE_CMD_E. */
13849 uint64_t reserved_11 : 1;
13850 uint64_t dma_read_cmd : 2; /**< [ 13: 12](R/W) Selects the NCB read command used by DMA accesses. See UCTL_DMA_READ_CMD_E. */
13851 uint64_t reserved_14_39 : 26;
13852 uint64_t xm_bad_dma_type : 4; /**< [ 43: 40](RO/H) ErrType error log for bad DMA access from UAHC. Encodes the type of error encountered
13853 (error largest encoded value has priority). See UCTL_XM_BAD_DMA_TYPE_E. */
13854 uint64_t reserved_44_46 : 3;
13855 uint64_t xm_bad_dma_wrn : 1; /**< [ 47: 47](RO/H) Read/write error log for bad DMA access from UAHC.
13856 0 = Read error log.
13857 1 = Write error log. */
13858 uint64_t xs_ncb_oob_osrc : 12; /**< [ 59: 48](RO/H) SRCID error log for out-of-bound UAHC register access. The NCB outbound SRCID for the OOB
13859 error.
13860 \<59:58\> = chipID.
13861 \<57\> = Request source: 0 = core, 1 = NCB-device.
13862 \<56:51\> = Core/NCB-device number. Note that for NCB devices, \<56\> is always 0.
13863 \<50:48\> = SubID. */
13864 uint64_t reserved_60_62 : 3;
13865 uint64_t xs_ncb_oob_wrn : 1; /**< [ 63: 63](RO/H) Read/write error log for out-of-bound UAHC register access.
13866 0 = read, 1 = write. */
13867 #endif /* Word 0 - End */
13868 } s;
13869 /* struct bdk_usbdrdx_uctl_shim_cfg_s cn; */
13870 };
13871 typedef union bdk_usbdrdx_uctl_shim_cfg bdk_usbdrdx_uctl_shim_cfg_t;
13872
13873 static inline uint64_t BDK_USBDRDX_UCTL_SHIM_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_SHIM_CFG(unsigned long a)13874 static inline uint64_t BDK_USBDRDX_UCTL_SHIM_CFG(unsigned long a)
13875 {
13876 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
13877 return 0x8680001000e8ll + 0x1000000000ll * ((a) & 0x1);
13878 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
13879 return 0x8680001000e8ll + 0x1000000000ll * ((a) & 0x1);
13880 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
13881 return 0x8680001000e8ll + 0x1000000000ll * ((a) & 0x1);
13882 __bdk_csr_fatal("USBDRDX_UCTL_SHIM_CFG", 1, a, 0, 0, 0);
13883 }
13884
13885 #define typedef_BDK_USBDRDX_UCTL_SHIM_CFG(a) bdk_usbdrdx_uctl_shim_cfg_t
13886 #define bustype_BDK_USBDRDX_UCTL_SHIM_CFG(a) BDK_CSR_TYPE_NCB
13887 #define basename_BDK_USBDRDX_UCTL_SHIM_CFG(a) "USBDRDX_UCTL_SHIM_CFG"
13888 #define device_bar_BDK_USBDRDX_UCTL_SHIM_CFG(a) 0x0 /* PF_BAR0 */
13889 #define busnum_BDK_USBDRDX_UCTL_SHIM_CFG(a) (a)
13890 #define arguments_BDK_USBDRDX_UCTL_SHIM_CFG(a) (a),-1,-1,-1
13891
13892 /**
13893 * Register (NCB) usbdrd#_uctl_spare0
13894 *
13895 * INTERNAL: USB UCTL Spare Register 0
13896 *
13897 * This register is a spare register. This register can be reset by NCB reset.
13898 */
13899 union bdk_usbdrdx_uctl_spare0
13900 {
13901 uint64_t u;
13902 struct bdk_usbdrdx_uctl_spare0_s
13903 {
13904 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13905 uint64_t spare : 64; /**< [ 63: 0](R/W) Internal:
13906 Reserved for ECO usage. */
13907 #else /* Word 0 - Little Endian */
13908 uint64_t spare : 64; /**< [ 63: 0](R/W) Internal:
13909 Reserved for ECO usage. */
13910 #endif /* Word 0 - End */
13911 } s;
13912 /* struct bdk_usbdrdx_uctl_spare0_s cn; */
13913 };
13914 typedef union bdk_usbdrdx_uctl_spare0 bdk_usbdrdx_uctl_spare0_t;
13915
13916 static inline uint64_t BDK_USBDRDX_UCTL_SPARE0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_SPARE0(unsigned long a)13917 static inline uint64_t BDK_USBDRDX_UCTL_SPARE0(unsigned long a)
13918 {
13919 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
13920 return 0x868000100010ll + 0x1000000000ll * ((a) & 0x1);
13921 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
13922 return 0x868000100010ll + 0x1000000000ll * ((a) & 0x1);
13923 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
13924 return 0x868000100010ll + 0x1000000000ll * ((a) & 0x1);
13925 __bdk_csr_fatal("USBDRDX_UCTL_SPARE0", 1, a, 0, 0, 0);
13926 }
13927
13928 #define typedef_BDK_USBDRDX_UCTL_SPARE0(a) bdk_usbdrdx_uctl_spare0_t
13929 #define bustype_BDK_USBDRDX_UCTL_SPARE0(a) BDK_CSR_TYPE_NCB
13930 #define basename_BDK_USBDRDX_UCTL_SPARE0(a) "USBDRDX_UCTL_SPARE0"
13931 #define device_bar_BDK_USBDRDX_UCTL_SPARE0(a) 0x0 /* PF_BAR0 */
13932 #define busnum_BDK_USBDRDX_UCTL_SPARE0(a) (a)
13933 #define arguments_BDK_USBDRDX_UCTL_SPARE0(a) (a),-1,-1,-1
13934
13935 /**
13936 * Register (NCB) usbdrd#_uctl_spare1
13937 *
13938 * INTERNAL: USB UCTL Spare Register 1
13939 *
13940 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
13941 *
13942 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
13943 */
13944 union bdk_usbdrdx_uctl_spare1
13945 {
13946 uint64_t u;
13947 struct bdk_usbdrdx_uctl_spare1_s
13948 {
13949 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13950 uint64_t spare : 64; /**< [ 63: 0](R/W) Internal:
13951 Reserved for ECO usage. */
13952 #else /* Word 0 - Little Endian */
13953 uint64_t spare : 64; /**< [ 63: 0](R/W) Internal:
13954 Reserved for ECO usage. */
13955 #endif /* Word 0 - End */
13956 } s;
13957 /* struct bdk_usbdrdx_uctl_spare1_s cn; */
13958 };
13959 typedef union bdk_usbdrdx_uctl_spare1 bdk_usbdrdx_uctl_spare1_t;
13960
13961 static inline uint64_t BDK_USBDRDX_UCTL_SPARE1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_SPARE1(unsigned long a)13962 static inline uint64_t BDK_USBDRDX_UCTL_SPARE1(unsigned long a)
13963 {
13964 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
13965 return 0x8680001000f8ll + 0x1000000000ll * ((a) & 0x1);
13966 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
13967 return 0x8680001000f8ll + 0x1000000000ll * ((a) & 0x1);
13968 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
13969 return 0x8680001000f8ll + 0x1000000000ll * ((a) & 0x1);
13970 __bdk_csr_fatal("USBDRDX_UCTL_SPARE1", 1, a, 0, 0, 0);
13971 }
13972
13973 #define typedef_BDK_USBDRDX_UCTL_SPARE1(a) bdk_usbdrdx_uctl_spare1_t
13974 #define bustype_BDK_USBDRDX_UCTL_SPARE1(a) BDK_CSR_TYPE_NCB
13975 #define basename_BDK_USBDRDX_UCTL_SPARE1(a) "USBDRDX_UCTL_SPARE1"
13976 #define device_bar_BDK_USBDRDX_UCTL_SPARE1(a) 0x0 /* PF_BAR0 */
13977 #define busnum_BDK_USBDRDX_UCTL_SPARE1(a) (a)
13978 #define arguments_BDK_USBDRDX_UCTL_SPARE1(a) (a),-1,-1,-1
13979
13980 /**
13981 * Register (NCB) usbdrd#_uctl_utmiclk_counter
13982 *
13983 * USB 2 Clock Counter Register
13984 * This register is accessible only when USBDRD()_UCTL_CTL[H_CLK_EN] = 1.
13985 *
13986 * This register can be reset by NCB reset or with USBDRD()_UCTL_CTL[UCTL_RST].
13987 */
13988 union bdk_usbdrdx_uctl_utmiclk_counter
13989 {
13990 uint64_t u;
13991 struct bdk_usbdrdx_uctl_utmiclk_counter_s
13992 {
13993 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13994 uint64_t counter : 64; /**< [ 63: 0](R/W) Internal:
13995 USB 2.0 free running clock counter. Increments each edge of the USB 2.0 reference clock. */
13996 #else /* Word 0 - Little Endian */
13997 uint64_t counter : 64; /**< [ 63: 0](R/W) Internal:
13998 USB 2.0 free running clock counter. Increments each edge of the USB 2.0 reference clock. */
13999 #endif /* Word 0 - End */
14000 } s;
14001 /* struct bdk_usbdrdx_uctl_utmiclk_counter_s cn; */
14002 };
14003 typedef union bdk_usbdrdx_uctl_utmiclk_counter bdk_usbdrdx_uctl_utmiclk_counter_t;
14004
14005 static inline uint64_t BDK_USBDRDX_UCTL_UTMICLK_COUNTER(unsigned long a) __attribute__ ((pure, always_inline));
BDK_USBDRDX_UCTL_UTMICLK_COUNTER(unsigned long a)14006 static inline uint64_t BDK_USBDRDX_UCTL_UTMICLK_COUNTER(unsigned long a)
14007 {
14008 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
14009 return 0x868000100018ll + 0x1000000000ll * ((a) & 0x1);
14010 __bdk_csr_fatal("USBDRDX_UCTL_UTMICLK_COUNTER", 1, a, 0, 0, 0);
14011 }
14012
14013 #define typedef_BDK_USBDRDX_UCTL_UTMICLK_COUNTER(a) bdk_usbdrdx_uctl_utmiclk_counter_t
14014 #define bustype_BDK_USBDRDX_UCTL_UTMICLK_COUNTER(a) BDK_CSR_TYPE_NCB
14015 #define basename_BDK_USBDRDX_UCTL_UTMICLK_COUNTER(a) "USBDRDX_UCTL_UTMICLK_COUNTER"
14016 #define device_bar_BDK_USBDRDX_UCTL_UTMICLK_COUNTER(a) 0x0 /* PF_BAR0 */
14017 #define busnum_BDK_USBDRDX_UCTL_UTMICLK_COUNTER(a) (a)
14018 #define arguments_BDK_USBDRDX_UCTL_UTMICLK_COUNTER(a) (a),-1,-1,-1
14019
14020 #endif /* __BDK_CSRS_USBDRD_H__ */
14021